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radeonsi: initialize SX_PS_DOWNCONVERT to 0 on Stoney
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend && blend->dual_src_blend &&
269 sctx->ps_shader.cso &&
270 (sctx->ps_shader.cso->ps_colors_written & 0x3) != 0x3)
271 mask = 0;
272
273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
274 }
275
276 /*
277 * Blender functions
278 */
279
280 static uint32_t si_translate_blend_function(int blend_func)
281 {
282 switch (blend_func) {
283 case PIPE_BLEND_ADD:
284 return V_028780_COMB_DST_PLUS_SRC;
285 case PIPE_BLEND_SUBTRACT:
286 return V_028780_COMB_SRC_MINUS_DST;
287 case PIPE_BLEND_REVERSE_SUBTRACT:
288 return V_028780_COMB_DST_MINUS_SRC;
289 case PIPE_BLEND_MIN:
290 return V_028780_COMB_MIN_DST_SRC;
291 case PIPE_BLEND_MAX:
292 return V_028780_COMB_MAX_DST_SRC;
293 default:
294 R600_ERR("Unknown blend function %d\n", blend_func);
295 assert(0);
296 break;
297 }
298 return 0;
299 }
300
301 static uint32_t si_translate_blend_factor(int blend_fact)
302 {
303 switch (blend_fact) {
304 case PIPE_BLENDFACTOR_ONE:
305 return V_028780_BLEND_ONE;
306 case PIPE_BLENDFACTOR_SRC_COLOR:
307 return V_028780_BLEND_SRC_COLOR;
308 case PIPE_BLENDFACTOR_SRC_ALPHA:
309 return V_028780_BLEND_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case PIPE_BLENDFACTOR_DST_COLOR:
313 return V_028780_BLEND_DST_COLOR;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE;
316 case PIPE_BLENDFACTOR_CONST_COLOR:
317 return V_028780_BLEND_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_CONST_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_ZERO:
321 return V_028780_BLEND_ZERO;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
334 case PIPE_BLENDFACTOR_SRC1_COLOR:
335 return V_028780_BLEND_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA:
337 return V_028780_BLEND_SRC1_ALPHA;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
339 return V_028780_BLEND_INV_SRC1_COLOR;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
341 return V_028780_BLEND_INV_SRC1_ALPHA;
342 default:
343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
344 assert(0);
345 break;
346 }
347 return 0;
348 }
349
350 static void *si_create_blend_state_mode(struct pipe_context *ctx,
351 const struct pipe_blend_state *state,
352 unsigned mode)
353 {
354 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
355 struct si_pm4_state *pm4 = &blend->pm4;
356
357 uint32_t color_control = 0;
358
359 if (blend == NULL)
360 return NULL;
361
362 blend->alpha_to_one = state->alpha_to_one;
363 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
364
365 if (state->logicop_enable) {
366 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
367 } else {
368 color_control |= S_028808_ROP3(0xcc);
369 }
370
371 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
372 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
373 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
374 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
375 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
376 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
377
378 blend->cb_target_mask = 0;
379 for (int i = 0; i < 8; i++) {
380 /* state->rt entries > 0 only written if independent blending */
381 const int j = state->independent_blend_enable ? i : 0;
382
383 unsigned eqRGB = state->rt[j].rgb_func;
384 unsigned srcRGB = state->rt[j].rgb_src_factor;
385 unsigned dstRGB = state->rt[j].rgb_dst_factor;
386 unsigned eqA = state->rt[j].alpha_func;
387 unsigned srcA = state->rt[j].alpha_src_factor;
388 unsigned dstA = state->rt[j].alpha_dst_factor;
389
390 unsigned blend_cntl = 0;
391
392 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
393 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
394
395 if (!state->rt[j].blend_enable) {
396 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
397 continue;
398 }
399
400 blend_cntl |= S_028780_ENABLE(1);
401 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
402 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
403 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
404
405 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
406 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
407 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
408 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
409 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
410 }
411 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
412 }
413
414 if (blend->cb_target_mask) {
415 color_control |= S_028808_MODE(mode);
416 } else {
417 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
418 }
419 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
420
421 return blend;
422 }
423
424 static void *si_create_blend_state(struct pipe_context *ctx,
425 const struct pipe_blend_state *state)
426 {
427 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
428 }
429
430 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
431 {
432 struct si_context *sctx = (struct si_context *)ctx;
433 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
434 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
435 }
436
437 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
438 {
439 struct si_context *sctx = (struct si_context *)ctx;
440 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
441 }
442
443 static void si_set_blend_color(struct pipe_context *ctx,
444 const struct pipe_blend_color *state)
445 {
446 struct si_context *sctx = (struct si_context *)ctx;
447
448 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
449 return;
450
451 sctx->blend_color.state = *state;
452 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
453 }
454
455 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
456 {
457 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
458
459 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
460 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
461 }
462
463 /*
464 * Clipping, scissors and viewport
465 */
466
467 static void si_set_clip_state(struct pipe_context *ctx,
468 const struct pipe_clip_state *state)
469 {
470 struct si_context *sctx = (struct si_context *)ctx;
471 struct pipe_constant_buffer cb;
472
473 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
474 return;
475
476 sctx->clip_state.state = *state;
477 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
478
479 cb.buffer = NULL;
480 cb.user_buffer = state->ucp;
481 cb.buffer_offset = 0;
482 cb.buffer_size = 4*4*8;
483 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
484 pipe_resource_reference(&cb.buffer, NULL);
485 }
486
487 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
488 {
489 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
490
491 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
492 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
493 }
494
495 #define SIX_BITS 0x3F
496
497 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
498 {
499 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
500 struct tgsi_shader_info *info = si_get_vs_info(sctx);
501 unsigned window_space =
502 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
503 unsigned clipdist_mask =
504 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
505
506 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
507 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
508 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
509 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
510 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
511 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
512 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
513 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
514 info->writes_edgeflag ||
515 info->writes_layer ||
516 info->writes_viewport_index) |
517 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
518 (sctx->queued.named.rasterizer->clip_plane_enable &
519 clipdist_mask));
520 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
521 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
522 (clipdist_mask ? 0 :
523 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
524 S_028810_CLIP_DISABLE(window_space));
525 }
526
527 static void si_set_scissor_states(struct pipe_context *ctx,
528 unsigned start_slot,
529 unsigned num_scissors,
530 const struct pipe_scissor_state *state)
531 {
532 struct si_context *sctx = (struct si_context *)ctx;
533 int i;
534
535 for (i = 0; i < num_scissors; i++)
536 sctx->scissors.states[start_slot + i] = state[i];
537
538 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
539 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
540 }
541
542 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
543 {
544 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
545 struct pipe_scissor_state *states = sctx->scissors.states;
546 unsigned mask = sctx->scissors.dirty_mask;
547
548 /* The simple case: Only 1 viewport is active. */
549 if (mask & 1 &&
550 !si_get_vs_info(sctx)->writes_viewport_index) {
551 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
552 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
553 S_028250_TL_Y(states[0].miny) |
554 S_028250_WINDOW_OFFSET_DISABLE(1));
555 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
556 S_028254_BR_Y(states[0].maxy));
557 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
558 return;
559 }
560
561 while (mask) {
562 int start, count, i;
563
564 u_bit_scan_consecutive_range(&mask, &start, &count);
565
566 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
567 start * 4 * 2, count * 2);
568 for (i = start; i < start+count; i++) {
569 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
570 S_028250_TL_Y(states[i].miny) |
571 S_028250_WINDOW_OFFSET_DISABLE(1));
572 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
573 S_028254_BR_Y(states[i].maxy));
574 }
575 }
576 sctx->scissors.dirty_mask = 0;
577 }
578
579 static void si_set_viewport_states(struct pipe_context *ctx,
580 unsigned start_slot,
581 unsigned num_viewports,
582 const struct pipe_viewport_state *state)
583 {
584 struct si_context *sctx = (struct si_context *)ctx;
585 int i;
586
587 for (i = 0; i < num_viewports; i++)
588 sctx->viewports.states[start_slot + i] = state[i];
589
590 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
591 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
592 }
593
594 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
595 {
596 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
597 struct pipe_viewport_state *states = sctx->viewports.states;
598 unsigned mask = sctx->viewports.dirty_mask;
599
600 /* The simple case: Only 1 viewport is active. */
601 if (mask & 1 &&
602 !si_get_vs_info(sctx)->writes_viewport_index) {
603 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
604 radeon_emit(cs, fui(states[0].scale[0]));
605 radeon_emit(cs, fui(states[0].translate[0]));
606 radeon_emit(cs, fui(states[0].scale[1]));
607 radeon_emit(cs, fui(states[0].translate[1]));
608 radeon_emit(cs, fui(states[0].scale[2]));
609 radeon_emit(cs, fui(states[0].translate[2]));
610 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
611 return;
612 }
613
614 while (mask) {
615 int start, count, i;
616
617 u_bit_scan_consecutive_range(&mask, &start, &count);
618
619 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
620 start * 4 * 6, count * 6);
621 for (i = start; i < start+count; i++) {
622 radeon_emit(cs, fui(states[i].scale[0]));
623 radeon_emit(cs, fui(states[i].translate[0]));
624 radeon_emit(cs, fui(states[i].scale[1]));
625 radeon_emit(cs, fui(states[i].translate[1]));
626 radeon_emit(cs, fui(states[i].scale[2]));
627 radeon_emit(cs, fui(states[i].translate[2]));
628 }
629 }
630 sctx->viewports.dirty_mask = 0;
631 }
632
633 /*
634 * inferred state between framebuffer and rasterizer
635 */
636 static void si_update_poly_offset_state(struct si_context *sctx)
637 {
638 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
639
640 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
641 return;
642
643 switch (sctx->framebuffer.state.zsbuf->texture->format) {
644 case PIPE_FORMAT_Z16_UNORM:
645 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
646 break;
647 default: /* 24-bit */
648 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
649 break;
650 case PIPE_FORMAT_Z32_FLOAT:
651 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
652 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
653 break;
654 }
655 }
656
657 /*
658 * Rasterizer
659 */
660
661 static uint32_t si_translate_fill(uint32_t func)
662 {
663 switch(func) {
664 case PIPE_POLYGON_MODE_FILL:
665 return V_028814_X_DRAW_TRIANGLES;
666 case PIPE_POLYGON_MODE_LINE:
667 return V_028814_X_DRAW_LINES;
668 case PIPE_POLYGON_MODE_POINT:
669 return V_028814_X_DRAW_POINTS;
670 default:
671 assert(0);
672 return V_028814_X_DRAW_POINTS;
673 }
674 }
675
676 static void *si_create_rs_state(struct pipe_context *ctx,
677 const struct pipe_rasterizer_state *state)
678 {
679 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
680 struct si_pm4_state *pm4 = &rs->pm4;
681 unsigned tmp, i;
682 float psize_min, psize_max;
683
684 if (rs == NULL) {
685 return NULL;
686 }
687
688 rs->two_side = state->light_twoside;
689 rs->multisample_enable = state->multisample;
690 rs->force_persample_interp = state->force_persample_interp;
691 rs->clip_plane_enable = state->clip_plane_enable;
692 rs->line_stipple_enable = state->line_stipple_enable;
693 rs->poly_stipple_enable = state->poly_stipple_enable;
694 rs->line_smooth = state->line_smooth;
695 rs->poly_smooth = state->poly_smooth;
696 rs->uses_poly_offset = state->offset_point || state->offset_line ||
697 state->offset_tri;
698 rs->clamp_fragment_color = state->clamp_fragment_color;
699 rs->flatshade = state->flatshade;
700 rs->sprite_coord_enable = state->sprite_coord_enable;
701 rs->rasterizer_discard = state->rasterizer_discard;
702 rs->pa_sc_line_stipple = state->line_stipple_enable ?
703 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
704 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
705 rs->pa_cl_clip_cntl =
706 S_028810_PS_UCP_MODE(3) |
707 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
708 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
709 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
710 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
711 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
712
713 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
714 S_0286D4_FLAT_SHADE_ENA(1) |
715 S_0286D4_PNT_SPRITE_ENA(1) |
716 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
717 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
718 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
719 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
720 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
721
722 /* point size 12.4 fixed point */
723 tmp = (unsigned)(state->point_size * 8.0);
724 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
725
726 if (state->point_size_per_vertex) {
727 psize_min = util_get_min_point_size(state);
728 psize_max = 8192;
729 } else {
730 /* Force the point size to be as if the vertex output was disabled. */
731 psize_min = state->point_size;
732 psize_max = state->point_size;
733 }
734 /* Divide by two, because 0.5 = 1 pixel. */
735 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
736 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
737 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
738
739 tmp = (unsigned)state->line_width * 8;
740 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
741 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
742 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
743 S_028A48_MSAA_ENABLE(state->multisample ||
744 state->poly_smooth ||
745 state->line_smooth) |
746 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
747
748 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
749 S_028BE4_PIX_CENTER(state->half_pixel_center) |
750 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
751
752 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
753 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
754 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
755 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
756 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
757 S_028814_FACE(!state->front_ccw) |
758 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
759 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
760 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
761 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
762 state->fill_back != PIPE_POLYGON_MODE_FILL) |
763 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
764 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
765 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
766 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
767
768 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
769 for (i = 0; i < 3; i++) {
770 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
771 float offset_units = state->offset_units;
772 float offset_scale = state->offset_scale * 16.0f;
773
774 switch (i) {
775 case 0: /* 16-bit zbuffer */
776 offset_units *= 4.0f;
777 break;
778 case 1: /* 24-bit zbuffer */
779 offset_units *= 2.0f;
780 break;
781 case 2: /* 32-bit zbuffer */
782 offset_units *= 1.0f;
783 break;
784 }
785
786 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
787 fui(offset_scale));
788 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
789 fui(offset_units));
790 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
791 fui(offset_scale));
792 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
793 fui(offset_units));
794 }
795
796 return rs;
797 }
798
799 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
800 {
801 struct si_context *sctx = (struct si_context *)ctx;
802 struct si_state_rasterizer *old_rs =
803 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
804 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
805
806 if (state == NULL)
807 return;
808
809 if (sctx->framebuffer.nr_samples > 1 &&
810 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
811 si_mark_atom_dirty(sctx, &sctx->db_render_state);
812
813 si_pm4_bind_state(sctx, rasterizer, rs);
814 si_update_poly_offset_state(sctx);
815
816 si_mark_atom_dirty(sctx, &sctx->clip_regs);
817 }
818
819 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
820 {
821 struct si_context *sctx = (struct si_context *)ctx;
822
823 if (sctx->queued.named.rasterizer == state)
824 si_pm4_bind_state(sctx, poly_offset, NULL);
825 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
826 }
827
828 /*
829 * infeered state between dsa and stencil ref
830 */
831 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
832 {
833 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
834 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
835 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
836
837 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
838 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
839 S_028430_STENCILMASK(dsa->valuemask[0]) |
840 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
841 S_028430_STENCILOPVAL(1));
842 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
843 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
844 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
845 S_028434_STENCILOPVAL_BF(1));
846 }
847
848 static void si_set_stencil_ref(struct pipe_context *ctx,
849 const struct pipe_stencil_ref *state)
850 {
851 struct si_context *sctx = (struct si_context *)ctx;
852
853 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
854 return;
855
856 sctx->stencil_ref.state = *state;
857 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
858 }
859
860
861 /*
862 * DSA
863 */
864
865 static uint32_t si_translate_stencil_op(int s_op)
866 {
867 switch (s_op) {
868 case PIPE_STENCIL_OP_KEEP:
869 return V_02842C_STENCIL_KEEP;
870 case PIPE_STENCIL_OP_ZERO:
871 return V_02842C_STENCIL_ZERO;
872 case PIPE_STENCIL_OP_REPLACE:
873 return V_02842C_STENCIL_REPLACE_TEST;
874 case PIPE_STENCIL_OP_INCR:
875 return V_02842C_STENCIL_ADD_CLAMP;
876 case PIPE_STENCIL_OP_DECR:
877 return V_02842C_STENCIL_SUB_CLAMP;
878 case PIPE_STENCIL_OP_INCR_WRAP:
879 return V_02842C_STENCIL_ADD_WRAP;
880 case PIPE_STENCIL_OP_DECR_WRAP:
881 return V_02842C_STENCIL_SUB_WRAP;
882 case PIPE_STENCIL_OP_INVERT:
883 return V_02842C_STENCIL_INVERT;
884 default:
885 R600_ERR("Unknown stencil op %d", s_op);
886 assert(0);
887 break;
888 }
889 return 0;
890 }
891
892 static void *si_create_dsa_state(struct pipe_context *ctx,
893 const struct pipe_depth_stencil_alpha_state *state)
894 {
895 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
896 struct si_pm4_state *pm4 = &dsa->pm4;
897 unsigned db_depth_control;
898 uint32_t db_stencil_control = 0;
899
900 if (dsa == NULL) {
901 return NULL;
902 }
903
904 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
905 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
906 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
907 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
908
909 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
910 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
911 S_028800_ZFUNC(state->depth.func) |
912 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
913
914 /* stencil */
915 if (state->stencil[0].enabled) {
916 db_depth_control |= S_028800_STENCIL_ENABLE(1);
917 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
918 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
919 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
920 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
921
922 if (state->stencil[1].enabled) {
923 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
924 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
925 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
926 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
927 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
928 }
929 }
930
931 /* alpha */
932 if (state->alpha.enabled) {
933 dsa->alpha_func = state->alpha.func;
934
935 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
936 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
937 } else {
938 dsa->alpha_func = PIPE_FUNC_ALWAYS;
939 }
940
941 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
942 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
943 if (state->depth.bounds_test) {
944 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
945 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
946 }
947
948 return dsa;
949 }
950
951 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
952 {
953 struct si_context *sctx = (struct si_context *)ctx;
954 struct si_state_dsa *dsa = state;
955
956 if (state == NULL)
957 return;
958
959 si_pm4_bind_state(sctx, dsa, dsa);
960
961 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
962 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
963 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
964 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
965 }
966 }
967
968 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
969 {
970 struct si_context *sctx = (struct si_context *)ctx;
971 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
972 }
973
974 static void *si_create_db_flush_dsa(struct si_context *sctx)
975 {
976 struct pipe_depth_stencil_alpha_state dsa = {};
977
978 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
979 }
980
981 /* DB RENDER STATE */
982
983 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
984 {
985 struct si_context *sctx = (struct si_context*)ctx;
986
987 si_mark_atom_dirty(sctx, &sctx->db_render_state);
988 }
989
990 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
991 {
992 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
993 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
994 unsigned db_shader_control;
995
996 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
997
998 /* DB_RENDER_CONTROL */
999 if (sctx->dbcb_depth_copy_enabled ||
1000 sctx->dbcb_stencil_copy_enabled) {
1001 radeon_emit(cs,
1002 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1003 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1004 S_028000_COPY_CENTROID(1) |
1005 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1006 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1007 radeon_emit(cs,
1008 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1009 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1010 } else if (sctx->db_depth_clear) {
1011 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1012 } else {
1013 radeon_emit(cs, 0);
1014 }
1015
1016 /* DB_COUNT_CONTROL (occlusion queries) */
1017 if (sctx->b.num_occlusion_queries > 0) {
1018 if (sctx->b.chip_class >= CIK) {
1019 radeon_emit(cs,
1020 S_028004_PERFECT_ZPASS_COUNTS(1) |
1021 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1022 S_028004_ZPASS_ENABLE(1) |
1023 S_028004_SLICE_EVEN_ENABLE(1) |
1024 S_028004_SLICE_ODD_ENABLE(1));
1025 } else {
1026 radeon_emit(cs,
1027 S_028004_PERFECT_ZPASS_COUNTS(1) |
1028 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1029 }
1030 } else {
1031 /* Disable occlusion queries. */
1032 if (sctx->b.chip_class >= CIK) {
1033 radeon_emit(cs, 0);
1034 } else {
1035 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1036 }
1037 }
1038
1039 /* DB_RENDER_OVERRIDE2 */
1040 if (sctx->db_depth_disable_expclear) {
1041 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1042 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1043 } else {
1044 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1045 }
1046
1047 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1048 sctx->ps_db_shader_control;
1049
1050 /* Bug workaround for smoothing (overrasterization) on SI. */
1051 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1052 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1053 else
1054 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1055
1056 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1057 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1058 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1059
1060 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1061 db_shader_control);
1062 }
1063
1064 /*
1065 * format translation
1066 */
1067 static uint32_t si_translate_colorformat(enum pipe_format format)
1068 {
1069 const struct util_format_description *desc = util_format_description(format);
1070
1071 #define HAS_SIZE(x,y,z,w) \
1072 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1073 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1074
1075 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1076 return V_028C70_COLOR_10_11_11;
1077
1078 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1079 return V_028C70_COLOR_INVALID;
1080
1081 switch (desc->nr_channels) {
1082 case 1:
1083 switch (desc->channel[0].size) {
1084 case 8:
1085 return V_028C70_COLOR_8;
1086 case 16:
1087 return V_028C70_COLOR_16;
1088 case 32:
1089 return V_028C70_COLOR_32;
1090 }
1091 break;
1092 case 2:
1093 if (desc->channel[0].size == desc->channel[1].size) {
1094 switch (desc->channel[0].size) {
1095 case 8:
1096 return V_028C70_COLOR_8_8;
1097 case 16:
1098 return V_028C70_COLOR_16_16;
1099 case 32:
1100 return V_028C70_COLOR_32_32;
1101 }
1102 } else if (HAS_SIZE(8,24,0,0)) {
1103 return V_028C70_COLOR_24_8;
1104 } else if (HAS_SIZE(24,8,0,0)) {
1105 return V_028C70_COLOR_8_24;
1106 }
1107 break;
1108 case 3:
1109 if (HAS_SIZE(5,6,5,0)) {
1110 return V_028C70_COLOR_5_6_5;
1111 } else if (HAS_SIZE(32,8,24,0)) {
1112 return V_028C70_COLOR_X24_8_32_FLOAT;
1113 }
1114 break;
1115 case 4:
1116 if (desc->channel[0].size == desc->channel[1].size &&
1117 desc->channel[0].size == desc->channel[2].size &&
1118 desc->channel[0].size == desc->channel[3].size) {
1119 switch (desc->channel[0].size) {
1120 case 4:
1121 return V_028C70_COLOR_4_4_4_4;
1122 case 8:
1123 return V_028C70_COLOR_8_8_8_8;
1124 case 16:
1125 return V_028C70_COLOR_16_16_16_16;
1126 case 32:
1127 return V_028C70_COLOR_32_32_32_32;
1128 }
1129 } else if (HAS_SIZE(5,5,5,1)) {
1130 return V_028C70_COLOR_1_5_5_5;
1131 } else if (HAS_SIZE(10,10,10,2)) {
1132 return V_028C70_COLOR_2_10_10_10;
1133 }
1134 break;
1135 }
1136 return V_028C70_COLOR_INVALID;
1137 }
1138
1139 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1140 {
1141 if (SI_BIG_ENDIAN) {
1142 switch(colorformat) {
1143 /* 8-bit buffers. */
1144 case V_028C70_COLOR_8:
1145 return V_028C70_ENDIAN_NONE;
1146
1147 /* 16-bit buffers. */
1148 case V_028C70_COLOR_5_6_5:
1149 case V_028C70_COLOR_1_5_5_5:
1150 case V_028C70_COLOR_4_4_4_4:
1151 case V_028C70_COLOR_16:
1152 case V_028C70_COLOR_8_8:
1153 return V_028C70_ENDIAN_8IN16;
1154
1155 /* 32-bit buffers. */
1156 case V_028C70_COLOR_8_8_8_8:
1157 case V_028C70_COLOR_2_10_10_10:
1158 case V_028C70_COLOR_8_24:
1159 case V_028C70_COLOR_24_8:
1160 case V_028C70_COLOR_16_16:
1161 return V_028C70_ENDIAN_8IN32;
1162
1163 /* 64-bit buffers. */
1164 case V_028C70_COLOR_16_16_16_16:
1165 return V_028C70_ENDIAN_8IN16;
1166
1167 case V_028C70_COLOR_32_32:
1168 return V_028C70_ENDIAN_8IN32;
1169
1170 /* 128-bit buffers. */
1171 case V_028C70_COLOR_32_32_32_32:
1172 return V_028C70_ENDIAN_8IN32;
1173 default:
1174 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1175 }
1176 } else {
1177 return V_028C70_ENDIAN_NONE;
1178 }
1179 }
1180
1181 /* Returns the size in bits of the widest component of a CB format */
1182 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1183 {
1184 switch(colorformat) {
1185 case V_028C70_COLOR_4_4_4_4:
1186 return 4;
1187
1188 case V_028C70_COLOR_1_5_5_5:
1189 case V_028C70_COLOR_5_5_5_1:
1190 return 5;
1191
1192 case V_028C70_COLOR_5_6_5:
1193 return 6;
1194
1195 case V_028C70_COLOR_8:
1196 case V_028C70_COLOR_8_8:
1197 case V_028C70_COLOR_8_8_8_8:
1198 return 8;
1199
1200 case V_028C70_COLOR_10_10_10_2:
1201 case V_028C70_COLOR_2_10_10_10:
1202 return 10;
1203
1204 case V_028C70_COLOR_10_11_11:
1205 case V_028C70_COLOR_11_11_10:
1206 return 11;
1207
1208 case V_028C70_COLOR_16:
1209 case V_028C70_COLOR_16_16:
1210 case V_028C70_COLOR_16_16_16_16:
1211 return 16;
1212
1213 case V_028C70_COLOR_8_24:
1214 case V_028C70_COLOR_24_8:
1215 return 24;
1216
1217 case V_028C70_COLOR_32:
1218 case V_028C70_COLOR_32_32:
1219 case V_028C70_COLOR_32_32_32_32:
1220 case V_028C70_COLOR_X24_8_32_FLOAT:
1221 return 32;
1222 }
1223
1224 assert(!"Unknown maximum component size");
1225 return 0;
1226 }
1227
1228 static uint32_t si_translate_dbformat(enum pipe_format format)
1229 {
1230 switch (format) {
1231 case PIPE_FORMAT_Z16_UNORM:
1232 return V_028040_Z_16;
1233 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1234 case PIPE_FORMAT_X8Z24_UNORM:
1235 case PIPE_FORMAT_Z24X8_UNORM:
1236 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1237 return V_028040_Z_24; /* deprecated on SI */
1238 case PIPE_FORMAT_Z32_FLOAT:
1239 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1240 return V_028040_Z_32_FLOAT;
1241 default:
1242 return V_028040_Z_INVALID;
1243 }
1244 }
1245
1246 /*
1247 * Texture translation
1248 */
1249
1250 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1251 enum pipe_format format,
1252 const struct util_format_description *desc,
1253 int first_non_void)
1254 {
1255 struct si_screen *sscreen = (struct si_screen*)screen;
1256 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1257 sscreen->b.info.drm_minor >= 31) ||
1258 sscreen->b.info.drm_major == 3;
1259 boolean uniform = TRUE;
1260 int i;
1261
1262 /* Colorspace (return non-RGB formats directly). */
1263 switch (desc->colorspace) {
1264 /* Depth stencil formats */
1265 case UTIL_FORMAT_COLORSPACE_ZS:
1266 switch (format) {
1267 case PIPE_FORMAT_Z16_UNORM:
1268 return V_008F14_IMG_DATA_FORMAT_16;
1269 case PIPE_FORMAT_X24S8_UINT:
1270 case PIPE_FORMAT_Z24X8_UNORM:
1271 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1272 return V_008F14_IMG_DATA_FORMAT_8_24;
1273 case PIPE_FORMAT_X8Z24_UNORM:
1274 case PIPE_FORMAT_S8X24_UINT:
1275 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1276 return V_008F14_IMG_DATA_FORMAT_24_8;
1277 case PIPE_FORMAT_S8_UINT:
1278 return V_008F14_IMG_DATA_FORMAT_8;
1279 case PIPE_FORMAT_Z32_FLOAT:
1280 return V_008F14_IMG_DATA_FORMAT_32;
1281 case PIPE_FORMAT_X32_S8X24_UINT:
1282 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1283 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1284 default:
1285 goto out_unknown;
1286 }
1287
1288 case UTIL_FORMAT_COLORSPACE_YUV:
1289 goto out_unknown; /* TODO */
1290
1291 case UTIL_FORMAT_COLORSPACE_SRGB:
1292 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1293 goto out_unknown;
1294 break;
1295
1296 default:
1297 break;
1298 }
1299
1300 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1301 if (!enable_compressed_formats)
1302 goto out_unknown;
1303
1304 switch (format) {
1305 case PIPE_FORMAT_RGTC1_SNORM:
1306 case PIPE_FORMAT_LATC1_SNORM:
1307 case PIPE_FORMAT_RGTC1_UNORM:
1308 case PIPE_FORMAT_LATC1_UNORM:
1309 return V_008F14_IMG_DATA_FORMAT_BC4;
1310 case PIPE_FORMAT_RGTC2_SNORM:
1311 case PIPE_FORMAT_LATC2_SNORM:
1312 case PIPE_FORMAT_RGTC2_UNORM:
1313 case PIPE_FORMAT_LATC2_UNORM:
1314 return V_008F14_IMG_DATA_FORMAT_BC5;
1315 default:
1316 goto out_unknown;
1317 }
1318 }
1319
1320 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1321 if (!enable_compressed_formats)
1322 goto out_unknown;
1323
1324 switch (format) {
1325 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1326 case PIPE_FORMAT_BPTC_SRGBA:
1327 return V_008F14_IMG_DATA_FORMAT_BC7;
1328 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1329 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1330 return V_008F14_IMG_DATA_FORMAT_BC6;
1331 default:
1332 goto out_unknown;
1333 }
1334 }
1335
1336 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1337 switch (format) {
1338 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1339 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1340 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1341 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1342 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1343 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1344 default:
1345 goto out_unknown;
1346 }
1347 }
1348
1349 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1350 if (!enable_compressed_formats)
1351 goto out_unknown;
1352
1353 if (!util_format_s3tc_enabled) {
1354 goto out_unknown;
1355 }
1356
1357 switch (format) {
1358 case PIPE_FORMAT_DXT1_RGB:
1359 case PIPE_FORMAT_DXT1_RGBA:
1360 case PIPE_FORMAT_DXT1_SRGB:
1361 case PIPE_FORMAT_DXT1_SRGBA:
1362 return V_008F14_IMG_DATA_FORMAT_BC1;
1363 case PIPE_FORMAT_DXT3_RGBA:
1364 case PIPE_FORMAT_DXT3_SRGBA:
1365 return V_008F14_IMG_DATA_FORMAT_BC2;
1366 case PIPE_FORMAT_DXT5_RGBA:
1367 case PIPE_FORMAT_DXT5_SRGBA:
1368 return V_008F14_IMG_DATA_FORMAT_BC3;
1369 default:
1370 goto out_unknown;
1371 }
1372 }
1373
1374 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1375 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1376 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1377 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1378 }
1379
1380 /* R8G8Bx_SNORM - TODO CxV8U8 */
1381
1382 /* See whether the components are of the same size. */
1383 for (i = 1; i < desc->nr_channels; i++) {
1384 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1385 }
1386
1387 /* Non-uniform formats. */
1388 if (!uniform) {
1389 switch(desc->nr_channels) {
1390 case 3:
1391 if (desc->channel[0].size == 5 &&
1392 desc->channel[1].size == 6 &&
1393 desc->channel[2].size == 5) {
1394 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1395 }
1396 goto out_unknown;
1397 case 4:
1398 if (desc->channel[0].size == 5 &&
1399 desc->channel[1].size == 5 &&
1400 desc->channel[2].size == 5 &&
1401 desc->channel[3].size == 1) {
1402 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1403 }
1404 if (desc->channel[0].size == 10 &&
1405 desc->channel[1].size == 10 &&
1406 desc->channel[2].size == 10 &&
1407 desc->channel[3].size == 2) {
1408 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1409 }
1410 goto out_unknown;
1411 }
1412 goto out_unknown;
1413 }
1414
1415 if (first_non_void < 0 || first_non_void > 3)
1416 goto out_unknown;
1417
1418 /* uniform formats */
1419 switch (desc->channel[first_non_void].size) {
1420 case 4:
1421 switch (desc->nr_channels) {
1422 #if 0 /* Not supported for render targets */
1423 case 2:
1424 return V_008F14_IMG_DATA_FORMAT_4_4;
1425 #endif
1426 case 4:
1427 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1428 }
1429 break;
1430 case 8:
1431 switch (desc->nr_channels) {
1432 case 1:
1433 return V_008F14_IMG_DATA_FORMAT_8;
1434 case 2:
1435 return V_008F14_IMG_DATA_FORMAT_8_8;
1436 case 4:
1437 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1438 }
1439 break;
1440 case 16:
1441 switch (desc->nr_channels) {
1442 case 1:
1443 return V_008F14_IMG_DATA_FORMAT_16;
1444 case 2:
1445 return V_008F14_IMG_DATA_FORMAT_16_16;
1446 case 4:
1447 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1448 }
1449 break;
1450 case 32:
1451 switch (desc->nr_channels) {
1452 case 1:
1453 return V_008F14_IMG_DATA_FORMAT_32;
1454 case 2:
1455 return V_008F14_IMG_DATA_FORMAT_32_32;
1456 #if 0 /* Not supported for render targets */
1457 case 3:
1458 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1459 #endif
1460 case 4:
1461 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1462 }
1463 }
1464
1465 out_unknown:
1466 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1467 return ~0;
1468 }
1469
1470 static unsigned si_tex_wrap(unsigned wrap)
1471 {
1472 switch (wrap) {
1473 default:
1474 case PIPE_TEX_WRAP_REPEAT:
1475 return V_008F30_SQ_TEX_WRAP;
1476 case PIPE_TEX_WRAP_CLAMP:
1477 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1478 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1479 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1480 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1481 return V_008F30_SQ_TEX_CLAMP_BORDER;
1482 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1483 return V_008F30_SQ_TEX_MIRROR;
1484 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1485 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1486 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1487 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1488 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1489 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1490 }
1491 }
1492
1493 static unsigned si_tex_filter(unsigned filter)
1494 {
1495 switch (filter) {
1496 default:
1497 case PIPE_TEX_FILTER_NEAREST:
1498 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1499 case PIPE_TEX_FILTER_LINEAR:
1500 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1501 }
1502 }
1503
1504 static unsigned si_tex_mipfilter(unsigned filter)
1505 {
1506 switch (filter) {
1507 case PIPE_TEX_MIPFILTER_NEAREST:
1508 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1509 case PIPE_TEX_MIPFILTER_LINEAR:
1510 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1511 default:
1512 case PIPE_TEX_MIPFILTER_NONE:
1513 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1514 }
1515 }
1516
1517 static unsigned si_tex_compare(unsigned compare)
1518 {
1519 switch (compare) {
1520 default:
1521 case PIPE_FUNC_NEVER:
1522 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1523 case PIPE_FUNC_LESS:
1524 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1525 case PIPE_FUNC_EQUAL:
1526 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1527 case PIPE_FUNC_LEQUAL:
1528 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1529 case PIPE_FUNC_GREATER:
1530 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1531 case PIPE_FUNC_NOTEQUAL:
1532 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1533 case PIPE_FUNC_GEQUAL:
1534 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1535 case PIPE_FUNC_ALWAYS:
1536 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1537 }
1538 }
1539
1540 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1541 unsigned nr_samples)
1542 {
1543 if (view_target == PIPE_TEXTURE_CUBE ||
1544 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1545 res_target = view_target;
1546
1547 switch (res_target) {
1548 default:
1549 case PIPE_TEXTURE_1D:
1550 return V_008F1C_SQ_RSRC_IMG_1D;
1551 case PIPE_TEXTURE_1D_ARRAY:
1552 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1553 case PIPE_TEXTURE_2D:
1554 case PIPE_TEXTURE_RECT:
1555 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1556 V_008F1C_SQ_RSRC_IMG_2D;
1557 case PIPE_TEXTURE_2D_ARRAY:
1558 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1559 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1560 case PIPE_TEXTURE_3D:
1561 return V_008F1C_SQ_RSRC_IMG_3D;
1562 case PIPE_TEXTURE_CUBE:
1563 case PIPE_TEXTURE_CUBE_ARRAY:
1564 return V_008F1C_SQ_RSRC_IMG_CUBE;
1565 }
1566 }
1567
1568 /*
1569 * Format support testing
1570 */
1571
1572 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1573 {
1574 return si_translate_texformat(screen, format, util_format_description(format),
1575 util_format_get_first_non_void_channel(format)) != ~0U;
1576 }
1577
1578 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1579 const struct util_format_description *desc,
1580 int first_non_void)
1581 {
1582 unsigned type = desc->channel[first_non_void].type;
1583 int i;
1584
1585 if (type == UTIL_FORMAT_TYPE_FIXED)
1586 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1587
1588 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1589 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1590
1591 if (desc->nr_channels == 4 &&
1592 desc->channel[0].size == 10 &&
1593 desc->channel[1].size == 10 &&
1594 desc->channel[2].size == 10 &&
1595 desc->channel[3].size == 2)
1596 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1597
1598 /* See whether the components are of the same size. */
1599 for (i = 0; i < desc->nr_channels; i++) {
1600 if (desc->channel[first_non_void].size != desc->channel[i].size)
1601 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1602 }
1603
1604 switch (desc->channel[first_non_void].size) {
1605 case 8:
1606 switch (desc->nr_channels) {
1607 case 1:
1608 return V_008F0C_BUF_DATA_FORMAT_8;
1609 case 2:
1610 return V_008F0C_BUF_DATA_FORMAT_8_8;
1611 case 3:
1612 case 4:
1613 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1614 }
1615 break;
1616 case 16:
1617 switch (desc->nr_channels) {
1618 case 1:
1619 return V_008F0C_BUF_DATA_FORMAT_16;
1620 case 2:
1621 return V_008F0C_BUF_DATA_FORMAT_16_16;
1622 case 3:
1623 case 4:
1624 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1625 }
1626 break;
1627 case 32:
1628 /* From the Southern Islands ISA documentation about MTBUF:
1629 * 'Memory reads of data in memory that is 32 or 64 bits do not
1630 * undergo any format conversion.'
1631 */
1632 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1633 !desc->channel[first_non_void].pure_integer)
1634 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1635
1636 switch (desc->nr_channels) {
1637 case 1:
1638 return V_008F0C_BUF_DATA_FORMAT_32;
1639 case 2:
1640 return V_008F0C_BUF_DATA_FORMAT_32_32;
1641 case 3:
1642 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1643 case 4:
1644 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1645 }
1646 break;
1647 }
1648
1649 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1650 }
1651
1652 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1653 const struct util_format_description *desc,
1654 int first_non_void)
1655 {
1656 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1657 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1658
1659 switch (desc->channel[first_non_void].type) {
1660 case UTIL_FORMAT_TYPE_SIGNED:
1661 if (desc->channel[first_non_void].normalized)
1662 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1663 else if (desc->channel[first_non_void].pure_integer)
1664 return V_008F0C_BUF_NUM_FORMAT_SINT;
1665 else
1666 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1667 break;
1668 case UTIL_FORMAT_TYPE_UNSIGNED:
1669 if (desc->channel[first_non_void].normalized)
1670 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1671 else if (desc->channel[first_non_void].pure_integer)
1672 return V_008F0C_BUF_NUM_FORMAT_UINT;
1673 else
1674 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1675 break;
1676 case UTIL_FORMAT_TYPE_FLOAT:
1677 default:
1678 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1679 }
1680 }
1681
1682 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1683 {
1684 const struct util_format_description *desc;
1685 int first_non_void;
1686 unsigned data_format;
1687
1688 desc = util_format_description(format);
1689 first_non_void = util_format_get_first_non_void_channel(format);
1690 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1691 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1692 }
1693
1694 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1695 {
1696 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1697 r600_translate_colorswap(format) != ~0U;
1698 }
1699
1700 static bool si_is_zs_format_supported(enum pipe_format format)
1701 {
1702 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1703 }
1704
1705 boolean si_is_format_supported(struct pipe_screen *screen,
1706 enum pipe_format format,
1707 enum pipe_texture_target target,
1708 unsigned sample_count,
1709 unsigned usage)
1710 {
1711 unsigned retval = 0;
1712
1713 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1714 R600_ERR("r600: unsupported texture type %d\n", target);
1715 return FALSE;
1716 }
1717
1718 if (!util_format_is_supported(format, usage))
1719 return FALSE;
1720
1721 if (sample_count > 1) {
1722 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1723 return FALSE;
1724
1725 switch (sample_count) {
1726 case 2:
1727 case 4:
1728 case 8:
1729 break;
1730 default:
1731 return FALSE;
1732 }
1733 }
1734
1735 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1736 if (target == PIPE_BUFFER) {
1737 if (si_is_vertex_format_supported(screen, format))
1738 retval |= PIPE_BIND_SAMPLER_VIEW;
1739 } else {
1740 if (si_is_sampler_format_supported(screen, format))
1741 retval |= PIPE_BIND_SAMPLER_VIEW;
1742 }
1743 }
1744
1745 if ((usage & (PIPE_BIND_RENDER_TARGET |
1746 PIPE_BIND_DISPLAY_TARGET |
1747 PIPE_BIND_SCANOUT |
1748 PIPE_BIND_SHARED |
1749 PIPE_BIND_BLENDABLE)) &&
1750 si_is_colorbuffer_format_supported(format)) {
1751 retval |= usage &
1752 (PIPE_BIND_RENDER_TARGET |
1753 PIPE_BIND_DISPLAY_TARGET |
1754 PIPE_BIND_SCANOUT |
1755 PIPE_BIND_SHARED);
1756 if (!util_format_is_pure_integer(format) &&
1757 !util_format_is_depth_or_stencil(format))
1758 retval |= usage & PIPE_BIND_BLENDABLE;
1759 }
1760
1761 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1762 si_is_zs_format_supported(format)) {
1763 retval |= PIPE_BIND_DEPTH_STENCIL;
1764 }
1765
1766 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1767 si_is_vertex_format_supported(screen, format)) {
1768 retval |= PIPE_BIND_VERTEX_BUFFER;
1769 }
1770
1771 if (usage & PIPE_BIND_TRANSFER_READ)
1772 retval |= PIPE_BIND_TRANSFER_READ;
1773 if (usage & PIPE_BIND_TRANSFER_WRITE)
1774 retval |= PIPE_BIND_TRANSFER_WRITE;
1775
1776 return retval == usage;
1777 }
1778
1779 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1780 {
1781 unsigned tile_mode_index = 0;
1782
1783 if (stencil) {
1784 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1785 } else {
1786 tile_mode_index = rtex->surface.tiling_index[level];
1787 }
1788 return tile_mode_index;
1789 }
1790
1791 /*
1792 * framebuffer handling
1793 */
1794
1795 static void si_initialize_color_surface(struct si_context *sctx,
1796 struct r600_surface *surf)
1797 {
1798 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1799 unsigned level = surf->base.u.tex.level;
1800 uint64_t offset = rtex->surface.level[level].offset;
1801 unsigned pitch, slice;
1802 unsigned color_info, color_attrib, color_pitch, color_view;
1803 unsigned tile_mode_index;
1804 unsigned format, swap, ntype, endian;
1805 const struct util_format_description *desc;
1806 int i;
1807 unsigned blend_clamp = 0, blend_bypass = 0;
1808 unsigned max_comp_size;
1809
1810 /* Layered rendering doesn't work with LINEAR_GENERAL.
1811 * (LINEAR_ALIGNED and others work) */
1812 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1813 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1814 offset += rtex->surface.level[level].slice_size *
1815 surf->base.u.tex.first_layer;
1816 color_view = 0;
1817 } else {
1818 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1819 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1820 }
1821
1822 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1823 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1824 if (slice) {
1825 slice = slice - 1;
1826 }
1827
1828 tile_mode_index = si_tile_mode_index(rtex, level, false);
1829
1830 desc = util_format_description(surf->base.format);
1831 for (i = 0; i < 4; i++) {
1832 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1833 break;
1834 }
1835 }
1836 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1837 ntype = V_028C70_NUMBER_FLOAT;
1838 } else {
1839 ntype = V_028C70_NUMBER_UNORM;
1840 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1841 ntype = V_028C70_NUMBER_SRGB;
1842 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1843 if (desc->channel[i].pure_integer) {
1844 ntype = V_028C70_NUMBER_SINT;
1845 } else {
1846 assert(desc->channel[i].normalized);
1847 ntype = V_028C70_NUMBER_SNORM;
1848 }
1849 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1850 if (desc->channel[i].pure_integer) {
1851 ntype = V_028C70_NUMBER_UINT;
1852 } else {
1853 assert(desc->channel[i].normalized);
1854 ntype = V_028C70_NUMBER_UNORM;
1855 }
1856 }
1857 }
1858
1859 format = si_translate_colorformat(surf->base.format);
1860 if (format == V_028C70_COLOR_INVALID) {
1861 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1862 }
1863 assert(format != V_028C70_COLOR_INVALID);
1864 swap = r600_translate_colorswap(surf->base.format);
1865 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1866 endian = V_028C70_ENDIAN_NONE;
1867 } else {
1868 endian = si_colorformat_endian_swap(format);
1869 }
1870
1871 /* blend clamp should be set for all NORM/SRGB types */
1872 if (ntype == V_028C70_NUMBER_UNORM ||
1873 ntype == V_028C70_NUMBER_SNORM ||
1874 ntype == V_028C70_NUMBER_SRGB)
1875 blend_clamp = 1;
1876
1877 /* set blend bypass according to docs if SINT/UINT or
1878 8/24 COLOR variants */
1879 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1880 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1881 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1882 blend_clamp = 0;
1883 blend_bypass = 1;
1884 }
1885
1886 color_info = S_028C70_FORMAT(format) |
1887 S_028C70_COMP_SWAP(swap) |
1888 S_028C70_BLEND_CLAMP(blend_clamp) |
1889 S_028C70_BLEND_BYPASS(blend_bypass) |
1890 S_028C70_NUMBER_TYPE(ntype) |
1891 S_028C70_ENDIAN(endian);
1892
1893 color_pitch = S_028C64_TILE_MAX(pitch);
1894
1895 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1896 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1897
1898 if (rtex->resource.b.b.nr_samples > 1) {
1899 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1900
1901 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1902 S_028C74_NUM_FRAGMENTS(log_samples);
1903
1904 if (rtex->fmask.size) {
1905 color_info |= S_028C70_COMPRESSION(1);
1906 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1907
1908 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1909
1910 if (sctx->b.chip_class == SI) {
1911 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1912 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1913 }
1914 if (sctx->b.chip_class >= CIK) {
1915 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1916 }
1917 }
1918 }
1919
1920 offset += rtex->resource.gpu_address;
1921
1922 surf->cb_color_base = offset >> 8;
1923 surf->cb_color_pitch = color_pitch;
1924 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1925 surf->cb_color_view = color_view;
1926 surf->cb_color_info = color_info;
1927 surf->cb_color_attrib = color_attrib;
1928
1929 if (sctx->b.chip_class >= VI && rtex->dcc_buffer) {
1930 unsigned max_uncompressed_block_size = 2;
1931 uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
1932
1933 if (rtex->surface.nsamples > 1) {
1934 if (rtex->surface.bpe == 1)
1935 max_uncompressed_block_size = 0;
1936 else if (rtex->surface.bpe == 2)
1937 max_uncompressed_block_size = 1;
1938 }
1939
1940 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1941 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1942 surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
1943 }
1944
1945 if (rtex->fmask.size) {
1946 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1947 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1948 } else {
1949 /* This must be set for fast clear to work without FMASK. */
1950 surf->cb_color_fmask = surf->cb_color_base;
1951 surf->cb_color_fmask_slice = surf->cb_color_slice;
1952 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1953
1954 if (sctx->b.chip_class == SI) {
1955 unsigned bankh = util_logbase2(rtex->surface.bankh);
1956 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1957 }
1958
1959 if (sctx->b.chip_class >= CIK) {
1960 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1961 }
1962 }
1963
1964 /* Determine pixel shader export format */
1965 max_comp_size = si_colorformat_max_comp_size(format);
1966 if (ntype == V_028C70_NUMBER_SRGB ||
1967 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1968 max_comp_size <= 10) ||
1969 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1970 surf->export_16bpc = true;
1971 }
1972
1973 surf->color_initialized = true;
1974 }
1975
1976 static void si_init_depth_surface(struct si_context *sctx,
1977 struct r600_surface *surf)
1978 {
1979 struct si_screen *sscreen = sctx->screen;
1980 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1981 unsigned level = surf->base.u.tex.level;
1982 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1983 unsigned format, tile_mode_index, array_mode;
1984 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1985 uint32_t z_info, s_info, db_depth_info;
1986 uint64_t z_offs, s_offs;
1987 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1988
1989 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1990 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1991 case PIPE_FORMAT_X8Z24_UNORM:
1992 case PIPE_FORMAT_Z24X8_UNORM:
1993 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1994 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1995 break;
1996 case PIPE_FORMAT_Z32_FLOAT:
1997 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1998 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1999 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2000 break;
2001 case PIPE_FORMAT_Z16_UNORM:
2002 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2003 break;
2004 default:
2005 assert(0);
2006 }
2007
2008 format = si_translate_dbformat(rtex->resource.b.b.format);
2009
2010 if (format == V_028040_Z_INVALID) {
2011 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2012 }
2013 assert(format != V_028040_Z_INVALID);
2014
2015 s_offs = z_offs = rtex->resource.gpu_address;
2016 z_offs += rtex->surface.level[level].offset;
2017 s_offs += rtex->surface.stencil_level[level].offset;
2018
2019 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2020
2021 z_info = S_028040_FORMAT(format);
2022 if (rtex->resource.b.b.nr_samples > 1) {
2023 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2024 }
2025
2026 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2027 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2028 else
2029 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2030
2031 if (sctx->b.chip_class >= CIK) {
2032 switch (rtex->surface.level[level].mode) {
2033 case RADEON_SURF_MODE_2D:
2034 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2035 break;
2036 case RADEON_SURF_MODE_1D:
2037 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2038 case RADEON_SURF_MODE_LINEAR:
2039 default:
2040 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2041 break;
2042 }
2043 tile_split = rtex->surface.tile_split;
2044 stile_split = rtex->surface.stencil_tile_split;
2045 macro_aspect = rtex->surface.mtilea;
2046 bankw = rtex->surface.bankw;
2047 bankh = rtex->surface.bankh;
2048 tile_split = cik_tile_split(tile_split);
2049 stile_split = cik_tile_split(stile_split);
2050 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2051 bankw = cik_bank_wh(bankw);
2052 bankh = cik_bank_wh(bankh);
2053 nbanks = si_num_banks(sscreen, rtex);
2054 tile_mode_index = si_tile_mode_index(rtex, level, false);
2055 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2056
2057 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2058 S_02803C_PIPE_CONFIG(pipe_config) |
2059 S_02803C_BANK_WIDTH(bankw) |
2060 S_02803C_BANK_HEIGHT(bankh) |
2061 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2062 S_02803C_NUM_BANKS(nbanks);
2063 z_info |= S_028040_TILE_SPLIT(tile_split);
2064 s_info |= S_028044_TILE_SPLIT(stile_split);
2065 } else {
2066 tile_mode_index = si_tile_mode_index(rtex, level, false);
2067 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2068 tile_mode_index = si_tile_mode_index(rtex, level, true);
2069 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2070 }
2071
2072 /* HiZ aka depth buffer htile */
2073 /* use htile only for first level */
2074 if (rtex->htile_buffer && !level) {
2075 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2076 S_028040_ALLOW_EXPCLEAR(1);
2077
2078 /* Use all of the htile_buffer for depth, because we don't
2079 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2080 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2081
2082 uint64_t va = rtex->htile_buffer->gpu_address;
2083 db_htile_data_base = va >> 8;
2084 db_htile_surface = S_028ABC_FULL_CACHE(1);
2085 } else {
2086 db_htile_data_base = 0;
2087 db_htile_surface = 0;
2088 }
2089
2090 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2091
2092 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2093 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2094 surf->db_htile_data_base = db_htile_data_base;
2095 surf->db_depth_info = db_depth_info;
2096 surf->db_z_info = z_info;
2097 surf->db_stencil_info = s_info;
2098 surf->db_depth_base = z_offs >> 8;
2099 surf->db_stencil_base = s_offs >> 8;
2100 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2101 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2102 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2103 levelinfo->nblk_y) / 64 - 1);
2104 surf->db_htile_surface = db_htile_surface;
2105 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2106
2107 surf->depth_initialized = true;
2108 }
2109
2110 static void si_set_framebuffer_state(struct pipe_context *ctx,
2111 const struct pipe_framebuffer_state *state)
2112 {
2113 struct si_context *sctx = (struct si_context *)ctx;
2114 struct pipe_constant_buffer constbuf = {0};
2115 struct r600_surface *surf = NULL;
2116 struct r600_texture *rtex;
2117 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2118 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2119 int i;
2120
2121 /* Only flush TC when changing the framebuffer state, because
2122 * the only client not using TC that can change textures is
2123 * the framebuffer.
2124 *
2125 * Flush all CB and DB caches here because all buffers can be used
2126 * for write by both TC (with shader image stores) and CB/DB.
2127 */
2128 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2129 SI_CONTEXT_INV_TC_L2 |
2130 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2131
2132 /* Take the maximum of the old and new count. If the new count is lower,
2133 * dirtying is needed to disable the unbound colorbuffers.
2134 */
2135 sctx->framebuffer.dirty_cbufs |=
2136 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2137 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2138
2139 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2140
2141 sctx->framebuffer.export_16bpc = 0;
2142 sctx->framebuffer.compressed_cb_mask = 0;
2143 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2144 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2145 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2146 util_format_is_pure_integer(state->cbufs[0]->format);
2147
2148 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2149 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2150
2151 for (i = 0; i < state->nr_cbufs; i++) {
2152 if (!state->cbufs[i])
2153 continue;
2154
2155 surf = (struct r600_surface*)state->cbufs[i];
2156 rtex = (struct r600_texture*)surf->base.texture;
2157
2158 if (!surf->color_initialized) {
2159 si_initialize_color_surface(sctx, surf);
2160 }
2161
2162 if (surf->export_16bpc) {
2163 sctx->framebuffer.export_16bpc |= 1 << i;
2164 }
2165
2166 if (rtex->fmask.size && rtex->cmask.size) {
2167 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2168 }
2169 r600_context_add_resource_size(ctx, surf->base.texture);
2170 }
2171 /* Set the 16BPC export for possible dual-src blending. */
2172 if (i == 1 && surf && surf->export_16bpc) {
2173 sctx->framebuffer.export_16bpc |= 1 << 1;
2174 }
2175
2176 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2177
2178 if (state->zsbuf) {
2179 surf = (struct r600_surface*)state->zsbuf;
2180
2181 if (!surf->depth_initialized) {
2182 si_init_depth_surface(sctx, surf);
2183 }
2184 r600_context_add_resource_size(ctx, surf->base.texture);
2185 }
2186
2187 si_update_poly_offset_state(sctx);
2188 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2189 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2190
2191 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2192 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2193 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2194
2195 /* Set sample locations as fragment shader constants. */
2196 switch (sctx->framebuffer.nr_samples) {
2197 case 1:
2198 constbuf.user_buffer = sctx->b.sample_locations_1x;
2199 break;
2200 case 2:
2201 constbuf.user_buffer = sctx->b.sample_locations_2x;
2202 break;
2203 case 4:
2204 constbuf.user_buffer = sctx->b.sample_locations_4x;
2205 break;
2206 case 8:
2207 constbuf.user_buffer = sctx->b.sample_locations_8x;
2208 break;
2209 case 16:
2210 constbuf.user_buffer = sctx->b.sample_locations_16x;
2211 break;
2212 default:
2213 assert(0);
2214 }
2215 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2216 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2217 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2218
2219 /* Smoothing (only possible with nr_samples == 1) uses the same
2220 * sample locations as the MSAA it simulates.
2221 *
2222 * Therefore, don't update the sample locations when
2223 * transitioning from no AA to smoothing-equivalent AA, and
2224 * vice versa.
2225 */
2226 if ((sctx->framebuffer.nr_samples != 1 ||
2227 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2228 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2229 old_nr_samples != 1))
2230 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2231 }
2232 }
2233
2234 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2235 {
2236 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2237 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2238 unsigned i, nr_cbufs = state->nr_cbufs;
2239 struct r600_texture *tex = NULL;
2240 struct r600_surface *cb = NULL;
2241
2242 /* Colorbuffers. */
2243 for (i = 0; i < nr_cbufs; i++) {
2244 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2245 continue;
2246
2247 cb = (struct r600_surface*)state->cbufs[i];
2248 if (!cb) {
2249 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2250 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2251 continue;
2252 }
2253
2254 tex = (struct r600_texture *)cb->base.texture;
2255 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2256 &tex->resource, RADEON_USAGE_READWRITE,
2257 tex->surface.nsamples > 1 ?
2258 RADEON_PRIO_COLOR_BUFFER_MSAA :
2259 RADEON_PRIO_COLOR_BUFFER);
2260
2261 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2262 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2263 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2264 RADEON_PRIO_CMASK);
2265 }
2266
2267 if (tex->dcc_buffer && tex->dcc_buffer != &tex->resource) {
2268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2269 tex->dcc_buffer, RADEON_USAGE_READWRITE,
2270 RADEON_PRIO_DCC);
2271 }
2272
2273 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2274 sctx->b.chip_class >= VI ? 14 : 13);
2275 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2276 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2277 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2278 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2279 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2280 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2281 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2282 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2283 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2284 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2285 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2286 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2287 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2288
2289 if (sctx->b.chip_class >= VI)
2290 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2291 }
2292 /* set CB_COLOR1_INFO for possible dual-src blending */
2293 if (i == 1 && state->cbufs[0] &&
2294 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2295 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2296 cb->cb_color_info | tex->cb_color_info);
2297 i++;
2298 }
2299 for (; i < 8 ; i++)
2300 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2301 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2302
2303 /* ZS buffer. */
2304 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2305 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2306 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2307
2308 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2309 &rtex->resource, RADEON_USAGE_READWRITE,
2310 zb->base.texture->nr_samples > 1 ?
2311 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2312 RADEON_PRIO_DEPTH_BUFFER);
2313
2314 if (zb->db_htile_data_base) {
2315 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2316 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2317 RADEON_PRIO_HTILE);
2318 }
2319
2320 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2321 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2322
2323 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2324 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2325 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2326 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2327 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2328 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2329 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2330 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2331 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2332 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2333 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2334
2335 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2336 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2337 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2338 zb->pa_su_poly_offset_db_fmt_cntl);
2339 } else if (sctx->framebuffer.dirty_zsbuf) {
2340 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2341 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2342 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2343 }
2344
2345 /* Framebuffer dimensions. */
2346 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2347 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2348 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2349
2350 sctx->framebuffer.dirty_cbufs = 0;
2351 sctx->framebuffer.dirty_zsbuf = false;
2352 }
2353
2354 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2355 struct r600_atom *atom)
2356 {
2357 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2358 unsigned nr_samples = sctx->framebuffer.nr_samples;
2359
2360 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2361 SI_NUM_SMOOTH_AA_SAMPLES);
2362 }
2363
2364 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2365 {
2366 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2367
2368 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2369 sctx->ps_iter_samples,
2370 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2371 }
2372
2373
2374 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2375 {
2376 struct si_context *sctx = (struct si_context *)ctx;
2377
2378 if (sctx->ps_iter_samples == min_samples)
2379 return;
2380
2381 sctx->ps_iter_samples = min_samples;
2382
2383 if (sctx->framebuffer.nr_samples > 1)
2384 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2385 }
2386
2387 /*
2388 * Samplers
2389 */
2390
2391 /**
2392 * Create a sampler view.
2393 *
2394 * @param ctx context
2395 * @param texture texture
2396 * @param state sampler view template
2397 * @param width0 width0 override (for compressed textures as int)
2398 * @param height0 height0 override (for compressed textures as int)
2399 * @param force_level set the base address to the level (for compressed textures)
2400 */
2401 struct pipe_sampler_view *
2402 si_create_sampler_view_custom(struct pipe_context *ctx,
2403 struct pipe_resource *texture,
2404 const struct pipe_sampler_view *state,
2405 unsigned width0, unsigned height0,
2406 unsigned force_level)
2407 {
2408 struct si_context *sctx = (struct si_context*)ctx;
2409 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2410 struct r600_texture *tmp = (struct r600_texture*)texture;
2411 const struct util_format_description *desc;
2412 unsigned format, num_format, base_level, first_level, last_level;
2413 uint32_t pitch = 0;
2414 unsigned char state_swizzle[4], swizzle[4];
2415 unsigned height, depth, width;
2416 enum pipe_format pipe_format = state->format;
2417 struct radeon_surf_level *surflevel;
2418 int first_non_void;
2419 uint64_t va;
2420 unsigned last_layer = state->u.tex.last_layer;
2421
2422 if (view == NULL)
2423 return NULL;
2424
2425 /* initialize base object */
2426 view->base = *state;
2427 view->base.texture = NULL;
2428 view->base.reference.count = 1;
2429 view->base.context = ctx;
2430
2431 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2432 if (!texture) {
2433 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2434 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2435 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2436 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2437 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2438 return &view->base;
2439 }
2440
2441 pipe_resource_reference(&view->base.texture, texture);
2442 view->resource = &tmp->resource;
2443
2444 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2445 state->format == PIPE_FORMAT_S8X24_UINT ||
2446 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2447 state->format == PIPE_FORMAT_S8_UINT)
2448 view->is_stencil_sampler = true;
2449
2450 /* Buffer resource. */
2451 if (texture->target == PIPE_BUFFER) {
2452 unsigned stride, num_records;
2453
2454 desc = util_format_description(state->format);
2455 first_non_void = util_format_get_first_non_void_channel(state->format);
2456 stride = desc->block.bits / 8;
2457 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2458 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2459 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2460
2461 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2462 num_records = MIN2(num_records, texture->width0 / stride);
2463
2464 if (sctx->b.chip_class >= VI)
2465 num_records *= stride;
2466
2467 view->state[4] = va;
2468 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2469 S_008F04_STRIDE(stride);
2470 view->state[6] = num_records;
2471 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2472 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2473 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2474 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2475 S_008F0C_NUM_FORMAT(num_format) |
2476 S_008F0C_DATA_FORMAT(format);
2477
2478 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2479 return &view->base;
2480 }
2481
2482 state_swizzle[0] = state->swizzle_r;
2483 state_swizzle[1] = state->swizzle_g;
2484 state_swizzle[2] = state->swizzle_b;
2485 state_swizzle[3] = state->swizzle_a;
2486
2487 surflevel = tmp->surface.level;
2488
2489 /* Texturing with separate depth and stencil. */
2490 if (tmp->is_depth && !tmp->is_flushing_texture) {
2491 switch (pipe_format) {
2492 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2493 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2494 break;
2495 case PIPE_FORMAT_X8Z24_UNORM:
2496 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2497 /* Z24 is always stored like this. */
2498 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2499 break;
2500 case PIPE_FORMAT_X24S8_UINT:
2501 case PIPE_FORMAT_S8X24_UINT:
2502 case PIPE_FORMAT_X32_S8X24_UINT:
2503 pipe_format = PIPE_FORMAT_S8_UINT;
2504 surflevel = tmp->surface.stencil_level;
2505 break;
2506 default:;
2507 }
2508 }
2509
2510 desc = util_format_description(pipe_format);
2511
2512 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2513 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2514 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2515
2516 switch (pipe_format) {
2517 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2518 case PIPE_FORMAT_X24S8_UINT:
2519 case PIPE_FORMAT_X32_S8X24_UINT:
2520 case PIPE_FORMAT_X8Z24_UNORM:
2521 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2522 break;
2523 default:
2524 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2525 }
2526 } else {
2527 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2528 }
2529
2530 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2531
2532 switch (pipe_format) {
2533 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2534 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2535 break;
2536 default:
2537 if (first_non_void < 0) {
2538 if (util_format_is_compressed(pipe_format)) {
2539 switch (pipe_format) {
2540 case PIPE_FORMAT_DXT1_SRGB:
2541 case PIPE_FORMAT_DXT1_SRGBA:
2542 case PIPE_FORMAT_DXT3_SRGBA:
2543 case PIPE_FORMAT_DXT5_SRGBA:
2544 case PIPE_FORMAT_BPTC_SRGBA:
2545 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2546 break;
2547 case PIPE_FORMAT_RGTC1_SNORM:
2548 case PIPE_FORMAT_LATC1_SNORM:
2549 case PIPE_FORMAT_RGTC2_SNORM:
2550 case PIPE_FORMAT_LATC2_SNORM:
2551 /* implies float, so use SNORM/UNORM to determine
2552 whether data is signed or not */
2553 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2554 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2555 break;
2556 default:
2557 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2558 break;
2559 }
2560 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2561 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2562 } else {
2563 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2564 }
2565 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2566 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2567 } else {
2568 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2569
2570 switch (desc->channel[first_non_void].type) {
2571 case UTIL_FORMAT_TYPE_FLOAT:
2572 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2573 break;
2574 case UTIL_FORMAT_TYPE_SIGNED:
2575 if (desc->channel[first_non_void].normalized)
2576 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2577 else if (desc->channel[first_non_void].pure_integer)
2578 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2579 else
2580 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2581 break;
2582 case UTIL_FORMAT_TYPE_UNSIGNED:
2583 if (desc->channel[first_non_void].normalized)
2584 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2585 else if (desc->channel[first_non_void].pure_integer)
2586 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2587 else
2588 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2589 }
2590 }
2591 }
2592
2593 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2594 if (format == ~0) {
2595 format = 0;
2596 }
2597
2598 base_level = 0;
2599 first_level = state->u.tex.first_level;
2600 last_level = state->u.tex.last_level;
2601 width = width0;
2602 height = height0;
2603 depth = texture->depth0;
2604
2605 if (force_level) {
2606 assert(force_level == first_level &&
2607 force_level == last_level);
2608 base_level = force_level;
2609 first_level = 0;
2610 last_level = 0;
2611 width = u_minify(width, force_level);
2612 height = u_minify(height, force_level);
2613 depth = u_minify(depth, force_level);
2614 }
2615
2616 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2617
2618 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2619 height = 1;
2620 depth = texture->array_size;
2621 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2622 depth = texture->array_size;
2623 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2624 depth = texture->array_size / 6;
2625
2626 /* This is not needed if state trackers set last_layer correctly. */
2627 if (state->target == PIPE_TEXTURE_1D ||
2628 state->target == PIPE_TEXTURE_2D ||
2629 state->target == PIPE_TEXTURE_RECT ||
2630 state->target == PIPE_TEXTURE_CUBE)
2631 last_layer = state->u.tex.first_layer;
2632
2633 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2634
2635 view->state[0] = va >> 8;
2636 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2637 S_008F14_DATA_FORMAT(format) |
2638 S_008F14_NUM_FORMAT(num_format));
2639 view->state[2] = (S_008F18_WIDTH(width - 1) |
2640 S_008F18_HEIGHT(height - 1));
2641 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2642 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2643 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2644 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2645 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2646 0 : first_level) |
2647 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2648 util_logbase2(texture->nr_samples) :
2649 last_level) |
2650 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2651 S_008F1C_POW2_PAD(texture->last_level > 0) |
2652 S_008F1C_TYPE(si_tex_dim(texture->target, state->target,
2653 texture->nr_samples)));
2654 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2655 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2656 S_008F24_LAST_ARRAY(last_layer));
2657
2658 if (tmp->dcc_buffer) {
2659 uint64_t dcc_offset = surflevel[base_level].dcc_offset;
2660 unsigned swap = r600_translate_colorswap(pipe_format);
2661
2662 view->state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2663 view->state[7] = (tmp->dcc_buffer->gpu_address + dcc_offset) >> 8;
2664 view->dcc_buffer = tmp->dcc_buffer;
2665 } else {
2666 view->state[6] = 0;
2667 view->state[7] = 0;
2668 }
2669
2670 /* Initialize the sampler view for FMASK. */
2671 if (tmp->fmask.size) {
2672 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2673 uint32_t fmask_format;
2674
2675 switch (texture->nr_samples) {
2676 case 2:
2677 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2678 break;
2679 case 4:
2680 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2681 break;
2682 case 8:
2683 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2684 break;
2685 default:
2686 assert(0);
2687 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2688 }
2689
2690 view->fmask_state[0] = va >> 8;
2691 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2692 S_008F14_DATA_FORMAT(fmask_format) |
2693 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2694 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2695 S_008F18_HEIGHT(height - 1);
2696 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2697 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2698 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2699 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2700 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2701 S_008F1C_TYPE(si_tex_dim(texture->target,
2702 state->target, 0));
2703 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2704 S_008F20_PITCH(tmp->fmask.pitch - 1);
2705 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2706 S_008F24_LAST_ARRAY(last_layer);
2707 view->fmask_state[6] = 0;
2708 view->fmask_state[7] = 0;
2709 }
2710
2711 return &view->base;
2712 }
2713
2714 static struct pipe_sampler_view *
2715 si_create_sampler_view(struct pipe_context *ctx,
2716 struct pipe_resource *texture,
2717 const struct pipe_sampler_view *state)
2718 {
2719 return si_create_sampler_view_custom(ctx, texture, state,
2720 texture ? texture->width0 : 0,
2721 texture ? texture->height0 : 0, 0);
2722 }
2723
2724 static void si_sampler_view_destroy(struct pipe_context *ctx,
2725 struct pipe_sampler_view *state)
2726 {
2727 struct si_sampler_view *view = (struct si_sampler_view *)state;
2728
2729 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2730 LIST_DELINIT(&view->list);
2731
2732 pipe_resource_reference(&state->texture, NULL);
2733 FREE(view);
2734 }
2735
2736 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2737 {
2738 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2739 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2740 (linear_filter &&
2741 (wrap == PIPE_TEX_WRAP_CLAMP ||
2742 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2743 }
2744
2745 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2746 {
2747 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2748 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2749
2750 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2751 state->border_color.ui[2] || state->border_color.ui[3]) &&
2752 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2753 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2754 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2755 }
2756
2757 static void *si_create_sampler_state(struct pipe_context *ctx,
2758 const struct pipe_sampler_state *state)
2759 {
2760 struct si_context *sctx = (struct si_context *)ctx;
2761 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2762 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2763 unsigned border_color_type, border_color_index = 0;
2764
2765 if (rstate == NULL) {
2766 return NULL;
2767 }
2768
2769 if (!sampler_state_needs_border_color(state))
2770 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2771 else if (state->border_color.f[0] == 0 &&
2772 state->border_color.f[1] == 0 &&
2773 state->border_color.f[2] == 0 &&
2774 state->border_color.f[3] == 0)
2775 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2776 else if (state->border_color.f[0] == 0 &&
2777 state->border_color.f[1] == 0 &&
2778 state->border_color.f[2] == 0 &&
2779 state->border_color.f[3] == 1)
2780 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2781 else if (state->border_color.f[0] == 1 &&
2782 state->border_color.f[1] == 1 &&
2783 state->border_color.f[2] == 1 &&
2784 state->border_color.f[3] == 1)
2785 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2786 else {
2787 int i;
2788
2789 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2790
2791 /* Check if the border has been uploaded already. */
2792 for (i = 0; i < sctx->border_color_count; i++)
2793 if (memcmp(&sctx->border_color_table[i], &state->border_color,
2794 sizeof(state->border_color)) == 0)
2795 break;
2796
2797 if (i >= SI_MAX_BORDER_COLORS) {
2798 /* Getting 4096 unique border colors is very unlikely. */
2799 fprintf(stderr, "radeonsi: The border color table is full. "
2800 "Any new border colors will be just black. "
2801 "Please file a bug.\n");
2802 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2803 } else {
2804 if (i == sctx->border_color_count) {
2805 /* Upload a new border color. */
2806 memcpy(&sctx->border_color_table[i], &state->border_color,
2807 sizeof(state->border_color));
2808 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
2809 &state->border_color,
2810 sizeof(state->border_color));
2811 sctx->border_color_count++;
2812 }
2813
2814 border_color_index = i;
2815 }
2816 }
2817
2818 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2819 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2820 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2821 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2822 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2823 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2824 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2825 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2826 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2827 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2828 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2829 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2830 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2831 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
2832 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2833 return rstate;
2834 }
2835
2836 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2837 {
2838 struct si_context *sctx = (struct si_context *)ctx;
2839
2840 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2841 return;
2842
2843 sctx->sample_mask.sample_mask = sample_mask;
2844 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2845 }
2846
2847 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2848 {
2849 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2850 unsigned mask = sctx->sample_mask.sample_mask;
2851
2852 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2853 radeon_emit(cs, mask | (mask << 16));
2854 radeon_emit(cs, mask | (mask << 16));
2855 }
2856
2857 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2858 {
2859 free(state);
2860 }
2861
2862 /*
2863 * Vertex elements & buffers
2864 */
2865
2866 static void *si_create_vertex_elements(struct pipe_context *ctx,
2867 unsigned count,
2868 const struct pipe_vertex_element *elements)
2869 {
2870 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2871 int i;
2872
2873 assert(count < SI_MAX_ATTRIBS);
2874 if (!v)
2875 return NULL;
2876
2877 v->count = count;
2878 for (i = 0; i < count; ++i) {
2879 const struct util_format_description *desc;
2880 unsigned data_format, num_format;
2881 int first_non_void;
2882
2883 desc = util_format_description(elements[i].src_format);
2884 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2885 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2886 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2887
2888 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2889 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2890 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2891 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2892 S_008F0C_NUM_FORMAT(num_format) |
2893 S_008F0C_DATA_FORMAT(data_format);
2894 v->format_size[i] = desc->block.bits / 8;
2895 }
2896 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2897
2898 return v;
2899 }
2900
2901 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2902 {
2903 struct si_context *sctx = (struct si_context *)ctx;
2904 struct si_vertex_element *v = (struct si_vertex_element*)state;
2905
2906 sctx->vertex_elements = v;
2907 sctx->vertex_buffers_dirty = true;
2908 }
2909
2910 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2911 {
2912 struct si_context *sctx = (struct si_context *)ctx;
2913
2914 if (sctx->vertex_elements == state)
2915 sctx->vertex_elements = NULL;
2916 FREE(state);
2917 }
2918
2919 static void si_set_vertex_buffers(struct pipe_context *ctx,
2920 unsigned start_slot, unsigned count,
2921 const struct pipe_vertex_buffer *buffers)
2922 {
2923 struct si_context *sctx = (struct si_context *)ctx;
2924 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2925 int i;
2926
2927 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2928
2929 if (buffers) {
2930 for (i = 0; i < count; i++) {
2931 const struct pipe_vertex_buffer *src = buffers + i;
2932 struct pipe_vertex_buffer *dsti = dst + i;
2933
2934 pipe_resource_reference(&dsti->buffer, src->buffer);
2935 dsti->buffer_offset = src->buffer_offset;
2936 dsti->stride = src->stride;
2937 r600_context_add_resource_size(ctx, src->buffer);
2938 }
2939 } else {
2940 for (i = 0; i < count; i++) {
2941 pipe_resource_reference(&dst[i].buffer, NULL);
2942 }
2943 }
2944 sctx->vertex_buffers_dirty = true;
2945 }
2946
2947 static void si_set_index_buffer(struct pipe_context *ctx,
2948 const struct pipe_index_buffer *ib)
2949 {
2950 struct si_context *sctx = (struct si_context *)ctx;
2951
2952 if (ib) {
2953 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2954 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2955 r600_context_add_resource_size(ctx, ib->buffer);
2956 } else {
2957 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2958 }
2959 }
2960
2961 /*
2962 * Misc
2963 */
2964 static void si_set_polygon_stipple(struct pipe_context *ctx,
2965 const struct pipe_poly_stipple *state)
2966 {
2967 struct si_context *sctx = (struct si_context *)ctx;
2968 struct pipe_resource *tex;
2969 struct pipe_sampler_view *view;
2970 bool is_zero = true;
2971 bool is_one = true;
2972 int i;
2973
2974 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2975 * the resource is NULL/invalid. Take advantage of this fact and skip
2976 * texture allocation if the stipple pattern is constant.
2977 *
2978 * This is an optimization for the common case when stippling isn't
2979 * used but set_polygon_stipple is still called by st/mesa.
2980 */
2981 for (i = 0; i < Elements(state->stipple); i++) {
2982 is_zero = is_zero && state->stipple[i] == 0;
2983 is_one = is_one && state->stipple[i] == 0xffffffff;
2984 }
2985
2986 if (is_zero || is_one) {
2987 struct pipe_sampler_view templ = {{0}};
2988
2989 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2990 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2991 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2992 /* The pattern should be inverted in the texture. */
2993 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2994
2995 view = ctx->create_sampler_view(ctx, NULL, &templ);
2996 } else {
2997 /* Create a new texture. */
2998 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2999 if (!tex)
3000 return;
3001
3002 view = util_pstipple_create_sampler_view(ctx, tex);
3003 pipe_resource_reference(&tex, NULL);
3004 }
3005
3006 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3007 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3008 pipe_sampler_view_reference(&view, NULL);
3009
3010 /* Bind the sampler state if needed. */
3011 if (!sctx->pstipple_sampler_state) {
3012 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3013 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3014 SI_POLY_STIPPLE_SAMPLER, 1,
3015 &sctx->pstipple_sampler_state);
3016 }
3017 }
3018
3019 static void si_set_tess_state(struct pipe_context *ctx,
3020 const float default_outer_level[4],
3021 const float default_inner_level[2])
3022 {
3023 struct si_context *sctx = (struct si_context *)ctx;
3024 struct pipe_constant_buffer cb;
3025 float array[8];
3026
3027 memcpy(array, default_outer_level, sizeof(float) * 4);
3028 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3029
3030 cb.buffer = NULL;
3031 cb.user_buffer = NULL;
3032 cb.buffer_size = sizeof(array);
3033
3034 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3035 (void*)array, sizeof(array),
3036 &cb.buffer_offset);
3037
3038 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3039 SI_DRIVER_STATE_CONST_BUF, &cb);
3040 pipe_resource_reference(&cb.buffer, NULL);
3041 }
3042
3043 static void si_texture_barrier(struct pipe_context *ctx)
3044 {
3045 struct si_context *sctx = (struct si_context *)ctx;
3046
3047 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3048 SI_CONTEXT_INV_TC_L2 |
3049 SI_CONTEXT_FLUSH_AND_INV_CB;
3050 }
3051
3052 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3053 {
3054 struct pipe_blend_state blend;
3055
3056 memset(&blend, 0, sizeof(blend));
3057 blend.independent_blend_enable = true;
3058 blend.rt[0].colormask = 0xf;
3059 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3060 }
3061
3062 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3063 bool include_draw_vbo)
3064 {
3065 si_need_cs_space((struct si_context*)ctx);
3066 }
3067
3068 static void si_init_config(struct si_context *sctx);
3069
3070 void si_init_state_functions(struct si_context *sctx)
3071 {
3072 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3073 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3074
3075 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3076 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3077 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3078 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3079 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3080 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3081 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3082 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3083 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3084 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3085 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3086 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3087 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3088
3089 sctx->b.b.create_blend_state = si_create_blend_state;
3090 sctx->b.b.bind_blend_state = si_bind_blend_state;
3091 sctx->b.b.delete_blend_state = si_delete_blend_state;
3092 sctx->b.b.set_blend_color = si_set_blend_color;
3093
3094 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3095 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3096 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3097
3098 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3099 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3100 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3101
3102 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3103 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3104 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3105 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3106
3107 sctx->b.b.set_clip_state = si_set_clip_state;
3108 sctx->b.b.set_scissor_states = si_set_scissor_states;
3109 sctx->b.b.set_viewport_states = si_set_viewport_states;
3110 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3111
3112 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3113 sctx->b.b.get_sample_position = cayman_get_sample_position;
3114
3115 sctx->b.b.create_sampler_state = si_create_sampler_state;
3116 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3117
3118 sctx->b.b.create_sampler_view = si_create_sampler_view;
3119 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3120
3121 sctx->b.b.set_sample_mask = si_set_sample_mask;
3122
3123 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3124 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3125 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3126 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3127 sctx->b.b.set_index_buffer = si_set_index_buffer;
3128
3129 sctx->b.b.texture_barrier = si_texture_barrier;
3130 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3131 sctx->b.b.set_min_samples = si_set_min_samples;
3132 sctx->b.b.set_tess_state = si_set_tess_state;
3133
3134 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3135 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3136
3137 sctx->b.b.draw_vbo = si_draw_vbo;
3138
3139 if (sctx->b.chip_class >= CIK) {
3140 sctx->b.dma_copy = cik_sdma_copy;
3141 } else {
3142 sctx->b.dma_copy = si_dma_copy;
3143 }
3144
3145 si_init_config(sctx);
3146 }
3147
3148 static void
3149 si_write_harvested_raster_configs(struct si_context *sctx,
3150 struct si_pm4_state *pm4,
3151 unsigned raster_config,
3152 unsigned raster_config_1)
3153 {
3154 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3155 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3156 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3157 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3158 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3159 unsigned rb_per_se = num_rb / num_se;
3160 unsigned se_mask[4];
3161 unsigned se;
3162
3163 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3164 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3165 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3166 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3167
3168 assert(num_se == 1 || num_se == 2 || num_se == 4);
3169 assert(sh_per_se == 1 || sh_per_se == 2);
3170 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3171
3172 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3173 * fields are for, so I'm leaving them as their default
3174 * values. */
3175
3176 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3177 (!se_mask[2] && !se_mask[3]))) {
3178 raster_config_1 &= C_028354_SE_PAIR_MAP;
3179
3180 if (!se_mask[0] && !se_mask[1]) {
3181 raster_config_1 |=
3182 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3183 } else {
3184 raster_config_1 |=
3185 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3186 }
3187 }
3188
3189 for (se = 0; se < num_se; se++) {
3190 unsigned raster_config_se = raster_config;
3191 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3192 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3193 int idx = (se / 2) * 2;
3194
3195 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3196 raster_config_se &= C_028350_SE_MAP;
3197
3198 if (!se_mask[idx]) {
3199 raster_config_se |=
3200 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3201 } else {
3202 raster_config_se |=
3203 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3204 }
3205 }
3206
3207 pkr0_mask &= rb_mask;
3208 pkr1_mask &= rb_mask;
3209 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3210 raster_config_se &= C_028350_PKR_MAP;
3211
3212 if (!pkr0_mask) {
3213 raster_config_se |=
3214 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3215 } else {
3216 raster_config_se |=
3217 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3218 }
3219 }
3220
3221 if (rb_per_se >= 2) {
3222 unsigned rb0_mask = 1 << (se * rb_per_se);
3223 unsigned rb1_mask = rb0_mask << 1;
3224
3225 rb0_mask &= rb_mask;
3226 rb1_mask &= rb_mask;
3227 if (!rb0_mask || !rb1_mask) {
3228 raster_config_se &= C_028350_RB_MAP_PKR0;
3229
3230 if (!rb0_mask) {
3231 raster_config_se |=
3232 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3233 } else {
3234 raster_config_se |=
3235 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3236 }
3237 }
3238
3239 if (rb_per_se > 2) {
3240 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3241 rb1_mask = rb0_mask << 1;
3242 rb0_mask &= rb_mask;
3243 rb1_mask &= rb_mask;
3244 if (!rb0_mask || !rb1_mask) {
3245 raster_config_se &= C_028350_RB_MAP_PKR1;
3246
3247 if (!rb0_mask) {
3248 raster_config_se |=
3249 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3250 } else {
3251 raster_config_se |=
3252 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3253 }
3254 }
3255 }
3256 }
3257
3258 /* GRBM_GFX_INDEX is privileged on VI */
3259 if (sctx->b.chip_class <= CIK)
3260 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3261 SE_INDEX(se) | SH_BROADCAST_WRITES |
3262 INSTANCE_BROADCAST_WRITES);
3263 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3264 if (sctx->b.chip_class >= CIK)
3265 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3266 }
3267
3268 /* GRBM_GFX_INDEX is privileged on VI */
3269 if (sctx->b.chip_class <= CIK)
3270 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3271 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3272 INSTANCE_BROADCAST_WRITES);
3273 }
3274
3275 static void si_init_config(struct si_context *sctx)
3276 {
3277 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3278 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3279 unsigned raster_config, raster_config_1;
3280 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3281 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3282 int i;
3283
3284 if (pm4 == NULL)
3285 return;
3286
3287 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3288 si_pm4_cmd_add(pm4, 0x80000000);
3289 si_pm4_cmd_add(pm4, 0x80000000);
3290 si_pm4_cmd_end(pm4, false);
3291
3292 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3293 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3294
3295 /* FIXME calculate these values somehow ??? */
3296 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3297 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3298 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3299
3300 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3301 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3302
3303 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3304 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3305 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3306 if (sctx->b.chip_class < CIK)
3307 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3308 S_008A14_CLIP_VTX_REORDER_ENA(1));
3309
3310 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3311 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3312
3313 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3314
3315 for (i = 0; i < 16; i++) {
3316 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3317 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3318 }
3319
3320 switch (sctx->screen->b.family) {
3321 case CHIP_TAHITI:
3322 case CHIP_PITCAIRN:
3323 raster_config = 0x2a00126a;
3324 raster_config_1 = 0x00000000;
3325 break;
3326 case CHIP_VERDE:
3327 raster_config = 0x0000124a;
3328 raster_config_1 = 0x00000000;
3329 break;
3330 case CHIP_OLAND:
3331 raster_config = 0x00000082;
3332 raster_config_1 = 0x00000000;
3333 break;
3334 case CHIP_HAINAN:
3335 raster_config = 0x00000000;
3336 raster_config_1 = 0x00000000;
3337 break;
3338 case CHIP_BONAIRE:
3339 raster_config = 0x16000012;
3340 raster_config_1 = 0x00000000;
3341 break;
3342 case CHIP_HAWAII:
3343 raster_config = 0x3a00161a;
3344 raster_config_1 = 0x0000002e;
3345 break;
3346 case CHIP_FIJI:
3347 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3348 raster_config = 0x16000012; /* 0x3a00161a */
3349 raster_config_1 = 0x0000002a; /* 0x0000002e */
3350 break;
3351 case CHIP_TONGA:
3352 raster_config = 0x16000012;
3353 raster_config_1 = 0x0000002a;
3354 break;
3355 case CHIP_ICELAND:
3356 raster_config = 0x00000002;
3357 raster_config_1 = 0x00000000;
3358 break;
3359 case CHIP_CARRIZO:
3360 raster_config = 0x00000002;
3361 raster_config_1 = 0x00000000;
3362 break;
3363 case CHIP_KAVERI:
3364 /* KV should be 0x00000002, but that causes problems with radeon */
3365 raster_config = 0x00000000; /* 0x00000002 */
3366 raster_config_1 = 0x00000000;
3367 break;
3368 case CHIP_KABINI:
3369 case CHIP_MULLINS:
3370 case CHIP_STONEY:
3371 raster_config = 0x00000000;
3372 raster_config_1 = 0x00000000;
3373 break;
3374 default:
3375 fprintf(stderr,
3376 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3377 raster_config = 0x00000000;
3378 raster_config_1 = 0x00000000;
3379 break;
3380 }
3381
3382 /* Always use the default config when all backends are enabled
3383 * (or when we failed to determine the enabled backends).
3384 */
3385 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3386 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3387 raster_config);
3388 if (sctx->b.chip_class >= CIK)
3389 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3390 raster_config_1);
3391 } else {
3392 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3393 }
3394
3395 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3396 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3397 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3398 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3399 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3400 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3401 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3402
3403 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3404 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3405 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3406 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3407 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3408 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3409 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3410 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3411 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3412 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3413 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3414 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3415 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3416
3417 /* There is a hang if stencil is used and fast stencil is enabled
3418 * regardless of whether HTILE is depth-only or not.
3419 */
3420 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3421 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3422 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3423 S_02800C_FAST_STENCIL_DISABLE(1));
3424
3425 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3426 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3427 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3428
3429 if (sctx->b.chip_class >= CIK) {
3430 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3431 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3432 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3433 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3434 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3435 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3436 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3437 }
3438
3439 if (sctx->b.chip_class >= VI) {
3440 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3441 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3442 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3443 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3444 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3445 }
3446
3447 if (sctx->b.family == CHIP_STONEY)
3448 si_pm4_set_reg(pm4, R_028754_SX_PS_DOWNCONVERT, 0);
3449
3450 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3451 if (sctx->b.chip_class >= CIK)
3452 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3453 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3454 RADEON_PRIO_BORDER_COLORS);
3455
3456 si_pm4_upload_indirect_buffer(sctx, pm4);
3457 sctx->init_config = pm4;
3458 }