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radeonsi: disallow MIN/MAX blend equations for dual source blending
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 /* Only set dual source blending for MRT0 to avoid a hang. */
464 if (i >= 1 && blend->dual_src_blend)
465 continue;
466
467 /* Only addition and subtraction equations are supported with
468 * dual source blending.
469 */
470 if (blend->dual_src_blend &&
471 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
472 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
473 assert(!"Unsupported equation for dual source blending");
474 continue;
475 }
476
477 if (!state->rt[j].colormask)
478 continue;
479
480 /* cb_render_state will disable unused ones */
481 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
482
483 if (!state->rt[j].blend_enable) {
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* Blending optimizations for Stoney.
489 * These transformations don't change the behavior.
490 *
491 * First, get rid of DST in the blend factors:
492 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
493 */
494 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
495 PIPE_BLENDFACTOR_DST_COLOR,
496 PIPE_BLENDFACTOR_SRC_COLOR);
497 si_blend_remove_dst(&eqA, &srcA, &dstA,
498 PIPE_BLENDFACTOR_DST_COLOR,
499 PIPE_BLENDFACTOR_SRC_COLOR);
500 si_blend_remove_dst(&eqA, &srcA, &dstA,
501 PIPE_BLENDFACTOR_DST_ALPHA,
502 PIPE_BLENDFACTOR_SRC_ALPHA);
503
504 /* Look up the ideal settings from tables. */
505 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
506 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
507 srcA_opt = si_translate_blend_opt_factor(srcA, true);
508 dstA_opt = si_translate_blend_opt_factor(dstA, true);
509
510 /* Handle interdependencies. */
511 if (si_blend_factor_uses_dst(srcRGB))
512 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
513 if (si_blend_factor_uses_dst(srcA))
514 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
515
516 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
517 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
518 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
519 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
521
522 /* Set the final value. */
523 sx_mrt_blend_opt[i] =
524 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
525 S_028760_COLOR_DST_OPT(dstRGB_opt) |
526 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
527 S_028760_ALPHA_SRC_OPT(srcA_opt) |
528 S_028760_ALPHA_DST_OPT(dstA_opt) |
529 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
530
531 /* Set blend state. */
532 blend_cntl |= S_028780_ENABLE(1);
533 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
534 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
535 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
536
537 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
538 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
539 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
540 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
541 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
542 }
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544
545 blend->blend_enable_4bit |= 0xfu << (i * 4);
546
547 /* This is only important for formats without alpha. */
548 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
549 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
550 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
551 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
552 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
553 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
554 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
555 }
556
557 if (blend->cb_target_mask) {
558 color_control |= S_028808_MODE(mode);
559 } else {
560 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
561 }
562
563 if (sctx->b.family == CHIP_STONEY) {
564 for (int i = 0; i < 8; i++)
565 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
566 sx_mrt_blend_opt[i]);
567
568 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
569 if (blend->dual_src_blend || state->logicop_enable ||
570 mode == V_028808_CB_RESOLVE)
571 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
572 }
573
574 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
575 return blend;
576 }
577
578 static void *si_create_blend_state(struct pipe_context *ctx,
579 const struct pipe_blend_state *state)
580 {
581 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
582 }
583
584 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
588 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
589 sctx->do_update_shaders = true;
590 }
591
592 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
596 }
597
598 static void si_set_blend_color(struct pipe_context *ctx,
599 const struct pipe_blend_color *state)
600 {
601 struct si_context *sctx = (struct si_context *)ctx;
602
603 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
604 return;
605
606 sctx->blend_color.state = *state;
607 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
608 }
609
610 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
611 {
612 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
613
614 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
615 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
616 }
617
618 /*
619 * Clipping
620 */
621
622 static void si_set_clip_state(struct pipe_context *ctx,
623 const struct pipe_clip_state *state)
624 {
625 struct si_context *sctx = (struct si_context *)ctx;
626 struct pipe_constant_buffer cb;
627
628 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
629 return;
630
631 sctx->clip_state.state = *state;
632 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
633
634 cb.buffer = NULL;
635 cb.user_buffer = state->ucp;
636 cb.buffer_offset = 0;
637 cb.buffer_size = 4*4*8;
638 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
639 pipe_resource_reference(&cb.buffer, NULL);
640 }
641
642 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
643 {
644 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
645
646 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
647 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
648 }
649
650 #define SIX_BITS 0x3F
651
652 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
653 {
654 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
655 struct tgsi_shader_info *info = si_get_vs_info(sctx);
656 unsigned window_space =
657 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
658 unsigned clipdist_mask =
659 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
660
661 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
662 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
663 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
664 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
665 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
666 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
667 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
668 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
669 info->writes_edgeflag ||
670 info->writes_layer ||
671 info->writes_viewport_index) |
672 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
673 (sctx->queued.named.rasterizer->clip_plane_enable &
674 clipdist_mask));
675 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
676 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
677 (clipdist_mask ? 0 :
678 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
679 S_028810_CLIP_DISABLE(window_space));
680
681 /* reuse needs to be set off if we write oViewport */
682 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
683 S_028AB4_REUSE_OFF(info->writes_viewport_index));
684 }
685
686 /*
687 * inferred state between framebuffer and rasterizer
688 */
689 static void si_update_poly_offset_state(struct si_context *sctx)
690 {
691 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
692
693 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
694 return;
695
696 switch (sctx->framebuffer.state.zsbuf->texture->format) {
697 case PIPE_FORMAT_Z16_UNORM:
698 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
699 break;
700 default: /* 24-bit */
701 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
702 break;
703 case PIPE_FORMAT_Z32_FLOAT:
704 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
705 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
706 break;
707 }
708 }
709
710 /*
711 * Rasterizer
712 */
713
714 static uint32_t si_translate_fill(uint32_t func)
715 {
716 switch(func) {
717 case PIPE_POLYGON_MODE_FILL:
718 return V_028814_X_DRAW_TRIANGLES;
719 case PIPE_POLYGON_MODE_LINE:
720 return V_028814_X_DRAW_LINES;
721 case PIPE_POLYGON_MODE_POINT:
722 return V_028814_X_DRAW_POINTS;
723 default:
724 assert(0);
725 return V_028814_X_DRAW_POINTS;
726 }
727 }
728
729 static void *si_create_rs_state(struct pipe_context *ctx,
730 const struct pipe_rasterizer_state *state)
731 {
732 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
733 struct si_pm4_state *pm4 = &rs->pm4;
734 unsigned tmp, i;
735 float psize_min, psize_max;
736
737 if (!rs) {
738 return NULL;
739 }
740
741 rs->scissor_enable = state->scissor;
742 rs->two_side = state->light_twoside;
743 rs->multisample_enable = state->multisample;
744 rs->force_persample_interp = state->force_persample_interp;
745 rs->clip_plane_enable = state->clip_plane_enable;
746 rs->line_stipple_enable = state->line_stipple_enable;
747 rs->poly_stipple_enable = state->poly_stipple_enable;
748 rs->line_smooth = state->line_smooth;
749 rs->poly_smooth = state->poly_smooth;
750 rs->uses_poly_offset = state->offset_point || state->offset_line ||
751 state->offset_tri;
752 rs->clamp_fragment_color = state->clamp_fragment_color;
753 rs->flatshade = state->flatshade;
754 rs->sprite_coord_enable = state->sprite_coord_enable;
755 rs->rasterizer_discard = state->rasterizer_discard;
756 rs->pa_sc_line_stipple = state->line_stipple_enable ?
757 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
758 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
759 rs->pa_cl_clip_cntl =
760 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
761 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
762 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
763 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
764 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
765
766 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
767 S_0286D4_FLAT_SHADE_ENA(1) |
768 S_0286D4_PNT_SPRITE_ENA(1) |
769 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
770 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
771 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
772 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
773 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
774
775 /* point size 12.4 fixed point */
776 tmp = (unsigned)(state->point_size * 8.0);
777 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
778
779 if (state->point_size_per_vertex) {
780 psize_min = util_get_min_point_size(state);
781 psize_max = 8192;
782 } else {
783 /* Force the point size to be as if the vertex output was disabled. */
784 psize_min = state->point_size;
785 psize_max = state->point_size;
786 }
787 /* Divide by two, because 0.5 = 1 pixel. */
788 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
789 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
790 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
791
792 tmp = (unsigned)state->line_width * 8;
793 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
794 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
795 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
796 S_028A48_MSAA_ENABLE(state->multisample ||
797 state->poly_smooth ||
798 state->line_smooth) |
799 S_028A48_VPORT_SCISSOR_ENABLE(1));
800
801 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
802 S_028BE4_PIX_CENTER(state->half_pixel_center) |
803 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
804
805 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
806 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
807 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
808 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
809 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
810 S_028814_FACE(!state->front_ccw) |
811 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
812 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
813 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
814 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
815 state->fill_back != PIPE_POLYGON_MODE_FILL) |
816 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
817 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
818 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
819 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
820
821 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
822 for (i = 0; i < 3; i++) {
823 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
824 float offset_units = state->offset_units;
825 float offset_scale = state->offset_scale * 16.0f;
826 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
827
828 if (!state->offset_units_unscaled) {
829 switch (i) {
830 case 0: /* 16-bit zbuffer */
831 offset_units *= 4.0f;
832 pa_su_poly_offset_db_fmt_cntl =
833 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
834 break;
835 case 1: /* 24-bit zbuffer */
836 offset_units *= 2.0f;
837 pa_su_poly_offset_db_fmt_cntl =
838 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
839 break;
840 case 2: /* 32-bit zbuffer */
841 offset_units *= 1.0f;
842 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
843 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
844 break;
845 }
846 }
847
848 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
849 fui(offset_scale));
850 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
851 fui(offset_units));
852 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
853 fui(offset_scale));
854 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
855 fui(offset_units));
856 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
857 pa_su_poly_offset_db_fmt_cntl);
858 }
859
860 return rs;
861 }
862
863 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
864 {
865 struct si_context *sctx = (struct si_context *)ctx;
866 struct si_state_rasterizer *old_rs =
867 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
868 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
869
870 if (!state)
871 return;
872
873 if (sctx->framebuffer.nr_samples > 1 &&
874 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
875 si_mark_atom_dirty(sctx, &sctx->db_render_state);
876
877 if (sctx->b.family >= CHIP_POLARIS10)
878 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
879 }
880
881 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
882
883 si_pm4_bind_state(sctx, rasterizer, rs);
884 si_update_poly_offset_state(sctx);
885
886 si_mark_atom_dirty(sctx, &sctx->clip_regs);
887 sctx->do_update_shaders = true;
888 }
889
890 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
891 {
892 struct si_context *sctx = (struct si_context *)ctx;
893
894 if (sctx->queued.named.rasterizer == state)
895 si_pm4_bind_state(sctx, poly_offset, NULL);
896 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
897 }
898
899 /*
900 * infeered state between dsa and stencil ref
901 */
902 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
903 {
904 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
905 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
906 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
907
908 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
909 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
910 S_028430_STENCILMASK(dsa->valuemask[0]) |
911 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
912 S_028430_STENCILOPVAL(1));
913 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
914 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
915 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
916 S_028434_STENCILOPVAL_BF(1));
917 }
918
919 static void si_set_stencil_ref(struct pipe_context *ctx,
920 const struct pipe_stencil_ref *state)
921 {
922 struct si_context *sctx = (struct si_context *)ctx;
923
924 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
925 return;
926
927 sctx->stencil_ref.state = *state;
928 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
929 }
930
931
932 /*
933 * DSA
934 */
935
936 static uint32_t si_translate_stencil_op(int s_op)
937 {
938 switch (s_op) {
939 case PIPE_STENCIL_OP_KEEP:
940 return V_02842C_STENCIL_KEEP;
941 case PIPE_STENCIL_OP_ZERO:
942 return V_02842C_STENCIL_ZERO;
943 case PIPE_STENCIL_OP_REPLACE:
944 return V_02842C_STENCIL_REPLACE_TEST;
945 case PIPE_STENCIL_OP_INCR:
946 return V_02842C_STENCIL_ADD_CLAMP;
947 case PIPE_STENCIL_OP_DECR:
948 return V_02842C_STENCIL_SUB_CLAMP;
949 case PIPE_STENCIL_OP_INCR_WRAP:
950 return V_02842C_STENCIL_ADD_WRAP;
951 case PIPE_STENCIL_OP_DECR_WRAP:
952 return V_02842C_STENCIL_SUB_WRAP;
953 case PIPE_STENCIL_OP_INVERT:
954 return V_02842C_STENCIL_INVERT;
955 default:
956 R600_ERR("Unknown stencil op %d", s_op);
957 assert(0);
958 break;
959 }
960 return 0;
961 }
962
963 static void *si_create_dsa_state(struct pipe_context *ctx,
964 const struct pipe_depth_stencil_alpha_state *state)
965 {
966 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
967 struct si_pm4_state *pm4 = &dsa->pm4;
968 unsigned db_depth_control;
969 uint32_t db_stencil_control = 0;
970
971 if (!dsa) {
972 return NULL;
973 }
974
975 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
976 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
977 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
978 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
979
980 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
981 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
982 S_028800_ZFUNC(state->depth.func) |
983 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
984
985 /* stencil */
986 if (state->stencil[0].enabled) {
987 db_depth_control |= S_028800_STENCIL_ENABLE(1);
988 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
989 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
990 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
991 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
992
993 if (state->stencil[1].enabled) {
994 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
995 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
996 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
997 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
998 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
999 }
1000 }
1001
1002 /* alpha */
1003 if (state->alpha.enabled) {
1004 dsa->alpha_func = state->alpha.func;
1005
1006 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1007 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1008 } else {
1009 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1010 }
1011
1012 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1013 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1014 if (state->depth.bounds_test) {
1015 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1016 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1017 }
1018
1019 return dsa;
1020 }
1021
1022 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1023 {
1024 struct si_context *sctx = (struct si_context *)ctx;
1025 struct si_state_dsa *dsa = state;
1026
1027 if (!state)
1028 return;
1029
1030 si_pm4_bind_state(sctx, dsa, dsa);
1031
1032 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1033 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1034 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1035 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1036 }
1037 sctx->do_update_shaders = true;
1038 }
1039
1040 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1041 {
1042 struct si_context *sctx = (struct si_context *)ctx;
1043 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1044 }
1045
1046 static void *si_create_db_flush_dsa(struct si_context *sctx)
1047 {
1048 struct pipe_depth_stencil_alpha_state dsa = {};
1049
1050 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1051 }
1052
1053 /* DB RENDER STATE */
1054
1055 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1056 {
1057 struct si_context *sctx = (struct si_context*)ctx;
1058
1059 /* Pipeline stat & streamout queries. */
1060 if (enable) {
1061 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1062 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1063 } else {
1064 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1065 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1066 }
1067
1068 /* Occlusion queries. */
1069 if (sctx->occlusion_queries_disabled != !enable) {
1070 sctx->occlusion_queries_disabled = !enable;
1071 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1072 }
1073 }
1074
1075 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1076 {
1077 struct si_context *sctx = (struct si_context*)ctx;
1078
1079 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1080 }
1081
1082 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1083 {
1084 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1085 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1086 unsigned db_shader_control;
1087
1088 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1089
1090 /* DB_RENDER_CONTROL */
1091 if (sctx->dbcb_depth_copy_enabled ||
1092 sctx->dbcb_stencil_copy_enabled) {
1093 radeon_emit(cs,
1094 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1095 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1096 S_028000_COPY_CENTROID(1) |
1097 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1098 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1099 radeon_emit(cs,
1100 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1101 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1102 } else {
1103 radeon_emit(cs,
1104 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1105 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1106 }
1107
1108 /* DB_COUNT_CONTROL (occlusion queries) */
1109 if (sctx->b.num_occlusion_queries > 0 &&
1110 !sctx->occlusion_queries_disabled) {
1111 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1112
1113 if (sctx->b.chip_class >= CIK) {
1114 radeon_emit(cs,
1115 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1116 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1117 S_028004_ZPASS_ENABLE(1) |
1118 S_028004_SLICE_EVEN_ENABLE(1) |
1119 S_028004_SLICE_ODD_ENABLE(1));
1120 } else {
1121 radeon_emit(cs,
1122 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1123 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1124 }
1125 } else {
1126 /* Disable occlusion queries. */
1127 if (sctx->b.chip_class >= CIK) {
1128 radeon_emit(cs, 0);
1129 } else {
1130 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1131 }
1132 }
1133
1134 /* DB_RENDER_OVERRIDE2 */
1135 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1136 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1137 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1138 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1139
1140 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1141 sctx->ps_db_shader_control;
1142
1143 /* Bug workaround for smoothing (overrasterization) on SI. */
1144 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1145 db_shader_control &= C_02880C_Z_ORDER;
1146 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1147 }
1148
1149 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1150 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1151 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1152
1153 if (sctx->b.family == CHIP_STONEY &&
1154 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1155 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1156
1157 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1158 db_shader_control);
1159 }
1160
1161 /*
1162 * format translation
1163 */
1164 static uint32_t si_translate_colorformat(enum pipe_format format)
1165 {
1166 const struct util_format_description *desc = util_format_description(format);
1167
1168 #define HAS_SIZE(x,y,z,w) \
1169 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1170 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1171
1172 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1173 return V_028C70_COLOR_10_11_11;
1174
1175 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1176 return V_028C70_COLOR_INVALID;
1177
1178 /* hw cannot support mixed formats (except depth/stencil, since
1179 * stencil is not written to). */
1180 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1181 return V_028C70_COLOR_INVALID;
1182
1183 switch (desc->nr_channels) {
1184 case 1:
1185 switch (desc->channel[0].size) {
1186 case 8:
1187 return V_028C70_COLOR_8;
1188 case 16:
1189 return V_028C70_COLOR_16;
1190 case 32:
1191 return V_028C70_COLOR_32;
1192 }
1193 break;
1194 case 2:
1195 if (desc->channel[0].size == desc->channel[1].size) {
1196 switch (desc->channel[0].size) {
1197 case 8:
1198 return V_028C70_COLOR_8_8;
1199 case 16:
1200 return V_028C70_COLOR_16_16;
1201 case 32:
1202 return V_028C70_COLOR_32_32;
1203 }
1204 } else if (HAS_SIZE(8,24,0,0)) {
1205 return V_028C70_COLOR_24_8;
1206 } else if (HAS_SIZE(24,8,0,0)) {
1207 return V_028C70_COLOR_8_24;
1208 }
1209 break;
1210 case 3:
1211 if (HAS_SIZE(5,6,5,0)) {
1212 return V_028C70_COLOR_5_6_5;
1213 } else if (HAS_SIZE(32,8,24,0)) {
1214 return V_028C70_COLOR_X24_8_32_FLOAT;
1215 }
1216 break;
1217 case 4:
1218 if (desc->channel[0].size == desc->channel[1].size &&
1219 desc->channel[0].size == desc->channel[2].size &&
1220 desc->channel[0].size == desc->channel[3].size) {
1221 switch (desc->channel[0].size) {
1222 case 4:
1223 return V_028C70_COLOR_4_4_4_4;
1224 case 8:
1225 return V_028C70_COLOR_8_8_8_8;
1226 case 16:
1227 return V_028C70_COLOR_16_16_16_16;
1228 case 32:
1229 return V_028C70_COLOR_32_32_32_32;
1230 }
1231 } else if (HAS_SIZE(5,5,5,1)) {
1232 return V_028C70_COLOR_1_5_5_5;
1233 } else if (HAS_SIZE(10,10,10,2)) {
1234 return V_028C70_COLOR_2_10_10_10;
1235 }
1236 break;
1237 }
1238 return V_028C70_COLOR_INVALID;
1239 }
1240
1241 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1242 {
1243 if (SI_BIG_ENDIAN) {
1244 switch(colorformat) {
1245 /* 8-bit buffers. */
1246 case V_028C70_COLOR_8:
1247 return V_028C70_ENDIAN_NONE;
1248
1249 /* 16-bit buffers. */
1250 case V_028C70_COLOR_5_6_5:
1251 case V_028C70_COLOR_1_5_5_5:
1252 case V_028C70_COLOR_4_4_4_4:
1253 case V_028C70_COLOR_16:
1254 case V_028C70_COLOR_8_8:
1255 return V_028C70_ENDIAN_8IN16;
1256
1257 /* 32-bit buffers. */
1258 case V_028C70_COLOR_8_8_8_8:
1259 case V_028C70_COLOR_2_10_10_10:
1260 case V_028C70_COLOR_8_24:
1261 case V_028C70_COLOR_24_8:
1262 case V_028C70_COLOR_16_16:
1263 return V_028C70_ENDIAN_8IN32;
1264
1265 /* 64-bit buffers. */
1266 case V_028C70_COLOR_16_16_16_16:
1267 return V_028C70_ENDIAN_8IN16;
1268
1269 case V_028C70_COLOR_32_32:
1270 return V_028C70_ENDIAN_8IN32;
1271
1272 /* 128-bit buffers. */
1273 case V_028C70_COLOR_32_32_32_32:
1274 return V_028C70_ENDIAN_8IN32;
1275 default:
1276 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1277 }
1278 } else {
1279 return V_028C70_ENDIAN_NONE;
1280 }
1281 }
1282
1283 static uint32_t si_translate_dbformat(enum pipe_format format)
1284 {
1285 switch (format) {
1286 case PIPE_FORMAT_Z16_UNORM:
1287 return V_028040_Z_16;
1288 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1289 case PIPE_FORMAT_X8Z24_UNORM:
1290 case PIPE_FORMAT_Z24X8_UNORM:
1291 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1292 return V_028040_Z_24; /* deprecated on SI */
1293 case PIPE_FORMAT_Z32_FLOAT:
1294 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1295 return V_028040_Z_32_FLOAT;
1296 default:
1297 return V_028040_Z_INVALID;
1298 }
1299 }
1300
1301 /*
1302 * Texture translation
1303 */
1304
1305 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1306 enum pipe_format format,
1307 const struct util_format_description *desc,
1308 int first_non_void)
1309 {
1310 struct si_screen *sscreen = (struct si_screen*)screen;
1311 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1312 sscreen->b.info.drm_minor >= 31) ||
1313 sscreen->b.info.drm_major == 3;
1314 bool uniform = true;
1315 int i;
1316
1317 /* Colorspace (return non-RGB formats directly). */
1318 switch (desc->colorspace) {
1319 /* Depth stencil formats */
1320 case UTIL_FORMAT_COLORSPACE_ZS:
1321 switch (format) {
1322 case PIPE_FORMAT_Z16_UNORM:
1323 return V_008F14_IMG_DATA_FORMAT_16;
1324 case PIPE_FORMAT_X24S8_UINT:
1325 case PIPE_FORMAT_Z24X8_UNORM:
1326 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1327 return V_008F14_IMG_DATA_FORMAT_8_24;
1328 case PIPE_FORMAT_X8Z24_UNORM:
1329 case PIPE_FORMAT_S8X24_UINT:
1330 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1331 return V_008F14_IMG_DATA_FORMAT_24_8;
1332 case PIPE_FORMAT_S8_UINT:
1333 return V_008F14_IMG_DATA_FORMAT_8;
1334 case PIPE_FORMAT_Z32_FLOAT:
1335 return V_008F14_IMG_DATA_FORMAT_32;
1336 case PIPE_FORMAT_X32_S8X24_UINT:
1337 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1338 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1339 default:
1340 goto out_unknown;
1341 }
1342
1343 case UTIL_FORMAT_COLORSPACE_YUV:
1344 goto out_unknown; /* TODO */
1345
1346 case UTIL_FORMAT_COLORSPACE_SRGB:
1347 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1348 goto out_unknown;
1349 break;
1350
1351 default:
1352 break;
1353 }
1354
1355 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1356 if (!enable_compressed_formats)
1357 goto out_unknown;
1358
1359 switch (format) {
1360 case PIPE_FORMAT_RGTC1_SNORM:
1361 case PIPE_FORMAT_LATC1_SNORM:
1362 case PIPE_FORMAT_RGTC1_UNORM:
1363 case PIPE_FORMAT_LATC1_UNORM:
1364 return V_008F14_IMG_DATA_FORMAT_BC4;
1365 case PIPE_FORMAT_RGTC2_SNORM:
1366 case PIPE_FORMAT_LATC2_SNORM:
1367 case PIPE_FORMAT_RGTC2_UNORM:
1368 case PIPE_FORMAT_LATC2_UNORM:
1369 return V_008F14_IMG_DATA_FORMAT_BC5;
1370 default:
1371 goto out_unknown;
1372 }
1373 }
1374
1375 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1376 sscreen->b.family == CHIP_STONEY) {
1377 switch (format) {
1378 case PIPE_FORMAT_ETC1_RGB8:
1379 case PIPE_FORMAT_ETC2_RGB8:
1380 case PIPE_FORMAT_ETC2_SRGB8:
1381 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1382 case PIPE_FORMAT_ETC2_RGB8A1:
1383 case PIPE_FORMAT_ETC2_SRGB8A1:
1384 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1385 case PIPE_FORMAT_ETC2_RGBA8:
1386 case PIPE_FORMAT_ETC2_SRGBA8:
1387 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1388 case PIPE_FORMAT_ETC2_R11_UNORM:
1389 case PIPE_FORMAT_ETC2_R11_SNORM:
1390 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1391 case PIPE_FORMAT_ETC2_RG11_UNORM:
1392 case PIPE_FORMAT_ETC2_RG11_SNORM:
1393 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1394 default:
1395 goto out_unknown;
1396 }
1397 }
1398
1399 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1400 if (!enable_compressed_formats)
1401 goto out_unknown;
1402
1403 switch (format) {
1404 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1405 case PIPE_FORMAT_BPTC_SRGBA:
1406 return V_008F14_IMG_DATA_FORMAT_BC7;
1407 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1408 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1409 return V_008F14_IMG_DATA_FORMAT_BC6;
1410 default:
1411 goto out_unknown;
1412 }
1413 }
1414
1415 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1416 switch (format) {
1417 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1418 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1419 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1420 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1421 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1422 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1423 default:
1424 goto out_unknown;
1425 }
1426 }
1427
1428 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1429 if (!enable_compressed_formats)
1430 goto out_unknown;
1431
1432 if (!util_format_s3tc_enabled) {
1433 goto out_unknown;
1434 }
1435
1436 switch (format) {
1437 case PIPE_FORMAT_DXT1_RGB:
1438 case PIPE_FORMAT_DXT1_RGBA:
1439 case PIPE_FORMAT_DXT1_SRGB:
1440 case PIPE_FORMAT_DXT1_SRGBA:
1441 return V_008F14_IMG_DATA_FORMAT_BC1;
1442 case PIPE_FORMAT_DXT3_RGBA:
1443 case PIPE_FORMAT_DXT3_SRGBA:
1444 return V_008F14_IMG_DATA_FORMAT_BC2;
1445 case PIPE_FORMAT_DXT5_RGBA:
1446 case PIPE_FORMAT_DXT5_SRGBA:
1447 return V_008F14_IMG_DATA_FORMAT_BC3;
1448 default:
1449 goto out_unknown;
1450 }
1451 }
1452
1453 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1454 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1455 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1456 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1457 }
1458
1459 /* R8G8Bx_SNORM - TODO CxV8U8 */
1460
1461 /* hw cannot support mixed formats (except depth/stencil, since only
1462 * depth is read).*/
1463 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1464 goto out_unknown;
1465
1466 /* See whether the components are of the same size. */
1467 for (i = 1; i < desc->nr_channels; i++) {
1468 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1469 }
1470
1471 /* Non-uniform formats. */
1472 if (!uniform) {
1473 switch(desc->nr_channels) {
1474 case 3:
1475 if (desc->channel[0].size == 5 &&
1476 desc->channel[1].size == 6 &&
1477 desc->channel[2].size == 5) {
1478 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1479 }
1480 goto out_unknown;
1481 case 4:
1482 if (desc->channel[0].size == 5 &&
1483 desc->channel[1].size == 5 &&
1484 desc->channel[2].size == 5 &&
1485 desc->channel[3].size == 1) {
1486 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1487 }
1488 if (desc->channel[0].size == 10 &&
1489 desc->channel[1].size == 10 &&
1490 desc->channel[2].size == 10 &&
1491 desc->channel[3].size == 2) {
1492 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1493 }
1494 goto out_unknown;
1495 }
1496 goto out_unknown;
1497 }
1498
1499 if (first_non_void < 0 || first_non_void > 3)
1500 goto out_unknown;
1501
1502 /* uniform formats */
1503 switch (desc->channel[first_non_void].size) {
1504 case 4:
1505 switch (desc->nr_channels) {
1506 #if 0 /* Not supported for render targets */
1507 case 2:
1508 return V_008F14_IMG_DATA_FORMAT_4_4;
1509 #endif
1510 case 4:
1511 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1512 }
1513 break;
1514 case 8:
1515 switch (desc->nr_channels) {
1516 case 1:
1517 return V_008F14_IMG_DATA_FORMAT_8;
1518 case 2:
1519 return V_008F14_IMG_DATA_FORMAT_8_8;
1520 case 4:
1521 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1522 }
1523 break;
1524 case 16:
1525 switch (desc->nr_channels) {
1526 case 1:
1527 return V_008F14_IMG_DATA_FORMAT_16;
1528 case 2:
1529 return V_008F14_IMG_DATA_FORMAT_16_16;
1530 case 4:
1531 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1532 }
1533 break;
1534 case 32:
1535 switch (desc->nr_channels) {
1536 case 1:
1537 return V_008F14_IMG_DATA_FORMAT_32;
1538 case 2:
1539 return V_008F14_IMG_DATA_FORMAT_32_32;
1540 #if 0 /* Not supported for render targets */
1541 case 3:
1542 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1543 #endif
1544 case 4:
1545 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1546 }
1547 }
1548
1549 out_unknown:
1550 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1551 return ~0;
1552 }
1553
1554 static unsigned si_tex_wrap(unsigned wrap)
1555 {
1556 switch (wrap) {
1557 default:
1558 case PIPE_TEX_WRAP_REPEAT:
1559 return V_008F30_SQ_TEX_WRAP;
1560 case PIPE_TEX_WRAP_CLAMP:
1561 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1562 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1563 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1564 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1565 return V_008F30_SQ_TEX_CLAMP_BORDER;
1566 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1567 return V_008F30_SQ_TEX_MIRROR;
1568 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1569 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1570 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1571 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1572 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1573 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1574 }
1575 }
1576
1577 static unsigned si_tex_mipfilter(unsigned filter)
1578 {
1579 switch (filter) {
1580 case PIPE_TEX_MIPFILTER_NEAREST:
1581 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1582 case PIPE_TEX_MIPFILTER_LINEAR:
1583 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1584 default:
1585 case PIPE_TEX_MIPFILTER_NONE:
1586 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1587 }
1588 }
1589
1590 static unsigned si_tex_compare(unsigned compare)
1591 {
1592 switch (compare) {
1593 default:
1594 case PIPE_FUNC_NEVER:
1595 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1596 case PIPE_FUNC_LESS:
1597 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1598 case PIPE_FUNC_EQUAL:
1599 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1600 case PIPE_FUNC_LEQUAL:
1601 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1602 case PIPE_FUNC_GREATER:
1603 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1604 case PIPE_FUNC_NOTEQUAL:
1605 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1606 case PIPE_FUNC_GEQUAL:
1607 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1608 case PIPE_FUNC_ALWAYS:
1609 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1610 }
1611 }
1612
1613 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1614 unsigned nr_samples)
1615 {
1616 if (view_target == PIPE_TEXTURE_CUBE ||
1617 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1618 res_target = view_target;
1619
1620 switch (res_target) {
1621 default:
1622 case PIPE_TEXTURE_1D:
1623 return V_008F1C_SQ_RSRC_IMG_1D;
1624 case PIPE_TEXTURE_1D_ARRAY:
1625 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1626 case PIPE_TEXTURE_2D:
1627 case PIPE_TEXTURE_RECT:
1628 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1629 V_008F1C_SQ_RSRC_IMG_2D;
1630 case PIPE_TEXTURE_2D_ARRAY:
1631 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1632 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1633 case PIPE_TEXTURE_3D:
1634 return V_008F1C_SQ_RSRC_IMG_3D;
1635 case PIPE_TEXTURE_CUBE:
1636 case PIPE_TEXTURE_CUBE_ARRAY:
1637 return V_008F1C_SQ_RSRC_IMG_CUBE;
1638 }
1639 }
1640
1641 /*
1642 * Format support testing
1643 */
1644
1645 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1646 {
1647 return si_translate_texformat(screen, format, util_format_description(format),
1648 util_format_get_first_non_void_channel(format)) != ~0U;
1649 }
1650
1651 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1652 const struct util_format_description *desc,
1653 int first_non_void)
1654 {
1655 unsigned type;
1656 int i;
1657
1658 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1659 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1660
1661 assert(first_non_void >= 0);
1662 type = desc->channel[first_non_void].type;
1663
1664 if (type == UTIL_FORMAT_TYPE_FIXED)
1665 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1666
1667 if (desc->nr_channels == 4 &&
1668 desc->channel[0].size == 10 &&
1669 desc->channel[1].size == 10 &&
1670 desc->channel[2].size == 10 &&
1671 desc->channel[3].size == 2)
1672 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1673
1674 /* See whether the components are of the same size. */
1675 for (i = 0; i < desc->nr_channels; i++) {
1676 if (desc->channel[first_non_void].size != desc->channel[i].size)
1677 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1678 }
1679
1680 switch (desc->channel[first_non_void].size) {
1681 case 8:
1682 switch (desc->nr_channels) {
1683 case 1:
1684 return V_008F0C_BUF_DATA_FORMAT_8;
1685 case 2:
1686 return V_008F0C_BUF_DATA_FORMAT_8_8;
1687 case 3:
1688 case 4:
1689 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1690 }
1691 break;
1692 case 16:
1693 switch (desc->nr_channels) {
1694 case 1:
1695 return V_008F0C_BUF_DATA_FORMAT_16;
1696 case 2:
1697 return V_008F0C_BUF_DATA_FORMAT_16_16;
1698 case 3:
1699 case 4:
1700 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1701 }
1702 break;
1703 case 32:
1704 /* From the Southern Islands ISA documentation about MTBUF:
1705 * 'Memory reads of data in memory that is 32 or 64 bits do not
1706 * undergo any format conversion.'
1707 */
1708 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1709 !desc->channel[first_non_void].pure_integer)
1710 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1711
1712 switch (desc->nr_channels) {
1713 case 1:
1714 return V_008F0C_BUF_DATA_FORMAT_32;
1715 case 2:
1716 return V_008F0C_BUF_DATA_FORMAT_32_32;
1717 case 3:
1718 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1719 case 4:
1720 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1721 }
1722 break;
1723 }
1724
1725 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1726 }
1727
1728 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1729 const struct util_format_description *desc,
1730 int first_non_void)
1731 {
1732 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1733 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1734
1735 assert(first_non_void >= 0);
1736
1737 switch (desc->channel[first_non_void].type) {
1738 case UTIL_FORMAT_TYPE_SIGNED:
1739 if (desc->channel[first_non_void].normalized)
1740 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1741 else if (desc->channel[first_non_void].pure_integer)
1742 return V_008F0C_BUF_NUM_FORMAT_SINT;
1743 else
1744 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1745 break;
1746 case UTIL_FORMAT_TYPE_UNSIGNED:
1747 if (desc->channel[first_non_void].normalized)
1748 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1749 else if (desc->channel[first_non_void].pure_integer)
1750 return V_008F0C_BUF_NUM_FORMAT_UINT;
1751 else
1752 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1753 break;
1754 case UTIL_FORMAT_TYPE_FLOAT:
1755 default:
1756 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1757 }
1758 }
1759
1760 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1761 {
1762 const struct util_format_description *desc;
1763 int first_non_void;
1764 unsigned data_format;
1765
1766 desc = util_format_description(format);
1767 first_non_void = util_format_get_first_non_void_channel(format);
1768 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1769 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1770 }
1771
1772 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1773 {
1774 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1775 r600_translate_colorswap(format, false) != ~0U;
1776 }
1777
1778 static bool si_is_zs_format_supported(enum pipe_format format)
1779 {
1780 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1781 }
1782
1783 static boolean si_is_format_supported(struct pipe_screen *screen,
1784 enum pipe_format format,
1785 enum pipe_texture_target target,
1786 unsigned sample_count,
1787 unsigned usage)
1788 {
1789 unsigned retval = 0;
1790
1791 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1792 R600_ERR("r600: unsupported texture type %d\n", target);
1793 return false;
1794 }
1795
1796 if (!util_format_is_supported(format, usage))
1797 return false;
1798
1799 if (sample_count > 1) {
1800 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1801 return false;
1802
1803 if (usage & PIPE_BIND_SHADER_IMAGE)
1804 return false;
1805
1806 switch (sample_count) {
1807 case 2:
1808 case 4:
1809 case 8:
1810 break;
1811 case 16:
1812 if (format == PIPE_FORMAT_NONE)
1813 return true;
1814 else
1815 return false;
1816 default:
1817 return false;
1818 }
1819 }
1820
1821 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1822 PIPE_BIND_SHADER_IMAGE)) {
1823 if (target == PIPE_BUFFER) {
1824 if (si_is_vertex_format_supported(screen, format))
1825 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1826 PIPE_BIND_SHADER_IMAGE);
1827 } else {
1828 if (si_is_sampler_format_supported(screen, format))
1829 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1830 PIPE_BIND_SHADER_IMAGE);
1831 }
1832 }
1833
1834 if ((usage & (PIPE_BIND_RENDER_TARGET |
1835 PIPE_BIND_DISPLAY_TARGET |
1836 PIPE_BIND_SCANOUT |
1837 PIPE_BIND_SHARED |
1838 PIPE_BIND_BLENDABLE)) &&
1839 si_is_colorbuffer_format_supported(format)) {
1840 retval |= usage &
1841 (PIPE_BIND_RENDER_TARGET |
1842 PIPE_BIND_DISPLAY_TARGET |
1843 PIPE_BIND_SCANOUT |
1844 PIPE_BIND_SHARED);
1845 if (!util_format_is_pure_integer(format) &&
1846 !util_format_is_depth_or_stencil(format))
1847 retval |= usage & PIPE_BIND_BLENDABLE;
1848 }
1849
1850 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1851 si_is_zs_format_supported(format)) {
1852 retval |= PIPE_BIND_DEPTH_STENCIL;
1853 }
1854
1855 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1856 si_is_vertex_format_supported(screen, format)) {
1857 retval |= PIPE_BIND_VERTEX_BUFFER;
1858 }
1859
1860 if (usage & PIPE_BIND_TRANSFER_READ)
1861 retval |= PIPE_BIND_TRANSFER_READ;
1862 if (usage & PIPE_BIND_TRANSFER_WRITE)
1863 retval |= PIPE_BIND_TRANSFER_WRITE;
1864
1865 if ((usage & PIPE_BIND_LINEAR) &&
1866 !util_format_is_compressed(format) &&
1867 !(usage & PIPE_BIND_DEPTH_STENCIL))
1868 retval |= PIPE_BIND_LINEAR;
1869
1870 return retval == usage;
1871 }
1872
1873 /*
1874 * framebuffer handling
1875 */
1876
1877 static void si_choose_spi_color_formats(struct r600_surface *surf,
1878 unsigned format, unsigned swap,
1879 unsigned ntype, bool is_depth)
1880 {
1881 /* Alpha is needed for alpha-to-coverage.
1882 * Blending may be with or without alpha.
1883 */
1884 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1885 unsigned alpha = 0; /* exports alpha, but may not support blending */
1886 unsigned blend = 0; /* supports blending, but may not export alpha */
1887 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1888
1889 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1890 * Other chips have multiple choices, though they are not necessarily better.
1891 */
1892 switch (format) {
1893 case V_028C70_COLOR_5_6_5:
1894 case V_028C70_COLOR_1_5_5_5:
1895 case V_028C70_COLOR_5_5_5_1:
1896 case V_028C70_COLOR_4_4_4_4:
1897 case V_028C70_COLOR_10_11_11:
1898 case V_028C70_COLOR_11_11_10:
1899 case V_028C70_COLOR_8:
1900 case V_028C70_COLOR_8_8:
1901 case V_028C70_COLOR_8_8_8_8:
1902 case V_028C70_COLOR_10_10_10_2:
1903 case V_028C70_COLOR_2_10_10_10:
1904 if (ntype == V_028C70_NUMBER_UINT)
1905 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1906 else if (ntype == V_028C70_NUMBER_SINT)
1907 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1908 else
1909 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1910 break;
1911
1912 case V_028C70_COLOR_16:
1913 case V_028C70_COLOR_16_16:
1914 case V_028C70_COLOR_16_16_16_16:
1915 if (ntype == V_028C70_NUMBER_UNORM ||
1916 ntype == V_028C70_NUMBER_SNORM) {
1917 /* UNORM16 and SNORM16 don't support blending */
1918 if (ntype == V_028C70_NUMBER_UNORM)
1919 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1920 else
1921 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1922
1923 /* Use 32 bits per channel for blending. */
1924 if (format == V_028C70_COLOR_16) {
1925 if (swap == V_028C70_SWAP_STD) { /* R */
1926 blend = V_028714_SPI_SHADER_32_R;
1927 blend_alpha = V_028714_SPI_SHADER_32_AR;
1928 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1929 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1930 else
1931 assert(0);
1932 } else if (format == V_028C70_COLOR_16_16) {
1933 if (swap == V_028C70_SWAP_STD) { /* RG */
1934 blend = V_028714_SPI_SHADER_32_GR;
1935 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1936 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1937 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1938 else
1939 assert(0);
1940 } else /* 16_16_16_16 */
1941 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1942 } else if (ntype == V_028C70_NUMBER_UINT)
1943 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1944 else if (ntype == V_028C70_NUMBER_SINT)
1945 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1946 else if (ntype == V_028C70_NUMBER_FLOAT)
1947 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1948 else
1949 assert(0);
1950 break;
1951
1952 case V_028C70_COLOR_32:
1953 if (swap == V_028C70_SWAP_STD) { /* R */
1954 blend = normal = V_028714_SPI_SHADER_32_R;
1955 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1956 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1957 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1958 else
1959 assert(0);
1960 break;
1961
1962 case V_028C70_COLOR_32_32:
1963 if (swap == V_028C70_SWAP_STD) { /* RG */
1964 blend = normal = V_028714_SPI_SHADER_32_GR;
1965 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1966 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1967 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1968 else
1969 assert(0);
1970 break;
1971
1972 case V_028C70_COLOR_32_32_32_32:
1973 case V_028C70_COLOR_8_24:
1974 case V_028C70_COLOR_24_8:
1975 case V_028C70_COLOR_X24_8_32_FLOAT:
1976 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1977 break;
1978
1979 default:
1980 assert(0);
1981 return;
1982 }
1983
1984 /* The DB->CB copy needs 32_ABGR. */
1985 if (is_depth)
1986 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1987
1988 surf->spi_shader_col_format = normal;
1989 surf->spi_shader_col_format_alpha = alpha;
1990 surf->spi_shader_col_format_blend = blend;
1991 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1992 }
1993
1994 static void si_initialize_color_surface(struct si_context *sctx,
1995 struct r600_surface *surf)
1996 {
1997 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1998 unsigned color_info, color_attrib, color_view;
1999 unsigned format, swap, ntype, endian;
2000 const struct util_format_description *desc;
2001 int i;
2002 unsigned blend_clamp = 0, blend_bypass = 0;
2003
2004 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2005 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2006
2007 desc = util_format_description(surf->base.format);
2008 for (i = 0; i < 4; i++) {
2009 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2010 break;
2011 }
2012 }
2013 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2014 ntype = V_028C70_NUMBER_FLOAT;
2015 } else {
2016 ntype = V_028C70_NUMBER_UNORM;
2017 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2018 ntype = V_028C70_NUMBER_SRGB;
2019 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2020 if (desc->channel[i].pure_integer) {
2021 ntype = V_028C70_NUMBER_SINT;
2022 } else {
2023 assert(desc->channel[i].normalized);
2024 ntype = V_028C70_NUMBER_SNORM;
2025 }
2026 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2027 if (desc->channel[i].pure_integer) {
2028 ntype = V_028C70_NUMBER_UINT;
2029 } else {
2030 assert(desc->channel[i].normalized);
2031 ntype = V_028C70_NUMBER_UNORM;
2032 }
2033 }
2034 }
2035
2036 format = si_translate_colorformat(surf->base.format);
2037 if (format == V_028C70_COLOR_INVALID) {
2038 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2039 }
2040 assert(format != V_028C70_COLOR_INVALID);
2041 swap = r600_translate_colorswap(surf->base.format, false);
2042 endian = si_colorformat_endian_swap(format);
2043
2044 /* blend clamp should be set for all NORM/SRGB types */
2045 if (ntype == V_028C70_NUMBER_UNORM ||
2046 ntype == V_028C70_NUMBER_SNORM ||
2047 ntype == V_028C70_NUMBER_SRGB)
2048 blend_clamp = 1;
2049
2050 /* set blend bypass according to docs if SINT/UINT or
2051 8/24 COLOR variants */
2052 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2053 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2054 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2055 blend_clamp = 0;
2056 blend_bypass = 1;
2057 }
2058
2059 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2060 (format == V_028C70_COLOR_8 ||
2061 format == V_028C70_COLOR_8_8 ||
2062 format == V_028C70_COLOR_8_8_8_8))
2063 surf->color_is_int8 = true;
2064
2065 color_info = S_028C70_FORMAT(format) |
2066 S_028C70_COMP_SWAP(swap) |
2067 S_028C70_BLEND_CLAMP(blend_clamp) |
2068 S_028C70_BLEND_BYPASS(blend_bypass) |
2069 S_028C70_NUMBER_TYPE(ntype) |
2070 S_028C70_ENDIAN(endian);
2071
2072 /* Intensity is implemented as Red, so treat it that way. */
2073 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2074 util_format_is_intensity(surf->base.format));
2075
2076 if (rtex->resource.b.b.nr_samples > 1) {
2077 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2078
2079 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2080 S_028C74_NUM_FRAGMENTS(log_samples);
2081
2082 if (rtex->fmask.size) {
2083 color_info |= S_028C70_COMPRESSION(1);
2084 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2085
2086 if (sctx->b.chip_class == SI) {
2087 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2088 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2089 }
2090 }
2091 }
2092
2093 surf->cb_color_view = color_view;
2094 surf->cb_color_info = color_info;
2095 surf->cb_color_attrib = color_attrib;
2096
2097 if (sctx->b.chip_class >= VI) {
2098 unsigned max_uncompressed_block_size = 2;
2099
2100 if (rtex->surface.nsamples > 1) {
2101 if (rtex->surface.bpe == 1)
2102 max_uncompressed_block_size = 0;
2103 else if (rtex->surface.bpe == 2)
2104 max_uncompressed_block_size = 1;
2105 }
2106
2107 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2108 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2109 }
2110
2111 /* This must be set for fast clear to work without FMASK. */
2112 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2113 unsigned bankh = util_logbase2(rtex->surface.bankh);
2114 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2115 }
2116
2117 /* Determine pixel shader export format */
2118 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2119
2120 surf->color_initialized = true;
2121 }
2122
2123 static void si_init_depth_surface(struct si_context *sctx,
2124 struct r600_surface *surf)
2125 {
2126 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2127 unsigned level = surf->base.u.tex.level;
2128 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2129 unsigned format;
2130 uint32_t z_info, s_info, db_depth_info;
2131 uint64_t z_offs, s_offs;
2132 uint32_t db_htile_data_base, db_htile_surface;
2133
2134 format = si_translate_dbformat(rtex->resource.b.b.format);
2135
2136 if (format == V_028040_Z_INVALID) {
2137 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2138 }
2139 assert(format != V_028040_Z_INVALID);
2140
2141 s_offs = z_offs = rtex->resource.gpu_address;
2142 z_offs += rtex->surface.level[level].offset;
2143 s_offs += rtex->surface.stencil_level[level].offset;
2144
2145 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2146
2147 z_info = S_028040_FORMAT(format);
2148 if (rtex->resource.b.b.nr_samples > 1) {
2149 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2150 }
2151
2152 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2153 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2154 else
2155 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2156
2157 if (sctx->b.chip_class >= CIK) {
2158 struct radeon_info *info = &sctx->screen->b.info;
2159 unsigned index = rtex->surface.tiling_index[level];
2160 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2161 unsigned macro_index = rtex->surface.macro_tile_index;
2162 unsigned tile_mode = info->si_tile_mode_array[index];
2163 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2164 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2165
2166 db_depth_info |=
2167 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2168 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2169 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2170 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2171 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2172 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2173 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2174 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2175 } else {
2176 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2177 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2178 tile_mode_index = si_tile_mode_index(rtex, level, true);
2179 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2180 }
2181
2182 /* HiZ aka depth buffer htile */
2183 /* use htile only for first level */
2184 if (rtex->htile_buffer && !level) {
2185 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2186 S_028040_ALLOW_EXPCLEAR(1);
2187
2188 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2189 /* Workaround: For a not yet understood reason, the
2190 * combination of MSAA, fast stencil clear and stencil
2191 * decompress messes with subsequent stencil buffer
2192 * uses. Problem was reproduced on Verde, Bonaire,
2193 * Tonga, and Carrizo.
2194 *
2195 * Disabling EXPCLEAR works around the problem.
2196 *
2197 * Check piglit's arb_texture_multisample-stencil-clear
2198 * test if you want to try changing this.
2199 */
2200 if (rtex->resource.b.b.nr_samples <= 1)
2201 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2202 } else
2203 /* Use all of the htile_buffer for depth if there's no stencil. */
2204 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2205
2206 uint64_t va = rtex->htile_buffer->gpu_address;
2207 db_htile_data_base = va >> 8;
2208 db_htile_surface = S_028ABC_FULL_CACHE(1);
2209 } else {
2210 db_htile_data_base = 0;
2211 db_htile_surface = 0;
2212 }
2213
2214 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2215
2216 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2217 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2218 surf->db_htile_data_base = db_htile_data_base;
2219 surf->db_depth_info = db_depth_info;
2220 surf->db_z_info = z_info;
2221 surf->db_stencil_info = s_info;
2222 surf->db_depth_base = z_offs >> 8;
2223 surf->db_stencil_base = s_offs >> 8;
2224 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2225 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2226 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2227 levelinfo->nblk_y) / 64 - 1);
2228 surf->db_htile_surface = db_htile_surface;
2229
2230 surf->depth_initialized = true;
2231 }
2232
2233 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2234 {
2235 for (int i = 0; i < state->nr_cbufs; ++i) {
2236 struct r600_surface *surf = NULL;
2237 struct r600_texture *rtex;
2238
2239 if (!state->cbufs[i])
2240 continue;
2241 surf = (struct r600_surface*)state->cbufs[i];
2242 rtex = (struct r600_texture*)surf->base.texture;
2243
2244 p_atomic_dec(&rtex->framebuffers_bound);
2245 }
2246 }
2247
2248 static void si_set_framebuffer_state(struct pipe_context *ctx,
2249 const struct pipe_framebuffer_state *state)
2250 {
2251 struct si_context *sctx = (struct si_context *)ctx;
2252 struct pipe_constant_buffer constbuf = {0};
2253 struct r600_surface *surf = NULL;
2254 struct r600_texture *rtex;
2255 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2256 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2257 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2258 int i;
2259
2260 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2261 if (!sctx->framebuffer.state.cbufs[i])
2262 continue;
2263
2264 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2265 if (rtex->dcc_gather_statistics)
2266 vi_separate_dcc_stop_query(ctx, rtex);
2267 }
2268
2269 /* Only flush TC when changing the framebuffer state, because
2270 * the only client not using TC that can change textures is
2271 * the framebuffer.
2272 *
2273 * Flush all CB and DB caches here because all buffers can be used
2274 * for write by both TC (with shader image stores) and CB/DB.
2275 */
2276 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2277 SI_CONTEXT_INV_GLOBAL_L2 |
2278 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2279 SI_CONTEXT_CS_PARTIAL_FLUSH;
2280
2281 /* Take the maximum of the old and new count. If the new count is lower,
2282 * dirtying is needed to disable the unbound colorbuffers.
2283 */
2284 sctx->framebuffer.dirty_cbufs |=
2285 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2286 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2287
2288 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2289 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2290
2291 sctx->framebuffer.spi_shader_col_format = 0;
2292 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2293 sctx->framebuffer.spi_shader_col_format_blend = 0;
2294 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2295 sctx->framebuffer.color_is_int8 = 0;
2296
2297 sctx->framebuffer.compressed_cb_mask = 0;
2298 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2299 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2300 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2301 util_format_is_pure_integer(state->cbufs[0]->format);
2302 sctx->framebuffer.any_dst_linear = false;
2303
2304 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2305 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2306
2307 for (i = 0; i < state->nr_cbufs; i++) {
2308 if (!state->cbufs[i])
2309 continue;
2310
2311 surf = (struct r600_surface*)state->cbufs[i];
2312 rtex = (struct r600_texture*)surf->base.texture;
2313
2314 if (!surf->color_initialized) {
2315 si_initialize_color_surface(sctx, surf);
2316 }
2317
2318 sctx->framebuffer.spi_shader_col_format |=
2319 surf->spi_shader_col_format << (i * 4);
2320 sctx->framebuffer.spi_shader_col_format_alpha |=
2321 surf->spi_shader_col_format_alpha << (i * 4);
2322 sctx->framebuffer.spi_shader_col_format_blend |=
2323 surf->spi_shader_col_format_blend << (i * 4);
2324 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2325 surf->spi_shader_col_format_blend_alpha << (i * 4);
2326
2327 if (surf->color_is_int8)
2328 sctx->framebuffer.color_is_int8 |= 1 << i;
2329
2330 if (rtex->fmask.size && rtex->cmask.size) {
2331 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2332 }
2333
2334 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2335 sctx->framebuffer.any_dst_linear = true;
2336
2337 r600_context_add_resource_size(ctx, surf->base.texture);
2338
2339 p_atomic_inc(&rtex->framebuffers_bound);
2340
2341 if (rtex->dcc_gather_statistics) {
2342 /* Dirty tracking must be enabled for DCC usage analysis. */
2343 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2344 vi_separate_dcc_start_query(ctx, rtex);
2345 }
2346 }
2347 /* Set the second SPI format for possible dual-src blending. */
2348 if (i == 1 && surf) {
2349 sctx->framebuffer.spi_shader_col_format |=
2350 surf->spi_shader_col_format << (i * 4);
2351 sctx->framebuffer.spi_shader_col_format_alpha |=
2352 surf->spi_shader_col_format_alpha << (i * 4);
2353 sctx->framebuffer.spi_shader_col_format_blend |=
2354 surf->spi_shader_col_format_blend << (i * 4);
2355 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2356 surf->spi_shader_col_format_blend_alpha << (i * 4);
2357 }
2358
2359 if (state->zsbuf) {
2360 surf = (struct r600_surface*)state->zsbuf;
2361
2362 if (!surf->depth_initialized) {
2363 si_init_depth_surface(sctx, surf);
2364 }
2365 r600_context_add_resource_size(ctx, surf->base.texture);
2366 }
2367
2368 si_update_poly_offset_state(sctx);
2369 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2370 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2371
2372 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2373 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2374
2375 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2376 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2377 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2378
2379 /* Set sample locations as fragment shader constants. */
2380 switch (sctx->framebuffer.nr_samples) {
2381 case 1:
2382 constbuf.user_buffer = sctx->b.sample_locations_1x;
2383 break;
2384 case 2:
2385 constbuf.user_buffer = sctx->b.sample_locations_2x;
2386 break;
2387 case 4:
2388 constbuf.user_buffer = sctx->b.sample_locations_4x;
2389 break;
2390 case 8:
2391 constbuf.user_buffer = sctx->b.sample_locations_8x;
2392 break;
2393 case 16:
2394 constbuf.user_buffer = sctx->b.sample_locations_16x;
2395 break;
2396 default:
2397 R600_ERR("Requested an invalid number of samples %i.\n",
2398 sctx->framebuffer.nr_samples);
2399 assert(0);
2400 }
2401 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2402 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2403
2404 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2405 }
2406
2407 sctx->need_check_render_feedback = true;
2408 sctx->do_update_shaders = true;
2409 }
2410
2411 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2412 {
2413 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2414 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2415 unsigned i, nr_cbufs = state->nr_cbufs;
2416 struct r600_texture *tex = NULL;
2417 struct r600_surface *cb = NULL;
2418 unsigned cb_color_info = 0;
2419
2420 /* Colorbuffers. */
2421 for (i = 0; i < nr_cbufs; i++) {
2422 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2423 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2424 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2425
2426 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2427 continue;
2428
2429 cb = (struct r600_surface*)state->cbufs[i];
2430 if (!cb) {
2431 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2432 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2433 continue;
2434 }
2435
2436 tex = (struct r600_texture *)cb->base.texture;
2437 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2438 &tex->resource, RADEON_USAGE_READWRITE,
2439 tex->surface.nsamples > 1 ?
2440 RADEON_PRIO_COLOR_BUFFER_MSAA :
2441 RADEON_PRIO_COLOR_BUFFER);
2442
2443 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2444 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2445 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2446 RADEON_PRIO_CMASK);
2447 }
2448
2449 if (tex->dcc_separate_buffer)
2450 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2451 tex->dcc_separate_buffer,
2452 RADEON_USAGE_READWRITE,
2453 RADEON_PRIO_DCC);
2454
2455 /* Compute mutable surface parameters. */
2456 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2457 slice_tile_max = cb->level_info->nblk_x *
2458 cb->level_info->nblk_y / 64 - 1;
2459 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2460
2461 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2462 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2463 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2464 cb_color_attrib = cb->cb_color_attrib |
2465 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2466
2467 if (tex->fmask.size) {
2468 if (sctx->b.chip_class >= CIK)
2469 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2470 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2471 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2472 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2473 } else {
2474 /* This must be set for fast clear to work without FMASK. */
2475 if (sctx->b.chip_class >= CIK)
2476 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2477 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2478 cb_color_fmask = cb_color_base;
2479 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2480 }
2481
2482 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2483
2484 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2485 bool is_msaa_resolve_dst = state->cbufs[0] &&
2486 state->cbufs[0]->texture->nr_samples > 1 &&
2487 state->cbufs[1] == &cb->base &&
2488 state->cbufs[1]->texture->nr_samples <= 1;
2489
2490 if (!is_msaa_resolve_dst)
2491 cb_color_info |= S_028C70_DCC_ENABLE(1);
2492 }
2493
2494 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2495 sctx->b.chip_class >= VI ? 14 : 13);
2496 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2497 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2498 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2499 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2500 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2501 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2502 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2503 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2504 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2505 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2506 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2507 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2508 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2509
2510 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2511 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2512 tex->dcc_offset +
2513 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2514 }
2515 /* set CB_COLOR1_INFO for possible dual-src blending */
2516 if (i == 1 && state->cbufs[0] &&
2517 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2518 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2519 cb_color_info);
2520 i++;
2521 }
2522 for (; i < 8 ; i++)
2523 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2524 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2525
2526 /* ZS buffer. */
2527 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2528 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2529 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2530
2531 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2532 &rtex->resource, RADEON_USAGE_READWRITE,
2533 zb->base.texture->nr_samples > 1 ?
2534 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2535 RADEON_PRIO_DEPTH_BUFFER);
2536
2537 if (zb->db_htile_data_base) {
2538 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2539 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2540 RADEON_PRIO_HTILE);
2541 }
2542
2543 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2544 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2545
2546 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2547 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2548 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2549 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2550 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2551 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2552 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2553 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2554 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2555 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2556 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2557
2558 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2559 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2560 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2561
2562 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2563 } else if (sctx->framebuffer.dirty_zsbuf) {
2564 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2565 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2566 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2567 }
2568
2569 /* Framebuffer dimensions. */
2570 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2571 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2572 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2573
2574 sctx->framebuffer.dirty_cbufs = 0;
2575 sctx->framebuffer.dirty_zsbuf = false;
2576 }
2577
2578 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2579 struct r600_atom *atom)
2580 {
2581 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2582 unsigned nr_samples = sctx->framebuffer.nr_samples;
2583
2584 /* Smoothing (only possible with nr_samples == 1) uses the same
2585 * sample locations as the MSAA it simulates.
2586 */
2587 if (nr_samples <= 1 && sctx->smoothing_enabled)
2588 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2589
2590 /* On Polaris, the small primitive filter uses the sample locations
2591 * even when MSAA is off, so we need to make sure they're set to 0.
2592 */
2593 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2594 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2595 sctx->msaa_sample_locs.nr_samples = nr_samples;
2596 cayman_emit_msaa_sample_locs(cs, nr_samples);
2597 }
2598
2599 if (sctx->b.family >= CHIP_POLARIS10) {
2600 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2601 unsigned small_prim_filter_cntl =
2602 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2603 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2604
2605 /* The alternative of setting sample locations to 0 would
2606 * require a DB flush to avoid Z errors, see
2607 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2608 */
2609 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2610 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2611
2612 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2613 small_prim_filter_cntl);
2614 }
2615 }
2616
2617 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2618 {
2619 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2620 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2621 /* 33% faster rendering to linear color buffers */
2622 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2623 unsigned sc_mode_cntl_1 =
2624 S_028A4C_WALK_SIZE(dst_is_linear) |
2625 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2626 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2627 /* always 1: */
2628 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2629 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2630 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2631 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2632 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2633 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2634
2635 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2636 sctx->ps_iter_samples,
2637 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2638 sc_mode_cntl_1);
2639 }
2640
2641 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2642 {
2643 struct si_context *sctx = (struct si_context *)ctx;
2644
2645 if (sctx->ps_iter_samples == min_samples)
2646 return;
2647
2648 sctx->ps_iter_samples = min_samples;
2649 sctx->do_update_shaders = true;
2650
2651 if (sctx->framebuffer.nr_samples > 1)
2652 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2653 }
2654
2655 /*
2656 * Samplers
2657 */
2658
2659 /**
2660 * Build the sampler view descriptor for a buffer texture.
2661 * @param state 256-bit descriptor; only the high 128 bits are filled in
2662 */
2663 void
2664 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2665 enum pipe_format format,
2666 unsigned first_element, unsigned last_element,
2667 uint32_t *state)
2668 {
2669 const struct util_format_description *desc;
2670 int first_non_void;
2671 uint64_t va;
2672 unsigned stride;
2673 unsigned num_records;
2674 unsigned num_format, data_format;
2675
2676 desc = util_format_description(format);
2677 first_non_void = util_format_get_first_non_void_channel(format);
2678 stride = desc->block.bits / 8;
2679 va = buf->gpu_address + first_element * stride;
2680 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2681 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2682
2683 num_records = last_element + 1 - first_element;
2684 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2685
2686 if (screen->b.chip_class >= VI)
2687 num_records *= stride;
2688
2689 state[4] = va;
2690 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2691 S_008F04_STRIDE(stride);
2692 state[6] = num_records;
2693 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2694 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2695 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2696 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2697 S_008F0C_NUM_FORMAT(num_format) |
2698 S_008F0C_DATA_FORMAT(data_format);
2699 }
2700
2701 /**
2702 * Build the sampler view descriptor for a texture.
2703 */
2704 void
2705 si_make_texture_descriptor(struct si_screen *screen,
2706 struct r600_texture *tex,
2707 bool sampler,
2708 enum pipe_texture_target target,
2709 enum pipe_format pipe_format,
2710 const unsigned char state_swizzle[4],
2711 unsigned first_level, unsigned last_level,
2712 unsigned first_layer, unsigned last_layer,
2713 unsigned width, unsigned height, unsigned depth,
2714 uint32_t *state,
2715 uint32_t *fmask_state)
2716 {
2717 struct pipe_resource *res = &tex->resource.b.b;
2718 const struct util_format_description *desc;
2719 unsigned char swizzle[4];
2720 int first_non_void;
2721 unsigned num_format, data_format, type;
2722 uint64_t va;
2723
2724 desc = util_format_description(pipe_format);
2725
2726 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2727 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2728 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2729
2730 switch (pipe_format) {
2731 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2732 case PIPE_FORMAT_X24S8_UINT:
2733 case PIPE_FORMAT_X32_S8X24_UINT:
2734 case PIPE_FORMAT_X8Z24_UNORM:
2735 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2736 break;
2737 default:
2738 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2739 }
2740 } else {
2741 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2742 }
2743
2744 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2745
2746 switch (pipe_format) {
2747 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2748 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2749 break;
2750 default:
2751 if (first_non_void < 0) {
2752 if (util_format_is_compressed(pipe_format)) {
2753 switch (pipe_format) {
2754 case PIPE_FORMAT_DXT1_SRGB:
2755 case PIPE_FORMAT_DXT1_SRGBA:
2756 case PIPE_FORMAT_DXT3_SRGBA:
2757 case PIPE_FORMAT_DXT5_SRGBA:
2758 case PIPE_FORMAT_BPTC_SRGBA:
2759 case PIPE_FORMAT_ETC2_SRGB8:
2760 case PIPE_FORMAT_ETC2_SRGB8A1:
2761 case PIPE_FORMAT_ETC2_SRGBA8:
2762 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2763 break;
2764 case PIPE_FORMAT_RGTC1_SNORM:
2765 case PIPE_FORMAT_LATC1_SNORM:
2766 case PIPE_FORMAT_RGTC2_SNORM:
2767 case PIPE_FORMAT_LATC2_SNORM:
2768 case PIPE_FORMAT_ETC2_R11_SNORM:
2769 case PIPE_FORMAT_ETC2_RG11_SNORM:
2770 /* implies float, so use SNORM/UNORM to determine
2771 whether data is signed or not */
2772 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2773 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2774 break;
2775 default:
2776 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2777 break;
2778 }
2779 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2780 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2781 } else {
2782 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2783 }
2784 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2785 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2786 } else {
2787 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2788
2789 switch (desc->channel[first_non_void].type) {
2790 case UTIL_FORMAT_TYPE_FLOAT:
2791 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2792 break;
2793 case UTIL_FORMAT_TYPE_SIGNED:
2794 if (desc->channel[first_non_void].normalized)
2795 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2796 else if (desc->channel[first_non_void].pure_integer)
2797 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2798 else
2799 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2800 break;
2801 case UTIL_FORMAT_TYPE_UNSIGNED:
2802 if (desc->channel[first_non_void].normalized)
2803 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2804 else if (desc->channel[first_non_void].pure_integer)
2805 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2806 else
2807 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2808 }
2809 }
2810 }
2811
2812 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2813 if (data_format == ~0) {
2814 data_format = 0;
2815 }
2816
2817 if (!sampler &&
2818 (res->target == PIPE_TEXTURE_CUBE ||
2819 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2820 res->target == PIPE_TEXTURE_3D)) {
2821 /* For the purpose of shader images, treat cube maps and 3D
2822 * textures as 2D arrays. For 3D textures, the address
2823 * calculations for mipmaps are different, so we rely on the
2824 * caller to effectively disable mipmaps.
2825 */
2826 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2827
2828 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2829 } else {
2830 type = si_tex_dim(res->target, target, res->nr_samples);
2831 }
2832
2833 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2834 height = 1;
2835 depth = res->array_size;
2836 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2837 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2838 if (sampler || res->target != PIPE_TEXTURE_3D)
2839 depth = res->array_size;
2840 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2841 depth = res->array_size / 6;
2842
2843 state[0] = 0;
2844 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2845 S_008F14_NUM_FORMAT(num_format));
2846 state[2] = (S_008F18_WIDTH(width - 1) |
2847 S_008F18_HEIGHT(height - 1));
2848 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2849 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2850 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2851 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2852 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2853 0 : first_level) |
2854 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2855 util_logbase2(res->nr_samples) :
2856 last_level) |
2857 S_008F1C_POW2_PAD(res->last_level > 0) |
2858 S_008F1C_TYPE(type));
2859 state[4] = S_008F20_DEPTH(depth - 1);
2860 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2861 S_008F24_LAST_ARRAY(last_layer));
2862 state[6] = 0;
2863 state[7] = 0;
2864
2865 if (tex->dcc_offset) {
2866 unsigned swap = r600_translate_colorswap(pipe_format, false);
2867
2868 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2869 } else {
2870 /* The last dword is unused by hw. The shader uses it to clear
2871 * bits in the first dword of sampler state.
2872 */
2873 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2874 if (first_level == last_level)
2875 state[7] = C_008F30_MAX_ANISO_RATIO;
2876 else
2877 state[7] = 0xffffffff;
2878 }
2879 }
2880
2881 /* Initialize the sampler view for FMASK. */
2882 if (tex->fmask.size) {
2883 uint32_t fmask_format;
2884
2885 va = tex->resource.gpu_address + tex->fmask.offset;
2886
2887 switch (res->nr_samples) {
2888 case 2:
2889 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2890 break;
2891 case 4:
2892 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2893 break;
2894 case 8:
2895 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2896 break;
2897 default:
2898 assert(0);
2899 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2900 }
2901
2902 fmask_state[0] = va >> 8;
2903 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2904 S_008F14_DATA_FORMAT(fmask_format) |
2905 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2906 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2907 S_008F18_HEIGHT(height - 1);
2908 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2909 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2910 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2911 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2912 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2913 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2914 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2915 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2916 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2917 S_008F24_LAST_ARRAY(last_layer);
2918 fmask_state[6] = 0;
2919 fmask_state[7] = 0;
2920 }
2921 }
2922
2923 /**
2924 * Create a sampler view.
2925 *
2926 * @param ctx context
2927 * @param texture texture
2928 * @param state sampler view template
2929 * @param width0 width0 override (for compressed textures as int)
2930 * @param height0 height0 override (for compressed textures as int)
2931 * @param force_level set the base address to the level (for compressed textures)
2932 */
2933 struct pipe_sampler_view *
2934 si_create_sampler_view_custom(struct pipe_context *ctx,
2935 struct pipe_resource *texture,
2936 const struct pipe_sampler_view *state,
2937 unsigned width0, unsigned height0,
2938 unsigned force_level)
2939 {
2940 struct si_context *sctx = (struct si_context*)ctx;
2941 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2942 struct r600_texture *tmp = (struct r600_texture*)texture;
2943 unsigned base_level, first_level, last_level;
2944 unsigned char state_swizzle[4];
2945 unsigned height, depth, width;
2946 unsigned last_layer = state->u.tex.last_layer;
2947 enum pipe_format pipe_format;
2948 const struct radeon_surf_level *surflevel;
2949
2950 if (!view)
2951 return NULL;
2952
2953 /* initialize base object */
2954 view->base = *state;
2955 view->base.texture = NULL;
2956 view->base.reference.count = 1;
2957 view->base.context = ctx;
2958
2959 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2960 if (!texture) {
2961 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2962 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2963 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2964 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2965 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2966 return &view->base;
2967 }
2968
2969 pipe_resource_reference(&view->base.texture, texture);
2970
2971 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2972 state->format == PIPE_FORMAT_S8X24_UINT ||
2973 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2974 state->format == PIPE_FORMAT_S8_UINT)
2975 view->is_stencil_sampler = true;
2976
2977 /* Buffer resource. */
2978 if (texture->target == PIPE_BUFFER) {
2979 si_make_buffer_descriptor(sctx->screen,
2980 (struct r600_resource *)texture,
2981 state->format,
2982 state->u.buf.first_element,
2983 state->u.buf.last_element,
2984 view->state);
2985
2986 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2987 return &view->base;
2988 }
2989
2990 state_swizzle[0] = state->swizzle_r;
2991 state_swizzle[1] = state->swizzle_g;
2992 state_swizzle[2] = state->swizzle_b;
2993 state_swizzle[3] = state->swizzle_a;
2994
2995 base_level = 0;
2996 first_level = state->u.tex.first_level;
2997 last_level = state->u.tex.last_level;
2998 width = width0;
2999 height = height0;
3000 depth = texture->depth0;
3001
3002 if (force_level) {
3003 assert(force_level == first_level &&
3004 force_level == last_level);
3005 base_level = force_level;
3006 first_level = 0;
3007 last_level = 0;
3008 width = u_minify(width, force_level);
3009 height = u_minify(height, force_level);
3010 depth = u_minify(depth, force_level);
3011 }
3012
3013 /* This is not needed if state trackers set last_layer correctly. */
3014 if (state->target == PIPE_TEXTURE_1D ||
3015 state->target == PIPE_TEXTURE_2D ||
3016 state->target == PIPE_TEXTURE_RECT ||
3017 state->target == PIPE_TEXTURE_CUBE)
3018 last_layer = state->u.tex.first_layer;
3019
3020 /* Texturing with separate depth and stencil. */
3021 pipe_format = state->format;
3022
3023 /* Depth/stencil texturing sometimes needs separate texture. */
3024 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3025 if (!tmp->flushed_depth_texture &&
3026 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3027 pipe_resource_reference(&view->base.texture, NULL);
3028 FREE(view);
3029 return NULL;
3030 }
3031
3032 assert(tmp->flushed_depth_texture);
3033
3034 /* Override format for the case where the flushed texture
3035 * contains only Z or only S.
3036 */
3037 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3038 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3039
3040 tmp = tmp->flushed_depth_texture;
3041 }
3042
3043 surflevel = tmp->surface.level;
3044
3045 if (tmp->db_compatible) {
3046 switch (pipe_format) {
3047 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3048 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3049 break;
3050 case PIPE_FORMAT_X8Z24_UNORM:
3051 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3052 /* Z24 is always stored like this for DB
3053 * compatibility.
3054 */
3055 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3056 break;
3057 case PIPE_FORMAT_X24S8_UINT:
3058 case PIPE_FORMAT_S8X24_UINT:
3059 case PIPE_FORMAT_X32_S8X24_UINT:
3060 pipe_format = PIPE_FORMAT_S8_UINT;
3061 surflevel = tmp->surface.stencil_level;
3062 break;
3063 default:;
3064 }
3065 }
3066
3067 si_make_texture_descriptor(sctx->screen, tmp, true,
3068 state->target, pipe_format, state_swizzle,
3069 first_level, last_level,
3070 state->u.tex.first_layer, last_layer,
3071 width, height, depth,
3072 view->state, view->fmask_state);
3073
3074 view->base_level_info = &surflevel[base_level];
3075 view->base_level = base_level;
3076 view->block_width = util_format_get_blockwidth(pipe_format);
3077 return &view->base;
3078 }
3079
3080 static struct pipe_sampler_view *
3081 si_create_sampler_view(struct pipe_context *ctx,
3082 struct pipe_resource *texture,
3083 const struct pipe_sampler_view *state)
3084 {
3085 return si_create_sampler_view_custom(ctx, texture, state,
3086 texture ? texture->width0 : 0,
3087 texture ? texture->height0 : 0, 0);
3088 }
3089
3090 static void si_sampler_view_destroy(struct pipe_context *ctx,
3091 struct pipe_sampler_view *state)
3092 {
3093 struct si_sampler_view *view = (struct si_sampler_view *)state;
3094
3095 if (state->texture && state->texture->target == PIPE_BUFFER)
3096 LIST_DELINIT(&view->list);
3097
3098 pipe_resource_reference(&state->texture, NULL);
3099 FREE(view);
3100 }
3101
3102 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3103 {
3104 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3105 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3106 (linear_filter &&
3107 (wrap == PIPE_TEX_WRAP_CLAMP ||
3108 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3109 }
3110
3111 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3112 {
3113 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3114 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3115
3116 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3117 state->border_color.ui[2] || state->border_color.ui[3]) &&
3118 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3119 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3120 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3121 }
3122
3123 static void *si_create_sampler_state(struct pipe_context *ctx,
3124 const struct pipe_sampler_state *state)
3125 {
3126 struct si_context *sctx = (struct si_context *)ctx;
3127 struct r600_common_screen *rscreen = sctx->b.screen;
3128 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3129 unsigned border_color_type, border_color_index = 0;
3130 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3131 : state->max_anisotropy;
3132 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3133
3134 if (!rstate) {
3135 return NULL;
3136 }
3137
3138 if (!sampler_state_needs_border_color(state))
3139 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3140 else if (state->border_color.f[0] == 0 &&
3141 state->border_color.f[1] == 0 &&
3142 state->border_color.f[2] == 0 &&
3143 state->border_color.f[3] == 0)
3144 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3145 else if (state->border_color.f[0] == 0 &&
3146 state->border_color.f[1] == 0 &&
3147 state->border_color.f[2] == 0 &&
3148 state->border_color.f[3] == 1)
3149 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3150 else if (state->border_color.f[0] == 1 &&
3151 state->border_color.f[1] == 1 &&
3152 state->border_color.f[2] == 1 &&
3153 state->border_color.f[3] == 1)
3154 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3155 else {
3156 int i;
3157
3158 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3159
3160 /* Check if the border has been uploaded already. */
3161 for (i = 0; i < sctx->border_color_count; i++)
3162 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3163 sizeof(state->border_color)) == 0)
3164 break;
3165
3166 if (i >= SI_MAX_BORDER_COLORS) {
3167 /* Getting 4096 unique border colors is very unlikely. */
3168 fprintf(stderr, "radeonsi: The border color table is full. "
3169 "Any new border colors will be just black. "
3170 "Please file a bug.\n");
3171 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3172 } else {
3173 if (i == sctx->border_color_count) {
3174 /* Upload a new border color. */
3175 memcpy(&sctx->border_color_table[i], &state->border_color,
3176 sizeof(state->border_color));
3177 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3178 &state->border_color,
3179 sizeof(state->border_color));
3180 sctx->border_color_count++;
3181 }
3182
3183 border_color_index = i;
3184 }
3185 }
3186
3187 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3188 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3189 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3190 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3191 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3192 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3193 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3194 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3195 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3196 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3197 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3198 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3199 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3200 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3201 S_008F38_MIP_POINT_PRECLAMP(1) |
3202 S_008F38_DISABLE_LSB_CEIL(1) |
3203 S_008F38_FILTER_PREC_FIX(1) |
3204 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3205 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3206 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3207 return rstate;
3208 }
3209
3210 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3211 {
3212 struct si_context *sctx = (struct si_context *)ctx;
3213
3214 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3215 return;
3216
3217 sctx->sample_mask.sample_mask = sample_mask;
3218 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3219 }
3220
3221 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3222 {
3223 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3224 unsigned mask = sctx->sample_mask.sample_mask;
3225
3226 /* Needed for line and polygon smoothing as well as for the Polaris
3227 * small primitive filter. We expect the state tracker to take care of
3228 * this for us.
3229 */
3230 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3231 (mask & 1 && sctx->blitter->running));
3232
3233 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3234 radeon_emit(cs, mask | (mask << 16));
3235 radeon_emit(cs, mask | (mask << 16));
3236 }
3237
3238 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3239 {
3240 free(state);
3241 }
3242
3243 /*
3244 * Vertex elements & buffers
3245 */
3246
3247 static void *si_create_vertex_elements(struct pipe_context *ctx,
3248 unsigned count,
3249 const struct pipe_vertex_element *elements)
3250 {
3251 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3252 int i;
3253
3254 assert(count <= SI_MAX_ATTRIBS);
3255 if (!v)
3256 return NULL;
3257
3258 v->count = count;
3259 for (i = 0; i < count; ++i) {
3260 const struct util_format_description *desc;
3261 unsigned data_format, num_format;
3262 int first_non_void;
3263
3264 desc = util_format_description(elements[i].src_format);
3265 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3266 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3267 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3268
3269 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3270 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3271 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3272 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3273 S_008F0C_NUM_FORMAT(num_format) |
3274 S_008F0C_DATA_FORMAT(data_format);
3275 v->format_size[i] = desc->block.bits / 8;
3276 }
3277 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3278
3279 return v;
3280 }
3281
3282 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3283 {
3284 struct si_context *sctx = (struct si_context *)ctx;
3285 struct si_vertex_element *v = (struct si_vertex_element*)state;
3286
3287 sctx->vertex_elements = v;
3288 sctx->vertex_buffers_dirty = true;
3289 sctx->do_update_shaders = true;
3290 }
3291
3292 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3293 {
3294 struct si_context *sctx = (struct si_context *)ctx;
3295
3296 if (sctx->vertex_elements == state)
3297 sctx->vertex_elements = NULL;
3298 FREE(state);
3299 }
3300
3301 static void si_set_vertex_buffers(struct pipe_context *ctx,
3302 unsigned start_slot, unsigned count,
3303 const struct pipe_vertex_buffer *buffers)
3304 {
3305 struct si_context *sctx = (struct si_context *)ctx;
3306 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3307 int i;
3308
3309 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3310
3311 if (buffers) {
3312 for (i = 0; i < count; i++) {
3313 const struct pipe_vertex_buffer *src = buffers + i;
3314 struct pipe_vertex_buffer *dsti = dst + i;
3315
3316 pipe_resource_reference(&dsti->buffer, src->buffer);
3317 dsti->buffer_offset = src->buffer_offset;
3318 dsti->stride = src->stride;
3319 r600_context_add_resource_size(ctx, src->buffer);
3320 }
3321 } else {
3322 for (i = 0; i < count; i++) {
3323 pipe_resource_reference(&dst[i].buffer, NULL);
3324 }
3325 }
3326 sctx->vertex_buffers_dirty = true;
3327 }
3328
3329 static void si_set_index_buffer(struct pipe_context *ctx,
3330 const struct pipe_index_buffer *ib)
3331 {
3332 struct si_context *sctx = (struct si_context *)ctx;
3333
3334 if (ib) {
3335 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3336 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3337 r600_context_add_resource_size(ctx, ib->buffer);
3338 } else {
3339 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3340 }
3341 }
3342
3343 /*
3344 * Misc
3345 */
3346
3347 static void si_set_tess_state(struct pipe_context *ctx,
3348 const float default_outer_level[4],
3349 const float default_inner_level[2])
3350 {
3351 struct si_context *sctx = (struct si_context *)ctx;
3352 struct pipe_constant_buffer cb;
3353 float array[8];
3354
3355 memcpy(array, default_outer_level, sizeof(float) * 4);
3356 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3357
3358 cb.buffer = NULL;
3359 cb.user_buffer = NULL;
3360 cb.buffer_size = sizeof(array);
3361
3362 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3363 (void*)array, sizeof(array),
3364 &cb.buffer_offset);
3365
3366 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3367 pipe_resource_reference(&cb.buffer, NULL);
3368 }
3369
3370 static void si_texture_barrier(struct pipe_context *ctx)
3371 {
3372 struct si_context *sctx = (struct si_context *)ctx;
3373
3374 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3375 SI_CONTEXT_INV_GLOBAL_L2 |
3376 SI_CONTEXT_FLUSH_AND_INV_CB |
3377 SI_CONTEXT_CS_PARTIAL_FLUSH;
3378 }
3379
3380 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3381 {
3382 struct si_context *sctx = (struct si_context *)ctx;
3383
3384 /* Subsequent commands must wait for all shader invocations to
3385 * complete. */
3386 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3387 SI_CONTEXT_CS_PARTIAL_FLUSH;
3388
3389 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3390 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3391 SI_CONTEXT_INV_VMEM_L1;
3392
3393 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3394 PIPE_BARRIER_SHADER_BUFFER |
3395 PIPE_BARRIER_TEXTURE |
3396 PIPE_BARRIER_IMAGE |
3397 PIPE_BARRIER_STREAMOUT_BUFFER |
3398 PIPE_BARRIER_GLOBAL_BUFFER)) {
3399 /* As far as I can tell, L1 contents are written back to L2
3400 * automatically at end of shader, but the contents of other
3401 * L1 caches might still be stale. */
3402 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3403 }
3404
3405 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3406 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3407
3408 /* Indices are read through TC L2 since VI. */
3409 if (sctx->screen->b.chip_class <= CIK)
3410 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3411 }
3412
3413 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3414 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3415
3416 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3417 PIPE_BARRIER_FRAMEBUFFER |
3418 PIPE_BARRIER_INDIRECT_BUFFER)) {
3419 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3420 *
3421 * We need to make sure that TC L1 & L2 are written back to
3422 * memory, because neither CPU accesses nor CB fetches consider
3423 * TC, but there's no need to invalidate any TC cache lines. */
3424 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3425 }
3426 }
3427
3428 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3429 {
3430 struct pipe_blend_state blend;
3431
3432 memset(&blend, 0, sizeof(blend));
3433 blend.independent_blend_enable = true;
3434 blend.rt[0].colormask = 0xf;
3435 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3436 }
3437
3438 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3439 bool include_draw_vbo)
3440 {
3441 si_need_cs_space((struct si_context*)ctx);
3442 }
3443
3444 static void si_init_config(struct si_context *sctx);
3445
3446 void si_init_state_functions(struct si_context *sctx)
3447 {
3448 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3449 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3450 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3451 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3452 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3453
3454 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3455 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3456 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3457 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3458 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3459 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3460 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3461 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3462 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3463 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3464 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3465
3466 sctx->b.b.create_blend_state = si_create_blend_state;
3467 sctx->b.b.bind_blend_state = si_bind_blend_state;
3468 sctx->b.b.delete_blend_state = si_delete_blend_state;
3469 sctx->b.b.set_blend_color = si_set_blend_color;
3470
3471 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3472 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3473 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3474
3475 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3476 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3477 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3478
3479 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3480 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3481 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3482 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3483 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3484
3485 sctx->b.b.set_clip_state = si_set_clip_state;
3486 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3487
3488 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3489 sctx->b.b.get_sample_position = cayman_get_sample_position;
3490
3491 sctx->b.b.create_sampler_state = si_create_sampler_state;
3492 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3493
3494 sctx->b.b.create_sampler_view = si_create_sampler_view;
3495 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3496
3497 sctx->b.b.set_sample_mask = si_set_sample_mask;
3498
3499 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3500 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3501 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3502 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3503 sctx->b.b.set_index_buffer = si_set_index_buffer;
3504
3505 sctx->b.b.texture_barrier = si_texture_barrier;
3506 sctx->b.b.memory_barrier = si_memory_barrier;
3507 sctx->b.b.set_min_samples = si_set_min_samples;
3508 sctx->b.b.set_tess_state = si_set_tess_state;
3509
3510 sctx->b.b.set_active_query_state = si_set_active_query_state;
3511 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3512 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3513
3514 sctx->b.b.draw_vbo = si_draw_vbo;
3515
3516 si_init_config(sctx);
3517 }
3518
3519 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3520 {
3521 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3522 }
3523
3524 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3525 struct r600_texture *rtex,
3526 struct radeon_bo_metadata *md)
3527 {
3528 struct si_screen *sscreen = (struct si_screen*)rscreen;
3529 struct pipe_resource *res = &rtex->resource.b.b;
3530 static const unsigned char swizzle[] = {
3531 PIPE_SWIZZLE_X,
3532 PIPE_SWIZZLE_Y,
3533 PIPE_SWIZZLE_Z,
3534 PIPE_SWIZZLE_W
3535 };
3536 uint32_t desc[8], i;
3537 bool is_array = util_resource_is_array_texture(res);
3538
3539 /* DRM 2.x.x doesn't support this. */
3540 if (rscreen->info.drm_major != 3)
3541 return;
3542
3543 assert(rtex->dcc_separate_buffer == NULL);
3544 assert(rtex->fmask.size == 0);
3545
3546 /* Metadata image format format version 1:
3547 * [0] = 1 (metadata format identifier)
3548 * [1] = (VENDOR_ID << 16) | PCI_ID
3549 * [2:9] = image descriptor for the whole resource
3550 * [2] is always 0, because the base address is cleared
3551 * [9] is the DCC offset bits [39:8] from the beginning of
3552 * the buffer
3553 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3554 */
3555
3556 md->metadata[0] = 1; /* metadata image format version 1 */
3557
3558 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3559 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3560
3561 si_make_texture_descriptor(sscreen, rtex, true,
3562 res->target, res->format,
3563 swizzle, 0, res->last_level, 0,
3564 is_array ? res->array_size - 1 : 0,
3565 res->width0, res->height0, res->depth0,
3566 desc, NULL);
3567
3568 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3569 rtex->surface.blk_w, false, desc);
3570
3571 /* Clear the base address and set the relative DCC offset. */
3572 desc[0] = 0;
3573 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3574 desc[7] = rtex->dcc_offset >> 8;
3575
3576 /* Dwords [2:9] contain the image descriptor. */
3577 memcpy(&md->metadata[2], desc, sizeof(desc));
3578
3579 /* Dwords [10:..] contain the mipmap level offsets. */
3580 for (i = 0; i <= res->last_level; i++)
3581 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3582
3583 md->size_metadata = (11 + res->last_level) * 4;
3584 }
3585
3586 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3587 struct r600_texture *rtex,
3588 struct radeon_bo_metadata *md)
3589 {
3590 uint32_t *desc = &md->metadata[2];
3591
3592 if (rscreen->chip_class < VI)
3593 return;
3594
3595 /* Return if DCC is enabled. The texture should be set up with it
3596 * already.
3597 */
3598 if (md->size_metadata >= 11 * 4 &&
3599 md->metadata[0] != 0 &&
3600 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3601 G_008F28_COMPRESSION_EN(desc[6])) {
3602 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3603 return;
3604 }
3605
3606 /* Disable DCC. These are always set by texture_from_handle and must
3607 * be cleared here.
3608 */
3609 rtex->dcc_offset = 0;
3610 }
3611
3612 void si_init_screen_state_functions(struct si_screen *sscreen)
3613 {
3614 sscreen->b.b.is_format_supported = si_is_format_supported;
3615 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3616 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3617 }
3618
3619 static void
3620 si_write_harvested_raster_configs(struct si_context *sctx,
3621 struct si_pm4_state *pm4,
3622 unsigned raster_config,
3623 unsigned raster_config_1)
3624 {
3625 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3626 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3627 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3628 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3629 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3630 unsigned rb_per_se = num_rb / num_se;
3631 unsigned se_mask[4];
3632 unsigned se;
3633
3634 se_mask[0] = ((1 << rb_per_se) - 1);
3635 se_mask[1] = (se_mask[0] << rb_per_se);
3636 se_mask[2] = (se_mask[1] << rb_per_se);
3637 se_mask[3] = (se_mask[2] << rb_per_se);
3638
3639 se_mask[0] &= rb_mask;
3640 se_mask[1] &= rb_mask;
3641 se_mask[2] &= rb_mask;
3642 se_mask[3] &= rb_mask;
3643
3644 assert(num_se == 1 || num_se == 2 || num_se == 4);
3645 assert(sh_per_se == 1 || sh_per_se == 2);
3646 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3647
3648 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3649 * fields are for, so I'm leaving them as their default
3650 * values. */
3651
3652 for (se = 0; se < num_se; se++) {
3653 unsigned raster_config_se = raster_config;
3654 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3655 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3656 int idx = (se / 2) * 2;
3657
3658 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3659 raster_config_se &= C_028350_SE_MAP;
3660
3661 if (!se_mask[idx]) {
3662 raster_config_se |=
3663 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3664 } else {
3665 raster_config_se |=
3666 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3667 }
3668 }
3669
3670 pkr0_mask &= rb_mask;
3671 pkr1_mask &= rb_mask;
3672 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3673 raster_config_se &= C_028350_PKR_MAP;
3674
3675 if (!pkr0_mask) {
3676 raster_config_se |=
3677 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3678 } else {
3679 raster_config_se |=
3680 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3681 }
3682 }
3683
3684 if (rb_per_se >= 2) {
3685 unsigned rb0_mask = 1 << (se * rb_per_se);
3686 unsigned rb1_mask = rb0_mask << 1;
3687
3688 rb0_mask &= rb_mask;
3689 rb1_mask &= rb_mask;
3690 if (!rb0_mask || !rb1_mask) {
3691 raster_config_se &= C_028350_RB_MAP_PKR0;
3692
3693 if (!rb0_mask) {
3694 raster_config_se |=
3695 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3696 } else {
3697 raster_config_se |=
3698 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3699 }
3700 }
3701
3702 if (rb_per_se > 2) {
3703 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3704 rb1_mask = rb0_mask << 1;
3705 rb0_mask &= rb_mask;
3706 rb1_mask &= rb_mask;
3707 if (!rb0_mask || !rb1_mask) {
3708 raster_config_se &= C_028350_RB_MAP_PKR1;
3709
3710 if (!rb0_mask) {
3711 raster_config_se |=
3712 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3713 } else {
3714 raster_config_se |=
3715 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3716 }
3717 }
3718 }
3719 }
3720
3721 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3722 if (sctx->b.chip_class < CIK)
3723 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3724 SE_INDEX(se) | SH_BROADCAST_WRITES |
3725 INSTANCE_BROADCAST_WRITES);
3726 else
3727 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3728 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3729 S_030800_INSTANCE_BROADCAST_WRITES(1));
3730 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3731 }
3732
3733 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3734 if (sctx->b.chip_class < CIK)
3735 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3736 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3737 INSTANCE_BROADCAST_WRITES);
3738 else {
3739 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3740 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3741 S_030800_INSTANCE_BROADCAST_WRITES(1));
3742
3743 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3744 (!se_mask[2] && !se_mask[3]))) {
3745 raster_config_1 &= C_028354_SE_PAIR_MAP;
3746
3747 if (!se_mask[0] && !se_mask[1]) {
3748 raster_config_1 |=
3749 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3750 } else {
3751 raster_config_1 |=
3752 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3753 }
3754 }
3755
3756 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3757 }
3758 }
3759
3760 static void si_init_config(struct si_context *sctx)
3761 {
3762 struct si_screen *sscreen = sctx->screen;
3763 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3764 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3765 unsigned raster_config, raster_config_1;
3766 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3767 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3768 int i;
3769
3770 if (!pm4)
3771 return;
3772
3773 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3774 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3775 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3776 si_pm4_cmd_end(pm4, false);
3777
3778 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3779 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3780
3781 /* FIXME calculate these values somehow ??? */
3782 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3783 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3784 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3785
3786 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3787 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3788
3789 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3790 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3791 if (sctx->b.chip_class < CIK)
3792 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3793 S_008A14_CLIP_VTX_REORDER_ENA(1));
3794
3795 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3796 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3797
3798 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3799
3800 for (i = 0; i < 16; i++) {
3801 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3802 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3803 }
3804
3805 switch (sctx->screen->b.family) {
3806 case CHIP_TAHITI:
3807 case CHIP_PITCAIRN:
3808 raster_config = 0x2a00126a;
3809 raster_config_1 = 0x00000000;
3810 break;
3811 case CHIP_VERDE:
3812 raster_config = 0x0000124a;
3813 raster_config_1 = 0x00000000;
3814 break;
3815 case CHIP_OLAND:
3816 raster_config = 0x00000082;
3817 raster_config_1 = 0x00000000;
3818 break;
3819 case CHIP_HAINAN:
3820 raster_config = 0x00000000;
3821 raster_config_1 = 0x00000000;
3822 break;
3823 case CHIP_BONAIRE:
3824 raster_config = 0x16000012;
3825 raster_config_1 = 0x00000000;
3826 break;
3827 case CHIP_HAWAII:
3828 raster_config = 0x3a00161a;
3829 raster_config_1 = 0x0000002e;
3830 break;
3831 case CHIP_FIJI:
3832 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3833 /* old kernels with old tiling config */
3834 raster_config = 0x16000012;
3835 raster_config_1 = 0x0000002a;
3836 } else {
3837 raster_config = 0x3a00161a;
3838 raster_config_1 = 0x0000002e;
3839 }
3840 break;
3841 case CHIP_POLARIS10:
3842 raster_config = 0x16000012;
3843 raster_config_1 = 0x0000002a;
3844 break;
3845 case CHIP_POLARIS11:
3846 raster_config = 0x16000012;
3847 raster_config_1 = 0x00000000;
3848 break;
3849 case CHIP_TONGA:
3850 raster_config = 0x16000012;
3851 raster_config_1 = 0x0000002a;
3852 break;
3853 case CHIP_ICELAND:
3854 if (num_rb == 1)
3855 raster_config = 0x00000000;
3856 else
3857 raster_config = 0x00000002;
3858 raster_config_1 = 0x00000000;
3859 break;
3860 case CHIP_CARRIZO:
3861 raster_config = 0x00000002;
3862 raster_config_1 = 0x00000000;
3863 break;
3864 case CHIP_KAVERI:
3865 /* KV should be 0x00000002, but that causes problems with radeon */
3866 raster_config = 0x00000000; /* 0x00000002 */
3867 raster_config_1 = 0x00000000;
3868 break;
3869 case CHIP_KABINI:
3870 case CHIP_MULLINS:
3871 case CHIP_STONEY:
3872 raster_config = 0x00000000;
3873 raster_config_1 = 0x00000000;
3874 break;
3875 default:
3876 fprintf(stderr,
3877 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3878 raster_config = 0x00000000;
3879 raster_config_1 = 0x00000000;
3880 break;
3881 }
3882
3883 /* Always use the default config when all backends are enabled
3884 * (or when we failed to determine the enabled backends).
3885 */
3886 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3887 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3888 raster_config);
3889 if (sctx->b.chip_class >= CIK)
3890 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3891 raster_config_1);
3892 } else {
3893 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3894 }
3895
3896 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3897 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3898 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3899 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3900 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3901 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3902 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3903
3904 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3905 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3906 S_028230_ER_TRI(0xA) |
3907 S_028230_ER_POINT(0xA) |
3908 S_028230_ER_RECT(0xA) |
3909 /* Required by DX10_DIAMOND_TEST_ENA: */
3910 S_028230_ER_LINE_LR(0x1A) |
3911 S_028230_ER_LINE_RL(0x26) |
3912 S_028230_ER_LINE_TB(0xA) |
3913 S_028230_ER_LINE_BT(0xA));
3914 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3915 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3916 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3917 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3918 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3919 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3920 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3921 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3922 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3923
3924 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3925 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3926 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3927
3928 if (sctx->b.chip_class >= CIK) {
3929 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3930 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3931 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3932 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3933
3934 if (sscreen->b.info.num_good_compute_units /
3935 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3936 /* Too few available compute units per SH. Disallowing
3937 * VS to run on CU0 could hurt us more than late VS
3938 * allocation would help.
3939 *
3940 * LATE_ALLOC_VS = 2 is the highest safe number.
3941 */
3942 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3943 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3944 } else {
3945 /* Set LATE_ALLOC_VS == 31. It should be less than
3946 * the number of scratch waves. Limitations:
3947 * - VS can't execute on CU0.
3948 * - If HS writes outputs to LDS, LS can't execute on CU0.
3949 */
3950 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3951 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3952 }
3953
3954 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3955 }
3956
3957 if (sctx->b.chip_class >= VI) {
3958 unsigned vgt_tess_distribution;
3959
3960 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3961 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3962 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3963 if (sctx->b.family < CHIP_POLARIS10)
3964 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3965 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3966
3967 vgt_tess_distribution =
3968 S_028B50_ACCUM_ISOLINE(32) |
3969 S_028B50_ACCUM_TRI(11) |
3970 S_028B50_ACCUM_QUAD(11) |
3971 S_028B50_DONUT_SPLIT(16);
3972
3973 /* Testing with Unigine Heaven extreme tesselation yielded best results
3974 * with TRAP_SPLIT = 3.
3975 */
3976 if (sctx->b.family == CHIP_FIJI ||
3977 sctx->b.family >= CHIP_POLARIS10)
3978 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3979
3980 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3981 } else {
3982 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3983 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3984 }
3985
3986 if (sctx->b.family == CHIP_STONEY)
3987 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3988
3989 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3990 if (sctx->b.chip_class >= CIK)
3991 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3992 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3993 RADEON_PRIO_BORDER_COLORS);
3994
3995 si_pm4_upload_indirect_buffer(sctx, pm4);
3996 sctx->init_config = pm4;
3997 }