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amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbuf
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_cmdbuf *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
91 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
92
93 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
94 * I think we don't have to do anything between IBs.
95 */
96 if (sctx->screen->dfsm_allowed &&
97 sctx->last_cb_target_mask != cb_target_mask) {
98 sctx->last_cb_target_mask = cb_target_mask;
99
100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
102 }
103
104 if (sctx->chip_class >= VI) {
105 /* DCC MSAA workaround for blending.
106 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
107 * COMBINER_DISABLE, but that would be more complicated.
108 */
109 bool oc_disable = (sctx->chip_class == VI ||
110 sctx->chip_class == GFX9) &&
111 blend &&
112 blend->blend_enable_4bit & cb_target_mask &&
113 sctx->framebuffer.nr_samples >= 2;
114
115 radeon_opt_set_context_reg(
116 sctx, R_028424_CB_DCC_CONTROL,
117 SI_TRACKED_CB_DCC_CONTROL,
118 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
119 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
120 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
121 }
122
123 /* RB+ register settings. */
124 if (sctx->screen->rbplus_allowed) {
125 unsigned spi_shader_col_format =
126 sctx->ps_shader.cso ?
127 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
128 unsigned sx_ps_downconvert = 0;
129 unsigned sx_blend_opt_epsilon = 0;
130 unsigned sx_blend_opt_control = 0;
131
132 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
133 struct r600_surface *surf =
134 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
135 unsigned format, swap, spi_format, colormask;
136 bool has_alpha, has_rgb;
137
138 if (!surf)
139 continue;
140
141 format = G_028C70_FORMAT(surf->cb_color_info);
142 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
143 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
144 colormask = (cb_target_mask >> (i * 4)) & 0xf;
145
146 /* Set if RGB and A are present. */
147 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
148
149 if (format == V_028C70_COLOR_8 ||
150 format == V_028C70_COLOR_16 ||
151 format == V_028C70_COLOR_32)
152 has_rgb = !has_alpha;
153 else
154 has_rgb = true;
155
156 /* Check the colormask and export format. */
157 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
158 has_rgb = false;
159 if (!(colormask & PIPE_MASK_A))
160 has_alpha = false;
161
162 if (spi_format == V_028714_SPI_SHADER_ZERO) {
163 has_rgb = false;
164 has_alpha = false;
165 }
166
167 /* Disable value checking for disabled channels. */
168 if (!has_rgb)
169 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
170 if (!has_alpha)
171 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
172
173 /* Enable down-conversion for 32bpp and smaller formats. */
174 switch (format) {
175 case V_028C70_COLOR_8:
176 case V_028C70_COLOR_8_8:
177 case V_028C70_COLOR_8_8_8_8:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
180 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
182 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
183 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
184 }
185 break;
186
187 case V_028C70_COLOR_5_6_5:
188 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
189 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
190 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
191 }
192 break;
193
194 case V_028C70_COLOR_1_5_5_5:
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
196 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
197 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
198 }
199 break;
200
201 case V_028C70_COLOR_4_4_4_4:
202 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
203 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
204 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
205 }
206 break;
207
208 case V_028C70_COLOR_32:
209 if (swap == V_028C70_SWAP_STD &&
210 spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV &&
213 spi_format == V_028714_SPI_SHADER_32_AR)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
215 break;
216
217 case V_028C70_COLOR_16:
218 case V_028C70_COLOR_16_16:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
224 if (swap == V_028C70_SWAP_STD ||
225 swap == V_028C70_SWAP_STD_REV)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
227 else
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
229 }
230 break;
231
232 case V_028C70_COLOR_10_11_11:
233 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
235 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
236 }
237 break;
238
239 case V_028C70_COLOR_2_10_10_10:
240 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
242 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
243 }
244 break;
245 }
246 }
247
248 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
249 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
250 SI_TRACKED_SX_PS_DOWNCONVERT,
251 sx_ps_downconvert, sx_blend_opt_epsilon,
252 sx_blend_opt_control);
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 PRINT_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 static void si_blend_check_commutativity(struct si_screen *sscreen,
374 struct si_state_blend *blend,
375 enum pipe_blend_func func,
376 enum pipe_blendfactor src,
377 enum pipe_blendfactor dst,
378 unsigned chanmask)
379 {
380 /* Src factor is allowed when it does not depend on Dst */
381 static const uint32_t src_allowed =
382 (1u << PIPE_BLENDFACTOR_ONE) |
383 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
384 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
386 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
387 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
389 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
397
398 if (dst == PIPE_BLENDFACTOR_ONE &&
399 (src_allowed & (1u << src))) {
400 /* Addition is commutative, but floating point addition isn't
401 * associative: subtle changes can be introduced via different
402 * rounding.
403 *
404 * Out-of-order is also non-deterministic, which means that
405 * this breaks OpenGL invariance requirements. So only enable
406 * out-of-order additive blending if explicitly allowed by a
407 * setting.
408 */
409 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
410 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
411 blend->commutative_4bit |= chanmask;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
425 *src_factor = PIPE_BLENDFACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == PIPE_BLEND_SUBTRACT)
430 *func = PIPE_BLEND_REVERSE_SUBTRACT;
431 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
432 *func = PIPE_BLEND_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
439 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
440 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
441 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
442 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
443 }
444
445 static void *si_create_blend_state_mode(struct pipe_context *ctx,
446 const struct pipe_blend_state *state,
447 unsigned mode)
448 {
449 struct si_context *sctx = (struct si_context*)ctx;
450 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
451 struct si_pm4_state *pm4 = &blend->pm4;
452 uint32_t sx_mrt_blend_opt[8] = {0};
453 uint32_t color_control = 0;
454
455 if (!blend)
456 return NULL;
457
458 blend->alpha_to_coverage = state->alpha_to_coverage;
459 blend->alpha_to_one = state->alpha_to_one;
460 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
461 blend->logicop_enable = state->logicop_enable;
462
463 if (state->logicop_enable) {
464 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
465 } else {
466 color_control |= S_028808_ROP3(0xcc);
467 }
468
469 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
472 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
475
476 if (state->alpha_to_coverage)
477 blend->need_src_alpha_4bit |= 0xf;
478
479 blend->cb_target_mask = 0;
480 blend->cb_target_enabled_4bit = 0;
481
482 for (int i = 0; i < 8; i++) {
483 /* state->rt entries > 0 only written if independent blending */
484 const int j = state->independent_blend_enable ? i : 0;
485
486 unsigned eqRGB = state->rt[j].rgb_func;
487 unsigned srcRGB = state->rt[j].rgb_src_factor;
488 unsigned dstRGB = state->rt[j].rgb_dst_factor;
489 unsigned eqA = state->rt[j].alpha_func;
490 unsigned srcA = state->rt[j].alpha_src_factor;
491 unsigned dstA = state->rt[j].alpha_dst_factor;
492
493 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
494 unsigned blend_cntl = 0;
495
496 sx_mrt_blend_opt[i] =
497 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
498 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
499
500 /* Only set dual source blending for MRT0 to avoid a hang. */
501 if (i >= 1 && blend->dual_src_blend) {
502 /* Vulkan does this for dual source blending. */
503 if (i == 1)
504 blend_cntl |= S_028780_ENABLE(1);
505
506 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
507 continue;
508 }
509
510 /* Only addition and subtraction equations are supported with
511 * dual source blending.
512 */
513 if (blend->dual_src_blend &&
514 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
515 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
518 continue;
519 }
520
521 /* cb_render_state will disable unused ones */
522 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
523 if (state->rt[j].colormask)
524 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
525
526 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 si_blend_check_commutativity(sctx->screen, blend,
532 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
533 si_blend_check_commutativity(sctx->screen, blend,
534 eqA, srcA, dstA, 0x8 << (4 * i));
535
536 /* Blending optimizations for RB+.
537 * These transformations don't change the behavior.
538 *
539 * First, get rid of DST in the blend factors:
540 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
541 */
542 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
543 PIPE_BLENDFACTOR_DST_COLOR,
544 PIPE_BLENDFACTOR_SRC_COLOR);
545 si_blend_remove_dst(&eqA, &srcA, &dstA,
546 PIPE_BLENDFACTOR_DST_COLOR,
547 PIPE_BLENDFACTOR_SRC_COLOR);
548 si_blend_remove_dst(&eqA, &srcA, &dstA,
549 PIPE_BLENDFACTOR_DST_ALPHA,
550 PIPE_BLENDFACTOR_SRC_ALPHA);
551
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
554 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
555 srcA_opt = si_translate_blend_opt_factor(srcA, true);
556 dstA_opt = si_translate_blend_opt_factor(dstA, true);
557
558 /* Handle interdependencies. */
559 if (si_blend_factor_uses_dst(srcRGB))
560 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
561 if (si_blend_factor_uses_dst(srcA))
562 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
563
564 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
565 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
566 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
567 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
568 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
569
570 /* Set the final value. */
571 sx_mrt_blend_opt[i] =
572 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
573 S_028760_COLOR_DST_OPT(dstRGB_opt) |
574 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
575 S_028760_ALPHA_SRC_OPT(srcA_opt) |
576 S_028760_ALPHA_DST_OPT(dstA_opt) |
577 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
578
579 /* Set blend state. */
580 blend_cntl |= S_028780_ENABLE(1);
581 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
582 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
583 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
584
585 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
586 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
587 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
588 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
589 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
590 }
591 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
592
593 blend->blend_enable_4bit |= 0xfu << (i * 4);
594
595 /* This is only important for formats without alpha. */
596 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
598 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
599 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
600 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
601 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
602 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
603 }
604
605 if (blend->cb_target_mask) {
606 color_control |= S_028808_MODE(mode);
607 } else {
608 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
609 }
610
611 if (sctx->screen->rbplus_allowed) {
612 /* Disable RB+ blend optimizations for dual source blending.
613 * Vulkan does this.
614 */
615 if (blend->dual_src_blend) {
616 for (int i = 0; i < 8; i++) {
617 sx_mrt_blend_opt[i] =
618 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
620 }
621 }
622
623 for (int i = 0; i < 8; i++)
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
625 sx_mrt_blend_opt[i]);
626
627 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
628 if (blend->dual_src_blend || state->logicop_enable ||
629 mode == V_028808_CB_RESOLVE)
630 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
631 }
632
633 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
634 return blend;
635 }
636
637 static void *si_create_blend_state(struct pipe_context *ctx,
638 const struct pipe_blend_state *state)
639 {
640 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
641 }
642
643 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 struct si_state_blend *old_blend = sctx->queued.named.blend;
647 struct si_state_blend *blend = (struct si_state_blend *)state;
648
649 if (!state)
650 return;
651
652 si_pm4_bind_state(sctx, blend, state);
653
654 if (!old_blend ||
655 old_blend->cb_target_mask != blend->cb_target_mask ||
656 old_blend->dual_src_blend != blend->dual_src_blend ||
657 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
658 sctx->framebuffer.nr_samples >= 2 &&
659 sctx->screen->dcc_msaa_allowed))
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
661
662 if (!old_blend ||
663 old_blend->cb_target_mask != blend->cb_target_mask ||
664 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
665 old_blend->alpha_to_one != blend->alpha_to_one ||
666 old_blend->dual_src_blend != blend->dual_src_blend ||
667 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
668 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
669 sctx->do_update_shaders = true;
670
671 if (sctx->screen->dpbb_allowed &&
672 (!old_blend ||
673 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
676 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
677
678 if (sctx->screen->has_out_of_order_rast &&
679 (!old_blend ||
680 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
681 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
682 old_blend->commutative_4bit != blend->commutative_4bit ||
683 old_blend->logicop_enable != blend->logicop_enable)))
684 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
685 }
686
687 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
691 }
692
693 static void si_set_blend_color(struct pipe_context *ctx,
694 const struct pipe_blend_color *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 static const struct pipe_blend_color zeros;
698
699 sctx->blend_color.state = *state;
700 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
701 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
702 }
703
704 static void si_emit_blend_color(struct si_context *sctx)
705 {
706 struct radeon_cmdbuf *cs = sctx->gfx_cs;
707
708 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
709 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
710 }
711
712 /*
713 * Clipping
714 */
715
716 static void si_set_clip_state(struct pipe_context *ctx,
717 const struct pipe_clip_state *state)
718 {
719 struct si_context *sctx = (struct si_context *)ctx;
720 struct pipe_constant_buffer cb;
721 static const struct pipe_clip_state zeros;
722
723 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
724 return;
725
726 sctx->clip_state.state = *state;
727 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
728 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
729
730 cb.buffer = NULL;
731 cb.user_buffer = state->ucp;
732 cb.buffer_offset = 0;
733 cb.buffer_size = 4*4*8;
734 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
735 pipe_resource_reference(&cb.buffer, NULL);
736 }
737
738 static void si_emit_clip_state(struct si_context *sctx)
739 {
740 struct radeon_cmdbuf *cs = sctx->gfx_cs;
741
742 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
743 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
744 }
745
746 static void si_emit_clip_regs(struct si_context *sctx)
747 {
748 struct si_shader *vs = si_get_vs_state(sctx);
749 struct si_shader_selector *vs_sel = vs->selector;
750 struct tgsi_shader_info *info = &vs_sel->info;
751 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
752 unsigned window_space =
753 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
754 unsigned clipdist_mask = vs_sel->clipdist_mask;
755 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
756 unsigned culldist_mask = vs_sel->culldist_mask;
757 unsigned total_mask;
758
759 if (vs->key.opt.clip_disable) {
760 assert(!info->culldist_writemask);
761 clipdist_mask = 0;
762 culldist_mask = 0;
763 }
764 total_mask = clipdist_mask | culldist_mask;
765
766 /* Clip distances on points have no effect, so need to be implemented
767 * as cull distances. This applies for the clipvertex case as well.
768 *
769 * Setting this for primitives other than points should have no adverse
770 * effects.
771 */
772 clipdist_mask &= rs->clip_plane_enable;
773 culldist_mask |= clipdist_mask;
774
775 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
776 SI_TRACKED_PA_CL_VS_OUT_CNTL,
777 vs_sel->pa_cl_vs_out_cntl |
778 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
779 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
780 clipdist_mask | (culldist_mask << 8));
781 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
782 SI_TRACKED_PA_CL_CLIP_CNTL,
783 rs->pa_cl_clip_cntl |
784 ucp_mask |
785 S_028810_CLIP_DISABLE(window_space));
786 }
787
788 /*
789 * inferred state between framebuffer and rasterizer
790 */
791 static void si_update_poly_offset_state(struct si_context *sctx)
792 {
793 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
794
795 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
796 si_pm4_bind_state(sctx, poly_offset, NULL);
797 return;
798 }
799
800 /* Use the user format, not db_render_format, so that the polygon
801 * offset behaves as expected by applications.
802 */
803 switch (sctx->framebuffer.state.zsbuf->texture->format) {
804 case PIPE_FORMAT_Z16_UNORM:
805 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
806 break;
807 default: /* 24-bit */
808 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
809 break;
810 case PIPE_FORMAT_Z32_FLOAT:
811 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
812 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
813 break;
814 }
815 }
816
817 /*
818 * Rasterizer
819 */
820
821 static uint32_t si_translate_fill(uint32_t func)
822 {
823 switch(func) {
824 case PIPE_POLYGON_MODE_FILL:
825 return V_028814_X_DRAW_TRIANGLES;
826 case PIPE_POLYGON_MODE_LINE:
827 return V_028814_X_DRAW_LINES;
828 case PIPE_POLYGON_MODE_POINT:
829 return V_028814_X_DRAW_POINTS;
830 default:
831 assert(0);
832 return V_028814_X_DRAW_POINTS;
833 }
834 }
835
836 static void *si_create_rs_state(struct pipe_context *ctx,
837 const struct pipe_rasterizer_state *state)
838 {
839 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
840 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
841 struct si_pm4_state *pm4 = &rs->pm4;
842 unsigned tmp, i;
843 float psize_min, psize_max;
844
845 if (!rs) {
846 return NULL;
847 }
848
849 rs->scissor_enable = state->scissor;
850 rs->clip_halfz = state->clip_halfz;
851 rs->two_side = state->light_twoside;
852 rs->multisample_enable = state->multisample;
853 rs->force_persample_interp = state->force_persample_interp;
854 rs->clip_plane_enable = state->clip_plane_enable;
855 rs->line_stipple_enable = state->line_stipple_enable;
856 rs->poly_stipple_enable = state->poly_stipple_enable;
857 rs->line_smooth = state->line_smooth;
858 rs->line_width = state->line_width;
859 rs->poly_smooth = state->poly_smooth;
860 rs->uses_poly_offset = state->offset_point || state->offset_line ||
861 state->offset_tri;
862 rs->clamp_fragment_color = state->clamp_fragment_color;
863 rs->clamp_vertex_color = state->clamp_vertex_color;
864 rs->flatshade = state->flatshade;
865 rs->sprite_coord_enable = state->sprite_coord_enable;
866 rs->rasterizer_discard = state->rasterizer_discard;
867 rs->pa_sc_line_stipple = state->line_stipple_enable ?
868 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
869 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
870 rs->pa_cl_clip_cntl =
871 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
872 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
873 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
874 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
875 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
876
877 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
878 S_0286D4_FLAT_SHADE_ENA(1) |
879 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
880 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
883 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
884 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
885
886 /* point size 12.4 fixed point */
887 tmp = (unsigned)(state->point_size * 8.0);
888 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
889
890 if (state->point_size_per_vertex) {
891 psize_min = util_get_min_point_size(state);
892 psize_max = 8192;
893 } else {
894 /* Force the point size to be as if the vertex output was disabled. */
895 psize_min = state->point_size;
896 psize_max = state->point_size;
897 }
898 rs->max_point_size = psize_max;
899
900 /* Divide by two, because 0.5 = 1 pixel. */
901 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
902 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
903 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
904
905 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
906 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
907 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
908 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
909 S_028A48_MSAA_ENABLE(state->multisample ||
910 state->poly_smooth ||
911 state->line_smooth) |
912 S_028A48_VPORT_SCISSOR_ENABLE(1) |
913 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
914
915 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
916 S_028BE4_PIX_CENTER(state->half_pixel_center) |
917 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
918
919 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
920 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
921 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
922 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
923 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
924 S_028814_FACE(!state->front_ccw) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
928 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
929 state->fill_back != PIPE_POLYGON_MODE_FILL) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
932
933 if (!rs->uses_poly_offset)
934 return rs;
935
936 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
937 if (!rs->pm4_poly_offset) {
938 FREE(rs);
939 return NULL;
940 }
941
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i = 0; i < 3; i++) {
944 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
945 float offset_units = state->offset_units;
946 float offset_scale = state->offset_scale * 16.0f;
947 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
948
949 if (!state->offset_units_unscaled) {
950 switch (i) {
951 case 0: /* 16-bit zbuffer */
952 offset_units *= 4.0f;
953 pa_su_poly_offset_db_fmt_cntl =
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
955 break;
956 case 1: /* 24-bit zbuffer */
957 offset_units *= 2.0f;
958 pa_su_poly_offset_db_fmt_cntl =
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
960 break;
961 case 2: /* 32-bit zbuffer */
962 offset_units *= 1.0f;
963 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
964 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
965 break;
966 }
967 }
968
969 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
970 fui(offset_scale));
971 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
972 fui(offset_units));
973 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
974 fui(offset_scale));
975 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
976 fui(offset_units));
977 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
978 pa_su_poly_offset_db_fmt_cntl);
979 }
980
981 return rs;
982 }
983
984 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
985 {
986 struct si_context *sctx = (struct si_context *)ctx;
987 struct si_state_rasterizer *old_rs =
988 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
989 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
990
991 if (!state)
992 return;
993
994 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
995 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
996
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx->screen->has_msaa_sample_loc_bug &&
999 sctx->framebuffer.nr_samples > 1)
1000 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1001 }
1002
1003 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1004 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1005
1006 si_pm4_bind_state(sctx, rasterizer, rs);
1007 si_update_poly_offset_state(sctx);
1008
1009 if (!old_rs ||
1010 old_rs->scissor_enable != rs->scissor_enable) {
1011 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1012 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1013 }
1014
1015 if (!old_rs ||
1016 old_rs->line_width != rs->line_width ||
1017 old_rs->max_point_size != rs->max_point_size)
1018 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1019
1020 if (!old_rs ||
1021 old_rs->clip_halfz != rs->clip_halfz) {
1022 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1023 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1024 }
1025
1026 if (!old_rs ||
1027 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1028 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1029 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1030
1031 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1032 rs->line_stipple_enable;
1033
1034 if (!old_rs ||
1035 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1036 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1037 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1038 old_rs->flatshade != rs->flatshade ||
1039 old_rs->two_side != rs->two_side ||
1040 old_rs->multisample_enable != rs->multisample_enable ||
1041 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1042 old_rs->poly_smooth != rs->poly_smooth ||
1043 old_rs->line_smooth != rs->line_smooth ||
1044 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1045 old_rs->force_persample_interp != rs->force_persample_interp)
1046 sctx->do_update_shaders = true;
1047 }
1048
1049 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1050 {
1051 struct si_context *sctx = (struct si_context *)ctx;
1052 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1053
1054 if (sctx->queued.named.rasterizer == state)
1055 si_pm4_bind_state(sctx, poly_offset, NULL);
1056
1057 FREE(rs->pm4_poly_offset);
1058 si_pm4_delete_state(sctx, rasterizer, rs);
1059 }
1060
1061 /*
1062 * infeered state between dsa and stencil ref
1063 */
1064 static void si_emit_stencil_ref(struct si_context *sctx)
1065 {
1066 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1067 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1068 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1069
1070 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1071 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1072 S_028430_STENCILMASK(dsa->valuemask[0]) |
1073 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1074 S_028430_STENCILOPVAL(1));
1075 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1076 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1077 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1078 S_028434_STENCILOPVAL_BF(1));
1079 }
1080
1081 static void si_set_stencil_ref(struct pipe_context *ctx,
1082 const struct pipe_stencil_ref *state)
1083 {
1084 struct si_context *sctx = (struct si_context *)ctx;
1085
1086 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1087 return;
1088
1089 sctx->stencil_ref.state = *state;
1090 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1091 }
1092
1093
1094 /*
1095 * DSA
1096 */
1097
1098 static uint32_t si_translate_stencil_op(int s_op)
1099 {
1100 switch (s_op) {
1101 case PIPE_STENCIL_OP_KEEP:
1102 return V_02842C_STENCIL_KEEP;
1103 case PIPE_STENCIL_OP_ZERO:
1104 return V_02842C_STENCIL_ZERO;
1105 case PIPE_STENCIL_OP_REPLACE:
1106 return V_02842C_STENCIL_REPLACE_TEST;
1107 case PIPE_STENCIL_OP_INCR:
1108 return V_02842C_STENCIL_ADD_CLAMP;
1109 case PIPE_STENCIL_OP_DECR:
1110 return V_02842C_STENCIL_SUB_CLAMP;
1111 case PIPE_STENCIL_OP_INCR_WRAP:
1112 return V_02842C_STENCIL_ADD_WRAP;
1113 case PIPE_STENCIL_OP_DECR_WRAP:
1114 return V_02842C_STENCIL_SUB_WRAP;
1115 case PIPE_STENCIL_OP_INVERT:
1116 return V_02842C_STENCIL_INVERT;
1117 default:
1118 PRINT_ERR("Unknown stencil op %d", s_op);
1119 assert(0);
1120 break;
1121 }
1122 return 0;
1123 }
1124
1125 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1126 {
1127 return s->enabled && s->writemask &&
1128 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1129 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1130 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1131 }
1132
1133 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1134 {
1135 /* REPLACE is normally order invariant, except when the stencil
1136 * reference value is written by the fragment shader. Tracking this
1137 * interaction does not seem worth the effort, so be conservative. */
1138 return op != PIPE_STENCIL_OP_INCR &&
1139 op != PIPE_STENCIL_OP_DECR &&
1140 op != PIPE_STENCIL_OP_REPLACE;
1141 }
1142
1143 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1144 * invariant in the sense that the set of passing fragments as well as the
1145 * final stencil buffer result does not depend on the order of fragments. */
1146 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1147 {
1148 return !state->enabled || !state->writemask ||
1149 /* The following assumes that Z writes are disabled. */
1150 (state->func == PIPE_FUNC_ALWAYS &&
1151 si_order_invariant_stencil_op(state->zpass_op) &&
1152 si_order_invariant_stencil_op(state->zfail_op)) ||
1153 (state->func == PIPE_FUNC_NEVER &&
1154 si_order_invariant_stencil_op(state->fail_op));
1155 }
1156
1157 static void *si_create_dsa_state(struct pipe_context *ctx,
1158 const struct pipe_depth_stencil_alpha_state *state)
1159 {
1160 struct si_context *sctx = (struct si_context *)ctx;
1161 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1162 struct si_pm4_state *pm4 = &dsa->pm4;
1163 unsigned db_depth_control;
1164 uint32_t db_stencil_control = 0;
1165
1166 if (!dsa) {
1167 return NULL;
1168 }
1169
1170 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1171 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1172 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1173 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1174
1175 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1176 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1177 S_028800_ZFUNC(state->depth.func) |
1178 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1179
1180 /* stencil */
1181 if (state->stencil[0].enabled) {
1182 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1183 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1184 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1185 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1186 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1187
1188 if (state->stencil[1].enabled) {
1189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1190 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1191 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1192 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1193 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1194 }
1195 }
1196
1197 /* alpha */
1198 if (state->alpha.enabled) {
1199 dsa->alpha_func = state->alpha.func;
1200
1201 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1202 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1203 } else {
1204 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1205 }
1206
1207 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1208 if (state->stencil[0].enabled)
1209 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1210 if (state->depth.bounds_test) {
1211 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1212 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1213 }
1214
1215 dsa->depth_enabled = state->depth.enabled;
1216 dsa->depth_write_enabled = state->depth.enabled &&
1217 state->depth.writemask;
1218 dsa->stencil_enabled = state->stencil[0].enabled;
1219 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1220 (si_dsa_writes_stencil(&state->stencil[0]) ||
1221 si_dsa_writes_stencil(&state->stencil[1]));
1222 dsa->db_can_write = dsa->depth_write_enabled ||
1223 dsa->stencil_write_enabled;
1224
1225 bool zfunc_is_ordered =
1226 state->depth.func == PIPE_FUNC_NEVER ||
1227 state->depth.func == PIPE_FUNC_LESS ||
1228 state->depth.func == PIPE_FUNC_LEQUAL ||
1229 state->depth.func == PIPE_FUNC_GREATER ||
1230 state->depth.func == PIPE_FUNC_GEQUAL;
1231
1232 bool nozwrite_and_order_invariant_stencil =
1233 !dsa->db_can_write ||
1234 (!dsa->depth_write_enabled &&
1235 si_order_invariant_stencil_state(&state->stencil[0]) &&
1236 si_order_invariant_stencil_state(&state->stencil[1]));
1237
1238 dsa->order_invariance[1].zs =
1239 nozwrite_and_order_invariant_stencil ||
1240 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1241 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1242
1243 dsa->order_invariance[1].pass_set =
1244 nozwrite_and_order_invariant_stencil ||
1245 (!dsa->stencil_write_enabled &&
1246 (state->depth.func == PIPE_FUNC_ALWAYS ||
1247 state->depth.func == PIPE_FUNC_NEVER));
1248 dsa->order_invariance[0].pass_set =
1249 !dsa->depth_write_enabled ||
1250 (state->depth.func == PIPE_FUNC_ALWAYS ||
1251 state->depth.func == PIPE_FUNC_NEVER);
1252
1253 dsa->order_invariance[1].pass_last =
1254 sctx->screen->assume_no_z_fights &&
1255 !dsa->stencil_write_enabled &&
1256 dsa->depth_write_enabled && zfunc_is_ordered;
1257 dsa->order_invariance[0].pass_last =
1258 sctx->screen->assume_no_z_fights &&
1259 dsa->depth_write_enabled && zfunc_is_ordered;
1260
1261 return dsa;
1262 }
1263
1264 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1268 struct si_state_dsa *dsa = state;
1269
1270 if (!state)
1271 return;
1272
1273 si_pm4_bind_state(sctx, dsa, dsa);
1274
1275 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1276 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1277 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1278 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1279 }
1280
1281 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1282 sctx->do_update_shaders = true;
1283
1284 if (sctx->screen->dpbb_allowed &&
1285 (!old_dsa ||
1286 (old_dsa->depth_enabled != dsa->depth_enabled ||
1287 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1288 old_dsa->db_can_write != dsa->db_can_write)))
1289 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1290
1291 if (sctx->screen->has_out_of_order_rast &&
1292 (!old_dsa ||
1293 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1294 sizeof(old_dsa->order_invariance))))
1295 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1296 }
1297
1298 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1299 {
1300 struct si_context *sctx = (struct si_context *)ctx;
1301 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1302 }
1303
1304 static void *si_create_db_flush_dsa(struct si_context *sctx)
1305 {
1306 struct pipe_depth_stencil_alpha_state dsa = {};
1307
1308 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1309 }
1310
1311 /* DB RENDER STATE */
1312
1313 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1314 {
1315 struct si_context *sctx = (struct si_context*)ctx;
1316
1317 /* Pipeline stat & streamout queries. */
1318 if (enable) {
1319 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1320 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1321 } else {
1322 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1323 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1324 }
1325
1326 /* Occlusion queries. */
1327 if (sctx->occlusion_queries_disabled != !enable) {
1328 sctx->occlusion_queries_disabled = !enable;
1329 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1330 }
1331 }
1332
1333 void si_set_occlusion_query_state(struct si_context *sctx,
1334 bool old_perfect_enable)
1335 {
1336 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1337
1338 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1339
1340 if (perfect_enable != old_perfect_enable)
1341 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1342 }
1343
1344 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1345 {
1346 st->saved_compute = sctx->cs_shader_state.program;
1347
1348 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1349 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1350 }
1351
1352 static void si_emit_db_render_state(struct si_context *sctx)
1353 {
1354 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1355 unsigned db_shader_control, db_render_control, db_count_control;
1356
1357 /* DB_RENDER_CONTROL */
1358 if (sctx->dbcb_depth_copy_enabled ||
1359 sctx->dbcb_stencil_copy_enabled) {
1360 db_render_control =
1361 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1362 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1363 S_028000_COPY_CENTROID(1) |
1364 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1365 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1366 db_render_control =
1367 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1368 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1369 } else {
1370 db_render_control =
1371 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1372 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1373 }
1374
1375 /* DB_COUNT_CONTROL (occlusion queries) */
1376 if (sctx->num_occlusion_queries > 0 &&
1377 !sctx->occlusion_queries_disabled) {
1378 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1379
1380 if (sctx->chip_class >= CIK) {
1381 db_count_control =
1382 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1383 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1384 S_028004_ZPASS_ENABLE(1) |
1385 S_028004_SLICE_EVEN_ENABLE(1) |
1386 S_028004_SLICE_ODD_ENABLE(1);
1387 } else {
1388 db_count_control =
1389 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1390 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1391 }
1392 } else {
1393 /* Disable occlusion queries. */
1394 if (sctx->chip_class >= CIK) {
1395 db_count_control = 0;
1396 } else {
1397 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1398 }
1399 }
1400
1401 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1402 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1403 db_count_control);
1404
1405 /* DB_RENDER_OVERRIDE2 */
1406 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1407 SI_TRACKED_DB_RENDER_OVERRIDE2,
1408 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1409 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1410 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1411
1412 db_shader_control = sctx->ps_db_shader_control;
1413
1414 /* Bug workaround for smoothing (overrasterization) on SI. */
1415 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1416 db_shader_control &= C_02880C_Z_ORDER;
1417 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1418 }
1419
1420 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1421 if (!rs->multisample_enable)
1422 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1423
1424 if (sctx->screen->has_rbplus &&
1425 !sctx->screen->rbplus_allowed)
1426 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1427
1428 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1429 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1430 }
1431
1432 /*
1433 * format translation
1434 */
1435 static uint32_t si_translate_colorformat(enum pipe_format format)
1436 {
1437 const struct util_format_description *desc = util_format_description(format);
1438 if (!desc)
1439 return V_028C70_COLOR_INVALID;
1440
1441 #define HAS_SIZE(x,y,z,w) \
1442 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1443 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1444
1445 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1446 return V_028C70_COLOR_10_11_11;
1447
1448 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1449 return V_028C70_COLOR_INVALID;
1450
1451 /* hw cannot support mixed formats (except depth/stencil, since
1452 * stencil is not written to). */
1453 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1454 return V_028C70_COLOR_INVALID;
1455
1456 switch (desc->nr_channels) {
1457 case 1:
1458 switch (desc->channel[0].size) {
1459 case 8:
1460 return V_028C70_COLOR_8;
1461 case 16:
1462 return V_028C70_COLOR_16;
1463 case 32:
1464 return V_028C70_COLOR_32;
1465 }
1466 break;
1467 case 2:
1468 if (desc->channel[0].size == desc->channel[1].size) {
1469 switch (desc->channel[0].size) {
1470 case 8:
1471 return V_028C70_COLOR_8_8;
1472 case 16:
1473 return V_028C70_COLOR_16_16;
1474 case 32:
1475 return V_028C70_COLOR_32_32;
1476 }
1477 } else if (HAS_SIZE(8,24,0,0)) {
1478 return V_028C70_COLOR_24_8;
1479 } else if (HAS_SIZE(24,8,0,0)) {
1480 return V_028C70_COLOR_8_24;
1481 }
1482 break;
1483 case 3:
1484 if (HAS_SIZE(5,6,5,0)) {
1485 return V_028C70_COLOR_5_6_5;
1486 } else if (HAS_SIZE(32,8,24,0)) {
1487 return V_028C70_COLOR_X24_8_32_FLOAT;
1488 }
1489 break;
1490 case 4:
1491 if (desc->channel[0].size == desc->channel[1].size &&
1492 desc->channel[0].size == desc->channel[2].size &&
1493 desc->channel[0].size == desc->channel[3].size) {
1494 switch (desc->channel[0].size) {
1495 case 4:
1496 return V_028C70_COLOR_4_4_4_4;
1497 case 8:
1498 return V_028C70_COLOR_8_8_8_8;
1499 case 16:
1500 return V_028C70_COLOR_16_16_16_16;
1501 case 32:
1502 return V_028C70_COLOR_32_32_32_32;
1503 }
1504 } else if (HAS_SIZE(5,5,5,1)) {
1505 return V_028C70_COLOR_1_5_5_5;
1506 } else if (HAS_SIZE(1,5,5,5)) {
1507 return V_028C70_COLOR_5_5_5_1;
1508 } else if (HAS_SIZE(10,10,10,2)) {
1509 return V_028C70_COLOR_2_10_10_10;
1510 }
1511 break;
1512 }
1513 return V_028C70_COLOR_INVALID;
1514 }
1515
1516 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1517 {
1518 if (SI_BIG_ENDIAN) {
1519 switch(colorformat) {
1520 /* 8-bit buffers. */
1521 case V_028C70_COLOR_8:
1522 return V_028C70_ENDIAN_NONE;
1523
1524 /* 16-bit buffers. */
1525 case V_028C70_COLOR_5_6_5:
1526 case V_028C70_COLOR_1_5_5_5:
1527 case V_028C70_COLOR_4_4_4_4:
1528 case V_028C70_COLOR_16:
1529 case V_028C70_COLOR_8_8:
1530 return V_028C70_ENDIAN_8IN16;
1531
1532 /* 32-bit buffers. */
1533 case V_028C70_COLOR_8_8_8_8:
1534 case V_028C70_COLOR_2_10_10_10:
1535 case V_028C70_COLOR_8_24:
1536 case V_028C70_COLOR_24_8:
1537 case V_028C70_COLOR_16_16:
1538 return V_028C70_ENDIAN_8IN32;
1539
1540 /* 64-bit buffers. */
1541 case V_028C70_COLOR_16_16_16_16:
1542 return V_028C70_ENDIAN_8IN16;
1543
1544 case V_028C70_COLOR_32_32:
1545 return V_028C70_ENDIAN_8IN32;
1546
1547 /* 128-bit buffers. */
1548 case V_028C70_COLOR_32_32_32_32:
1549 return V_028C70_ENDIAN_8IN32;
1550 default:
1551 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1552 }
1553 } else {
1554 return V_028C70_ENDIAN_NONE;
1555 }
1556 }
1557
1558 static uint32_t si_translate_dbformat(enum pipe_format format)
1559 {
1560 switch (format) {
1561 case PIPE_FORMAT_Z16_UNORM:
1562 return V_028040_Z_16;
1563 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1564 case PIPE_FORMAT_X8Z24_UNORM:
1565 case PIPE_FORMAT_Z24X8_UNORM:
1566 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1567 return V_028040_Z_24; /* deprecated on SI */
1568 case PIPE_FORMAT_Z32_FLOAT:
1569 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1570 return V_028040_Z_32_FLOAT;
1571 default:
1572 return V_028040_Z_INVALID;
1573 }
1574 }
1575
1576 /*
1577 * Texture translation
1578 */
1579
1580 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1581 enum pipe_format format,
1582 const struct util_format_description *desc,
1583 int first_non_void)
1584 {
1585 struct si_screen *sscreen = (struct si_screen*)screen;
1586 bool uniform = true;
1587 int i;
1588
1589 /* Colorspace (return non-RGB formats directly). */
1590 switch (desc->colorspace) {
1591 /* Depth stencil formats */
1592 case UTIL_FORMAT_COLORSPACE_ZS:
1593 switch (format) {
1594 case PIPE_FORMAT_Z16_UNORM:
1595 return V_008F14_IMG_DATA_FORMAT_16;
1596 case PIPE_FORMAT_X24S8_UINT:
1597 case PIPE_FORMAT_S8X24_UINT:
1598 /*
1599 * Implemented as an 8_8_8_8 data format to fix texture
1600 * gathers in stencil sampling. This affects at least
1601 * GL45-CTS.texture_cube_map_array.sampling on VI.
1602 */
1603 if (sscreen->info.chip_class <= VI)
1604 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1605
1606 if (format == PIPE_FORMAT_X24S8_UINT)
1607 return V_008F14_IMG_DATA_FORMAT_8_24;
1608 else
1609 return V_008F14_IMG_DATA_FORMAT_24_8;
1610 case PIPE_FORMAT_Z24X8_UNORM:
1611 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1612 return V_008F14_IMG_DATA_FORMAT_8_24;
1613 case PIPE_FORMAT_X8Z24_UNORM:
1614 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1615 return V_008F14_IMG_DATA_FORMAT_24_8;
1616 case PIPE_FORMAT_S8_UINT:
1617 return V_008F14_IMG_DATA_FORMAT_8;
1618 case PIPE_FORMAT_Z32_FLOAT:
1619 return V_008F14_IMG_DATA_FORMAT_32;
1620 case PIPE_FORMAT_X32_S8X24_UINT:
1621 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1622 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1623 default:
1624 goto out_unknown;
1625 }
1626
1627 case UTIL_FORMAT_COLORSPACE_YUV:
1628 goto out_unknown; /* TODO */
1629
1630 case UTIL_FORMAT_COLORSPACE_SRGB:
1631 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1632 goto out_unknown;
1633 break;
1634
1635 default:
1636 break;
1637 }
1638
1639 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1640 if (!sscreen->info.has_format_bc1_through_bc7)
1641 goto out_unknown;
1642
1643 switch (format) {
1644 case PIPE_FORMAT_RGTC1_SNORM:
1645 case PIPE_FORMAT_LATC1_SNORM:
1646 case PIPE_FORMAT_RGTC1_UNORM:
1647 case PIPE_FORMAT_LATC1_UNORM:
1648 return V_008F14_IMG_DATA_FORMAT_BC4;
1649 case PIPE_FORMAT_RGTC2_SNORM:
1650 case PIPE_FORMAT_LATC2_SNORM:
1651 case PIPE_FORMAT_RGTC2_UNORM:
1652 case PIPE_FORMAT_LATC2_UNORM:
1653 return V_008F14_IMG_DATA_FORMAT_BC5;
1654 default:
1655 goto out_unknown;
1656 }
1657 }
1658
1659 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1660 (sscreen->info.family == CHIP_STONEY ||
1661 sscreen->info.family == CHIP_VEGA10 ||
1662 sscreen->info.family == CHIP_RAVEN)) {
1663 switch (format) {
1664 case PIPE_FORMAT_ETC1_RGB8:
1665 case PIPE_FORMAT_ETC2_RGB8:
1666 case PIPE_FORMAT_ETC2_SRGB8:
1667 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1668 case PIPE_FORMAT_ETC2_RGB8A1:
1669 case PIPE_FORMAT_ETC2_SRGB8A1:
1670 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1671 case PIPE_FORMAT_ETC2_RGBA8:
1672 case PIPE_FORMAT_ETC2_SRGBA8:
1673 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1674 case PIPE_FORMAT_ETC2_R11_UNORM:
1675 case PIPE_FORMAT_ETC2_R11_SNORM:
1676 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1677 case PIPE_FORMAT_ETC2_RG11_UNORM:
1678 case PIPE_FORMAT_ETC2_RG11_SNORM:
1679 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1680 default:
1681 goto out_unknown;
1682 }
1683 }
1684
1685 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1686 if (!sscreen->info.has_format_bc1_through_bc7)
1687 goto out_unknown;
1688
1689 switch (format) {
1690 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1691 case PIPE_FORMAT_BPTC_SRGBA:
1692 return V_008F14_IMG_DATA_FORMAT_BC7;
1693 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1694 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1695 return V_008F14_IMG_DATA_FORMAT_BC6;
1696 default:
1697 goto out_unknown;
1698 }
1699 }
1700
1701 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1702 switch (format) {
1703 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1704 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1705 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1706 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1707 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1708 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1709 default:
1710 goto out_unknown;
1711 }
1712 }
1713
1714 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1715 if (!sscreen->info.has_format_bc1_through_bc7)
1716 goto out_unknown;
1717
1718 switch (format) {
1719 case PIPE_FORMAT_DXT1_RGB:
1720 case PIPE_FORMAT_DXT1_RGBA:
1721 case PIPE_FORMAT_DXT1_SRGB:
1722 case PIPE_FORMAT_DXT1_SRGBA:
1723 return V_008F14_IMG_DATA_FORMAT_BC1;
1724 case PIPE_FORMAT_DXT3_RGBA:
1725 case PIPE_FORMAT_DXT3_SRGBA:
1726 return V_008F14_IMG_DATA_FORMAT_BC2;
1727 case PIPE_FORMAT_DXT5_RGBA:
1728 case PIPE_FORMAT_DXT5_SRGBA:
1729 return V_008F14_IMG_DATA_FORMAT_BC3;
1730 default:
1731 goto out_unknown;
1732 }
1733 }
1734
1735 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1736 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1737 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1738 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1739 }
1740
1741 /* R8G8Bx_SNORM - TODO CxV8U8 */
1742
1743 /* hw cannot support mixed formats (except depth/stencil, since only
1744 * depth is read).*/
1745 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1746 goto out_unknown;
1747
1748 /* See whether the components are of the same size. */
1749 for (i = 1; i < desc->nr_channels; i++) {
1750 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1751 }
1752
1753 /* Non-uniform formats. */
1754 if (!uniform) {
1755 switch(desc->nr_channels) {
1756 case 3:
1757 if (desc->channel[0].size == 5 &&
1758 desc->channel[1].size == 6 &&
1759 desc->channel[2].size == 5) {
1760 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1761 }
1762 goto out_unknown;
1763 case 4:
1764 if (desc->channel[0].size == 5 &&
1765 desc->channel[1].size == 5 &&
1766 desc->channel[2].size == 5 &&
1767 desc->channel[3].size == 1) {
1768 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1769 }
1770 if (desc->channel[0].size == 1 &&
1771 desc->channel[1].size == 5 &&
1772 desc->channel[2].size == 5 &&
1773 desc->channel[3].size == 5) {
1774 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1775 }
1776 if (desc->channel[0].size == 10 &&
1777 desc->channel[1].size == 10 &&
1778 desc->channel[2].size == 10 &&
1779 desc->channel[3].size == 2) {
1780 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1781 }
1782 goto out_unknown;
1783 }
1784 goto out_unknown;
1785 }
1786
1787 if (first_non_void < 0 || first_non_void > 3)
1788 goto out_unknown;
1789
1790 /* uniform formats */
1791 switch (desc->channel[first_non_void].size) {
1792 case 4:
1793 switch (desc->nr_channels) {
1794 #if 0 /* Not supported for render targets */
1795 case 2:
1796 return V_008F14_IMG_DATA_FORMAT_4_4;
1797 #endif
1798 case 4:
1799 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1800 }
1801 break;
1802 case 8:
1803 switch (desc->nr_channels) {
1804 case 1:
1805 return V_008F14_IMG_DATA_FORMAT_8;
1806 case 2:
1807 return V_008F14_IMG_DATA_FORMAT_8_8;
1808 case 4:
1809 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1810 }
1811 break;
1812 case 16:
1813 switch (desc->nr_channels) {
1814 case 1:
1815 return V_008F14_IMG_DATA_FORMAT_16;
1816 case 2:
1817 return V_008F14_IMG_DATA_FORMAT_16_16;
1818 case 4:
1819 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1820 }
1821 break;
1822 case 32:
1823 switch (desc->nr_channels) {
1824 case 1:
1825 return V_008F14_IMG_DATA_FORMAT_32;
1826 case 2:
1827 return V_008F14_IMG_DATA_FORMAT_32_32;
1828 #if 0 /* Not supported for render targets */
1829 case 3:
1830 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1831 #endif
1832 case 4:
1833 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1834 }
1835 }
1836
1837 out_unknown:
1838 return ~0;
1839 }
1840
1841 static unsigned si_tex_wrap(unsigned wrap)
1842 {
1843 switch (wrap) {
1844 default:
1845 case PIPE_TEX_WRAP_REPEAT:
1846 return V_008F30_SQ_TEX_WRAP;
1847 case PIPE_TEX_WRAP_CLAMP:
1848 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1849 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1850 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1851 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1852 return V_008F30_SQ_TEX_CLAMP_BORDER;
1853 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1854 return V_008F30_SQ_TEX_MIRROR;
1855 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1856 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1857 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1858 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1859 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1860 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1861 }
1862 }
1863
1864 static unsigned si_tex_mipfilter(unsigned filter)
1865 {
1866 switch (filter) {
1867 case PIPE_TEX_MIPFILTER_NEAREST:
1868 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1869 case PIPE_TEX_MIPFILTER_LINEAR:
1870 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1871 default:
1872 case PIPE_TEX_MIPFILTER_NONE:
1873 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1874 }
1875 }
1876
1877 static unsigned si_tex_compare(unsigned compare)
1878 {
1879 switch (compare) {
1880 default:
1881 case PIPE_FUNC_NEVER:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1883 case PIPE_FUNC_LESS:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1885 case PIPE_FUNC_EQUAL:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1887 case PIPE_FUNC_LEQUAL:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1889 case PIPE_FUNC_GREATER:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1891 case PIPE_FUNC_NOTEQUAL:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1893 case PIPE_FUNC_GEQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1895 case PIPE_FUNC_ALWAYS:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1897 }
1898 }
1899
1900 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1901 unsigned view_target, unsigned nr_samples)
1902 {
1903 unsigned res_target = rtex->buffer.b.b.target;
1904
1905 if (view_target == PIPE_TEXTURE_CUBE ||
1906 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1907 res_target = view_target;
1908 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1909 else if (res_target == PIPE_TEXTURE_CUBE ||
1910 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1911 res_target = PIPE_TEXTURE_2D_ARRAY;
1912
1913 /* GFX9 allocates 1D textures as 2D. */
1914 if ((res_target == PIPE_TEXTURE_1D ||
1915 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1916 sscreen->info.chip_class >= GFX9 &&
1917 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1918 if (res_target == PIPE_TEXTURE_1D)
1919 res_target = PIPE_TEXTURE_2D;
1920 else
1921 res_target = PIPE_TEXTURE_2D_ARRAY;
1922 }
1923
1924 switch (res_target) {
1925 default:
1926 case PIPE_TEXTURE_1D:
1927 return V_008F1C_SQ_RSRC_IMG_1D;
1928 case PIPE_TEXTURE_1D_ARRAY:
1929 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1930 case PIPE_TEXTURE_2D:
1931 case PIPE_TEXTURE_RECT:
1932 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1933 V_008F1C_SQ_RSRC_IMG_2D;
1934 case PIPE_TEXTURE_2D_ARRAY:
1935 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1936 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1937 case PIPE_TEXTURE_3D:
1938 return V_008F1C_SQ_RSRC_IMG_3D;
1939 case PIPE_TEXTURE_CUBE:
1940 case PIPE_TEXTURE_CUBE_ARRAY:
1941 return V_008F1C_SQ_RSRC_IMG_CUBE;
1942 }
1943 }
1944
1945 /*
1946 * Format support testing
1947 */
1948
1949 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1950 {
1951 const struct util_format_description *desc = util_format_description(format);
1952 if (!desc)
1953 return false;
1954
1955 return si_translate_texformat(screen, format, desc,
1956 util_format_get_first_non_void_channel(format)) != ~0U;
1957 }
1958
1959 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1960 const struct util_format_description *desc,
1961 int first_non_void)
1962 {
1963 int i;
1964
1965 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1966 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1967
1968 assert(first_non_void >= 0);
1969
1970 if (desc->nr_channels == 4 &&
1971 desc->channel[0].size == 10 &&
1972 desc->channel[1].size == 10 &&
1973 desc->channel[2].size == 10 &&
1974 desc->channel[3].size == 2)
1975 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1976
1977 /* See whether the components are of the same size. */
1978 for (i = 0; i < desc->nr_channels; i++) {
1979 if (desc->channel[first_non_void].size != desc->channel[i].size)
1980 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1981 }
1982
1983 switch (desc->channel[first_non_void].size) {
1984 case 8:
1985 switch (desc->nr_channels) {
1986 case 1:
1987 case 3: /* 3 loads */
1988 return V_008F0C_BUF_DATA_FORMAT_8;
1989 case 2:
1990 return V_008F0C_BUF_DATA_FORMAT_8_8;
1991 case 4:
1992 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1993 }
1994 break;
1995 case 16:
1996 switch (desc->nr_channels) {
1997 case 1:
1998 case 3: /* 3 loads */
1999 return V_008F0C_BUF_DATA_FORMAT_16;
2000 case 2:
2001 return V_008F0C_BUF_DATA_FORMAT_16_16;
2002 case 4:
2003 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2004 }
2005 break;
2006 case 32:
2007 switch (desc->nr_channels) {
2008 case 1:
2009 return V_008F0C_BUF_DATA_FORMAT_32;
2010 case 2:
2011 return V_008F0C_BUF_DATA_FORMAT_32_32;
2012 case 3:
2013 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2014 case 4:
2015 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2016 }
2017 break;
2018 case 64:
2019 /* Legacy double formats. */
2020 switch (desc->nr_channels) {
2021 case 1: /* 1 load */
2022 return V_008F0C_BUF_DATA_FORMAT_32_32;
2023 case 2: /* 1 load */
2024 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2025 case 3: /* 3 loads */
2026 return V_008F0C_BUF_DATA_FORMAT_32_32;
2027 case 4: /* 2 loads */
2028 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2029 }
2030 break;
2031 }
2032
2033 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2034 }
2035
2036 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2037 const struct util_format_description *desc,
2038 int first_non_void)
2039 {
2040 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2041 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2042
2043 assert(first_non_void >= 0);
2044
2045 switch (desc->channel[first_non_void].type) {
2046 case UTIL_FORMAT_TYPE_SIGNED:
2047 case UTIL_FORMAT_TYPE_FIXED:
2048 if (desc->channel[first_non_void].size >= 32 ||
2049 desc->channel[first_non_void].pure_integer)
2050 return V_008F0C_BUF_NUM_FORMAT_SINT;
2051 else if (desc->channel[first_non_void].normalized)
2052 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2053 else
2054 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2055 break;
2056 case UTIL_FORMAT_TYPE_UNSIGNED:
2057 if (desc->channel[first_non_void].size >= 32 ||
2058 desc->channel[first_non_void].pure_integer)
2059 return V_008F0C_BUF_NUM_FORMAT_UINT;
2060 else if (desc->channel[first_non_void].normalized)
2061 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2062 else
2063 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2064 break;
2065 case UTIL_FORMAT_TYPE_FLOAT:
2066 default:
2067 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2068 }
2069 }
2070
2071 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2072 enum pipe_format format,
2073 unsigned usage)
2074 {
2075 const struct util_format_description *desc;
2076 int first_non_void;
2077 unsigned data_format;
2078
2079 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2080 PIPE_BIND_SAMPLER_VIEW |
2081 PIPE_BIND_VERTEX_BUFFER)) == 0);
2082
2083 desc = util_format_description(format);
2084 if (!desc)
2085 return 0;
2086
2087 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2088 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2089 * for read-only access (with caveats surrounding bounds checks), but
2090 * obviously fails for write access which we have to implement for
2091 * shader images. Luckily, OpenGL doesn't expect this to be supported
2092 * anyway, and so the only impact is on PBO uploads / downloads, which
2093 * shouldn't be expected to be fast for GL_RGB anyway.
2094 */
2095 if (desc->block.bits == 3 * 8 ||
2096 desc->block.bits == 3 * 16) {
2097 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2098 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2099 if (!usage)
2100 return 0;
2101 }
2102 }
2103
2104 first_non_void = util_format_get_first_non_void_channel(format);
2105 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2106 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2107 return 0;
2108
2109 return usage;
2110 }
2111
2112 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2113 {
2114 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2115 si_translate_colorswap(format, false) != ~0U;
2116 }
2117
2118 static bool si_is_zs_format_supported(enum pipe_format format)
2119 {
2120 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2121 }
2122
2123 static boolean si_is_format_supported(struct pipe_screen *screen,
2124 enum pipe_format format,
2125 enum pipe_texture_target target,
2126 unsigned sample_count,
2127 unsigned usage)
2128 {
2129 struct si_screen *sscreen = (struct si_screen *)screen;
2130 unsigned retval = 0;
2131
2132 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2133 PRINT_ERR("r600: unsupported texture type %d\n", target);
2134 return false;
2135 }
2136
2137 if (!util_format_is_supported(format, usage))
2138 return false;
2139
2140 if (sample_count > 1) {
2141 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2142 return false;
2143
2144 if (usage & PIPE_BIND_SHADER_IMAGE)
2145 return false;
2146
2147 switch (sample_count) {
2148 case 2:
2149 case 4:
2150 case 8:
2151 break;
2152 case 16:
2153 /* Allow resource_copy_region with nr_samples == 16. */
2154 if (sscreen->eqaa_force_coverage_samples == 16 &&
2155 !util_format_is_depth_or_stencil(format))
2156 return true;
2157 if (format == PIPE_FORMAT_NONE)
2158 return true;
2159 else
2160 return false;
2161 default:
2162 return false;
2163 }
2164 }
2165
2166 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2167 PIPE_BIND_SHADER_IMAGE)) {
2168 if (target == PIPE_BUFFER) {
2169 retval |= si_is_vertex_format_supported(
2170 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2171 PIPE_BIND_SHADER_IMAGE));
2172 } else {
2173 if (si_is_sampler_format_supported(screen, format))
2174 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2175 PIPE_BIND_SHADER_IMAGE);
2176 }
2177 }
2178
2179 if ((usage & (PIPE_BIND_RENDER_TARGET |
2180 PIPE_BIND_DISPLAY_TARGET |
2181 PIPE_BIND_SCANOUT |
2182 PIPE_BIND_SHARED |
2183 PIPE_BIND_BLENDABLE)) &&
2184 si_is_colorbuffer_format_supported(format)) {
2185 retval |= usage &
2186 (PIPE_BIND_RENDER_TARGET |
2187 PIPE_BIND_DISPLAY_TARGET |
2188 PIPE_BIND_SCANOUT |
2189 PIPE_BIND_SHARED);
2190 if (!util_format_is_pure_integer(format) &&
2191 !util_format_is_depth_or_stencil(format))
2192 retval |= usage & PIPE_BIND_BLENDABLE;
2193 }
2194
2195 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2196 si_is_zs_format_supported(format)) {
2197 retval |= PIPE_BIND_DEPTH_STENCIL;
2198 }
2199
2200 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2201 retval |= si_is_vertex_format_supported(screen, format,
2202 PIPE_BIND_VERTEX_BUFFER);
2203 }
2204
2205 if ((usage & PIPE_BIND_LINEAR) &&
2206 !util_format_is_compressed(format) &&
2207 !(usage & PIPE_BIND_DEPTH_STENCIL))
2208 retval |= PIPE_BIND_LINEAR;
2209
2210 return retval == usage;
2211 }
2212
2213 /*
2214 * framebuffer handling
2215 */
2216
2217 static void si_choose_spi_color_formats(struct r600_surface *surf,
2218 unsigned format, unsigned swap,
2219 unsigned ntype, bool is_depth)
2220 {
2221 /* Alpha is needed for alpha-to-coverage.
2222 * Blending may be with or without alpha.
2223 */
2224 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2225 unsigned alpha = 0; /* exports alpha, but may not support blending */
2226 unsigned blend = 0; /* supports blending, but may not export alpha */
2227 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2228
2229 /* Choose the SPI color formats. These are required values for RB+.
2230 * Other chips have multiple choices, though they are not necessarily better.
2231 */
2232 switch (format) {
2233 case V_028C70_COLOR_5_6_5:
2234 case V_028C70_COLOR_1_5_5_5:
2235 case V_028C70_COLOR_5_5_5_1:
2236 case V_028C70_COLOR_4_4_4_4:
2237 case V_028C70_COLOR_10_11_11:
2238 case V_028C70_COLOR_11_11_10:
2239 case V_028C70_COLOR_8:
2240 case V_028C70_COLOR_8_8:
2241 case V_028C70_COLOR_8_8_8_8:
2242 case V_028C70_COLOR_10_10_10_2:
2243 case V_028C70_COLOR_2_10_10_10:
2244 if (ntype == V_028C70_NUMBER_UINT)
2245 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2246 else if (ntype == V_028C70_NUMBER_SINT)
2247 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2248 else
2249 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2250 break;
2251
2252 case V_028C70_COLOR_16:
2253 case V_028C70_COLOR_16_16:
2254 case V_028C70_COLOR_16_16_16_16:
2255 if (ntype == V_028C70_NUMBER_UNORM ||
2256 ntype == V_028C70_NUMBER_SNORM) {
2257 /* UNORM16 and SNORM16 don't support blending */
2258 if (ntype == V_028C70_NUMBER_UNORM)
2259 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2260 else
2261 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2262
2263 /* Use 32 bits per channel for blending. */
2264 if (format == V_028C70_COLOR_16) {
2265 if (swap == V_028C70_SWAP_STD) { /* R */
2266 blend = V_028714_SPI_SHADER_32_R;
2267 blend_alpha = V_028714_SPI_SHADER_32_AR;
2268 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2269 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2270 else
2271 assert(0);
2272 } else if (format == V_028C70_COLOR_16_16) {
2273 if (swap == V_028C70_SWAP_STD) { /* RG */
2274 blend = V_028714_SPI_SHADER_32_GR;
2275 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2276 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2277 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2278 else
2279 assert(0);
2280 } else /* 16_16_16_16 */
2281 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2282 } else if (ntype == V_028C70_NUMBER_UINT)
2283 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2284 else if (ntype == V_028C70_NUMBER_SINT)
2285 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2286 else if (ntype == V_028C70_NUMBER_FLOAT)
2287 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2288 else
2289 assert(0);
2290 break;
2291
2292 case V_028C70_COLOR_32:
2293 if (swap == V_028C70_SWAP_STD) { /* R */
2294 blend = normal = V_028714_SPI_SHADER_32_R;
2295 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2296 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2297 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2298 else
2299 assert(0);
2300 break;
2301
2302 case V_028C70_COLOR_32_32:
2303 if (swap == V_028C70_SWAP_STD) { /* RG */
2304 blend = normal = V_028714_SPI_SHADER_32_GR;
2305 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2306 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2307 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2308 else
2309 assert(0);
2310 break;
2311
2312 case V_028C70_COLOR_32_32_32_32:
2313 case V_028C70_COLOR_8_24:
2314 case V_028C70_COLOR_24_8:
2315 case V_028C70_COLOR_X24_8_32_FLOAT:
2316 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2317 break;
2318
2319 default:
2320 assert(0);
2321 return;
2322 }
2323
2324 /* The DB->CB copy needs 32_ABGR. */
2325 if (is_depth)
2326 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2327
2328 surf->spi_shader_col_format = normal;
2329 surf->spi_shader_col_format_alpha = alpha;
2330 surf->spi_shader_col_format_blend = blend;
2331 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2332 }
2333
2334 static void si_initialize_color_surface(struct si_context *sctx,
2335 struct r600_surface *surf)
2336 {
2337 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2338 unsigned color_info, color_attrib;
2339 unsigned format, swap, ntype, endian;
2340 const struct util_format_description *desc;
2341 int firstchan;
2342 unsigned blend_clamp = 0, blend_bypass = 0;
2343
2344 desc = util_format_description(surf->base.format);
2345 for (firstchan = 0; firstchan < 4; firstchan++) {
2346 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2347 break;
2348 }
2349 }
2350 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2351 ntype = V_028C70_NUMBER_FLOAT;
2352 } else {
2353 ntype = V_028C70_NUMBER_UNORM;
2354 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2355 ntype = V_028C70_NUMBER_SRGB;
2356 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2357 if (desc->channel[firstchan].pure_integer) {
2358 ntype = V_028C70_NUMBER_SINT;
2359 } else {
2360 assert(desc->channel[firstchan].normalized);
2361 ntype = V_028C70_NUMBER_SNORM;
2362 }
2363 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2364 if (desc->channel[firstchan].pure_integer) {
2365 ntype = V_028C70_NUMBER_UINT;
2366 } else {
2367 assert(desc->channel[firstchan].normalized);
2368 ntype = V_028C70_NUMBER_UNORM;
2369 }
2370 }
2371 }
2372
2373 format = si_translate_colorformat(surf->base.format);
2374 if (format == V_028C70_COLOR_INVALID) {
2375 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2376 }
2377 assert(format != V_028C70_COLOR_INVALID);
2378 swap = si_translate_colorswap(surf->base.format, false);
2379 endian = si_colorformat_endian_swap(format);
2380
2381 /* blend clamp should be set for all NORM/SRGB types */
2382 if (ntype == V_028C70_NUMBER_UNORM ||
2383 ntype == V_028C70_NUMBER_SNORM ||
2384 ntype == V_028C70_NUMBER_SRGB)
2385 blend_clamp = 1;
2386
2387 /* set blend bypass according to docs if SINT/UINT or
2388 8/24 COLOR variants */
2389 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2390 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2391 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2392 blend_clamp = 0;
2393 blend_bypass = 1;
2394 }
2395
2396 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2397 if (format == V_028C70_COLOR_8 ||
2398 format == V_028C70_COLOR_8_8 ||
2399 format == V_028C70_COLOR_8_8_8_8)
2400 surf->color_is_int8 = true;
2401 else if (format == V_028C70_COLOR_10_10_10_2 ||
2402 format == V_028C70_COLOR_2_10_10_10)
2403 surf->color_is_int10 = true;
2404 }
2405
2406 color_info = S_028C70_FORMAT(format) |
2407 S_028C70_COMP_SWAP(swap) |
2408 S_028C70_BLEND_CLAMP(blend_clamp) |
2409 S_028C70_BLEND_BYPASS(blend_bypass) |
2410 S_028C70_SIMPLE_FLOAT(1) |
2411 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2412 ntype != V_028C70_NUMBER_SNORM &&
2413 ntype != V_028C70_NUMBER_SRGB &&
2414 format != V_028C70_COLOR_8_24 &&
2415 format != V_028C70_COLOR_24_8) |
2416 S_028C70_NUMBER_TYPE(ntype) |
2417 S_028C70_ENDIAN(endian);
2418
2419 /* Intensity is implemented as Red, so treat it that way. */
2420 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2421 util_format_is_intensity(surf->base.format));
2422
2423 if (rtex->buffer.b.b.nr_samples > 1) {
2424 unsigned log_samples = util_logbase2(rtex->buffer.b.b.nr_samples);
2425 unsigned log_fragments = util_logbase2(rtex->num_color_samples);
2426
2427 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2428 S_028C74_NUM_FRAGMENTS(log_fragments);
2429
2430 if (rtex->surface.fmask_size) {
2431 color_info |= S_028C70_COMPRESSION(1);
2432 unsigned fmask_bankh = util_logbase2(rtex->surface.u.legacy.fmask.bankh);
2433
2434 if (sctx->chip_class == SI) {
2435 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2436 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2437 }
2438 }
2439 }
2440
2441 if (sctx->chip_class >= VI) {
2442 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2443 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2444
2445 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2446 64 for APU because all of our APUs to date use DIMMs which have
2447 a request granularity size of 64B while all other chips have a
2448 32B request size */
2449 if (!sctx->screen->info.has_dedicated_vram)
2450 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2451
2452 if (rtex->num_color_samples > 1) {
2453 if (rtex->surface.bpe == 1)
2454 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2455 else if (rtex->surface.bpe == 2)
2456 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2457 }
2458
2459 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2460 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2461 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2462 }
2463
2464 /* This must be set for fast clear to work without FMASK. */
2465 if (!rtex->surface.fmask_size && sctx->chip_class == SI) {
2466 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2467 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2468 }
2469
2470 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2471 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2472
2473 if (sctx->chip_class >= GFX9) {
2474 unsigned mip0_depth = util_max_layer(&rtex->buffer.b.b, 0);
2475
2476 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2477 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2478 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2479 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2480 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2481 S_028C68_MAX_MIP(rtex->buffer.b.b.last_level);
2482 }
2483
2484 surf->cb_color_view = color_view;
2485 surf->cb_color_info = color_info;
2486 surf->cb_color_attrib = color_attrib;
2487
2488 /* Determine pixel shader export format */
2489 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2490
2491 surf->color_initialized = true;
2492 }
2493
2494 static void si_init_depth_surface(struct si_context *sctx,
2495 struct r600_surface *surf)
2496 {
2497 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2498 unsigned level = surf->base.u.tex.level;
2499 unsigned format, stencil_format;
2500 uint32_t z_info, s_info;
2501
2502 format = si_translate_dbformat(rtex->db_render_format);
2503 stencil_format = rtex->surface.has_stencil ?
2504 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2505
2506 assert(format != V_028040_Z_INVALID);
2507 if (format == V_028040_Z_INVALID)
2508 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->buffer.b.b.format);
2509
2510 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2511 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2512 surf->db_htile_data_base = 0;
2513 surf->db_htile_surface = 0;
2514
2515 if (sctx->chip_class >= GFX9) {
2516 assert(rtex->surface.u.gfx9.surf_offset == 0);
2517 surf->db_depth_base = rtex->buffer.gpu_address >> 8;
2518 surf->db_stencil_base = (rtex->buffer.gpu_address +
2519 rtex->surface.u.gfx9.stencil_offset) >> 8;
2520 z_info = S_028038_FORMAT(format) |
2521 S_028038_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples)) |
2522 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2523 S_028038_MAXMIP(rtex->buffer.b.b.last_level);
2524 s_info = S_02803C_FORMAT(stencil_format) |
2525 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2526 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2527 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2528 surf->db_depth_view |= S_028008_MIPID(level);
2529 surf->db_depth_size = S_02801C_X_MAX(rtex->buffer.b.b.width0 - 1) |
2530 S_02801C_Y_MAX(rtex->buffer.b.b.height0 - 1);
2531
2532 if (si_htile_enabled(rtex, level)) {
2533 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2534 S_028038_ALLOW_EXPCLEAR(1);
2535
2536 if (rtex->tc_compatible_htile) {
2537 unsigned max_zplanes = 4;
2538
2539 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2540 rtex->buffer.b.b.nr_samples > 1)
2541 max_zplanes = 2;
2542
2543 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2544 S_028038_ITERATE_FLUSH(1);
2545 s_info |= S_02803C_ITERATE_FLUSH(1);
2546 }
2547
2548 if (rtex->surface.has_stencil) {
2549 /* Stencil buffer workaround ported from the SI-CI-VI code.
2550 * See that for explanation.
2551 */
2552 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->buffer.b.b.nr_samples <= 1);
2553 } else {
2554 /* Use all HTILE for depth if there's no stencil. */
2555 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2556 }
2557
2558 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2559 rtex->htile_offset) >> 8;
2560 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2561 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2562 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2563 }
2564 } else {
2565 /* SI-CI-VI */
2566 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2567
2568 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2569
2570 surf->db_depth_base = (rtex->buffer.gpu_address +
2571 rtex->surface.u.legacy.level[level].offset) >> 8;
2572 surf->db_stencil_base = (rtex->buffer.gpu_address +
2573 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2574
2575 z_info = S_028040_FORMAT(format) |
2576 S_028040_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples));
2577 s_info = S_028044_FORMAT(stencil_format);
2578 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2579
2580 if (sctx->chip_class >= CIK) {
2581 struct radeon_info *info = &sctx->screen->info;
2582 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2583 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2584 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2585 unsigned tile_mode = info->si_tile_mode_array[index];
2586 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2587 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2588
2589 surf->db_depth_info |=
2590 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2591 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2592 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2593 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2594 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2595 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2596 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2597 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2598 } else {
2599 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2600 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2601 tile_mode_index = si_tile_mode_index(rtex, level, true);
2602 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2603 }
2604
2605 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2606 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2607 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2608 levelinfo->nblk_y) / 64 - 1);
2609
2610 if (si_htile_enabled(rtex, level)) {
2611 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2612 S_028040_ALLOW_EXPCLEAR(1);
2613
2614 if (rtex->surface.has_stencil) {
2615 /* Workaround: For a not yet understood reason, the
2616 * combination of MSAA, fast stencil clear and stencil
2617 * decompress messes with subsequent stencil buffer
2618 * uses. Problem was reproduced on Verde, Bonaire,
2619 * Tonga, and Carrizo.
2620 *
2621 * Disabling EXPCLEAR works around the problem.
2622 *
2623 * Check piglit's arb_texture_multisample-stencil-clear
2624 * test if you want to try changing this.
2625 */
2626 if (rtex->buffer.b.b.nr_samples <= 1)
2627 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2628 } else if (!rtex->tc_compatible_htile) {
2629 /* Use all of the htile_buffer for depth if there's no stencil.
2630 * This must not be set when TC-compatible HTILE is enabled
2631 * due to a hw bug.
2632 */
2633 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2634 }
2635
2636 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2637 rtex->htile_offset) >> 8;
2638 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2639
2640 if (rtex->tc_compatible_htile) {
2641 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2642
2643 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2644 if (rtex->buffer.b.b.nr_samples <= 1)
2645 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2646 else if (rtex->buffer.b.b.nr_samples <= 4)
2647 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2648 else
2649 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2650 }
2651 }
2652 }
2653
2654 surf->db_z_info = z_info;
2655 surf->db_stencil_info = s_info;
2656
2657 surf->depth_initialized = true;
2658 }
2659
2660 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2661 {
2662 if (sctx->decompression_enabled)
2663 return;
2664
2665 if (sctx->framebuffer.state.zsbuf) {
2666 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2667 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2668
2669 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2670
2671 if (rtex->surface.has_stencil)
2672 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2673 }
2674
2675 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2676 while (compressed_cb_mask) {
2677 unsigned i = u_bit_scan(&compressed_cb_mask);
2678 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2679 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2680
2681 if (rtex->surface.fmask_size)
2682 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2683 if (rtex->dcc_gather_statistics)
2684 rtex->separate_dcc_dirty = true;
2685 }
2686 }
2687
2688 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2689 {
2690 for (int i = 0; i < state->nr_cbufs; ++i) {
2691 struct r600_surface *surf = NULL;
2692 struct r600_texture *rtex;
2693
2694 if (!state->cbufs[i])
2695 continue;
2696 surf = (struct r600_surface*)state->cbufs[i];
2697 rtex = (struct r600_texture*)surf->base.texture;
2698
2699 p_atomic_dec(&rtex->framebuffers_bound);
2700 }
2701 }
2702
2703 static void si_set_framebuffer_state(struct pipe_context *ctx,
2704 const struct pipe_framebuffer_state *state)
2705 {
2706 struct si_context *sctx = (struct si_context *)ctx;
2707 struct pipe_constant_buffer constbuf = {0};
2708 struct r600_surface *surf = NULL;
2709 struct r600_texture *rtex;
2710 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2711 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2712 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2713 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2714 bool old_has_stencil =
2715 old_has_zsbuf &&
2716 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2717 bool unbound = false;
2718 int i;
2719
2720 si_update_fb_dirtiness_after_rendering(sctx);
2721
2722 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2723 if (!sctx->framebuffer.state.cbufs[i])
2724 continue;
2725
2726 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2727 if (rtex->dcc_gather_statistics)
2728 vi_separate_dcc_stop_query(sctx, rtex);
2729 }
2730
2731 /* Disable DCC if the formats are incompatible. */
2732 for (i = 0; i < state->nr_cbufs; i++) {
2733 if (!state->cbufs[i])
2734 continue;
2735
2736 surf = (struct r600_surface*)state->cbufs[i];
2737 rtex = (struct r600_texture*)surf->base.texture;
2738
2739 if (!surf->dcc_incompatible)
2740 continue;
2741
2742 /* Since the DCC decompression calls back into set_framebuffer-
2743 * _state, we need to unbind the framebuffer, so that
2744 * vi_separate_dcc_stop_query isn't called twice with the same
2745 * color buffer.
2746 */
2747 if (!unbound) {
2748 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2749 unbound = true;
2750 }
2751
2752 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2753 if (!si_texture_disable_dcc(sctx, rtex))
2754 si_decompress_dcc(sctx, rtex);
2755
2756 surf->dcc_incompatible = false;
2757 }
2758
2759 /* Only flush TC when changing the framebuffer state, because
2760 * the only client not using TC that can change textures is
2761 * the framebuffer.
2762 *
2763 * Wait for compute shaders because of possible transitions:
2764 * - FB write -> shader read
2765 * - shader write -> FB read
2766 *
2767 * DB caches are flushed on demand (using si_decompress_textures).
2768 *
2769 * When MSAA is enabled, CB and TC caches are flushed on demand
2770 * (after FMASK decompression). Shader write -> FB read transitions
2771 * cannot happen for MSAA textures, because MSAA shader images are
2772 * not supported.
2773 *
2774 * Only flush and wait for CB if there is actually a bound color buffer.
2775 */
2776 if (sctx->framebuffer.uncompressed_cb_mask)
2777 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2778 sctx->framebuffer.CB_has_shader_readable_metadata);
2779
2780 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2781
2782 /* u_blitter doesn't invoke depth decompression when it does multiple
2783 * blits in a row, but the only case when it matters for DB is when
2784 * doing generate_mipmap. So here we flush DB manually between
2785 * individual generate_mipmap blits.
2786 * Note that lower mipmap levels aren't compressed.
2787 */
2788 if (sctx->generate_mipmap_for_depth) {
2789 si_make_DB_shader_coherent(sctx, 1, false,
2790 sctx->framebuffer.DB_has_shader_readable_metadata);
2791 } else if (sctx->chip_class == GFX9) {
2792 /* It appears that DB metadata "leaks" in a sequence of:
2793 * - depth clear
2794 * - DCC decompress for shader image writes (with DB disabled)
2795 * - render with DEPTH_BEFORE_SHADER=1
2796 * Flushing DB metadata works around the problem.
2797 */
2798 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2799 }
2800
2801 /* Take the maximum of the old and new count. If the new count is lower,
2802 * dirtying is needed to disable the unbound colorbuffers.
2803 */
2804 sctx->framebuffer.dirty_cbufs |=
2805 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2806 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2807
2808 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2809 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2810
2811 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2812 sctx->framebuffer.spi_shader_col_format = 0;
2813 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2814 sctx->framebuffer.spi_shader_col_format_blend = 0;
2815 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2816 sctx->framebuffer.color_is_int8 = 0;
2817 sctx->framebuffer.color_is_int10 = 0;
2818
2819 sctx->framebuffer.compressed_cb_mask = 0;
2820 sctx->framebuffer.uncompressed_cb_mask = 0;
2821 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2822 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2823 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2824 sctx->framebuffer.any_dst_linear = false;
2825 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2826 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2827
2828 for (i = 0; i < state->nr_cbufs; i++) {
2829 if (!state->cbufs[i])
2830 continue;
2831
2832 surf = (struct r600_surface*)state->cbufs[i];
2833 rtex = (struct r600_texture*)surf->base.texture;
2834
2835 if (!surf->color_initialized) {
2836 si_initialize_color_surface(sctx, surf);
2837 }
2838
2839 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2840 sctx->framebuffer.spi_shader_col_format |=
2841 surf->spi_shader_col_format << (i * 4);
2842 sctx->framebuffer.spi_shader_col_format_alpha |=
2843 surf->spi_shader_col_format_alpha << (i * 4);
2844 sctx->framebuffer.spi_shader_col_format_blend |=
2845 surf->spi_shader_col_format_blend << (i * 4);
2846 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2847 surf->spi_shader_col_format_blend_alpha << (i * 4);
2848
2849 if (surf->color_is_int8)
2850 sctx->framebuffer.color_is_int8 |= 1 << i;
2851 if (surf->color_is_int10)
2852 sctx->framebuffer.color_is_int10 |= 1 << i;
2853
2854 if (rtex->surface.fmask_size)
2855 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2856 else
2857 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2858
2859 /* Don't update nr_color_samples for non-AA buffers.
2860 * (e.g. destination of MSAA resolve)
2861 */
2862 if (rtex->buffer.b.b.nr_samples >= 2 &&
2863 rtex->num_color_samples < rtex->buffer.b.b.nr_samples) {
2864 sctx->framebuffer.nr_color_samples =
2865 MIN2(sctx->framebuffer.nr_color_samples,
2866 rtex->num_color_samples);
2867 }
2868
2869 if (rtex->surface.is_linear)
2870 sctx->framebuffer.any_dst_linear = true;
2871
2872 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2873 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2874
2875 si_context_add_resource_size(sctx, surf->base.texture);
2876
2877 p_atomic_inc(&rtex->framebuffers_bound);
2878
2879 if (rtex->dcc_gather_statistics) {
2880 /* Dirty tracking must be enabled for DCC usage analysis. */
2881 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2882 vi_separate_dcc_start_query(sctx, rtex);
2883 }
2884 }
2885
2886 struct r600_texture *zstex = NULL;
2887
2888 if (state->zsbuf) {
2889 surf = (struct r600_surface*)state->zsbuf;
2890 zstex = (struct r600_texture*)surf->base.texture;
2891
2892 if (!surf->depth_initialized) {
2893 si_init_depth_surface(sctx, surf);
2894 }
2895
2896 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2897 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2898
2899 si_context_add_resource_size(sctx, surf->base.texture);
2900 }
2901
2902 si_update_ps_colorbuf0_slot(sctx);
2903 si_update_poly_offset_state(sctx);
2904 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2905 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2906
2907 if (sctx->screen->dpbb_allowed)
2908 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2909
2910 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2911 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2912
2913 if (sctx->screen->has_out_of_order_rast &&
2914 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2915 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2916 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2917 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2918
2919 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2920 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2921 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2922
2923 /* Set sample locations as fragment shader constants. */
2924 switch (sctx->framebuffer.nr_samples) {
2925 case 1:
2926 constbuf.user_buffer = sctx->sample_locations_1x;
2927 break;
2928 case 2:
2929 constbuf.user_buffer = sctx->sample_locations_2x;
2930 break;
2931 case 4:
2932 constbuf.user_buffer = sctx->sample_locations_4x;
2933 break;
2934 case 8:
2935 constbuf.user_buffer = sctx->sample_locations_8x;
2936 break;
2937 case 16:
2938 constbuf.user_buffer = sctx->sample_locations_16x;
2939 break;
2940 default:
2941 PRINT_ERR("Requested an invalid number of samples %i.\n",
2942 sctx->framebuffer.nr_samples);
2943 assert(0);
2944 }
2945 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2946 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2947
2948 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2949 }
2950
2951 sctx->do_update_shaders = true;
2952
2953 if (!sctx->decompression_enabled) {
2954 /* Prevent textures decompression when the framebuffer state
2955 * changes come from the decompression passes themselves.
2956 */
2957 sctx->need_check_render_feedback = true;
2958 }
2959 }
2960
2961 static void si_emit_framebuffer_state(struct si_context *sctx)
2962 {
2963 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2964 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2965 unsigned i, nr_cbufs = state->nr_cbufs;
2966 struct r600_texture *tex = NULL;
2967 struct r600_surface *cb = NULL;
2968 unsigned cb_color_info = 0;
2969
2970 /* Colorbuffers. */
2971 for (i = 0; i < nr_cbufs; i++) {
2972 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2973 unsigned cb_color_attrib;
2974
2975 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2976 continue;
2977
2978 cb = (struct r600_surface*)state->cbufs[i];
2979 if (!cb) {
2980 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2981 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2982 continue;
2983 }
2984
2985 tex = (struct r600_texture *)cb->base.texture;
2986 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2987 &tex->buffer, RADEON_USAGE_READWRITE,
2988 tex->buffer.b.b.nr_samples > 1 ?
2989 RADEON_PRIO_COLOR_BUFFER_MSAA :
2990 RADEON_PRIO_COLOR_BUFFER);
2991
2992 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2993 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2994 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2995 RADEON_PRIO_CMASK);
2996 }
2997
2998 if (tex->dcc_separate_buffer)
2999 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3000 tex->dcc_separate_buffer,
3001 RADEON_USAGE_READWRITE,
3002 RADEON_PRIO_DCC);
3003
3004 /* Compute mutable surface parameters. */
3005 cb_color_base = tex->buffer.gpu_address >> 8;
3006 cb_color_fmask = 0;
3007 cb_color_cmask = tex->cmask.base_address_reg;
3008 cb_dcc_base = 0;
3009 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3010 cb_color_attrib = cb->cb_color_attrib;
3011
3012 if (cb->base.u.tex.level > 0)
3013 cb_color_info &= C_028C70_FAST_CLEAR;
3014
3015 if (tex->surface.fmask_size) {
3016 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3017 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3018 }
3019
3020 /* Set up DCC. */
3021 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3022 bool is_msaa_resolve_dst = state->cbufs[0] &&
3023 state->cbufs[0]->texture->nr_samples > 1 &&
3024 state->cbufs[1] == &cb->base &&
3025 state->cbufs[1]->texture->nr_samples <= 1;
3026
3027 if (!is_msaa_resolve_dst)
3028 cb_color_info |= S_028C70_DCC_ENABLE(1);
3029
3030 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3031 tex->dcc_offset) >> 8;
3032 cb_dcc_base |= tex->surface.tile_swizzle;
3033 }
3034
3035 if (sctx->chip_class >= GFX9) {
3036 struct gfx9_surf_meta_flags meta;
3037
3038 if (tex->dcc_offset)
3039 meta = tex->surface.u.gfx9.dcc;
3040 else
3041 meta = tex->surface.u.gfx9.cmask;
3042
3043 /* Set mutable surface parameters. */
3044 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3045 cb_color_base |= tex->surface.tile_swizzle;
3046 if (!tex->surface.fmask_size)
3047 cb_color_fmask = cb_color_base;
3048 if (cb->base.u.tex.level > 0)
3049 cb_color_cmask = cb_color_base;
3050 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3051 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3052 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3053 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3054
3055 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3056 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3057 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3058 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3059 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3060 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3061 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3062 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3063 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3064 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3065 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3066 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3067 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3068 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3069 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3070 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3071
3072 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3073 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3074 } else {
3075 /* Compute mutable surface parameters (SI-CI-VI). */
3076 const struct legacy_surf_level *level_info =
3077 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3078 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3079 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3080
3081 cb_color_base += level_info->offset >> 8;
3082 /* Only macrotiled modes can set tile swizzle. */
3083 if (level_info->mode == RADEON_SURF_MODE_2D)
3084 cb_color_base |= tex->surface.tile_swizzle;
3085
3086 if (!tex->surface.fmask_size)
3087 cb_color_fmask = cb_color_base;
3088 if (cb->base.u.tex.level > 0)
3089 cb_color_cmask = cb_color_base;
3090 if (cb_dcc_base)
3091 cb_dcc_base += level_info->dcc_offset >> 8;
3092
3093 pitch_tile_max = level_info->nblk_x / 8 - 1;
3094 slice_tile_max = level_info->nblk_x *
3095 level_info->nblk_y / 64 - 1;
3096 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3097
3098 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3099 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3100 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3101
3102 if (tex->surface.fmask_size) {
3103 if (sctx->chip_class >= CIK)
3104 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3105 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3106 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3107 } else {
3108 /* This must be set for fast clear to work without FMASK. */
3109 if (sctx->chip_class >= CIK)
3110 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3111 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3112 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3113 }
3114
3115 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3116 sctx->chip_class >= VI ? 14 : 13);
3117 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3118 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3119 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3120 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3121 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3122 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3123 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3124 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3125 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3126 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3127 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3128 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3129 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3130
3131 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3132 radeon_emit(cs, cb_dcc_base);
3133 }
3134 }
3135 for (; i < 8 ; i++)
3136 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3137 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3138
3139 /* ZS buffer. */
3140 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3141 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3142 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3143
3144 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3145 &rtex->buffer, RADEON_USAGE_READWRITE,
3146 zb->base.texture->nr_samples > 1 ?
3147 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3148 RADEON_PRIO_DEPTH_BUFFER);
3149
3150 if (sctx->chip_class >= GFX9) {
3151 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3152 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3153 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3154 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3155
3156 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3157 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3158 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3159 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3160 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3161 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3162 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3163 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3164 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3165 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3166 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3167 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3168
3169 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3170 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3171 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3172 } else {
3173 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3174
3175 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3176 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3177 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3178 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3179 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3180 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3181 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3182 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3183 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3184 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3185 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3186 }
3187
3188 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3189 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3190 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3191
3192 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3193 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3194 } else if (sctx->framebuffer.dirty_zsbuf) {
3195 if (sctx->chip_class >= GFX9)
3196 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3197 else
3198 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3199
3200 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3201 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3202 }
3203
3204 /* Framebuffer dimensions. */
3205 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3206 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3207 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3208
3209 if (sctx->screen->dfsm_allowed) {
3210 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3211 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3212 }
3213
3214 sctx->framebuffer.dirty_cbufs = 0;
3215 sctx->framebuffer.dirty_zsbuf = false;
3216 }
3217
3218 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3219 {
3220 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3221 unsigned nr_samples = sctx->framebuffer.nr_samples;
3222 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3223
3224 /* Smoothing (only possible with nr_samples == 1) uses the same
3225 * sample locations as the MSAA it simulates.
3226 */
3227 if (nr_samples <= 1 && sctx->smoothing_enabled)
3228 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3229
3230 /* On Polaris, the small primitive filter uses the sample locations
3231 * even when MSAA is off, so we need to make sure they're set to 0.
3232 */
3233 if (has_msaa_sample_loc_bug)
3234 nr_samples = MAX2(nr_samples, 1);
3235
3236 if (nr_samples != sctx->sample_locs_num_samples) {
3237 sctx->sample_locs_num_samples = nr_samples;
3238 si_emit_sample_locations(cs, nr_samples);
3239 }
3240
3241 if (sctx->family >= CHIP_POLARIS10) {
3242 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3243 unsigned small_prim_filter_cntl =
3244 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3245 /* line bug */
3246 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3247
3248 /* The alternative of setting sample locations to 0 would
3249 * require a DB flush to avoid Z errors, see
3250 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3251 */
3252 if (has_msaa_sample_loc_bug &&
3253 sctx->framebuffer.nr_samples > 1 &&
3254 !rs->multisample_enable)
3255 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3256
3257 radeon_opt_set_context_reg(sctx,
3258 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3259 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3260 small_prim_filter_cntl);
3261 }
3262 }
3263
3264 static bool si_out_of_order_rasterization(struct si_context *sctx)
3265 {
3266 struct si_state_blend *blend = sctx->queued.named.blend;
3267 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3268
3269 if (!sctx->screen->has_out_of_order_rast)
3270 return false;
3271
3272 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3273
3274 if (blend) {
3275 colormask &= blend->cb_target_enabled_4bit;
3276 } else {
3277 colormask = 0;
3278 }
3279
3280 /* Conservative: No logic op. */
3281 if (colormask && blend->logicop_enable)
3282 return false;
3283
3284 struct si_dsa_order_invariance dsa_order_invariant = {
3285 .zs = true, .pass_set = true, .pass_last = false
3286 };
3287
3288 if (sctx->framebuffer.state.zsbuf) {
3289 struct r600_texture *zstex =
3290 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3291 bool has_stencil = zstex->surface.has_stencil;
3292 dsa_order_invariant = dsa->order_invariance[has_stencil];
3293 if (!dsa_order_invariant.zs)
3294 return false;
3295
3296 /* The set of PS invocations is always order invariant,
3297 * except when early Z/S tests are requested. */
3298 if (sctx->ps_shader.cso &&
3299 sctx->ps_shader.cso->info.writes_memory &&
3300 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3301 !dsa_order_invariant.pass_set)
3302 return false;
3303
3304 if (sctx->num_perfect_occlusion_queries != 0 &&
3305 !dsa_order_invariant.pass_set)
3306 return false;
3307 }
3308
3309 if (!colormask)
3310 return true;
3311
3312 unsigned blendmask = colormask & blend->blend_enable_4bit;
3313
3314 if (blendmask) {
3315 /* Only commutative blending. */
3316 if (blendmask & ~blend->commutative_4bit)
3317 return false;
3318
3319 if (!dsa_order_invariant.pass_set)
3320 return false;
3321 }
3322
3323 if (colormask & ~blendmask) {
3324 if (!dsa_order_invariant.pass_last)
3325 return false;
3326 }
3327
3328 return true;
3329 }
3330
3331 static void si_emit_msaa_config(struct si_context *sctx)
3332 {
3333 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3334 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3335 /* 33% faster rendering to linear color buffers */
3336 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3337 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3338 unsigned sc_mode_cntl_1 =
3339 S_028A4C_WALK_SIZE(dst_is_linear) |
3340 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3341 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3342 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3343 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3344 /* always 1: */
3345 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3346 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3347 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3348 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3349 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3350 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3351 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3352 S_028804_INCOHERENT_EQAA_READS(1) |
3353 S_028804_INTERPOLATE_COMP_Z(1) |
3354 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3355 unsigned coverage_samples, color_samples, z_samples;
3356
3357 /* S: Coverage samples (up to 16x):
3358 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3359 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3360 *
3361 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3362 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3363 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3364 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3365 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3366 * # Z samples).
3367 *
3368 * F: Color samples (up to 8x, must be <= coverage samples):
3369 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3370 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3371 *
3372 * Can be anything between coverage and color samples:
3373 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3374 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3375 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3376 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3377 * # All are currently set the same as coverage samples.
3378 *
3379 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3380 * flag for undefined color samples. A shader-based resolve must handle unknowns
3381 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3382 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3383 * useful. The CB resolve always drops unknowns.
3384 *
3385 * Sensible AA configurations:
3386 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3387 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3388 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3389 * EQAA 8s 8z 8f = 8x MSAA
3390 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3391 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3392 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3393 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3394 * EQAA 4s 4z 4f = 4x MSAA
3395 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3396 * EQAA 2s 2z 2f = 2x MSAA
3397 */
3398 if (sctx->framebuffer.nr_samples > 1) {
3399 coverage_samples = sctx->framebuffer.nr_samples;
3400 color_samples = sctx->framebuffer.nr_color_samples;
3401
3402 if (sctx->framebuffer.state.zsbuf) {
3403 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3404 z_samples = MAX2(1, z_samples);
3405 } else {
3406 z_samples = coverage_samples;
3407 }
3408 } else if (sctx->smoothing_enabled) {
3409 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3410 } else {
3411 coverage_samples = color_samples = z_samples = 1;
3412 }
3413
3414 /* Required by OpenGL line rasterization.
3415 *
3416 * TODO: We should also enable perpendicular endcaps for AA lines,
3417 * but that requires implementing line stippling in the pixel
3418 * shader. SC can only do line stippling with axis-aligned
3419 * endcaps.
3420 */
3421 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3422 unsigned sc_aa_config = 0;
3423
3424 if (coverage_samples > 1) {
3425 /* distance from the pixel center, indexed by log2(nr_samples) */
3426 static unsigned max_dist[] = {
3427 0, /* unused */
3428 4, /* 2x MSAA */
3429 6, /* 4x MSAA */
3430 7, /* 8x MSAA */
3431 8, /* 16x MSAA */
3432 };
3433 unsigned log_samples = util_logbase2(coverage_samples);
3434 unsigned log_z_samples = util_logbase2(z_samples);
3435 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3436 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3437
3438 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3439 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3440 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3441 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3442
3443 if (sctx->framebuffer.nr_samples > 1) {
3444 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3445 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3446 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3447 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3448 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3449 } else if (sctx->smoothing_enabled) {
3450 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3451 }
3452 }
3453
3454 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3455 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3456 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3457 sc_aa_config);
3458 /* R_028804_DB_EQAA */
3459 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3460 db_eqaa);
3461 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3462 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3463 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3464
3465 /* GFX9: Flush DFSM when the AA mode changes. */
3466 if (sctx->screen->dfsm_allowed) {
3467 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3468 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3469 }
3470 }
3471
3472 void si_update_ps_iter_samples(struct si_context *sctx)
3473 {
3474 if (sctx->framebuffer.nr_samples > 1)
3475 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3476 if (sctx->screen->dpbb_allowed)
3477 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3478 }
3479
3480 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3481 {
3482 struct si_context *sctx = (struct si_context *)ctx;
3483
3484 /* The hardware can only do sample shading with 2^n samples. */
3485 min_samples = util_next_power_of_two(min_samples);
3486
3487 if (sctx->ps_iter_samples == min_samples)
3488 return;
3489
3490 sctx->ps_iter_samples = min_samples;
3491 sctx->do_update_shaders = true;
3492
3493 si_update_ps_iter_samples(sctx);
3494 }
3495
3496 /*
3497 * Samplers
3498 */
3499
3500 /**
3501 * Build the sampler view descriptor for a buffer texture.
3502 * @param state 256-bit descriptor; only the high 128 bits are filled in
3503 */
3504 void
3505 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3506 enum pipe_format format,
3507 unsigned offset, unsigned size,
3508 uint32_t *state)
3509 {
3510 const struct util_format_description *desc;
3511 int first_non_void;
3512 unsigned stride;
3513 unsigned num_records;
3514 unsigned num_format, data_format;
3515
3516 desc = util_format_description(format);
3517 first_non_void = util_format_get_first_non_void_channel(format);
3518 stride = desc->block.bits / 8;
3519 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3520 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3521
3522 num_records = size / stride;
3523 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3524
3525 /* The NUM_RECORDS field has a different meaning depending on the chip,
3526 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3527 *
3528 * SI-CIK:
3529 * - If STRIDE == 0, it's in byte units.
3530 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3531 *
3532 * VI:
3533 * - For SMEM and STRIDE == 0, it's in byte units.
3534 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3535 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3536 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3537 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3538 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3539 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3540 * That way the same descriptor can be used by both SMEM and VMEM.
3541 *
3542 * GFX9:
3543 * - For SMEM and STRIDE == 0, it's in byte units.
3544 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3545 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3546 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3547 */
3548 if (screen->info.chip_class >= GFX9)
3549 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3550 * from STRIDE to bytes. This works around it by setting
3551 * NUM_RECORDS to at least the size of one element, so that
3552 * the first element is readable when IDXEN == 0.
3553 *
3554 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3555 * IDXEN is enforced?
3556 */
3557 num_records = num_records ? MAX2(num_records, stride) : 0;
3558 else if (screen->info.chip_class == VI)
3559 num_records *= stride;
3560
3561 state[4] = 0;
3562 state[5] = S_008F04_STRIDE(stride);
3563 state[6] = num_records;
3564 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3565 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3566 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3567 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3568 S_008F0C_NUM_FORMAT(num_format) |
3569 S_008F0C_DATA_FORMAT(data_format);
3570 }
3571
3572 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3573 {
3574 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3575
3576 if (swizzle[3] == PIPE_SWIZZLE_X) {
3577 /* For the pre-defined border color values (white, opaque
3578 * black, transparent black), the only thing that matters is
3579 * that the alpha channel winds up in the correct place
3580 * (because the RGB channels are all the same) so either of
3581 * these enumerations will work.
3582 */
3583 if (swizzle[2] == PIPE_SWIZZLE_Y)
3584 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3585 else
3586 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3587 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3588 if (swizzle[1] == PIPE_SWIZZLE_Y)
3589 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3590 else
3591 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3592 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3593 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3594 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3595 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3596 }
3597
3598 return bc_swizzle;
3599 }
3600
3601 /**
3602 * Build the sampler view descriptor for a texture.
3603 */
3604 void
3605 si_make_texture_descriptor(struct si_screen *screen,
3606 struct r600_texture *tex,
3607 bool sampler,
3608 enum pipe_texture_target target,
3609 enum pipe_format pipe_format,
3610 const unsigned char state_swizzle[4],
3611 unsigned first_level, unsigned last_level,
3612 unsigned first_layer, unsigned last_layer,
3613 unsigned width, unsigned height, unsigned depth,
3614 uint32_t *state,
3615 uint32_t *fmask_state)
3616 {
3617 struct pipe_resource *res = &tex->buffer.b.b;
3618 const struct util_format_description *desc;
3619 unsigned char swizzle[4];
3620 int first_non_void;
3621 unsigned num_format, data_format, type, num_samples;
3622 uint64_t va;
3623
3624 desc = util_format_description(pipe_format);
3625
3626 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3627 MAX2(1, res->nr_samples) : tex->num_color_samples;
3628
3629 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3630 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3631 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3632 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3633
3634 switch (pipe_format) {
3635 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3636 case PIPE_FORMAT_X32_S8X24_UINT:
3637 case PIPE_FORMAT_X8Z24_UNORM:
3638 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3639 break;
3640 case PIPE_FORMAT_X24S8_UINT:
3641 /*
3642 * X24S8 is implemented as an 8_8_8_8 data format, to
3643 * fix texture gathers. This affects at least
3644 * GL45-CTS.texture_cube_map_array.sampling on VI.
3645 */
3646 if (screen->info.chip_class <= VI)
3647 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3648 else
3649 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3650 break;
3651 default:
3652 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3653 }
3654 } else {
3655 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3656 }
3657
3658 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3659
3660 switch (pipe_format) {
3661 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3662 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3663 break;
3664 default:
3665 if (first_non_void < 0) {
3666 if (util_format_is_compressed(pipe_format)) {
3667 switch (pipe_format) {
3668 case PIPE_FORMAT_DXT1_SRGB:
3669 case PIPE_FORMAT_DXT1_SRGBA:
3670 case PIPE_FORMAT_DXT3_SRGBA:
3671 case PIPE_FORMAT_DXT5_SRGBA:
3672 case PIPE_FORMAT_BPTC_SRGBA:
3673 case PIPE_FORMAT_ETC2_SRGB8:
3674 case PIPE_FORMAT_ETC2_SRGB8A1:
3675 case PIPE_FORMAT_ETC2_SRGBA8:
3676 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3677 break;
3678 case PIPE_FORMAT_RGTC1_SNORM:
3679 case PIPE_FORMAT_LATC1_SNORM:
3680 case PIPE_FORMAT_RGTC2_SNORM:
3681 case PIPE_FORMAT_LATC2_SNORM:
3682 case PIPE_FORMAT_ETC2_R11_SNORM:
3683 case PIPE_FORMAT_ETC2_RG11_SNORM:
3684 /* implies float, so use SNORM/UNORM to determine
3685 whether data is signed or not */
3686 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3687 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3688 break;
3689 default:
3690 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3691 break;
3692 }
3693 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3694 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3695 } else {
3696 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3697 }
3698 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3699 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3700 } else {
3701 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3702
3703 switch (desc->channel[first_non_void].type) {
3704 case UTIL_FORMAT_TYPE_FLOAT:
3705 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3706 break;
3707 case UTIL_FORMAT_TYPE_SIGNED:
3708 if (desc->channel[first_non_void].normalized)
3709 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3710 else if (desc->channel[first_non_void].pure_integer)
3711 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3712 else
3713 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3714 break;
3715 case UTIL_FORMAT_TYPE_UNSIGNED:
3716 if (desc->channel[first_non_void].normalized)
3717 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3718 else if (desc->channel[first_non_void].pure_integer)
3719 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3720 else
3721 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3722 }
3723 }
3724 }
3725
3726 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3727 if (data_format == ~0) {
3728 data_format = 0;
3729 }
3730
3731 /* S8 with Z32 HTILE needs a special format. */
3732 if (screen->info.chip_class >= GFX9 &&
3733 pipe_format == PIPE_FORMAT_S8_UINT &&
3734 tex->tc_compatible_htile)
3735 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3736
3737 if (!sampler &&
3738 (res->target == PIPE_TEXTURE_CUBE ||
3739 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3740 (screen->info.chip_class <= VI &&
3741 res->target == PIPE_TEXTURE_3D))) {
3742 /* For the purpose of shader images, treat cube maps and 3D
3743 * textures as 2D arrays. For 3D textures, the address
3744 * calculations for mipmaps are different, so we rely on the
3745 * caller to effectively disable mipmaps.
3746 */
3747 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3748
3749 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3750 } else {
3751 type = si_tex_dim(screen, tex, target, num_samples);
3752 }
3753
3754 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3755 height = 1;
3756 depth = res->array_size;
3757 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3758 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3759 if (sampler || res->target != PIPE_TEXTURE_3D)
3760 depth = res->array_size;
3761 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3762 depth = res->array_size / 6;
3763
3764 state[0] = 0;
3765 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3766 S_008F14_NUM_FORMAT_GFX6(num_format));
3767 state[2] = (S_008F18_WIDTH(width - 1) |
3768 S_008F18_HEIGHT(height - 1) |
3769 S_008F18_PERF_MOD(4));
3770 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3771 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3772 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3773 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3774 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3775 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3776 util_logbase2(num_samples) :
3777 last_level) |
3778 S_008F1C_TYPE(type));
3779 state[4] = 0;
3780 state[5] = S_008F24_BASE_ARRAY(first_layer);
3781 state[6] = 0;
3782 state[7] = 0;
3783
3784 if (screen->info.chip_class >= GFX9) {
3785 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3786
3787 /* Depth is the the last accessible layer on Gfx9.
3788 * The hw doesn't need to know the total number of layers.
3789 */
3790 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3791 state[4] |= S_008F20_DEPTH(depth - 1);
3792 else
3793 state[4] |= S_008F20_DEPTH(last_layer);
3794
3795 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3796 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3797 util_logbase2(num_samples) :
3798 tex->buffer.b.b.last_level);
3799 } else {
3800 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3801 state[4] |= S_008F20_DEPTH(depth - 1);
3802 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3803 }
3804
3805 if (tex->dcc_offset) {
3806 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3807 } else {
3808 /* The last dword is unused by hw. The shader uses it to clear
3809 * bits in the first dword of sampler state.
3810 */
3811 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3812 if (first_level == last_level)
3813 state[7] = C_008F30_MAX_ANISO_RATIO;
3814 else
3815 state[7] = 0xffffffff;
3816 }
3817 }
3818
3819 /* Initialize the sampler view for FMASK. */
3820 if (tex->surface.fmask_size) {
3821 uint32_t data_format, num_format;
3822
3823 va = tex->buffer.gpu_address + tex->fmask_offset;
3824
3825 #define FMASK(s,f) (((unsigned)(s) * 16) + (f))
3826 if (screen->info.chip_class >= GFX9) {
3827 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3828 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3829 case FMASK(2,1):
3830 num_format = V_008F14_IMG_FMASK_8_2_1;
3831 break;
3832 case FMASK(2,2):
3833 num_format = V_008F14_IMG_FMASK_8_2_2;
3834 break;
3835 case FMASK(4,1):
3836 num_format = V_008F14_IMG_FMASK_8_4_1;
3837 break;
3838 case FMASK(4,2):
3839 num_format = V_008F14_IMG_FMASK_8_4_2;
3840 break;
3841 case FMASK(4,4):
3842 num_format = V_008F14_IMG_FMASK_8_4_4;
3843 break;
3844 case FMASK(8,1):
3845 num_format = V_008F14_IMG_FMASK_8_8_1;
3846 break;
3847 case FMASK(8,2):
3848 num_format = V_008F14_IMG_FMASK_16_8_2;
3849 break;
3850 case FMASK(8,4):
3851 num_format = V_008F14_IMG_FMASK_32_8_4;
3852 break;
3853 case FMASK(8,8):
3854 num_format = V_008F14_IMG_FMASK_32_8_8;
3855 break;
3856 case FMASK(16,1):
3857 num_format = V_008F14_IMG_FMASK_16_16_1;
3858 break;
3859 case FMASK(16,2):
3860 num_format = V_008F14_IMG_FMASK_32_16_2;
3861 break;
3862 case FMASK(16,4):
3863 num_format = V_008F14_IMG_FMASK_64_16_4;
3864 break;
3865 case FMASK(16,8):
3866 num_format = V_008F14_IMG_FMASK_64_16_8;
3867 break;
3868 default:
3869 unreachable("invalid nr_samples");
3870 }
3871 } else {
3872 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3873 case FMASK(2,1):
3874 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3875 break;
3876 case FMASK(2,2):
3877 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3878 break;
3879 case FMASK(4,1):
3880 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3881 break;
3882 case FMASK(4,2):
3883 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3884 break;
3885 case FMASK(4,4):
3886 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3887 break;
3888 case FMASK(8,1):
3889 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3890 break;
3891 case FMASK(8,2):
3892 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3893 break;
3894 case FMASK(8,4):
3895 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3896 break;
3897 case FMASK(8,8):
3898 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3899 break;
3900 case FMASK(16,1):
3901 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3902 break;
3903 case FMASK(16,2):
3904 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3905 break;
3906 case FMASK(16,4):
3907 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3908 break;
3909 case FMASK(16,8):
3910 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3911 break;
3912 default:
3913 unreachable("invalid nr_samples");
3914 }
3915 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3916 }
3917 #undef FMASK
3918
3919 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3920 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3921 S_008F14_DATA_FORMAT_GFX6(data_format) |
3922 S_008F14_NUM_FORMAT_GFX6(num_format);
3923 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3924 S_008F18_HEIGHT(height - 1);
3925 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3926 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3927 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3928 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3929 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3930 fmask_state[4] = 0;
3931 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3932 fmask_state[6] = 0;
3933 fmask_state[7] = 0;
3934
3935 if (screen->info.chip_class >= GFX9) {
3936 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3937 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3938 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3939 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3940 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3941 } else {
3942 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3943 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3944 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3945 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3946 }
3947 }
3948 }
3949
3950 /**
3951 * Create a sampler view.
3952 *
3953 * @param ctx context
3954 * @param texture texture
3955 * @param state sampler view template
3956 * @param width0 width0 override (for compressed textures as int)
3957 * @param height0 height0 override (for compressed textures as int)
3958 * @param force_level set the base address to the level (for compressed textures)
3959 */
3960 struct pipe_sampler_view *
3961 si_create_sampler_view_custom(struct pipe_context *ctx,
3962 struct pipe_resource *texture,
3963 const struct pipe_sampler_view *state,
3964 unsigned width0, unsigned height0,
3965 unsigned force_level)
3966 {
3967 struct si_context *sctx = (struct si_context*)ctx;
3968 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3969 struct r600_texture *tmp = (struct r600_texture*)texture;
3970 unsigned base_level, first_level, last_level;
3971 unsigned char state_swizzle[4];
3972 unsigned height, depth, width;
3973 unsigned last_layer = state->u.tex.last_layer;
3974 enum pipe_format pipe_format;
3975 const struct legacy_surf_level *surflevel;
3976
3977 if (!view)
3978 return NULL;
3979
3980 /* initialize base object */
3981 view->base = *state;
3982 view->base.texture = NULL;
3983 view->base.reference.count = 1;
3984 view->base.context = ctx;
3985
3986 assert(texture);
3987 pipe_resource_reference(&view->base.texture, texture);
3988
3989 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3990 state->format == PIPE_FORMAT_S8X24_UINT ||
3991 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3992 state->format == PIPE_FORMAT_S8_UINT)
3993 view->is_stencil_sampler = true;
3994
3995 /* Buffer resource. */
3996 if (texture->target == PIPE_BUFFER) {
3997 si_make_buffer_descriptor(sctx->screen,
3998 r600_resource(texture),
3999 state->format,
4000 state->u.buf.offset,
4001 state->u.buf.size,
4002 view->state);
4003 return &view->base;
4004 }
4005
4006 state_swizzle[0] = state->swizzle_r;
4007 state_swizzle[1] = state->swizzle_g;
4008 state_swizzle[2] = state->swizzle_b;
4009 state_swizzle[3] = state->swizzle_a;
4010
4011 base_level = 0;
4012 first_level = state->u.tex.first_level;
4013 last_level = state->u.tex.last_level;
4014 width = width0;
4015 height = height0;
4016 depth = texture->depth0;
4017
4018 if (sctx->chip_class <= VI && force_level) {
4019 assert(force_level == first_level &&
4020 force_level == last_level);
4021 base_level = force_level;
4022 first_level = 0;
4023 last_level = 0;
4024 width = u_minify(width, force_level);
4025 height = u_minify(height, force_level);
4026 depth = u_minify(depth, force_level);
4027 }
4028
4029 /* This is not needed if state trackers set last_layer correctly. */
4030 if (state->target == PIPE_TEXTURE_1D ||
4031 state->target == PIPE_TEXTURE_2D ||
4032 state->target == PIPE_TEXTURE_RECT ||
4033 state->target == PIPE_TEXTURE_CUBE)
4034 last_layer = state->u.tex.first_layer;
4035
4036 /* Texturing with separate depth and stencil. */
4037 pipe_format = state->format;
4038
4039 /* Depth/stencil texturing sometimes needs separate texture. */
4040 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
4041 if (!tmp->flushed_depth_texture &&
4042 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4043 pipe_resource_reference(&view->base.texture, NULL);
4044 FREE(view);
4045 return NULL;
4046 }
4047
4048 assert(tmp->flushed_depth_texture);
4049
4050 /* Override format for the case where the flushed texture
4051 * contains only Z or only S.
4052 */
4053 if (tmp->flushed_depth_texture->buffer.b.b.format != tmp->buffer.b.b.format)
4054 pipe_format = tmp->flushed_depth_texture->buffer.b.b.format;
4055
4056 tmp = tmp->flushed_depth_texture;
4057 }
4058
4059 surflevel = tmp->surface.u.legacy.level;
4060
4061 if (tmp->db_compatible) {
4062 if (!view->is_stencil_sampler)
4063 pipe_format = tmp->db_render_format;
4064
4065 switch (pipe_format) {
4066 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4067 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4068 break;
4069 case PIPE_FORMAT_X8Z24_UNORM:
4070 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4071 /* Z24 is always stored like this for DB
4072 * compatibility.
4073 */
4074 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4075 break;
4076 case PIPE_FORMAT_X24S8_UINT:
4077 case PIPE_FORMAT_S8X24_UINT:
4078 case PIPE_FORMAT_X32_S8X24_UINT:
4079 pipe_format = PIPE_FORMAT_S8_UINT;
4080 surflevel = tmp->surface.u.legacy.stencil_level;
4081 break;
4082 default:;
4083 }
4084 }
4085
4086 view->dcc_incompatible =
4087 vi_dcc_formats_are_incompatible(texture,
4088 state->u.tex.first_level,
4089 state->format);
4090
4091 si_make_texture_descriptor(sctx->screen, tmp, true,
4092 state->target, pipe_format, state_swizzle,
4093 first_level, last_level,
4094 state->u.tex.first_layer, last_layer,
4095 width, height, depth,
4096 view->state, view->fmask_state);
4097
4098 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4099 view->is_integer =
4100 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4101 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4102 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4103 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4104 view->base_level_info = &surflevel[base_level];
4105 view->base_level = base_level;
4106 view->block_width = util_format_get_blockwidth(pipe_format);
4107 return &view->base;
4108 }
4109
4110 static struct pipe_sampler_view *
4111 si_create_sampler_view(struct pipe_context *ctx,
4112 struct pipe_resource *texture,
4113 const struct pipe_sampler_view *state)
4114 {
4115 return si_create_sampler_view_custom(ctx, texture, state,
4116 texture ? texture->width0 : 0,
4117 texture ? texture->height0 : 0, 0);
4118 }
4119
4120 static void si_sampler_view_destroy(struct pipe_context *ctx,
4121 struct pipe_sampler_view *state)
4122 {
4123 struct si_sampler_view *view = (struct si_sampler_view *)state;
4124
4125 pipe_resource_reference(&state->texture, NULL);
4126 FREE(view);
4127 }
4128
4129 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4130 {
4131 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4132 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4133 (linear_filter &&
4134 (wrap == PIPE_TEX_WRAP_CLAMP ||
4135 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4136 }
4137
4138 static uint32_t si_translate_border_color(struct si_context *sctx,
4139 const struct pipe_sampler_state *state,
4140 const union pipe_color_union *color,
4141 bool is_integer)
4142 {
4143 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4144 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4145
4146 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4147 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4148 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4149 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4150
4151 #define simple_border_types(elt) \
4152 do { \
4153 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4154 color->elt[2] == 0 && color->elt[3] == 0) \
4155 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4156 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4157 color->elt[2] == 0 && color->elt[3] == 1) \
4158 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4159 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4160 color->elt[2] == 1 && color->elt[3] == 1) \
4161 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4162 } while (false)
4163
4164 if (is_integer)
4165 simple_border_types(ui);
4166 else
4167 simple_border_types(f);
4168
4169 #undef simple_border_types
4170
4171 int i;
4172
4173 /* Check if the border has been uploaded already. */
4174 for (i = 0; i < sctx->border_color_count; i++)
4175 if (memcmp(&sctx->border_color_table[i], color,
4176 sizeof(*color)) == 0)
4177 break;
4178
4179 if (i >= SI_MAX_BORDER_COLORS) {
4180 /* Getting 4096 unique border colors is very unlikely. */
4181 fprintf(stderr, "radeonsi: The border color table is full. "
4182 "Any new border colors will be just black. "
4183 "Please file a bug.\n");
4184 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4185 }
4186
4187 if (i == sctx->border_color_count) {
4188 /* Upload a new border color. */
4189 memcpy(&sctx->border_color_table[i], color,
4190 sizeof(*color));
4191 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4192 color, sizeof(*color));
4193 sctx->border_color_count++;
4194 }
4195
4196 return S_008F3C_BORDER_COLOR_PTR(i) |
4197 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4198 }
4199
4200 static inline int S_FIXED(float value, unsigned frac_bits)
4201 {
4202 return value * (1 << frac_bits);
4203 }
4204
4205 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4206 {
4207 if (filter == PIPE_TEX_FILTER_LINEAR)
4208 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4209 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4210 else
4211 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4212 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4213 }
4214
4215 static inline unsigned si_tex_aniso_filter(unsigned filter)
4216 {
4217 if (filter < 2)
4218 return 0;
4219 if (filter < 4)
4220 return 1;
4221 if (filter < 8)
4222 return 2;
4223 if (filter < 16)
4224 return 3;
4225 return 4;
4226 }
4227
4228 static void *si_create_sampler_state(struct pipe_context *ctx,
4229 const struct pipe_sampler_state *state)
4230 {
4231 struct si_context *sctx = (struct si_context *)ctx;
4232 struct si_screen *sscreen = sctx->screen;
4233 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4234 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4235 : state->max_anisotropy;
4236 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4237 union pipe_color_union clamped_border_color;
4238
4239 if (!rstate) {
4240 return NULL;
4241 }
4242
4243 #ifdef DEBUG
4244 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4245 #endif
4246 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4247 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4248 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4249 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4250 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4251 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4252 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4253 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4254 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4255 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4256 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4257 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4258 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4259 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4260 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4261 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4262 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4263 S_008F38_MIP_POINT_PRECLAMP(0) |
4264 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4265 S_008F38_FILTER_PREC_FIX(1) |
4266 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4267 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4268
4269 /* Create sampler resource for integer textures. */
4270 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4271 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4272
4273 /* Create sampler resource for upgraded depth textures. */
4274 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4275
4276 for (unsigned i = 0; i < 4; ++i) {
4277 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4278 * when the border color is 1.0. */
4279 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4280 }
4281
4282 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4283 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4284 else
4285 rstate->upgraded_depth_val[3] =
4286 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4287 S_008F3C_UPGRADED_DEPTH(1);
4288
4289 return rstate;
4290 }
4291
4292 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4293 {
4294 struct si_context *sctx = (struct si_context *)ctx;
4295
4296 if (sctx->sample_mask == (uint16_t)sample_mask)
4297 return;
4298
4299 sctx->sample_mask = sample_mask;
4300 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4301 }
4302
4303 static void si_emit_sample_mask(struct si_context *sctx)
4304 {
4305 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4306 unsigned mask = sctx->sample_mask;
4307
4308 /* Needed for line and polygon smoothing as well as for the Polaris
4309 * small primitive filter. We expect the state tracker to take care of
4310 * this for us.
4311 */
4312 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4313 (mask & 1 && sctx->blitter->running));
4314
4315 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4316 radeon_emit(cs, mask | (mask << 16));
4317 radeon_emit(cs, mask | (mask << 16));
4318 }
4319
4320 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4321 {
4322 #ifdef DEBUG
4323 struct si_sampler_state *s = state;
4324
4325 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4326 s->magic = 0;
4327 #endif
4328 free(state);
4329 }
4330
4331 /*
4332 * Vertex elements & buffers
4333 */
4334
4335 static void *si_create_vertex_elements(struct pipe_context *ctx,
4336 unsigned count,
4337 const struct pipe_vertex_element *elements)
4338 {
4339 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4340 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4341 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4342 int i;
4343
4344 assert(count <= SI_MAX_ATTRIBS);
4345 if (!v)
4346 return NULL;
4347
4348 v->count = count;
4349 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4350
4351 for (i = 0; i < count; ++i) {
4352 const struct util_format_description *desc;
4353 const struct util_format_channel_description *channel;
4354 unsigned data_format, num_format;
4355 int first_non_void;
4356 unsigned vbo_index = elements[i].vertex_buffer_index;
4357 unsigned char swizzle[4];
4358
4359 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4360 FREE(v);
4361 return NULL;
4362 }
4363
4364 if (elements[i].instance_divisor) {
4365 v->uses_instance_divisors = true;
4366 v->instance_divisors[i] = elements[i].instance_divisor;
4367
4368 if (v->instance_divisors[i] == 1)
4369 v->instance_divisor_is_one |= 1u << i;
4370 else
4371 v->instance_divisor_is_fetched |= 1u << i;
4372 }
4373
4374 if (!used[vbo_index]) {
4375 v->first_vb_use_mask |= 1 << i;
4376 used[vbo_index] = true;
4377 }
4378
4379 desc = util_format_description(elements[i].src_format);
4380 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4381 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4382 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4383 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4384 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4385
4386 v->format_size[i] = desc->block.bits / 8;
4387 v->src_offset[i] = elements[i].src_offset;
4388 v->vertex_buffer_index[i] = vbo_index;
4389
4390 /* The hardware always treats the 2-bit alpha channel as
4391 * unsigned, so a shader workaround is needed. The affected
4392 * chips are VI and older except Stoney (GFX8.1).
4393 */
4394 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4395 sscreen->info.chip_class <= VI &&
4396 sscreen->info.family != CHIP_STONEY) {
4397 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4398 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4399 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4400 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4401 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4402 /* This isn't actually used in OpenGL. */
4403 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4404 }
4405 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4406 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4407 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4408 else
4409 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4410 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4411 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4412 if (channel->normalized) {
4413 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4414 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4415 else
4416 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4417 } else {
4418 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4419 }
4420 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4421 if (channel->normalized) {
4422 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4423 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4424 else
4425 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4426 } else {
4427 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4428 }
4429 }
4430 } else if (channel && channel->size == 64 &&
4431 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4432 switch (desc->nr_channels) {
4433 case 1:
4434 case 2:
4435 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4436 swizzle[0] = PIPE_SWIZZLE_X;
4437 swizzle[1] = PIPE_SWIZZLE_Y;
4438 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4439 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4440 break;
4441 case 3:
4442 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4443 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4444 swizzle[1] = PIPE_SWIZZLE_Y;
4445 swizzle[2] = PIPE_SWIZZLE_0;
4446 swizzle[3] = PIPE_SWIZZLE_0;
4447 break;
4448 case 4:
4449 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4450 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4451 swizzle[1] = PIPE_SWIZZLE_Y;
4452 swizzle[2] = PIPE_SWIZZLE_Z;
4453 swizzle[3] = PIPE_SWIZZLE_W;
4454 break;
4455 default:
4456 assert(0);
4457 }
4458 } else if (channel && desc->nr_channels == 3) {
4459 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4460
4461 if (channel->size == 8) {
4462 if (channel->pure_integer)
4463 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4464 else
4465 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4466 } else if (channel->size == 16) {
4467 if (channel->pure_integer)
4468 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4469 else
4470 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4471 }
4472 }
4473
4474 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4475 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4476 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4477 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4478 S_008F0C_NUM_FORMAT(num_format) |
4479 S_008F0C_DATA_FORMAT(data_format);
4480 }
4481 return v;
4482 }
4483
4484 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4485 {
4486 struct si_context *sctx = (struct si_context *)ctx;
4487 struct si_vertex_elements *old = sctx->vertex_elements;
4488 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4489
4490 sctx->vertex_elements = v;
4491 sctx->vertex_buffers_dirty = true;
4492
4493 if (v &&
4494 (!old ||
4495 old->count != v->count ||
4496 old->uses_instance_divisors != v->uses_instance_divisors ||
4497 v->uses_instance_divisors || /* we don't check which divisors changed */
4498 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4499 sctx->do_update_shaders = true;
4500
4501 if (v && v->instance_divisor_is_fetched) {
4502 struct pipe_constant_buffer cb;
4503
4504 cb.buffer = NULL;
4505 cb.user_buffer = v->instance_divisors;
4506 cb.buffer_offset = 0;
4507 cb.buffer_size = sizeof(uint32_t) * v->count;
4508 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4509 }
4510 }
4511
4512 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4513 {
4514 struct si_context *sctx = (struct si_context *)ctx;
4515
4516 if (sctx->vertex_elements == state)
4517 sctx->vertex_elements = NULL;
4518 FREE(state);
4519 }
4520
4521 static void si_set_vertex_buffers(struct pipe_context *ctx,
4522 unsigned start_slot, unsigned count,
4523 const struct pipe_vertex_buffer *buffers)
4524 {
4525 struct si_context *sctx = (struct si_context *)ctx;
4526 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4527 int i;
4528
4529 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4530
4531 if (buffers) {
4532 for (i = 0; i < count; i++) {
4533 const struct pipe_vertex_buffer *src = buffers + i;
4534 struct pipe_vertex_buffer *dsti = dst + i;
4535 struct pipe_resource *buf = src->buffer.resource;
4536
4537 pipe_resource_reference(&dsti->buffer.resource, buf);
4538 dsti->buffer_offset = src->buffer_offset;
4539 dsti->stride = src->stride;
4540 si_context_add_resource_size(sctx, buf);
4541 if (buf)
4542 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4543 }
4544 } else {
4545 for (i = 0; i < count; i++) {
4546 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4547 }
4548 }
4549 sctx->vertex_buffers_dirty = true;
4550 }
4551
4552 /*
4553 * Misc
4554 */
4555
4556 static void si_set_tess_state(struct pipe_context *ctx,
4557 const float default_outer_level[4],
4558 const float default_inner_level[2])
4559 {
4560 struct si_context *sctx = (struct si_context *)ctx;
4561 struct pipe_constant_buffer cb;
4562 float array[8];
4563
4564 memcpy(array, default_outer_level, sizeof(float) * 4);
4565 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4566
4567 cb.buffer = NULL;
4568 cb.user_buffer = NULL;
4569 cb.buffer_size = sizeof(array);
4570
4571 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4572 (void*)array, sizeof(array),
4573 &cb.buffer_offset);
4574
4575 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4576 pipe_resource_reference(&cb.buffer, NULL);
4577 }
4578
4579 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4580 {
4581 struct si_context *sctx = (struct si_context *)ctx;
4582
4583 si_update_fb_dirtiness_after_rendering(sctx);
4584
4585 /* Multisample surfaces are flushed in si_decompress_textures. */
4586 if (sctx->framebuffer.uncompressed_cb_mask)
4587 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4588 sctx->framebuffer.CB_has_shader_readable_metadata);
4589 }
4590
4591 /* This only ensures coherency for shader image/buffer stores. */
4592 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4593 {
4594 struct si_context *sctx = (struct si_context *)ctx;
4595
4596 /* Subsequent commands must wait for all shader invocations to
4597 * complete. */
4598 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4599 SI_CONTEXT_CS_PARTIAL_FLUSH;
4600
4601 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4602 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4603 SI_CONTEXT_INV_VMEM_L1;
4604
4605 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4606 PIPE_BARRIER_SHADER_BUFFER |
4607 PIPE_BARRIER_TEXTURE |
4608 PIPE_BARRIER_IMAGE |
4609 PIPE_BARRIER_STREAMOUT_BUFFER |
4610 PIPE_BARRIER_GLOBAL_BUFFER)) {
4611 /* As far as I can tell, L1 contents are written back to L2
4612 * automatically at end of shader, but the contents of other
4613 * L1 caches might still be stale. */
4614 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4615 }
4616
4617 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4618 /* Indices are read through TC L2 since VI.
4619 * L1 isn't used.
4620 */
4621 if (sctx->screen->info.chip_class <= CIK)
4622 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4623 }
4624
4625 /* MSAA color, any depth and any stencil are flushed in
4626 * si_decompress_textures when needed.
4627 */
4628 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4629 sctx->framebuffer.uncompressed_cb_mask) {
4630 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4631
4632 if (sctx->chip_class <= VI)
4633 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4634 }
4635
4636 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4637 if (sctx->screen->info.chip_class <= VI &&
4638 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4639 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4640 }
4641
4642 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4643 {
4644 struct pipe_blend_state blend;
4645
4646 memset(&blend, 0, sizeof(blend));
4647 blend.independent_blend_enable = true;
4648 blend.rt[0].colormask = 0xf;
4649 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4650 }
4651
4652 static void si_init_config(struct si_context *sctx);
4653
4654 void si_init_state_functions(struct si_context *sctx)
4655 {
4656 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4657 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4658 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4659 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4660 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4661 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4662 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4663 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4664 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4665 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4666 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4667
4668 sctx->b.create_blend_state = si_create_blend_state;
4669 sctx->b.bind_blend_state = si_bind_blend_state;
4670 sctx->b.delete_blend_state = si_delete_blend_state;
4671 sctx->b.set_blend_color = si_set_blend_color;
4672
4673 sctx->b.create_rasterizer_state = si_create_rs_state;
4674 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4675 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4676
4677 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4678 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4679 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4680
4681 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4682 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4683 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4684 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4685 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4686
4687 sctx->b.set_clip_state = si_set_clip_state;
4688 sctx->b.set_stencil_ref = si_set_stencil_ref;
4689
4690 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4691
4692 sctx->b.create_sampler_state = si_create_sampler_state;
4693 sctx->b.delete_sampler_state = si_delete_sampler_state;
4694
4695 sctx->b.create_sampler_view = si_create_sampler_view;
4696 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4697
4698 sctx->b.set_sample_mask = si_set_sample_mask;
4699
4700 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4701 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4702 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4703 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4704
4705 sctx->b.texture_barrier = si_texture_barrier;
4706 sctx->b.memory_barrier = si_memory_barrier;
4707 sctx->b.set_min_samples = si_set_min_samples;
4708 sctx->b.set_tess_state = si_set_tess_state;
4709
4710 sctx->b.set_active_query_state = si_set_active_query_state;
4711
4712 sctx->b.draw_vbo = si_draw_vbo;
4713
4714 si_init_config(sctx);
4715 }
4716
4717 void si_init_screen_state_functions(struct si_screen *sscreen)
4718 {
4719 sscreen->b.is_format_supported = si_is_format_supported;
4720 }
4721
4722 static void si_set_grbm_gfx_index(struct si_context *sctx,
4723 struct si_pm4_state *pm4, unsigned value)
4724 {
4725 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4726 R_00802C_GRBM_GFX_INDEX;
4727 si_pm4_set_reg(pm4, reg, value);
4728 }
4729
4730 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4731 struct si_pm4_state *pm4, unsigned se)
4732 {
4733 assert(se == ~0 || se < sctx->screen->info.max_se);
4734 si_set_grbm_gfx_index(sctx, pm4,
4735 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4736 S_030800_SE_INDEX(se)) |
4737 S_030800_SH_BROADCAST_WRITES(1) |
4738 S_030800_INSTANCE_BROADCAST_WRITES(1));
4739 }
4740
4741 static void
4742 si_write_harvested_raster_configs(struct si_context *sctx,
4743 struct si_pm4_state *pm4,
4744 unsigned raster_config,
4745 unsigned raster_config_1)
4746 {
4747 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4748 unsigned raster_config_se[4];
4749 unsigned se;
4750
4751 ac_get_harvested_configs(&sctx->screen->info,
4752 raster_config,
4753 &raster_config_1,
4754 raster_config_se);
4755
4756 for (se = 0; se < num_se; se++) {
4757 si_set_grbm_gfx_index_se(sctx, pm4, se);
4758 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4759 }
4760 si_set_grbm_gfx_index(sctx, pm4, ~0);
4761
4762 if (sctx->chip_class >= CIK) {
4763 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4764 }
4765 }
4766
4767 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4768 {
4769 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4770 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4771 unsigned raster_config, raster_config_1;
4772
4773 ac_get_raster_config(&sctx->screen->info,
4774 &raster_config,
4775 &raster_config_1);
4776
4777 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4778 /* Always use the default config when all backends are enabled
4779 * (or when we failed to determine the enabled backends).
4780 */
4781 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4782 raster_config);
4783 if (sctx->chip_class >= CIK)
4784 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4785 raster_config_1);
4786 } else {
4787 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4788 }
4789 }
4790
4791 static void si_init_config(struct si_context *sctx)
4792 {
4793 struct si_screen *sscreen = sctx->screen;
4794 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4795 bool has_clear_state = sscreen->has_clear_state;
4796 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4797
4798 /* Only SI can disable CLEAR_STATE for now. */
4799 assert(has_clear_state || sscreen->info.chip_class == SI);
4800
4801 if (!pm4)
4802 return;
4803
4804 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4805 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4806 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4807 si_pm4_cmd_end(pm4, false);
4808
4809 if (has_clear_state) {
4810 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4811 si_pm4_cmd_add(pm4, 0);
4812 si_pm4_cmd_end(pm4, false);
4813 }
4814
4815 if (sctx->chip_class <= VI)
4816 si_set_raster_config(sctx, pm4);
4817
4818 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4819 if (!has_clear_state)
4820 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4821
4822 /* FIXME calculate these values somehow ??? */
4823 if (sctx->chip_class <= VI) {
4824 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4825 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4826 }
4827
4828 if (!has_clear_state) {
4829 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4830 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4831 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4832 }
4833
4834 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4835 if (!has_clear_state)
4836 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4837 if (sctx->chip_class < CIK)
4838 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4839 S_008A14_CLIP_VTX_REORDER_ENA(1));
4840
4841 if (!has_clear_state)
4842 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4843
4844 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4845 * I don't know why. Deduced by trial and error.
4846 */
4847 if (sctx->chip_class <= CIK) {
4848 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4849 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4850 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4851 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4852 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4853 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4854 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4855 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4856 }
4857
4858 if (!has_clear_state) {
4859 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4860 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4861 S_028230_ER_TRI(0xA) |
4862 S_028230_ER_POINT(0xA) |
4863 S_028230_ER_RECT(0xA) |
4864 /* Required by DX10_DIAMOND_TEST_ENA: */
4865 S_028230_ER_LINE_LR(0x1A) |
4866 S_028230_ER_LINE_RL(0x26) |
4867 S_028230_ER_LINE_TB(0xA) |
4868 S_028230_ER_LINE_BT(0xA));
4869 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4870 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4871 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4872 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4873 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4874 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4875 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4876 }
4877
4878 if (sctx->chip_class >= GFX9) {
4879 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4880 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4881 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4882 } else {
4883 /* These registers, when written, also overwrite the CLEAR_STATE
4884 * context, so we can't rely on CLEAR_STATE setting them.
4885 * It would be an issue if there was another UMD changing them.
4886 */
4887 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4888 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4889 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4890 }
4891
4892 if (sctx->chip_class >= CIK) {
4893 if (sctx->chip_class >= GFX9) {
4894 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4895 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4896 } else {
4897 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4898 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4899 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4900 S_00B41C_WAVE_LIMIT(0x3F));
4901 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4902 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4903
4904 /* If this is 0, Bonaire can hang even if GS isn't being used.
4905 * Other chips are unaffected. These are suboptimal values,
4906 * but we don't use on-chip GS.
4907 */
4908 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4909 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4910 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4911 }
4912 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4913 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4914
4915 /* Compute LATE_ALLOC_VS.LIMIT. */
4916 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4917 (sscreen->info.max_se *
4918 sscreen->info.max_sh_per_se);
4919 unsigned late_alloc_limit; /* The limit is per SH. */
4920
4921 if (sctx->family == CHIP_KABINI) {
4922 late_alloc_limit = 0; /* Potential hang on Kabini. */
4923 } else if (num_cu_per_sh <= 4) {
4924 /* Too few available compute units per SH. Disallowing
4925 * VS to run on one CU could hurt us more than late VS
4926 * allocation would help.
4927 *
4928 * 2 is the highest safe number that allows us to keep
4929 * all CUs enabled.
4930 */
4931 late_alloc_limit = 2;
4932 } else {
4933 /* This is a good initial value, allowing 1 late_alloc
4934 * wave per SIMD on num_cu - 2.
4935 */
4936 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4937
4938 /* The limit is 0-based, so 0 means 1. */
4939 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4940 late_alloc_limit -= 1;
4941 }
4942
4943 /* VS can't execute on one CU if the limit is > 2. */
4944 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4945 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4946 S_00B118_WAVE_LIMIT(0x3F));
4947 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4948 S_00B11C_LIMIT(late_alloc_limit));
4949 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4950 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4951 }
4952
4953 if (sctx->chip_class >= VI) {
4954 unsigned vgt_tess_distribution;
4955
4956 vgt_tess_distribution =
4957 S_028B50_ACCUM_ISOLINE(32) |
4958 S_028B50_ACCUM_TRI(11) |
4959 S_028B50_ACCUM_QUAD(11) |
4960 S_028B50_DONUT_SPLIT(16);
4961
4962 /* Testing with Unigine Heaven extreme tesselation yielded best results
4963 * with TRAP_SPLIT = 3.
4964 */
4965 if (sctx->family == CHIP_FIJI ||
4966 sctx->family >= CHIP_POLARIS10)
4967 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4968
4969 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4970 } else if (!has_clear_state) {
4971 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4972 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4973 }
4974
4975 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4976 if (sctx->chip_class >= CIK) {
4977 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4978 S_028084_ADDRESS(border_color_va >> 40));
4979 }
4980 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4981 RADEON_PRIO_BORDER_COLORS);
4982
4983 if (sctx->chip_class >= GFX9) {
4984 unsigned num_se = sscreen->info.max_se;
4985 unsigned pc_lines = 0;
4986
4987 switch (sctx->family) {
4988 case CHIP_VEGA10:
4989 case CHIP_VEGA12:
4990 pc_lines = 4096;
4991 break;
4992 case CHIP_RAVEN:
4993 pc_lines = 1024;
4994 break;
4995 default:
4996 assert(0);
4997 }
4998
4999 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5000 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5001 S_028C48_MAX_PRIM_PER_BATCH(1023));
5002 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5003 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5004 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5005 }
5006
5007 si_pm4_upload_indirect_buffer(sctx, pm4);
5008 sctx->init_config = pm4;
5009 }