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radeonsi: disallow compute-based culling if polygon mode is enabled
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/format/u_format.h"
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit &
86 blend->cb_target_mask;
87 unsigned i;
88
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
92 *
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
94 */
95 if (blend->dual_src_blend &&
96 sctx->ps_shader.cso &&
97 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
98 cb_target_mask = 0;
99
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
102 */
103 if (sctx->screen->dpbb_allowed &&
104 sctx->last_cb_target_mask != cb_target_mask) {
105 sctx->last_cb_target_mask = cb_target_mask;
106
107 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
108 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
109 }
110
111 unsigned initial_cdw = cs->current.cdw;
112 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
113 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
114
115 if (sctx->chip_class >= GFX8) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
119 */
120 bool oc_disable = blend->dcc_msaa_corruption_4bit & cb_target_mask &&
121 sctx->framebuffer.nr_samples >= 2;
122 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
123
124 radeon_opt_set_context_reg(
125 sctx, R_028424_CB_DCC_CONTROL,
126 SI_TRACKED_CB_DCC_CONTROL,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
131 }
132
133 /* RB+ register settings. */
134 if (sctx->screen->info.rbplus_allowed) {
135 unsigned spi_shader_col_format =
136 sctx->ps_shader.cso ?
137 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
138 unsigned sx_ps_downconvert = 0;
139 unsigned sx_blend_opt_epsilon = 0;
140 unsigned sx_blend_opt_control = 0;
141
142 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
143 struct si_surface *surf =
144 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
145 unsigned format, swap, spi_format, colormask;
146 bool has_alpha, has_rgb;
147
148 if (!surf) {
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
152 * enable RB+.
153 */
154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
155 continue;
156 }
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 break;
253
254 case V_028C70_COLOR_2_10_10_10:
255 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
256 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
257 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
258 }
259 break;
260 }
261 }
262
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
265 */
266 if (!sx_ps_downconvert)
267 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
268
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
271 SI_TRACKED_SX_PS_DOWNCONVERT,
272 sx_ps_downconvert, sx_blend_opt_epsilon,
273 sx_blend_opt_control);
274 }
275 if (initial_cdw != cs->current.cdw)
276 sctx->context_roll = true;
277 }
278
279 /*
280 * Blender functions
281 */
282
283 static uint32_t si_translate_blend_function(int blend_func)
284 {
285 switch (blend_func) {
286 case PIPE_BLEND_ADD:
287 return V_028780_COMB_DST_PLUS_SRC;
288 case PIPE_BLEND_SUBTRACT:
289 return V_028780_COMB_SRC_MINUS_DST;
290 case PIPE_BLEND_REVERSE_SUBTRACT:
291 return V_028780_COMB_DST_MINUS_SRC;
292 case PIPE_BLEND_MIN:
293 return V_028780_COMB_MIN_DST_SRC;
294 case PIPE_BLEND_MAX:
295 return V_028780_COMB_MAX_DST_SRC;
296 default:
297 PRINT_ERR("Unknown blend function %d\n", blend_func);
298 assert(0);
299 break;
300 }
301 return 0;
302 }
303
304 static uint32_t si_translate_blend_factor(int blend_fact)
305 {
306 switch (blend_fact) {
307 case PIPE_BLENDFACTOR_ONE:
308 return V_028780_BLEND_ONE;
309 case PIPE_BLENDFACTOR_SRC_COLOR:
310 return V_028780_BLEND_SRC_COLOR;
311 case PIPE_BLENDFACTOR_SRC_ALPHA:
312 return V_028780_BLEND_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_DST_ALPHA:
314 return V_028780_BLEND_DST_ALPHA;
315 case PIPE_BLENDFACTOR_DST_COLOR:
316 return V_028780_BLEND_DST_COLOR;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE;
319 case PIPE_BLENDFACTOR_CONST_COLOR:
320 return V_028780_BLEND_CONSTANT_COLOR;
321 case PIPE_BLENDFACTOR_CONST_ALPHA:
322 return V_028780_BLEND_CONSTANT_ALPHA;
323 case PIPE_BLENDFACTOR_ZERO:
324 return V_028780_BLEND_ZERO;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
337 case PIPE_BLENDFACTOR_SRC1_COLOR:
338 return V_028780_BLEND_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA:
340 return V_028780_BLEND_SRC1_ALPHA;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
342 return V_028780_BLEND_INV_SRC1_COLOR;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
344 return V_028780_BLEND_INV_SRC1_ALPHA;
345 default:
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
347 assert(0);
348 break;
349 }
350 return 0;
351 }
352
353 static uint32_t si_translate_blend_opt_function(int blend_func)
354 {
355 switch (blend_func) {
356 case PIPE_BLEND_ADD:
357 return V_028760_OPT_COMB_ADD;
358 case PIPE_BLEND_SUBTRACT:
359 return V_028760_OPT_COMB_SUBTRACT;
360 case PIPE_BLEND_REVERSE_SUBTRACT:
361 return V_028760_OPT_COMB_REVSUBTRACT;
362 case PIPE_BLEND_MIN:
363 return V_028760_OPT_COMB_MIN;
364 case PIPE_BLEND_MAX:
365 return V_028760_OPT_COMB_MAX;
366 default:
367 return V_028760_OPT_COMB_BLEND_DISABLED;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
372 {
373 switch (blend_fact) {
374 case PIPE_BLENDFACTOR_ZERO:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
376 case PIPE_BLENDFACTOR_ONE:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
378 case PIPE_BLENDFACTOR_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
382 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
384 case PIPE_BLENDFACTOR_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
389 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
391 default:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
393 }
394 }
395
396 static void si_blend_check_commutativity(struct si_screen *sscreen,
397 struct si_state_blend *blend,
398 enum pipe_blend_func func,
399 enum pipe_blendfactor src,
400 enum pipe_blendfactor dst,
401 unsigned chanmask)
402 {
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed =
405 (1u << PIPE_BLENDFACTOR_ONE) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_ZERO) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
420
421 if (dst == PIPE_BLENDFACTOR_ONE &&
422 (src_allowed & (1u << src))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
425 * rounding.
426 *
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
430 * setting.
431 */
432 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
433 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
434 blend->commutative_4bit |= chanmask;
435 }
436 }
437
438 /**
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
441 */
442 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
443 unsigned *dst_factor, unsigned expected_dst,
444 unsigned replacement_src)
445 {
446 if (*src_factor == expected_dst &&
447 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
448 *src_factor = PIPE_BLENDFACTOR_ZERO;
449 *dst_factor = replacement_src;
450
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func == PIPE_BLEND_SUBTRACT)
453 *func = PIPE_BLEND_REVERSE_SUBTRACT;
454 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
455 *func = PIPE_BLEND_SUBTRACT;
456 }
457 }
458
459 static bool si_blend_factor_uses_dst(unsigned factor)
460 {
461 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
462 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
464 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
465 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
466 }
467
468 static void *si_create_blend_state_mode(struct pipe_context *ctx,
469 const struct pipe_blend_state *state,
470 unsigned mode)
471 {
472 struct si_context *sctx = (struct si_context*)ctx;
473 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
474 struct si_pm4_state *pm4 = &blend->pm4;
475 uint32_t sx_mrt_blend_opt[8] = {0};
476 uint32_t color_control = 0;
477 bool logicop_enable = state->logicop_enable &&
478 state->logicop_func != PIPE_LOGICOP_COPY;
479
480 if (!blend)
481 return NULL;
482
483 blend->alpha_to_coverage = state->alpha_to_coverage;
484 blend->alpha_to_one = state->alpha_to_one;
485 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
486 blend->logicop_enable = logicop_enable;
487
488 if (logicop_enable) {
489 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
490 } else {
491 color_control |= S_028808_ROP3(0xcc);
492 }
493
494 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
501
502 if (state->alpha_to_coverage)
503 blend->need_src_alpha_4bit |= 0xf;
504
505 blend->cb_target_mask = 0;
506 blend->cb_target_enabled_4bit = 0;
507
508 for (int i = 0; i < 8; i++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j = state->independent_blend_enable ? i : 0;
511
512 unsigned eqRGB = state->rt[j].rgb_func;
513 unsigned srcRGB = state->rt[j].rgb_src_factor;
514 unsigned dstRGB = state->rt[j].rgb_dst_factor;
515 unsigned eqA = state->rt[j].alpha_func;
516 unsigned srcA = state->rt[j].alpha_src_factor;
517 unsigned dstA = state->rt[j].alpha_dst_factor;
518
519 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
520 unsigned blend_cntl = 0;
521
522 sx_mrt_blend_opt[i] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
525
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i >= 1 && blend->dual_src_blend) {
528 /* Vulkan does this for dual source blending. */
529 if (i == 1)
530 blend_cntl |= S_028780_ENABLE(1);
531
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
538 */
539 if (blend->dual_src_blend &&
540 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
541 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544 continue;
545 }
546
547 /* cb_render_state will disable unused ones */
548 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
549 if (state->rt[j].colormask)
550 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
551
552 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
553 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
554 continue;
555 }
556
557 si_blend_check_commutativity(sctx->screen, blend,
558 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
559 si_blend_check_commutativity(sctx->screen, blend,
560 eqA, srcA, dstA, 0x8 << (4 * i));
561
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
564 *
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
567 */
568 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
569 PIPE_BLENDFACTOR_DST_COLOR,
570 PIPE_BLENDFACTOR_SRC_COLOR);
571 si_blend_remove_dst(&eqA, &srcA, &dstA,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_ALPHA,
576 PIPE_BLENDFACTOR_SRC_ALPHA);
577
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
580 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
581 srcA_opt = si_translate_blend_opt_factor(srcA, true);
582 dstA_opt = si_translate_blend_opt_factor(dstA, true);
583
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB))
586 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
587 if (si_blend_factor_uses_dst(srcA))
588 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
589
590 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
591 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
592 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
594 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
595
596 /* Set the final value. */
597 sx_mrt_blend_opt[i] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt) |
602 S_028760_ALPHA_DST_OPT(dstA_opt) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
604
605 /* Set blend state. */
606 blend_cntl |= S_028780_ENABLE(1);
607 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
608 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
609 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
610
611 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
612 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
614 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
615 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
616 }
617 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
618
619 blend->blend_enable_4bit |= 0xfu << (i * 4);
620
621 if (sctx->family <= CHIP_NAVI14)
622 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (sctx->family <= CHIP_NAVI14 && logicop_enable)
635 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
636
637 if (blend->cb_target_mask) {
638 color_control |= S_028808_MODE(mode);
639 } else {
640 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
641 }
642
643 if (sctx->screen->info.rbplus_allowed) {
644 /* Disable RB+ blend optimizations for dual source blending.
645 * Vulkan does this.
646 */
647 if (blend->dual_src_blend) {
648 for (int i = 0; i < 8; i++) {
649 sx_mrt_blend_opt[i] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
652 }
653 }
654
655 for (int i = 0; i < 8; i++)
656 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
657 sx_mrt_blend_opt[i]);
658
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend->dual_src_blend || logicop_enable ||
661 mode == V_028808_CB_RESOLVE)
662 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
663 }
664
665 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
666 return blend;
667 }
668
669 static void *si_create_blend_state(struct pipe_context *ctx,
670 const struct pipe_blend_state *state)
671 {
672 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
673 }
674
675 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
676 {
677 struct si_context *sctx = (struct si_context *)ctx;
678 struct si_state_blend *old_blend = sctx->queued.named.blend;
679 struct si_state_blend *blend = (struct si_state_blend *)state;
680
681 if (!blend)
682 blend = (struct si_state_blend *)sctx->noop_blend;
683
684 si_pm4_bind_state(sctx, blend, blend);
685
686 if (old_blend->cb_target_mask != blend->cb_target_mask ||
687 old_blend->dual_src_blend != blend->dual_src_blend ||
688 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
689 sctx->framebuffer.nr_samples >= 2 &&
690 sctx->screen->dcc_msaa_allowed))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
692
693 if (old_blend->cb_target_mask != blend->cb_target_mask ||
694 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
695 old_blend->alpha_to_one != blend->alpha_to_one ||
696 old_blend->dual_src_blend != blend->dual_src_blend ||
697 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
698 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
699 sctx->do_update_shaders = true;
700
701 if (sctx->screen->dpbb_allowed &&
702 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
709 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
710 old_blend->commutative_4bit != blend->commutative_4bit ||
711 old_blend->logicop_enable != blend->logicop_enable)))
712 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
713 }
714
715 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718
719 if (sctx->queued.named.blend == state)
720 si_bind_blend_state(ctx, sctx->noop_blend);
721
722 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
723 }
724
725 static void si_set_blend_color(struct pipe_context *ctx,
726 const struct pipe_blend_color *state)
727 {
728 struct si_context *sctx = (struct si_context *)ctx;
729 static const struct pipe_blend_color zeros;
730
731 sctx->blend_color.state = *state;
732 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
733 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
734 }
735
736 static void si_emit_blend_color(struct si_context *sctx)
737 {
738 struct radeon_cmdbuf *cs = sctx->gfx_cs;
739
740 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
741 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
742 }
743
744 /*
745 * Clipping
746 */
747
748 static void si_set_clip_state(struct pipe_context *ctx,
749 const struct pipe_clip_state *state)
750 {
751 struct si_context *sctx = (struct si_context *)ctx;
752 struct pipe_constant_buffer cb;
753 static const struct pipe_clip_state zeros;
754
755 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
756 return;
757
758 sctx->clip_state.state = *state;
759 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
760 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
761
762 cb.buffer = NULL;
763 cb.user_buffer = state->ucp;
764 cb.buffer_offset = 0;
765 cb.buffer_size = 4*4*8;
766 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
767 pipe_resource_reference(&cb.buffer, NULL);
768 }
769
770 static void si_emit_clip_state(struct si_context *sctx)
771 {
772 struct radeon_cmdbuf *cs = sctx->gfx_cs;
773
774 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
775 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
776 }
777
778 static void si_emit_clip_regs(struct si_context *sctx)
779 {
780 struct si_shader *vs = si_get_vs_state(sctx);
781 struct si_shader_selector *vs_sel = vs->selector;
782 struct tgsi_shader_info *info = &vs_sel->info;
783 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
784 unsigned window_space =
785 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
786 unsigned clipdist_mask = vs_sel->clipdist_mask;
787 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
788 unsigned culldist_mask = vs_sel->culldist_mask;
789 unsigned total_mask;
790
791 if (vs->key.opt.clip_disable) {
792 assert(!info->culldist_writemask);
793 clipdist_mask = 0;
794 culldist_mask = 0;
795 }
796 total_mask = clipdist_mask | culldist_mask;
797
798 /* Clip distances on points have no effect, so need to be implemented
799 * as cull distances. This applies for the clipvertex case as well.
800 *
801 * Setting this for primitives other than points should have no adverse
802 * effects.
803 */
804 clipdist_mask &= rs->clip_plane_enable;
805 culldist_mask |= clipdist_mask;
806
807 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
808 unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
810 clipdist_mask | (culldist_mask << 8);
811
812 if (sctx->chip_class >= GFX10) {
813 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
814 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
815 pa_cl_cntl,
816 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
817 } else {
818 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
819 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
820 vs_sel->pa_cl_vs_out_cntl | pa_cl_cntl);
821 }
822 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
823 SI_TRACKED_PA_CL_CLIP_CNTL,
824 rs->pa_cl_clip_cntl |
825 ucp_mask |
826 S_028810_CLIP_DISABLE(window_space));
827
828 if (initial_cdw != sctx->gfx_cs->current.cdw)
829 sctx->context_roll = true;
830 }
831
832 /*
833 * inferred state between framebuffer and rasterizer
834 */
835 static void si_update_poly_offset_state(struct si_context *sctx)
836 {
837 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
838
839 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
840 si_pm4_bind_state(sctx, poly_offset, NULL);
841 return;
842 }
843
844 /* Use the user format, not db_render_format, so that the polygon
845 * offset behaves as expected by applications.
846 */
847 switch (sctx->framebuffer.state.zsbuf->texture->format) {
848 case PIPE_FORMAT_Z16_UNORM:
849 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
850 break;
851 default: /* 24-bit */
852 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
853 break;
854 case PIPE_FORMAT_Z32_FLOAT:
855 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
856 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
857 break;
858 }
859 }
860
861 /*
862 * Rasterizer
863 */
864
865 static uint32_t si_translate_fill(uint32_t func)
866 {
867 switch(func) {
868 case PIPE_POLYGON_MODE_FILL:
869 return V_028814_X_DRAW_TRIANGLES;
870 case PIPE_POLYGON_MODE_LINE:
871 return V_028814_X_DRAW_LINES;
872 case PIPE_POLYGON_MODE_POINT:
873 return V_028814_X_DRAW_POINTS;
874 default:
875 assert(0);
876 return V_028814_X_DRAW_POINTS;
877 }
878 }
879
880 static void *si_create_rs_state(struct pipe_context *ctx,
881 const struct pipe_rasterizer_state *state)
882 {
883 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
884 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
885 struct si_pm4_state *pm4 = &rs->pm4;
886 unsigned tmp, i;
887 float psize_min, psize_max;
888
889 if (!rs) {
890 return NULL;
891 }
892
893 if (!state->front_ccw) {
894 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
895 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
896 } else {
897 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
898 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
899 }
900 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
901 rs->provoking_vertex_first = state->flatshade_first;
902 rs->scissor_enable = state->scissor;
903 rs->clip_halfz = state->clip_halfz;
904 rs->two_side = state->light_twoside;
905 rs->multisample_enable = state->multisample;
906 rs->force_persample_interp = state->force_persample_interp;
907 rs->clip_plane_enable = state->clip_plane_enable;
908 rs->half_pixel_center = state->half_pixel_center;
909 rs->line_stipple_enable = state->line_stipple_enable;
910 rs->poly_stipple_enable = state->poly_stipple_enable;
911 rs->line_smooth = state->line_smooth;
912 rs->line_width = state->line_width;
913 rs->poly_smooth = state->poly_smooth;
914 rs->uses_poly_offset = state->offset_point || state->offset_line ||
915 state->offset_tri;
916 rs->clamp_fragment_color = state->clamp_fragment_color;
917 rs->clamp_vertex_color = state->clamp_vertex_color;
918 rs->flatshade = state->flatshade;
919 rs->flatshade_first = state->flatshade_first;
920 rs->sprite_coord_enable = state->sprite_coord_enable;
921 rs->rasterizer_discard = state->rasterizer_discard;
922 rs->polygon_mode_enabled = state->fill_front != PIPE_POLYGON_MODE_FILL ||
923 state->fill_back != PIPE_POLYGON_MODE_FILL;
924 rs->pa_sc_line_stipple = state->line_stipple_enable ?
925 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
926 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
927 rs->pa_cl_clip_cntl =
928 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
929 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
930 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
931 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
932 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
933
934 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
935 S_0286D4_FLAT_SHADE_ENA(1) |
936 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
937 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
938 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
939 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
940 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
941 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
942
943 /* point size 12.4 fixed point */
944 tmp = (unsigned)(state->point_size * 8.0);
945 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
946
947 if (state->point_size_per_vertex) {
948 psize_min = util_get_min_point_size(state);
949 psize_max = SI_MAX_POINT_SIZE;
950 } else {
951 /* Force the point size to be as if the vertex output was disabled. */
952 psize_min = state->point_size;
953 psize_max = state->point_size;
954 }
955 rs->max_point_size = psize_max;
956
957 /* Divide by two, because 0.5 = 1 pixel. */
958 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
959 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
960 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
961
962 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
963 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
964 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
965 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
966 S_028A48_MSAA_ENABLE(state->multisample ||
967 state->poly_smooth ||
968 state->line_smooth) |
969 S_028A48_VPORT_SCISSOR_ENABLE(1) |
970 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
971
972 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
973 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
974 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
975 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
976 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
977 S_028814_FACE(!state->front_ccw) |
978 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
979 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
980 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
981 S_028814_POLY_MODE(rs->polygon_mode_enabled) |
982 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
983 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
984
985 if (!rs->uses_poly_offset)
986 return rs;
987
988 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
989 if (!rs->pm4_poly_offset) {
990 FREE(rs);
991 return NULL;
992 }
993
994 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
995 for (i = 0; i < 3; i++) {
996 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
997 float offset_units = state->offset_units;
998 float offset_scale = state->offset_scale * 16.0f;
999 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1000
1001 if (!state->offset_units_unscaled) {
1002 switch (i) {
1003 case 0: /* 16-bit zbuffer */
1004 offset_units *= 4.0f;
1005 pa_su_poly_offset_db_fmt_cntl =
1006 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1007 break;
1008 case 1: /* 24-bit zbuffer */
1009 offset_units *= 2.0f;
1010 pa_su_poly_offset_db_fmt_cntl =
1011 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1012 break;
1013 case 2: /* 32-bit zbuffer */
1014 offset_units *= 1.0f;
1015 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1016 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1017 break;
1018 }
1019 }
1020
1021 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1022 fui(offset_scale));
1023 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1024 fui(offset_units));
1025 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1026 fui(offset_scale));
1027 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1028 fui(offset_units));
1029 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1030 pa_su_poly_offset_db_fmt_cntl);
1031 }
1032
1033 return rs;
1034 }
1035
1036 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1037 {
1038 struct si_context *sctx = (struct si_context *)ctx;
1039 struct si_state_rasterizer *old_rs =
1040 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1041 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1042
1043 if (!rs)
1044 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1045
1046 if (old_rs->multisample_enable != rs->multisample_enable) {
1047 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1048
1049 /* Update the small primitive filter workaround if necessary. */
1050 if (sctx->screen->info.has_msaa_sample_loc_bug &&
1051 sctx->framebuffer.nr_samples > 1)
1052 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1053 }
1054
1055 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1056 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1057
1058 si_pm4_bind_state(sctx, rasterizer, rs);
1059 si_update_poly_offset_state(sctx);
1060
1061 if (old_rs->scissor_enable != rs->scissor_enable)
1062 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1063
1064 if (old_rs->line_width != rs->line_width ||
1065 old_rs->max_point_size != rs->max_point_size ||
1066 old_rs->half_pixel_center != rs->half_pixel_center)
1067 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1068
1069 if (old_rs->clip_halfz != rs->clip_halfz)
1070 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1071
1072 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1073 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1074 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1075
1076 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1077 rs->line_stipple_enable;
1078
1079 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1080 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1081 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1082 old_rs->flatshade != rs->flatshade ||
1083 old_rs->two_side != rs->two_side ||
1084 old_rs->multisample_enable != rs->multisample_enable ||
1085 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1086 old_rs->poly_smooth != rs->poly_smooth ||
1087 old_rs->line_smooth != rs->line_smooth ||
1088 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1089 old_rs->force_persample_interp != rs->force_persample_interp)
1090 sctx->do_update_shaders = true;
1091 }
1092
1093 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1094 {
1095 struct si_context *sctx = (struct si_context *)ctx;
1096 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1097
1098 if (sctx->queued.named.rasterizer == state)
1099 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1100
1101 FREE(rs->pm4_poly_offset);
1102 si_pm4_delete_state(sctx, rasterizer, rs);
1103 }
1104
1105 /*
1106 * infeered state between dsa and stencil ref
1107 */
1108 static void si_emit_stencil_ref(struct si_context *sctx)
1109 {
1110 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1111 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1112 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1113
1114 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1115 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1116 S_028430_STENCILMASK(dsa->valuemask[0]) |
1117 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1118 S_028430_STENCILOPVAL(1));
1119 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1120 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1121 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1122 S_028434_STENCILOPVAL_BF(1));
1123 }
1124
1125 static void si_set_stencil_ref(struct pipe_context *ctx,
1126 const struct pipe_stencil_ref *state)
1127 {
1128 struct si_context *sctx = (struct si_context *)ctx;
1129
1130 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1131 return;
1132
1133 sctx->stencil_ref.state = *state;
1134 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1135 }
1136
1137
1138 /*
1139 * DSA
1140 */
1141
1142 static uint32_t si_translate_stencil_op(int s_op)
1143 {
1144 switch (s_op) {
1145 case PIPE_STENCIL_OP_KEEP:
1146 return V_02842C_STENCIL_KEEP;
1147 case PIPE_STENCIL_OP_ZERO:
1148 return V_02842C_STENCIL_ZERO;
1149 case PIPE_STENCIL_OP_REPLACE:
1150 return V_02842C_STENCIL_REPLACE_TEST;
1151 case PIPE_STENCIL_OP_INCR:
1152 return V_02842C_STENCIL_ADD_CLAMP;
1153 case PIPE_STENCIL_OP_DECR:
1154 return V_02842C_STENCIL_SUB_CLAMP;
1155 case PIPE_STENCIL_OP_INCR_WRAP:
1156 return V_02842C_STENCIL_ADD_WRAP;
1157 case PIPE_STENCIL_OP_DECR_WRAP:
1158 return V_02842C_STENCIL_SUB_WRAP;
1159 case PIPE_STENCIL_OP_INVERT:
1160 return V_02842C_STENCIL_INVERT;
1161 default:
1162 PRINT_ERR("Unknown stencil op %d", s_op);
1163 assert(0);
1164 break;
1165 }
1166 return 0;
1167 }
1168
1169 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1170 {
1171 return s->enabled && s->writemask &&
1172 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1173 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1174 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1175 }
1176
1177 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1178 {
1179 /* REPLACE is normally order invariant, except when the stencil
1180 * reference value is written by the fragment shader. Tracking this
1181 * interaction does not seem worth the effort, so be conservative. */
1182 return op != PIPE_STENCIL_OP_INCR &&
1183 op != PIPE_STENCIL_OP_DECR &&
1184 op != PIPE_STENCIL_OP_REPLACE;
1185 }
1186
1187 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1188 * invariant in the sense that the set of passing fragments as well as the
1189 * final stencil buffer result does not depend on the order of fragments. */
1190 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1191 {
1192 return !state->enabled || !state->writemask ||
1193 /* The following assumes that Z writes are disabled. */
1194 (state->func == PIPE_FUNC_ALWAYS &&
1195 si_order_invariant_stencil_op(state->zpass_op) &&
1196 si_order_invariant_stencil_op(state->zfail_op)) ||
1197 (state->func == PIPE_FUNC_NEVER &&
1198 si_order_invariant_stencil_op(state->fail_op));
1199 }
1200
1201 static void *si_create_dsa_state(struct pipe_context *ctx,
1202 const struct pipe_depth_stencil_alpha_state *state)
1203 {
1204 struct si_context *sctx = (struct si_context *)ctx;
1205 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1206 struct si_pm4_state *pm4 = &dsa->pm4;
1207 unsigned db_depth_control;
1208 uint32_t db_stencil_control = 0;
1209
1210 if (!dsa) {
1211 return NULL;
1212 }
1213
1214 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1215 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1216 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1217 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1218
1219 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1220 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1221 S_028800_ZFUNC(state->depth.func) |
1222 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1223
1224 /* stencil */
1225 if (state->stencil[0].enabled) {
1226 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1227 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1228 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1229 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1230 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1231
1232 if (state->stencil[1].enabled) {
1233 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1234 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1235 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1236 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1237 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1238 }
1239 }
1240
1241 /* alpha */
1242 if (state->alpha.enabled) {
1243 dsa->alpha_func = state->alpha.func;
1244
1245 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1246 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1247 } else {
1248 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1249 }
1250
1251 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1252 if (state->stencil[0].enabled)
1253 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1254 if (state->depth.bounds_test) {
1255 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1256 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1257 }
1258
1259 dsa->depth_enabled = state->depth.enabled;
1260 dsa->depth_write_enabled = state->depth.enabled &&
1261 state->depth.writemask;
1262 dsa->stencil_enabled = state->stencil[0].enabled;
1263 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1264 (si_dsa_writes_stencil(&state->stencil[0]) ||
1265 si_dsa_writes_stencil(&state->stencil[1]));
1266 dsa->db_can_write = dsa->depth_write_enabled ||
1267 dsa->stencil_write_enabled;
1268
1269 bool zfunc_is_ordered =
1270 state->depth.func == PIPE_FUNC_NEVER ||
1271 state->depth.func == PIPE_FUNC_LESS ||
1272 state->depth.func == PIPE_FUNC_LEQUAL ||
1273 state->depth.func == PIPE_FUNC_GREATER ||
1274 state->depth.func == PIPE_FUNC_GEQUAL;
1275
1276 bool nozwrite_and_order_invariant_stencil =
1277 !dsa->db_can_write ||
1278 (!dsa->depth_write_enabled &&
1279 si_order_invariant_stencil_state(&state->stencil[0]) &&
1280 si_order_invariant_stencil_state(&state->stencil[1]));
1281
1282 dsa->order_invariance[1].zs =
1283 nozwrite_and_order_invariant_stencil ||
1284 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1285 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1286
1287 dsa->order_invariance[1].pass_set =
1288 nozwrite_and_order_invariant_stencil ||
1289 (!dsa->stencil_write_enabled &&
1290 (state->depth.func == PIPE_FUNC_ALWAYS ||
1291 state->depth.func == PIPE_FUNC_NEVER));
1292 dsa->order_invariance[0].pass_set =
1293 !dsa->depth_write_enabled ||
1294 (state->depth.func == PIPE_FUNC_ALWAYS ||
1295 state->depth.func == PIPE_FUNC_NEVER);
1296
1297 dsa->order_invariance[1].pass_last =
1298 sctx->screen->assume_no_z_fights &&
1299 !dsa->stencil_write_enabled &&
1300 dsa->depth_write_enabled && zfunc_is_ordered;
1301 dsa->order_invariance[0].pass_last =
1302 sctx->screen->assume_no_z_fights &&
1303 dsa->depth_write_enabled && zfunc_is_ordered;
1304
1305 return dsa;
1306 }
1307
1308 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1309 {
1310 struct si_context *sctx = (struct si_context *)ctx;
1311 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1312 struct si_state_dsa *dsa = state;
1313
1314 if (!dsa)
1315 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1316
1317 si_pm4_bind_state(sctx, dsa, dsa);
1318
1319 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1320 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1321 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1322 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1323 }
1324
1325 if (old_dsa->alpha_func != dsa->alpha_func)
1326 sctx->do_update_shaders = true;
1327
1328 if (sctx->screen->dpbb_allowed &&
1329 ((old_dsa->depth_enabled != dsa->depth_enabled ||
1330 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1331 old_dsa->db_can_write != dsa->db_can_write)))
1332 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1333
1334 if (sctx->screen->has_out_of_order_rast &&
1335 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1336 sizeof(old_dsa->order_invariance))))
1337 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1338 }
1339
1340 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1341 {
1342 struct si_context *sctx = (struct si_context *)ctx;
1343
1344 if (sctx->queued.named.dsa == state)
1345 si_bind_dsa_state(ctx, sctx->noop_dsa);
1346
1347 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1348 }
1349
1350 static void *si_create_db_flush_dsa(struct si_context *sctx)
1351 {
1352 struct pipe_depth_stencil_alpha_state dsa = {};
1353
1354 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1355 }
1356
1357 /* DB RENDER STATE */
1358
1359 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1360 {
1361 struct si_context *sctx = (struct si_context*)ctx;
1362
1363 /* Pipeline stat & streamout queries. */
1364 if (enable) {
1365 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1366 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1367 } else {
1368 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1369 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1370 }
1371
1372 /* Occlusion queries. */
1373 if (sctx->occlusion_queries_disabled != !enable) {
1374 sctx->occlusion_queries_disabled = !enable;
1375 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1376 }
1377 }
1378
1379 void si_set_occlusion_query_state(struct si_context *sctx,
1380 bool old_perfect_enable)
1381 {
1382 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1383
1384 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1385
1386 if (perfect_enable != old_perfect_enable)
1387 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1388 }
1389
1390 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1391 {
1392 st->saved_compute = sctx->cs_shader_state.program;
1393
1394 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1395 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1396
1397 st->saved_ssbo_writable_mask = 0;
1398
1399 for (unsigned i = 0; i < 3; i++) {
1400 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1401 (1u << si_get_shaderbuf_slot(i)))
1402 st->saved_ssbo_writable_mask |= 1 << i;
1403 }
1404 }
1405
1406 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1407 {
1408 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1409
1410 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1411 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1412
1413 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1414 st->saved_ssbo_writable_mask);
1415 for (unsigned i = 0; i < 3; ++i)
1416 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1417 }
1418
1419 static void si_emit_db_render_state(struct si_context *sctx)
1420 {
1421 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1422 unsigned db_shader_control, db_render_control, db_count_control;
1423 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1424
1425 /* DB_RENDER_CONTROL */
1426 if (sctx->dbcb_depth_copy_enabled ||
1427 sctx->dbcb_stencil_copy_enabled) {
1428 db_render_control =
1429 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1430 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1431 S_028000_COPY_CENTROID(1) |
1432 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1433 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1434 db_render_control =
1435 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1436 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1437 } else {
1438 db_render_control =
1439 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1440 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1441 }
1442
1443 /* DB_COUNT_CONTROL (occlusion queries) */
1444 if (sctx->num_occlusion_queries > 0 &&
1445 !sctx->occlusion_queries_disabled) {
1446 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1447 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1448
1449 if (sctx->chip_class >= GFX7) {
1450 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1451
1452 /* Stoney doesn't increment occlusion query counters
1453 * if the sample rate is 16x. Use 8x sample rate instead.
1454 */
1455 if (sctx->family == CHIP_STONEY)
1456 log_sample_rate = MIN2(log_sample_rate, 3);
1457
1458 db_count_control =
1459 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1460 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1461 S_028004_SAMPLE_RATE(log_sample_rate) |
1462 S_028004_ZPASS_ENABLE(1) |
1463 S_028004_SLICE_EVEN_ENABLE(1) |
1464 S_028004_SLICE_ODD_ENABLE(1);
1465 } else {
1466 db_count_control =
1467 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1468 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1469 }
1470 } else {
1471 /* Disable occlusion queries. */
1472 if (sctx->chip_class >= GFX7) {
1473 db_count_control = 0;
1474 } else {
1475 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1476 }
1477 }
1478
1479 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1480 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1481 db_count_control);
1482
1483 /* DB_RENDER_OVERRIDE2 */
1484 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1485 SI_TRACKED_DB_RENDER_OVERRIDE2,
1486 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1487 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1488 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1489
1490 db_shader_control = sctx->ps_db_shader_control;
1491
1492 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1493 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1494 db_shader_control &= C_02880C_Z_ORDER;
1495 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1496 }
1497
1498 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1499 if (!rs->multisample_enable)
1500 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1501
1502 if (sctx->screen->info.has_rbplus &&
1503 !sctx->screen->info.rbplus_allowed)
1504 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1505
1506 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1507 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1508
1509 if (initial_cdw != sctx->gfx_cs->current.cdw)
1510 sctx->context_roll = true;
1511 }
1512
1513 /*
1514 * format translation
1515 */
1516 static uint32_t si_translate_colorformat(enum pipe_format format)
1517 {
1518 const struct util_format_description *desc = util_format_description(format);
1519 if (!desc)
1520 return V_028C70_COLOR_INVALID;
1521
1522 #define HAS_SIZE(x,y,z,w) \
1523 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1524 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1525
1526 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1527 return V_028C70_COLOR_10_11_11;
1528
1529 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1530 return V_028C70_COLOR_INVALID;
1531
1532 /* hw cannot support mixed formats (except depth/stencil, since
1533 * stencil is not written to). */
1534 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1535 return V_028C70_COLOR_INVALID;
1536
1537 switch (desc->nr_channels) {
1538 case 1:
1539 switch (desc->channel[0].size) {
1540 case 8:
1541 return V_028C70_COLOR_8;
1542 case 16:
1543 return V_028C70_COLOR_16;
1544 case 32:
1545 return V_028C70_COLOR_32;
1546 }
1547 break;
1548 case 2:
1549 if (desc->channel[0].size == desc->channel[1].size) {
1550 switch (desc->channel[0].size) {
1551 case 8:
1552 return V_028C70_COLOR_8_8;
1553 case 16:
1554 return V_028C70_COLOR_16_16;
1555 case 32:
1556 return V_028C70_COLOR_32_32;
1557 }
1558 } else if (HAS_SIZE(8,24,0,0)) {
1559 return V_028C70_COLOR_24_8;
1560 } else if (HAS_SIZE(24,8,0,0)) {
1561 return V_028C70_COLOR_8_24;
1562 }
1563 break;
1564 case 3:
1565 if (HAS_SIZE(5,6,5,0)) {
1566 return V_028C70_COLOR_5_6_5;
1567 } else if (HAS_SIZE(32,8,24,0)) {
1568 return V_028C70_COLOR_X24_8_32_FLOAT;
1569 }
1570 break;
1571 case 4:
1572 if (desc->channel[0].size == desc->channel[1].size &&
1573 desc->channel[0].size == desc->channel[2].size &&
1574 desc->channel[0].size == desc->channel[3].size) {
1575 switch (desc->channel[0].size) {
1576 case 4:
1577 return V_028C70_COLOR_4_4_4_4;
1578 case 8:
1579 return V_028C70_COLOR_8_8_8_8;
1580 case 16:
1581 return V_028C70_COLOR_16_16_16_16;
1582 case 32:
1583 return V_028C70_COLOR_32_32_32_32;
1584 }
1585 } else if (HAS_SIZE(5,5,5,1)) {
1586 return V_028C70_COLOR_1_5_5_5;
1587 } else if (HAS_SIZE(1,5,5,5)) {
1588 return V_028C70_COLOR_5_5_5_1;
1589 } else if (HAS_SIZE(10,10,10,2)) {
1590 return V_028C70_COLOR_2_10_10_10;
1591 }
1592 break;
1593 }
1594 return V_028C70_COLOR_INVALID;
1595 }
1596
1597 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1598 {
1599 if (SI_BIG_ENDIAN) {
1600 switch(colorformat) {
1601 /* 8-bit buffers. */
1602 case V_028C70_COLOR_8:
1603 return V_028C70_ENDIAN_NONE;
1604
1605 /* 16-bit buffers. */
1606 case V_028C70_COLOR_5_6_5:
1607 case V_028C70_COLOR_1_5_5_5:
1608 case V_028C70_COLOR_4_4_4_4:
1609 case V_028C70_COLOR_16:
1610 case V_028C70_COLOR_8_8:
1611 return V_028C70_ENDIAN_8IN16;
1612
1613 /* 32-bit buffers. */
1614 case V_028C70_COLOR_8_8_8_8:
1615 case V_028C70_COLOR_2_10_10_10:
1616 case V_028C70_COLOR_8_24:
1617 case V_028C70_COLOR_24_8:
1618 case V_028C70_COLOR_16_16:
1619 return V_028C70_ENDIAN_8IN32;
1620
1621 /* 64-bit buffers. */
1622 case V_028C70_COLOR_16_16_16_16:
1623 return V_028C70_ENDIAN_8IN16;
1624
1625 case V_028C70_COLOR_32_32:
1626 return V_028C70_ENDIAN_8IN32;
1627
1628 /* 128-bit buffers. */
1629 case V_028C70_COLOR_32_32_32_32:
1630 return V_028C70_ENDIAN_8IN32;
1631 default:
1632 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1633 }
1634 } else {
1635 return V_028C70_ENDIAN_NONE;
1636 }
1637 }
1638
1639 static uint32_t si_translate_dbformat(enum pipe_format format)
1640 {
1641 switch (format) {
1642 case PIPE_FORMAT_Z16_UNORM:
1643 return V_028040_Z_16;
1644 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1645 case PIPE_FORMAT_X8Z24_UNORM:
1646 case PIPE_FORMAT_Z24X8_UNORM:
1647 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1648 return V_028040_Z_24; /* deprecated on AMD GCN */
1649 case PIPE_FORMAT_Z32_FLOAT:
1650 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1651 return V_028040_Z_32_FLOAT;
1652 default:
1653 return V_028040_Z_INVALID;
1654 }
1655 }
1656
1657 /*
1658 * Texture translation
1659 */
1660
1661 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1662 enum pipe_format format,
1663 const struct util_format_description *desc,
1664 int first_non_void)
1665 {
1666 struct si_screen *sscreen = (struct si_screen*)screen;
1667 bool uniform = true;
1668 int i;
1669
1670 assert(sscreen->info.chip_class <= GFX9);
1671
1672 /* Colorspace (return non-RGB formats directly). */
1673 switch (desc->colorspace) {
1674 /* Depth stencil formats */
1675 case UTIL_FORMAT_COLORSPACE_ZS:
1676 switch (format) {
1677 case PIPE_FORMAT_Z16_UNORM:
1678 return V_008F14_IMG_DATA_FORMAT_16;
1679 case PIPE_FORMAT_X24S8_UINT:
1680 case PIPE_FORMAT_S8X24_UINT:
1681 /*
1682 * Implemented as an 8_8_8_8 data format to fix texture
1683 * gathers in stencil sampling. This affects at least
1684 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1685 */
1686 if (sscreen->info.chip_class <= GFX8)
1687 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1688
1689 if (format == PIPE_FORMAT_X24S8_UINT)
1690 return V_008F14_IMG_DATA_FORMAT_8_24;
1691 else
1692 return V_008F14_IMG_DATA_FORMAT_24_8;
1693 case PIPE_FORMAT_Z24X8_UNORM:
1694 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1695 return V_008F14_IMG_DATA_FORMAT_8_24;
1696 case PIPE_FORMAT_X8Z24_UNORM:
1697 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1698 return V_008F14_IMG_DATA_FORMAT_24_8;
1699 case PIPE_FORMAT_S8_UINT:
1700 return V_008F14_IMG_DATA_FORMAT_8;
1701 case PIPE_FORMAT_Z32_FLOAT:
1702 return V_008F14_IMG_DATA_FORMAT_32;
1703 case PIPE_FORMAT_X32_S8X24_UINT:
1704 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1705 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1706 default:
1707 goto out_unknown;
1708 }
1709
1710 case UTIL_FORMAT_COLORSPACE_YUV:
1711 goto out_unknown; /* TODO */
1712
1713 case UTIL_FORMAT_COLORSPACE_SRGB:
1714 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1715 goto out_unknown;
1716 break;
1717
1718 default:
1719 break;
1720 }
1721
1722 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1723 if (!sscreen->info.has_format_bc1_through_bc7)
1724 goto out_unknown;
1725
1726 switch (format) {
1727 case PIPE_FORMAT_RGTC1_SNORM:
1728 case PIPE_FORMAT_LATC1_SNORM:
1729 case PIPE_FORMAT_RGTC1_UNORM:
1730 case PIPE_FORMAT_LATC1_UNORM:
1731 return V_008F14_IMG_DATA_FORMAT_BC4;
1732 case PIPE_FORMAT_RGTC2_SNORM:
1733 case PIPE_FORMAT_LATC2_SNORM:
1734 case PIPE_FORMAT_RGTC2_UNORM:
1735 case PIPE_FORMAT_LATC2_UNORM:
1736 return V_008F14_IMG_DATA_FORMAT_BC5;
1737 default:
1738 goto out_unknown;
1739 }
1740 }
1741
1742 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1743 (sscreen->info.family == CHIP_STONEY ||
1744 sscreen->info.family == CHIP_VEGA10 ||
1745 sscreen->info.family == CHIP_RAVEN)) {
1746 switch (format) {
1747 case PIPE_FORMAT_ETC1_RGB8:
1748 case PIPE_FORMAT_ETC2_RGB8:
1749 case PIPE_FORMAT_ETC2_SRGB8:
1750 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1751 case PIPE_FORMAT_ETC2_RGB8A1:
1752 case PIPE_FORMAT_ETC2_SRGB8A1:
1753 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1754 case PIPE_FORMAT_ETC2_RGBA8:
1755 case PIPE_FORMAT_ETC2_SRGBA8:
1756 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1757 case PIPE_FORMAT_ETC2_R11_UNORM:
1758 case PIPE_FORMAT_ETC2_R11_SNORM:
1759 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1760 case PIPE_FORMAT_ETC2_RG11_UNORM:
1761 case PIPE_FORMAT_ETC2_RG11_SNORM:
1762 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1763 default:
1764 goto out_unknown;
1765 }
1766 }
1767
1768 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1769 if (!sscreen->info.has_format_bc1_through_bc7)
1770 goto out_unknown;
1771
1772 switch (format) {
1773 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1774 case PIPE_FORMAT_BPTC_SRGBA:
1775 return V_008F14_IMG_DATA_FORMAT_BC7;
1776 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1777 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1778 return V_008F14_IMG_DATA_FORMAT_BC6;
1779 default:
1780 goto out_unknown;
1781 }
1782 }
1783
1784 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1785 switch (format) {
1786 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1787 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1788 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1789 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1790 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1791 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1792 default:
1793 goto out_unknown;
1794 }
1795 }
1796
1797 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1798 if (!sscreen->info.has_format_bc1_through_bc7)
1799 goto out_unknown;
1800
1801 switch (format) {
1802 case PIPE_FORMAT_DXT1_RGB:
1803 case PIPE_FORMAT_DXT1_RGBA:
1804 case PIPE_FORMAT_DXT1_SRGB:
1805 case PIPE_FORMAT_DXT1_SRGBA:
1806 return V_008F14_IMG_DATA_FORMAT_BC1;
1807 case PIPE_FORMAT_DXT3_RGBA:
1808 case PIPE_FORMAT_DXT3_SRGBA:
1809 return V_008F14_IMG_DATA_FORMAT_BC2;
1810 case PIPE_FORMAT_DXT5_RGBA:
1811 case PIPE_FORMAT_DXT5_SRGBA:
1812 return V_008F14_IMG_DATA_FORMAT_BC3;
1813 default:
1814 goto out_unknown;
1815 }
1816 }
1817
1818 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1819 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1820 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1821 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1822 }
1823
1824 /* R8G8Bx_SNORM - TODO CxV8U8 */
1825
1826 /* hw cannot support mixed formats (except depth/stencil, since only
1827 * depth is read).*/
1828 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1829 goto out_unknown;
1830
1831 /* See whether the components are of the same size. */
1832 for (i = 1; i < desc->nr_channels; i++) {
1833 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1834 }
1835
1836 /* Non-uniform formats. */
1837 if (!uniform) {
1838 switch(desc->nr_channels) {
1839 case 3:
1840 if (desc->channel[0].size == 5 &&
1841 desc->channel[1].size == 6 &&
1842 desc->channel[2].size == 5) {
1843 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1844 }
1845 goto out_unknown;
1846 case 4:
1847 if (desc->channel[0].size == 5 &&
1848 desc->channel[1].size == 5 &&
1849 desc->channel[2].size == 5 &&
1850 desc->channel[3].size == 1) {
1851 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1852 }
1853 if (desc->channel[0].size == 1 &&
1854 desc->channel[1].size == 5 &&
1855 desc->channel[2].size == 5 &&
1856 desc->channel[3].size == 5) {
1857 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1858 }
1859 if (desc->channel[0].size == 10 &&
1860 desc->channel[1].size == 10 &&
1861 desc->channel[2].size == 10 &&
1862 desc->channel[3].size == 2) {
1863 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1864 }
1865 goto out_unknown;
1866 }
1867 goto out_unknown;
1868 }
1869
1870 if (first_non_void < 0 || first_non_void > 3)
1871 goto out_unknown;
1872
1873 /* uniform formats */
1874 switch (desc->channel[first_non_void].size) {
1875 case 4:
1876 switch (desc->nr_channels) {
1877 #if 0 /* Not supported for render targets */
1878 case 2:
1879 return V_008F14_IMG_DATA_FORMAT_4_4;
1880 #endif
1881 case 4:
1882 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1883 }
1884 break;
1885 case 8:
1886 switch (desc->nr_channels) {
1887 case 1:
1888 return V_008F14_IMG_DATA_FORMAT_8;
1889 case 2:
1890 return V_008F14_IMG_DATA_FORMAT_8_8;
1891 case 4:
1892 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1893 }
1894 break;
1895 case 16:
1896 switch (desc->nr_channels) {
1897 case 1:
1898 return V_008F14_IMG_DATA_FORMAT_16;
1899 case 2:
1900 return V_008F14_IMG_DATA_FORMAT_16_16;
1901 case 4:
1902 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1903 }
1904 break;
1905 case 32:
1906 switch (desc->nr_channels) {
1907 case 1:
1908 return V_008F14_IMG_DATA_FORMAT_32;
1909 case 2:
1910 return V_008F14_IMG_DATA_FORMAT_32_32;
1911 #if 0 /* Not supported for render targets */
1912 case 3:
1913 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1914 #endif
1915 case 4:
1916 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1917 }
1918 }
1919
1920 out_unknown:
1921 return ~0;
1922 }
1923
1924 static unsigned si_tex_wrap(unsigned wrap)
1925 {
1926 switch (wrap) {
1927 default:
1928 case PIPE_TEX_WRAP_REPEAT:
1929 return V_008F30_SQ_TEX_WRAP;
1930 case PIPE_TEX_WRAP_CLAMP:
1931 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1932 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1933 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1934 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1935 return V_008F30_SQ_TEX_CLAMP_BORDER;
1936 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1937 return V_008F30_SQ_TEX_MIRROR;
1938 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1939 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1940 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1941 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1942 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1943 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1944 }
1945 }
1946
1947 static unsigned si_tex_mipfilter(unsigned filter)
1948 {
1949 switch (filter) {
1950 case PIPE_TEX_MIPFILTER_NEAREST:
1951 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1952 case PIPE_TEX_MIPFILTER_LINEAR:
1953 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1954 default:
1955 case PIPE_TEX_MIPFILTER_NONE:
1956 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1957 }
1958 }
1959
1960 static unsigned si_tex_compare(unsigned compare)
1961 {
1962 switch (compare) {
1963 default:
1964 case PIPE_FUNC_NEVER:
1965 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1966 case PIPE_FUNC_LESS:
1967 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1968 case PIPE_FUNC_EQUAL:
1969 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1970 case PIPE_FUNC_LEQUAL:
1971 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1972 case PIPE_FUNC_GREATER:
1973 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1974 case PIPE_FUNC_NOTEQUAL:
1975 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1976 case PIPE_FUNC_GEQUAL:
1977 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1978 case PIPE_FUNC_ALWAYS:
1979 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1980 }
1981 }
1982
1983 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1984 unsigned view_target, unsigned nr_samples)
1985 {
1986 unsigned res_target = tex->buffer.b.b.target;
1987
1988 if (view_target == PIPE_TEXTURE_CUBE ||
1989 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1990 res_target = view_target;
1991 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1992 else if (res_target == PIPE_TEXTURE_CUBE ||
1993 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1994 res_target = PIPE_TEXTURE_2D_ARRAY;
1995
1996 /* GFX9 allocates 1D textures as 2D. */
1997 if ((res_target == PIPE_TEXTURE_1D ||
1998 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1999 sscreen->info.chip_class == GFX9 &&
2000 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2001 if (res_target == PIPE_TEXTURE_1D)
2002 res_target = PIPE_TEXTURE_2D;
2003 else
2004 res_target = PIPE_TEXTURE_2D_ARRAY;
2005 }
2006
2007 switch (res_target) {
2008 default:
2009 case PIPE_TEXTURE_1D:
2010 return V_008F1C_SQ_RSRC_IMG_1D;
2011 case PIPE_TEXTURE_1D_ARRAY:
2012 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2013 case PIPE_TEXTURE_2D:
2014 case PIPE_TEXTURE_RECT:
2015 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2016 V_008F1C_SQ_RSRC_IMG_2D;
2017 case PIPE_TEXTURE_2D_ARRAY:
2018 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2019 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2020 case PIPE_TEXTURE_3D:
2021 return V_008F1C_SQ_RSRC_IMG_3D;
2022 case PIPE_TEXTURE_CUBE:
2023 case PIPE_TEXTURE_CUBE_ARRAY:
2024 return V_008F1C_SQ_RSRC_IMG_CUBE;
2025 }
2026 }
2027
2028 /*
2029 * Format support testing
2030 */
2031
2032 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2033 {
2034 struct si_screen *sscreen = (struct si_screen *)screen;
2035
2036 if (sscreen->info.chip_class >= GFX10) {
2037 const struct gfx10_format *fmt = &gfx10_format_table[format];
2038 if (!fmt->img_format || fmt->buffers_only)
2039 return false;
2040 return true;
2041 }
2042
2043 const struct util_format_description *desc = util_format_description(format);
2044 if (!desc)
2045 return false;
2046
2047 return si_translate_texformat(screen, format, desc,
2048 util_format_get_first_non_void_channel(format)) != ~0U;
2049 }
2050
2051 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2052 const struct util_format_description *desc,
2053 int first_non_void)
2054 {
2055 int i;
2056
2057 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2058
2059 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2060 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2061
2062 assert(first_non_void >= 0);
2063
2064 if (desc->nr_channels == 4 &&
2065 desc->channel[0].size == 10 &&
2066 desc->channel[1].size == 10 &&
2067 desc->channel[2].size == 10 &&
2068 desc->channel[3].size == 2)
2069 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2070
2071 /* See whether the components are of the same size. */
2072 for (i = 0; i < desc->nr_channels; i++) {
2073 if (desc->channel[first_non_void].size != desc->channel[i].size)
2074 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2075 }
2076
2077 switch (desc->channel[first_non_void].size) {
2078 case 8:
2079 switch (desc->nr_channels) {
2080 case 1:
2081 case 3: /* 3 loads */
2082 return V_008F0C_BUF_DATA_FORMAT_8;
2083 case 2:
2084 return V_008F0C_BUF_DATA_FORMAT_8_8;
2085 case 4:
2086 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2087 }
2088 break;
2089 case 16:
2090 switch (desc->nr_channels) {
2091 case 1:
2092 case 3: /* 3 loads */
2093 return V_008F0C_BUF_DATA_FORMAT_16;
2094 case 2:
2095 return V_008F0C_BUF_DATA_FORMAT_16_16;
2096 case 4:
2097 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2098 }
2099 break;
2100 case 32:
2101 switch (desc->nr_channels) {
2102 case 1:
2103 return V_008F0C_BUF_DATA_FORMAT_32;
2104 case 2:
2105 return V_008F0C_BUF_DATA_FORMAT_32_32;
2106 case 3:
2107 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2108 case 4:
2109 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2110 }
2111 break;
2112 case 64:
2113 /* Legacy double formats. */
2114 switch (desc->nr_channels) {
2115 case 1: /* 1 load */
2116 return V_008F0C_BUF_DATA_FORMAT_32_32;
2117 case 2: /* 1 load */
2118 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2119 case 3: /* 3 loads */
2120 return V_008F0C_BUF_DATA_FORMAT_32_32;
2121 case 4: /* 2 loads */
2122 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2123 }
2124 break;
2125 }
2126
2127 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2128 }
2129
2130 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2131 const struct util_format_description *desc,
2132 int first_non_void)
2133 {
2134 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2135
2136 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2137 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2138
2139 assert(first_non_void >= 0);
2140
2141 switch (desc->channel[first_non_void].type) {
2142 case UTIL_FORMAT_TYPE_SIGNED:
2143 case UTIL_FORMAT_TYPE_FIXED:
2144 if (desc->channel[first_non_void].size >= 32 ||
2145 desc->channel[first_non_void].pure_integer)
2146 return V_008F0C_BUF_NUM_FORMAT_SINT;
2147 else if (desc->channel[first_non_void].normalized)
2148 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2149 else
2150 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2151 break;
2152 case UTIL_FORMAT_TYPE_UNSIGNED:
2153 if (desc->channel[first_non_void].size >= 32 ||
2154 desc->channel[first_non_void].pure_integer)
2155 return V_008F0C_BUF_NUM_FORMAT_UINT;
2156 else if (desc->channel[first_non_void].normalized)
2157 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2158 else
2159 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2160 break;
2161 case UTIL_FORMAT_TYPE_FLOAT:
2162 default:
2163 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2164 }
2165 }
2166
2167 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2168 enum pipe_format format,
2169 unsigned usage)
2170 {
2171 struct si_screen *sscreen = (struct si_screen *)screen;
2172 const struct util_format_description *desc;
2173 int first_non_void;
2174 unsigned data_format;
2175
2176 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2177 PIPE_BIND_SAMPLER_VIEW |
2178 PIPE_BIND_VERTEX_BUFFER)) == 0);
2179
2180 desc = util_format_description(format);
2181 if (!desc)
2182 return 0;
2183
2184 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2185 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2186 * for read-only access (with caveats surrounding bounds checks), but
2187 * obviously fails for write access which we have to implement for
2188 * shader images. Luckily, OpenGL doesn't expect this to be supported
2189 * anyway, and so the only impact is on PBO uploads / downloads, which
2190 * shouldn't be expected to be fast for GL_RGB anyway.
2191 */
2192 if (desc->block.bits == 3 * 8 ||
2193 desc->block.bits == 3 * 16) {
2194 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2195 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2196 if (!usage)
2197 return 0;
2198 }
2199 }
2200
2201 if (sscreen->info.chip_class >= GFX10) {
2202 const struct gfx10_format *fmt = &gfx10_format_table[format];
2203 if (!fmt->img_format || fmt->img_format >= 128)
2204 return 0;
2205 return usage;
2206 }
2207
2208 first_non_void = util_format_get_first_non_void_channel(format);
2209 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2210 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2211 return 0;
2212
2213 return usage;
2214 }
2215
2216 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2217 {
2218 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2219 si_translate_colorswap(format, false) != ~0U;
2220 }
2221
2222 static bool si_is_zs_format_supported(enum pipe_format format)
2223 {
2224 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2225 }
2226
2227 static bool si_is_format_supported(struct pipe_screen *screen,
2228 enum pipe_format format,
2229 enum pipe_texture_target target,
2230 unsigned sample_count,
2231 unsigned storage_sample_count,
2232 unsigned usage)
2233 {
2234 struct si_screen *sscreen = (struct si_screen *)screen;
2235 unsigned retval = 0;
2236
2237 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2238 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2239 return false;
2240 }
2241
2242 if (util_format_get_num_planes(format) >= 2) {
2243 return util_format_planar_is_supported(screen, format, target,
2244 sample_count,
2245 storage_sample_count,
2246 usage);
2247 }
2248
2249 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2250 return false;
2251
2252 if (sample_count > 1) {
2253 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2254 return false;
2255
2256 /* Only power-of-two sample counts are supported. */
2257 if (!util_is_power_of_two_or_zero(sample_count) ||
2258 !util_is_power_of_two_or_zero(storage_sample_count))
2259 return false;
2260
2261 /* MSAA support without framebuffer attachments. */
2262 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2263 return true;
2264
2265 if (!sscreen->info.has_eqaa_surface_allocator ||
2266 util_format_is_depth_or_stencil(format)) {
2267 /* Color without EQAA or depth/stencil. */
2268 if (sample_count > 8 ||
2269 sample_count != storage_sample_count)
2270 return false;
2271 } else {
2272 /* Color with EQAA. */
2273 if (sample_count > 16 ||
2274 storage_sample_count > 8)
2275 return false;
2276 }
2277 }
2278
2279 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2280 PIPE_BIND_SHADER_IMAGE)) {
2281 if (target == PIPE_BUFFER) {
2282 retval |= si_is_vertex_format_supported(
2283 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2284 PIPE_BIND_SHADER_IMAGE));
2285 } else {
2286 if (si_is_sampler_format_supported(screen, format))
2287 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2288 PIPE_BIND_SHADER_IMAGE);
2289 }
2290 }
2291
2292 if ((usage & (PIPE_BIND_RENDER_TARGET |
2293 PIPE_BIND_DISPLAY_TARGET |
2294 PIPE_BIND_SCANOUT |
2295 PIPE_BIND_SHARED |
2296 PIPE_BIND_BLENDABLE)) &&
2297 si_is_colorbuffer_format_supported(format)) {
2298 retval |= usage &
2299 (PIPE_BIND_RENDER_TARGET |
2300 PIPE_BIND_DISPLAY_TARGET |
2301 PIPE_BIND_SCANOUT |
2302 PIPE_BIND_SHARED);
2303 if (!util_format_is_pure_integer(format) &&
2304 !util_format_is_depth_or_stencil(format))
2305 retval |= usage & PIPE_BIND_BLENDABLE;
2306 }
2307
2308 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2309 si_is_zs_format_supported(format)) {
2310 retval |= PIPE_BIND_DEPTH_STENCIL;
2311 }
2312
2313 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2314 retval |= si_is_vertex_format_supported(screen, format,
2315 PIPE_BIND_VERTEX_BUFFER);
2316 }
2317
2318 if ((usage & PIPE_BIND_LINEAR) &&
2319 !util_format_is_compressed(format) &&
2320 !(usage & PIPE_BIND_DEPTH_STENCIL))
2321 retval |= PIPE_BIND_LINEAR;
2322
2323 return retval == usage;
2324 }
2325
2326 /*
2327 * framebuffer handling
2328 */
2329
2330 static void si_choose_spi_color_formats(struct si_surface *surf,
2331 unsigned format, unsigned swap,
2332 unsigned ntype, bool is_depth)
2333 {
2334 /* Alpha is needed for alpha-to-coverage.
2335 * Blending may be with or without alpha.
2336 */
2337 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2338 unsigned alpha = 0; /* exports alpha, but may not support blending */
2339 unsigned blend = 0; /* supports blending, but may not export alpha */
2340 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2341
2342 /* Choose the SPI color formats. These are required values for RB+.
2343 * Other chips have multiple choices, though they are not necessarily better.
2344 */
2345 switch (format) {
2346 case V_028C70_COLOR_5_6_5:
2347 case V_028C70_COLOR_1_5_5_5:
2348 case V_028C70_COLOR_5_5_5_1:
2349 case V_028C70_COLOR_4_4_4_4:
2350 case V_028C70_COLOR_10_11_11:
2351 case V_028C70_COLOR_11_11_10:
2352 case V_028C70_COLOR_8:
2353 case V_028C70_COLOR_8_8:
2354 case V_028C70_COLOR_8_8_8_8:
2355 case V_028C70_COLOR_10_10_10_2:
2356 case V_028C70_COLOR_2_10_10_10:
2357 if (ntype == V_028C70_NUMBER_UINT)
2358 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2359 else if (ntype == V_028C70_NUMBER_SINT)
2360 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2361 else
2362 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2363 break;
2364
2365 case V_028C70_COLOR_16:
2366 case V_028C70_COLOR_16_16:
2367 case V_028C70_COLOR_16_16_16_16:
2368 if (ntype == V_028C70_NUMBER_UNORM ||
2369 ntype == V_028C70_NUMBER_SNORM) {
2370 /* UNORM16 and SNORM16 don't support blending */
2371 if (ntype == V_028C70_NUMBER_UNORM)
2372 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2373 else
2374 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2375
2376 /* Use 32 bits per channel for blending. */
2377 if (format == V_028C70_COLOR_16) {
2378 if (swap == V_028C70_SWAP_STD) { /* R */
2379 blend = V_028714_SPI_SHADER_32_R;
2380 blend_alpha = V_028714_SPI_SHADER_32_AR;
2381 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2382 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2383 else
2384 assert(0);
2385 } else if (format == V_028C70_COLOR_16_16) {
2386 if (swap == V_028C70_SWAP_STD) { /* RG */
2387 blend = V_028714_SPI_SHADER_32_GR;
2388 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2389 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2390 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2391 else
2392 assert(0);
2393 } else /* 16_16_16_16 */
2394 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2395 } else if (ntype == V_028C70_NUMBER_UINT)
2396 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2397 else if (ntype == V_028C70_NUMBER_SINT)
2398 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2399 else if (ntype == V_028C70_NUMBER_FLOAT)
2400 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2401 else
2402 assert(0);
2403 break;
2404
2405 case V_028C70_COLOR_32:
2406 if (swap == V_028C70_SWAP_STD) { /* R */
2407 blend = normal = V_028714_SPI_SHADER_32_R;
2408 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2409 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2410 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2411 else
2412 assert(0);
2413 break;
2414
2415 case V_028C70_COLOR_32_32:
2416 if (swap == V_028C70_SWAP_STD) { /* RG */
2417 blend = normal = V_028714_SPI_SHADER_32_GR;
2418 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2419 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2420 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2421 else
2422 assert(0);
2423 break;
2424
2425 case V_028C70_COLOR_32_32_32_32:
2426 case V_028C70_COLOR_8_24:
2427 case V_028C70_COLOR_24_8:
2428 case V_028C70_COLOR_X24_8_32_FLOAT:
2429 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2430 break;
2431
2432 default:
2433 assert(0);
2434 return;
2435 }
2436
2437 /* The DB->CB copy needs 32_ABGR. */
2438 if (is_depth)
2439 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2440
2441 surf->spi_shader_col_format = normal;
2442 surf->spi_shader_col_format_alpha = alpha;
2443 surf->spi_shader_col_format_blend = blend;
2444 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2445 }
2446
2447 static void si_initialize_color_surface(struct si_context *sctx,
2448 struct si_surface *surf)
2449 {
2450 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2451 unsigned color_info, color_attrib;
2452 unsigned format, swap, ntype, endian;
2453 const struct util_format_description *desc;
2454 int firstchan;
2455 unsigned blend_clamp = 0, blend_bypass = 0;
2456
2457 desc = util_format_description(surf->base.format);
2458 for (firstchan = 0; firstchan < 4; firstchan++) {
2459 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2460 break;
2461 }
2462 }
2463 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2464 ntype = V_028C70_NUMBER_FLOAT;
2465 } else {
2466 ntype = V_028C70_NUMBER_UNORM;
2467 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2468 ntype = V_028C70_NUMBER_SRGB;
2469 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2470 if (desc->channel[firstchan].pure_integer) {
2471 ntype = V_028C70_NUMBER_SINT;
2472 } else {
2473 assert(desc->channel[firstchan].normalized);
2474 ntype = V_028C70_NUMBER_SNORM;
2475 }
2476 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2477 if (desc->channel[firstchan].pure_integer) {
2478 ntype = V_028C70_NUMBER_UINT;
2479 } else {
2480 assert(desc->channel[firstchan].normalized);
2481 ntype = V_028C70_NUMBER_UNORM;
2482 }
2483 }
2484 }
2485
2486 format = si_translate_colorformat(surf->base.format);
2487 if (format == V_028C70_COLOR_INVALID) {
2488 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2489 }
2490 assert(format != V_028C70_COLOR_INVALID);
2491 swap = si_translate_colorswap(surf->base.format, false);
2492 endian = si_colorformat_endian_swap(format);
2493
2494 /* blend clamp should be set for all NORM/SRGB types */
2495 if (ntype == V_028C70_NUMBER_UNORM ||
2496 ntype == V_028C70_NUMBER_SNORM ||
2497 ntype == V_028C70_NUMBER_SRGB)
2498 blend_clamp = 1;
2499
2500 /* set blend bypass according to docs if SINT/UINT or
2501 8/24 COLOR variants */
2502 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2503 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2504 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2505 blend_clamp = 0;
2506 blend_bypass = 1;
2507 }
2508
2509 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2510 if (format == V_028C70_COLOR_8 ||
2511 format == V_028C70_COLOR_8_8 ||
2512 format == V_028C70_COLOR_8_8_8_8)
2513 surf->color_is_int8 = true;
2514 else if (format == V_028C70_COLOR_10_10_10_2 ||
2515 format == V_028C70_COLOR_2_10_10_10)
2516 surf->color_is_int10 = true;
2517 }
2518
2519 color_info = S_028C70_FORMAT(format) |
2520 S_028C70_COMP_SWAP(swap) |
2521 S_028C70_BLEND_CLAMP(blend_clamp) |
2522 S_028C70_BLEND_BYPASS(blend_bypass) |
2523 S_028C70_SIMPLE_FLOAT(1) |
2524 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2525 ntype != V_028C70_NUMBER_SNORM &&
2526 ntype != V_028C70_NUMBER_SRGB &&
2527 format != V_028C70_COLOR_8_24 &&
2528 format != V_028C70_COLOR_24_8) |
2529 S_028C70_NUMBER_TYPE(ntype) |
2530 S_028C70_ENDIAN(endian);
2531
2532 /* Intensity is implemented as Red, so treat it that way. */
2533 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2534 util_format_is_intensity(surf->base.format));
2535
2536 if (tex->buffer.b.b.nr_samples > 1) {
2537 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2538 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2539
2540 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2541 S_028C74_NUM_FRAGMENTS(log_fragments);
2542
2543 if (tex->surface.fmask_offset) {
2544 color_info |= S_028C70_COMPRESSION(1);
2545 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2546
2547 if (sctx->chip_class == GFX6) {
2548 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2549 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2550 }
2551 }
2552 }
2553
2554 if (sctx->chip_class >= GFX10) {
2555 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2556
2557 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2558 64 for APU because all of our APUs to date use DIMMs which have
2559 a request granularity size of 64B while all other chips have a
2560 32B request size */
2561 if (!sctx->screen->info.has_dedicated_vram)
2562 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2563
2564 surf->cb_dcc_control =
2565 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2566 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2567 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2568 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2569 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2570 } else if (sctx->chip_class >= GFX8) {
2571 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2572 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2573
2574 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2575 64 for APU because all of our APUs to date use DIMMs which have
2576 a request granularity size of 64B while all other chips have a
2577 32B request size */
2578 if (!sctx->screen->info.has_dedicated_vram)
2579 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2580
2581 if (tex->buffer.b.b.nr_storage_samples > 1) {
2582 if (tex->surface.bpe == 1)
2583 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2584 else if (tex->surface.bpe == 2)
2585 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2586 }
2587
2588 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2589 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2590 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2591 }
2592
2593 /* This must be set for fast clear to work without FMASK. */
2594 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2595 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2596 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2597 }
2598
2599 /* GFX10 field has the same base shift as the GFX6 field */
2600 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2601 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2602 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2603
2604 if (sctx->chip_class >= GFX10) {
2605 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2606
2607 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2608 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2609 S_028EE0_RESOURCE_LEVEL(1);
2610 } else if (sctx->chip_class == GFX9) {
2611 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2612 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2613 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2614 }
2615
2616 if (sctx->chip_class >= GFX9) {
2617 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2618 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2619 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2620 }
2621
2622 surf->cb_color_view = color_view;
2623 surf->cb_color_info = color_info;
2624 surf->cb_color_attrib = color_attrib;
2625
2626 /* Determine pixel shader export format */
2627 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2628
2629 surf->color_initialized = true;
2630 }
2631
2632 static void si_init_depth_surface(struct si_context *sctx,
2633 struct si_surface *surf)
2634 {
2635 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2636 unsigned level = surf->base.u.tex.level;
2637 unsigned format, stencil_format;
2638 uint32_t z_info, s_info;
2639
2640 format = si_translate_dbformat(tex->db_render_format);
2641 stencil_format = tex->surface.has_stencil ?
2642 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2643
2644 assert(format != V_028040_Z_INVALID);
2645 if (format == V_028040_Z_INVALID)
2646 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2647
2648 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2649 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2650 surf->db_htile_data_base = 0;
2651 surf->db_htile_surface = 0;
2652
2653 if (sctx->chip_class >= GFX10) {
2654 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2655 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2656 }
2657
2658 if (sctx->chip_class >= GFX9) {
2659 assert(tex->surface.u.gfx9.surf_offset == 0);
2660 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2661 surf->db_stencil_base = (tex->buffer.gpu_address +
2662 tex->surface.u.gfx9.stencil_offset) >> 8;
2663 z_info = S_028038_FORMAT(format) |
2664 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2665 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2666 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2667 s_info = S_02803C_FORMAT(stencil_format) |
2668 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2669
2670 if (sctx->chip_class == GFX9) {
2671 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2672 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2673 }
2674 surf->db_depth_view |= S_028008_MIPID(level);
2675 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2676 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2677
2678 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2679 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2680 S_028038_ALLOW_EXPCLEAR(1);
2681
2682 if (tex->tc_compatible_htile) {
2683 unsigned max_zplanes = 4;
2684
2685 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2686 tex->buffer.b.b.nr_samples > 1)
2687 max_zplanes = 2;
2688
2689 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2690
2691 if (sctx->chip_class >= GFX10) {
2692 z_info |= S_028040_ITERATE_FLUSH(1);
2693 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2694 } else {
2695 z_info |= S_028038_ITERATE_FLUSH(1);
2696 s_info |= S_02803C_ITERATE_FLUSH(1);
2697 }
2698 }
2699
2700 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2701 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2702 * See that for explanation.
2703 */
2704 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2705 } else {
2706 /* Use all HTILE for depth if there's no stencil. */
2707 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2708 }
2709
2710 surf->db_htile_data_base = (tex->buffer.gpu_address +
2711 tex->surface.htile_offset) >> 8;
2712 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2713 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2714 if (sctx->chip_class == GFX9) {
2715 surf->db_htile_surface |=
2716 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2717 }
2718 }
2719 } else {
2720 /* GFX6-GFX8 */
2721 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2722
2723 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2724
2725 surf->db_depth_base = (tex->buffer.gpu_address +
2726 tex->surface.u.legacy.level[level].offset) >> 8;
2727 surf->db_stencil_base = (tex->buffer.gpu_address +
2728 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2729
2730 z_info = S_028040_FORMAT(format) |
2731 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2732 s_info = S_028044_FORMAT(stencil_format);
2733 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2734
2735 if (sctx->chip_class >= GFX7) {
2736 struct radeon_info *info = &sctx->screen->info;
2737 unsigned index = tex->surface.u.legacy.tiling_index[level];
2738 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2739 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2740 unsigned tile_mode = info->si_tile_mode_array[index];
2741 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2742 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2743
2744 surf->db_depth_info |=
2745 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2746 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2747 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2748 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2749 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2750 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2751 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2752 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2753 } else {
2754 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2755 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2756 tile_mode_index = si_tile_mode_index(tex, level, true);
2757 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2758 }
2759
2760 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2761 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2762 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2763 levelinfo->nblk_y) / 64 - 1);
2764
2765 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2766 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2767 S_028040_ALLOW_EXPCLEAR(1);
2768
2769 if (tex->surface.has_stencil) {
2770 /* Workaround: For a not yet understood reason, the
2771 * combination of MSAA, fast stencil clear and stencil
2772 * decompress messes with subsequent stencil buffer
2773 * uses. Problem was reproduced on Verde, Bonaire,
2774 * Tonga, and Carrizo.
2775 *
2776 * Disabling EXPCLEAR works around the problem.
2777 *
2778 * Check piglit's arb_texture_multisample-stencil-clear
2779 * test if you want to try changing this.
2780 */
2781 if (tex->buffer.b.b.nr_samples <= 1)
2782 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2783 } else if (!tex->tc_compatible_htile) {
2784 /* Use all of the htile_buffer for depth if there's no stencil.
2785 * This must not be set when TC-compatible HTILE is enabled
2786 * due to a hw bug.
2787 */
2788 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2789 }
2790
2791 surf->db_htile_data_base = (tex->buffer.gpu_address +
2792 tex->surface.htile_offset) >> 8;
2793 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2794
2795 if (tex->tc_compatible_htile) {
2796 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2797
2798 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2799 if (tex->buffer.b.b.nr_samples <= 1)
2800 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2801 else if (tex->buffer.b.b.nr_samples <= 4)
2802 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2803 else
2804 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2805 }
2806 }
2807 }
2808
2809 surf->db_z_info = z_info;
2810 surf->db_stencil_info = s_info;
2811
2812 surf->depth_initialized = true;
2813 }
2814
2815 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2816 {
2817 if (sctx->decompression_enabled)
2818 return;
2819
2820 if (sctx->framebuffer.state.zsbuf) {
2821 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2822 struct si_texture *tex = (struct si_texture *)surf->texture;
2823
2824 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2825
2826 if (tex->surface.has_stencil)
2827 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2828 }
2829
2830 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2831 while (compressed_cb_mask) {
2832 unsigned i = u_bit_scan(&compressed_cb_mask);
2833 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2834 struct si_texture *tex = (struct si_texture*)surf->texture;
2835
2836 if (tex->surface.fmask_offset) {
2837 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2838 tex->fmask_is_not_identity = true;
2839 }
2840 if (tex->dcc_gather_statistics)
2841 tex->separate_dcc_dirty = true;
2842 }
2843 }
2844
2845 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2846 {
2847 for (int i = 0; i < state->nr_cbufs; ++i) {
2848 struct si_surface *surf = NULL;
2849 struct si_texture *tex;
2850
2851 if (!state->cbufs[i])
2852 continue;
2853 surf = (struct si_surface*)state->cbufs[i];
2854 tex = (struct si_texture*)surf->base.texture;
2855
2856 p_atomic_dec(&tex->framebuffers_bound);
2857 }
2858 }
2859
2860 static void si_set_framebuffer_state(struct pipe_context *ctx,
2861 const struct pipe_framebuffer_state *state)
2862 {
2863 struct si_context *sctx = (struct si_context *)ctx;
2864 struct si_surface *surf = NULL;
2865 struct si_texture *tex;
2866 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2867 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2868 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2869 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2870 bool old_has_stencil =
2871 old_has_zsbuf &&
2872 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2873 bool unbound = false;
2874 int i;
2875
2876 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2877 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2878 * We could implement the full workaround here, but it's a useless case.
2879 */
2880 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2881 unreachable("the framebuffer shouldn't have zero area");
2882 return;
2883 }
2884
2885 si_update_fb_dirtiness_after_rendering(sctx);
2886
2887 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2888 if (!sctx->framebuffer.state.cbufs[i])
2889 continue;
2890
2891 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2892 if (tex->dcc_gather_statistics)
2893 vi_separate_dcc_stop_query(sctx, tex);
2894 }
2895
2896 /* Disable DCC if the formats are incompatible. */
2897 for (i = 0; i < state->nr_cbufs; i++) {
2898 if (!state->cbufs[i])
2899 continue;
2900
2901 surf = (struct si_surface*)state->cbufs[i];
2902 tex = (struct si_texture*)surf->base.texture;
2903
2904 if (!surf->dcc_incompatible)
2905 continue;
2906
2907 /* Since the DCC decompression calls back into set_framebuffer-
2908 * _state, we need to unbind the framebuffer, so that
2909 * vi_separate_dcc_stop_query isn't called twice with the same
2910 * color buffer.
2911 */
2912 if (!unbound) {
2913 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2914 unbound = true;
2915 }
2916
2917 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2918 if (!si_texture_disable_dcc(sctx, tex))
2919 si_decompress_dcc(sctx, tex);
2920
2921 surf->dcc_incompatible = false;
2922 }
2923
2924 /* Only flush TC when changing the framebuffer state, because
2925 * the only client not using TC that can change textures is
2926 * the framebuffer.
2927 *
2928 * Wait for compute shaders because of possible transitions:
2929 * - FB write -> shader read
2930 * - shader write -> FB read
2931 *
2932 * DB caches are flushed on demand (using si_decompress_textures).
2933 *
2934 * When MSAA is enabled, CB and TC caches are flushed on demand
2935 * (after FMASK decompression). Shader write -> FB read transitions
2936 * cannot happen for MSAA textures, because MSAA shader images are
2937 * not supported.
2938 *
2939 * Only flush and wait for CB if there is actually a bound color buffer.
2940 */
2941 if (sctx->framebuffer.uncompressed_cb_mask) {
2942 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2943 sctx->framebuffer.CB_has_shader_readable_metadata,
2944 sctx->framebuffer.all_DCC_pipe_aligned);
2945 }
2946
2947 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2948
2949 /* u_blitter doesn't invoke depth decompression when it does multiple
2950 * blits in a row, but the only case when it matters for DB is when
2951 * doing generate_mipmap. So here we flush DB manually between
2952 * individual generate_mipmap blits.
2953 * Note that lower mipmap levels aren't compressed.
2954 */
2955 if (sctx->generate_mipmap_for_depth) {
2956 si_make_DB_shader_coherent(sctx, 1, false,
2957 sctx->framebuffer.DB_has_shader_readable_metadata);
2958 } else if (sctx->chip_class == GFX9) {
2959 /* It appears that DB metadata "leaks" in a sequence of:
2960 * - depth clear
2961 * - DCC decompress for shader image writes (with DB disabled)
2962 * - render with DEPTH_BEFORE_SHADER=1
2963 * Flushing DB metadata works around the problem.
2964 */
2965 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2966 }
2967
2968 /* Take the maximum of the old and new count. If the new count is lower,
2969 * dirtying is needed to disable the unbound colorbuffers.
2970 */
2971 sctx->framebuffer.dirty_cbufs |=
2972 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2973 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2974
2975 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2976 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2977
2978 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2979 sctx->framebuffer.spi_shader_col_format = 0;
2980 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2981 sctx->framebuffer.spi_shader_col_format_blend = 0;
2982 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2983 sctx->framebuffer.color_is_int8 = 0;
2984 sctx->framebuffer.color_is_int10 = 0;
2985
2986 sctx->framebuffer.compressed_cb_mask = 0;
2987 sctx->framebuffer.uncompressed_cb_mask = 0;
2988 sctx->framebuffer.displayable_dcc_cb_mask = 0;
2989 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2990 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2991 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2992 sctx->framebuffer.any_dst_linear = false;
2993 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2994 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2995 sctx->framebuffer.all_DCC_pipe_aligned = true;
2996 sctx->framebuffer.min_bytes_per_pixel = 0;
2997
2998 for (i = 0; i < state->nr_cbufs; i++) {
2999 if (!state->cbufs[i])
3000 continue;
3001
3002 surf = (struct si_surface*)state->cbufs[i];
3003 tex = (struct si_texture*)surf->base.texture;
3004
3005 if (!surf->color_initialized) {
3006 si_initialize_color_surface(sctx, surf);
3007 }
3008
3009 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
3010 sctx->framebuffer.spi_shader_col_format |=
3011 surf->spi_shader_col_format << (i * 4);
3012 sctx->framebuffer.spi_shader_col_format_alpha |=
3013 surf->spi_shader_col_format_alpha << (i * 4);
3014 sctx->framebuffer.spi_shader_col_format_blend |=
3015 surf->spi_shader_col_format_blend << (i * 4);
3016 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
3017 surf->spi_shader_col_format_blend_alpha << (i * 4);
3018
3019 if (surf->color_is_int8)
3020 sctx->framebuffer.color_is_int8 |= 1 << i;
3021 if (surf->color_is_int10)
3022 sctx->framebuffer.color_is_int10 |= 1 << i;
3023
3024 if (tex->surface.fmask_offset)
3025 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3026 else
3027 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3028
3029 if (tex->surface.dcc_offset)
3030 sctx->framebuffer.displayable_dcc_cb_mask |= 1 << i;
3031
3032 /* Don't update nr_color_samples for non-AA buffers.
3033 * (e.g. destination of MSAA resolve)
3034 */
3035 if (tex->buffer.b.b.nr_samples >= 2 &&
3036 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3037 sctx->framebuffer.nr_color_samples =
3038 MIN2(sctx->framebuffer.nr_color_samples,
3039 tex->buffer.b.b.nr_storage_samples);
3040 sctx->framebuffer.nr_color_samples =
3041 MAX2(1, sctx->framebuffer.nr_color_samples);
3042 }
3043
3044 if (tex->surface.is_linear)
3045 sctx->framebuffer.any_dst_linear = true;
3046
3047 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3048 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3049
3050 if (sctx->chip_class >= GFX9 &&
3051 !tex->surface.u.gfx9.dcc.pipe_aligned)
3052 sctx->framebuffer.all_DCC_pipe_aligned = false;
3053 }
3054
3055 si_context_add_resource_size(sctx, surf->base.texture);
3056
3057 p_atomic_inc(&tex->framebuffers_bound);
3058
3059 if (tex->dcc_gather_statistics) {
3060 /* Dirty tracking must be enabled for DCC usage analysis. */
3061 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3062 vi_separate_dcc_start_query(sctx, tex);
3063 }
3064
3065 /* Update the minimum but don't keep 0. */
3066 if (!sctx->framebuffer.min_bytes_per_pixel ||
3067 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3068 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3069 }
3070
3071 /* For optimal DCC performance. */
3072 if (sctx->chip_class >= GFX10)
3073 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3074 else
3075 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3076
3077 struct si_texture *zstex = NULL;
3078
3079 if (state->zsbuf) {
3080 surf = (struct si_surface*)state->zsbuf;
3081 zstex = (struct si_texture*)surf->base.texture;
3082
3083 if (!surf->depth_initialized) {
3084 si_init_depth_surface(sctx, surf);
3085 }
3086
3087 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3088 PIPE_MASK_ZS))
3089 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3090
3091 si_context_add_resource_size(sctx, surf->base.texture);
3092
3093 /* Update the minimum but don't keep 0. */
3094 if (!sctx->framebuffer.min_bytes_per_pixel ||
3095 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3096 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
3097 }
3098
3099 si_update_ps_colorbuf0_slot(sctx);
3100 si_update_poly_offset_state(sctx);
3101 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3102 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3103
3104 if (sctx->screen->dpbb_allowed)
3105 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3106
3107 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3108 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3109
3110 if (sctx->screen->has_out_of_order_rast &&
3111 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3112 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3113 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3114 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3115
3116 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3117 struct pipe_constant_buffer constbuf = {0};
3118
3119 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3120 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3121
3122 constbuf.buffer = sctx->sample_pos_buffer;
3123
3124 /* Set sample locations as fragment shader constants. */
3125 switch (sctx->framebuffer.nr_samples) {
3126 case 1:
3127 constbuf.buffer_offset = 0;
3128 break;
3129 case 2:
3130 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3131 (ubyte*)sctx->sample_positions.x1;
3132 break;
3133 case 4:
3134 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3135 (ubyte*)sctx->sample_positions.x1;
3136 break;
3137 case 8:
3138 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3139 (ubyte*)sctx->sample_positions.x1;
3140 break;
3141 case 16:
3142 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3143 (ubyte*)sctx->sample_positions.x1;
3144 break;
3145 default:
3146 PRINT_ERR("Requested an invalid number of samples %i.\n",
3147 sctx->framebuffer.nr_samples);
3148 assert(0);
3149 }
3150 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3151 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3152
3153 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3154 }
3155
3156 sctx->do_update_shaders = true;
3157
3158 if (!sctx->decompression_enabled) {
3159 /* Prevent textures decompression when the framebuffer state
3160 * changes come from the decompression passes themselves.
3161 */
3162 sctx->need_check_render_feedback = true;
3163 }
3164 }
3165
3166 static void si_emit_framebuffer_state(struct si_context *sctx)
3167 {
3168 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3169 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3170 unsigned i, nr_cbufs = state->nr_cbufs;
3171 struct si_texture *tex = NULL;
3172 struct si_surface *cb = NULL;
3173 unsigned cb_color_info = 0;
3174
3175 /* Colorbuffers. */
3176 for (i = 0; i < nr_cbufs; i++) {
3177 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3178 unsigned cb_color_attrib;
3179
3180 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3181 continue;
3182
3183 cb = (struct si_surface*)state->cbufs[i];
3184 if (!cb) {
3185 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3186 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3187 continue;
3188 }
3189
3190 tex = (struct si_texture *)cb->base.texture;
3191 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3192 &tex->buffer, RADEON_USAGE_READWRITE,
3193 tex->buffer.b.b.nr_samples > 1 ?
3194 RADEON_PRIO_COLOR_BUFFER_MSAA :
3195 RADEON_PRIO_COLOR_BUFFER);
3196
3197 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3198 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3199 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3200 RADEON_PRIO_SEPARATE_META);
3201 }
3202
3203 if (tex->dcc_separate_buffer)
3204 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3205 tex->dcc_separate_buffer,
3206 RADEON_USAGE_READWRITE,
3207 RADEON_PRIO_SEPARATE_META);
3208
3209 /* Compute mutable surface parameters. */
3210 cb_color_base = tex->buffer.gpu_address >> 8;
3211 cb_color_fmask = 0;
3212 cb_color_cmask = tex->cmask_base_address_reg;
3213 cb_dcc_base = 0;
3214 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3215 cb_color_attrib = cb->cb_color_attrib;
3216
3217 if (cb->base.u.tex.level > 0)
3218 cb_color_info &= C_028C70_FAST_CLEAR;
3219
3220 if (tex->surface.fmask_offset) {
3221 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3222 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3223 }
3224
3225 /* Set up DCC. */
3226 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3227 bool is_msaa_resolve_dst = state->cbufs[0] &&
3228 state->cbufs[0]->texture->nr_samples > 1 &&
3229 state->cbufs[1] == &cb->base &&
3230 state->cbufs[1]->texture->nr_samples <= 1;
3231
3232 if (!is_msaa_resolve_dst)
3233 cb_color_info |= S_028C70_DCC_ENABLE(1);
3234
3235 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3236 tex->surface.dcc_offset) >> 8;
3237
3238 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3239 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3240 cb_dcc_base |= dcc_tile_swizzle;
3241 }
3242
3243 if (sctx->chip_class >= GFX10) {
3244 unsigned cb_color_attrib3;
3245
3246 /* Set mutable surface parameters. */
3247 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3248 cb_color_base |= tex->surface.tile_swizzle;
3249 if (!tex->surface.fmask_offset)
3250 cb_color_fmask = cb_color_base;
3251 if (cb->base.u.tex.level > 0)
3252 cb_color_cmask = cb_color_base;
3253
3254 cb_color_attrib3 = cb->cb_color_attrib3 |
3255 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3256 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3257 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3258 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3259
3260 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3261 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3262 radeon_emit(cs, 0); /* hole */
3263 radeon_emit(cs, 0); /* hole */
3264 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3265 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3266 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3267 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3268 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3269 radeon_emit(cs, 0); /* hole */
3270 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3271 radeon_emit(cs, 0); /* hole */
3272 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3273 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3274 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3275
3276 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3277 cb_color_base >> 32);
3278 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3279 cb_color_cmask >> 32);
3280 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3281 cb_color_fmask >> 32);
3282 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3283 cb_dcc_base >> 32);
3284 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3285 cb->cb_color_attrib2);
3286 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3287 cb_color_attrib3);
3288 } else if (sctx->chip_class == GFX9) {
3289 struct gfx9_surf_meta_flags meta;
3290
3291 if (tex->surface.dcc_offset)
3292 meta = tex->surface.u.gfx9.dcc;
3293 else
3294 meta = tex->surface.u.gfx9.cmask;
3295
3296 /* Set mutable surface parameters. */
3297 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3298 cb_color_base |= tex->surface.tile_swizzle;
3299 if (!tex->surface.fmask_offset)
3300 cb_color_fmask = cb_color_base;
3301 if (cb->base.u.tex.level > 0)
3302 cb_color_cmask = cb_color_base;
3303 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3304 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3305 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3306 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3307
3308 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3309 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3310 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3311 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3312 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3313 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3314 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3315 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3316 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3317 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3318 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3319 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3320 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3321 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3322 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3323 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3324
3325 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3326 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3327 } else {
3328 /* Compute mutable surface parameters (GFX6-GFX8). */
3329 const struct legacy_surf_level *level_info =
3330 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3331 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3332 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3333
3334 cb_color_base += level_info->offset >> 8;
3335 /* Only macrotiled modes can set tile swizzle. */
3336 if (level_info->mode == RADEON_SURF_MODE_2D)
3337 cb_color_base |= tex->surface.tile_swizzle;
3338
3339 if (!tex->surface.fmask_offset)
3340 cb_color_fmask = cb_color_base;
3341 if (cb->base.u.tex.level > 0)
3342 cb_color_cmask = cb_color_base;
3343 if (cb_dcc_base)
3344 cb_dcc_base += level_info->dcc_offset >> 8;
3345
3346 pitch_tile_max = level_info->nblk_x / 8 - 1;
3347 slice_tile_max = level_info->nblk_x *
3348 level_info->nblk_y / 64 - 1;
3349 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3350
3351 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3352 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3353 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3354
3355 if (tex->surface.fmask_offset) {
3356 if (sctx->chip_class >= GFX7)
3357 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3358 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3359 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3360 } else {
3361 /* This must be set for fast clear to work without FMASK. */
3362 if (sctx->chip_class >= GFX7)
3363 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3364 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3365 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3366 }
3367
3368 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3369 sctx->chip_class >= GFX8 ? 14 : 13);
3370 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3371 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3372 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3373 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3374 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3375 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3376 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3377 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3378 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3379 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3380 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3381 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3382 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3383
3384 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3385 radeon_emit(cs, cb_dcc_base);
3386 }
3387 }
3388 for (; i < 8 ; i++)
3389 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3390 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3391
3392 /* ZS buffer. */
3393 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3394 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3395 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3396
3397 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3398 &tex->buffer, RADEON_USAGE_READWRITE,
3399 zb->base.texture->nr_samples > 1 ?
3400 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3401 RADEON_PRIO_DEPTH_BUFFER);
3402
3403 if (sctx->chip_class >= GFX10) {
3404 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3405 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3406
3407 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3408 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3409 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3410 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3411 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3412 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3413 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3414 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3415 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3416
3417 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3418 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3419 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3420 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3421 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3422 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3423 } else if (sctx->chip_class == GFX9) {
3424 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3425 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3426 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3427 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3428
3429 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3430 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3431 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3432 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3433 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3434 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3435 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3436 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3437 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3438 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3439 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3440 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3441
3442 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3443 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3444 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3445 } else {
3446 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3447
3448 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3449 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3450 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3451 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3452 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3453 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3454 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3455 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3456 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3457 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3458 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3459 }
3460
3461 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3462 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3463 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3464
3465 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3466 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3467 } else if (sctx->framebuffer.dirty_zsbuf) {
3468 if (sctx->chip_class == GFX9)
3469 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3470 else
3471 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3472
3473 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3474 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3475 }
3476
3477 /* Framebuffer dimensions. */
3478 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3479 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3480 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3481
3482 if (sctx->screen->dfsm_allowed) {
3483 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3484 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3485 }
3486
3487 sctx->framebuffer.dirty_cbufs = 0;
3488 sctx->framebuffer.dirty_zsbuf = false;
3489 }
3490
3491 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3492 {
3493 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3494 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3495 unsigned nr_samples = sctx->framebuffer.nr_samples;
3496 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3497
3498 /* Smoothing (only possible with nr_samples == 1) uses the same
3499 * sample locations as the MSAA it simulates.
3500 */
3501 if (nr_samples <= 1 && sctx->smoothing_enabled)
3502 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3503
3504 /* On Polaris, the small primitive filter uses the sample locations
3505 * even when MSAA is off, so we need to make sure they're set to 0.
3506 *
3507 * GFX10 uses sample locations unconditionally, so they always need
3508 * to be set up.
3509 */
3510 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3511 sctx->chip_class >= GFX10) &&
3512 nr_samples != sctx->sample_locs_num_samples) {
3513 sctx->sample_locs_num_samples = nr_samples;
3514 si_emit_sample_locations(cs, nr_samples);
3515 }
3516
3517 if (sctx->family >= CHIP_POLARIS10) {
3518 unsigned small_prim_filter_cntl =
3519 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3520 /* line bug */
3521 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3522
3523 /* The alternative of setting sample locations to 0 would
3524 * require a DB flush to avoid Z errors, see
3525 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3526 */
3527 if (has_msaa_sample_loc_bug &&
3528 sctx->framebuffer.nr_samples > 1 &&
3529 !rs->multisample_enable)
3530 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3531
3532 radeon_opt_set_context_reg(sctx,
3533 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3534 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3535 small_prim_filter_cntl);
3536 }
3537
3538 /* The exclusion bits can be set to improve rasterization efficiency
3539 * if no sample lies on the pixel boundary (-8 sample offset).
3540 */
3541 bool exclusion = sctx->chip_class >= GFX7 &&
3542 (!rs->multisample_enable || nr_samples != 16);
3543 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3544 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3545 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3546 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3547 }
3548
3549 static bool si_out_of_order_rasterization(struct si_context *sctx)
3550 {
3551 struct si_state_blend *blend = sctx->queued.named.blend;
3552 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3553
3554 if (!sctx->screen->has_out_of_order_rast)
3555 return false;
3556
3557 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3558
3559 colormask &= blend->cb_target_enabled_4bit;
3560
3561 /* Conservative: No logic op. */
3562 if (colormask && blend->logicop_enable)
3563 return false;
3564
3565 struct si_dsa_order_invariance dsa_order_invariant = {
3566 .zs = true, .pass_set = true, .pass_last = false
3567 };
3568
3569 if (sctx->framebuffer.state.zsbuf) {
3570 struct si_texture *zstex =
3571 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3572 bool has_stencil = zstex->surface.has_stencil;
3573 dsa_order_invariant = dsa->order_invariance[has_stencil];
3574 if (!dsa_order_invariant.zs)
3575 return false;
3576
3577 /* The set of PS invocations is always order invariant,
3578 * except when early Z/S tests are requested. */
3579 if (sctx->ps_shader.cso &&
3580 sctx->ps_shader.cso->info.writes_memory &&
3581 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3582 !dsa_order_invariant.pass_set)
3583 return false;
3584
3585 if (sctx->num_perfect_occlusion_queries != 0 &&
3586 !dsa_order_invariant.pass_set)
3587 return false;
3588 }
3589
3590 if (!colormask)
3591 return true;
3592
3593 unsigned blendmask = colormask & blend->blend_enable_4bit;
3594
3595 if (blendmask) {
3596 /* Only commutative blending. */
3597 if (blendmask & ~blend->commutative_4bit)
3598 return false;
3599
3600 if (!dsa_order_invariant.pass_set)
3601 return false;
3602 }
3603
3604 if (colormask & ~blendmask) {
3605 if (!dsa_order_invariant.pass_last)
3606 return false;
3607 }
3608
3609 return true;
3610 }
3611
3612 static void si_emit_msaa_config(struct si_context *sctx)
3613 {
3614 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3615 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3616 /* 33% faster rendering to linear color buffers */
3617 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3618 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3619 unsigned sc_mode_cntl_1 =
3620 S_028A4C_WALK_SIZE(dst_is_linear) |
3621 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3622 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3623 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3624 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3625 /* always 1: */
3626 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3627 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3628 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3629 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3630 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3631 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3632 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3633 S_028804_INCOHERENT_EQAA_READS(1) |
3634 S_028804_INTERPOLATE_COMP_Z(1) |
3635 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3636 unsigned coverage_samples, color_samples, z_samples;
3637 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3638
3639 /* S: Coverage samples (up to 16x):
3640 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3641 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3642 *
3643 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3644 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3645 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3646 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3647 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3648 * # Z samples).
3649 *
3650 * F: Color samples (up to 8x, must be <= coverage samples):
3651 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3652 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3653 *
3654 * Can be anything between coverage and color samples:
3655 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3656 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3657 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3658 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3659 * # All are currently set the same as coverage samples.
3660 *
3661 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3662 * flag for undefined color samples. A shader-based resolve must handle unknowns
3663 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3664 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3665 * useful. The CB resolve always drops unknowns.
3666 *
3667 * Sensible AA configurations:
3668 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3669 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3670 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3671 * EQAA 8s 8z 8f = 8x MSAA
3672 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3673 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3674 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3675 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3676 * EQAA 4s 4z 4f = 4x MSAA
3677 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3678 * EQAA 2s 2z 2f = 2x MSAA
3679 */
3680 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3681 coverage_samples = sctx->framebuffer.nr_samples;
3682 color_samples = sctx->framebuffer.nr_color_samples;
3683
3684 if (sctx->framebuffer.state.zsbuf) {
3685 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3686 z_samples = MAX2(1, z_samples);
3687 } else {
3688 z_samples = coverage_samples;
3689 }
3690 } else if (sctx->smoothing_enabled) {
3691 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3692 } else {
3693 coverage_samples = color_samples = z_samples = 1;
3694 }
3695
3696 /* Required by OpenGL line rasterization.
3697 *
3698 * TODO: We should also enable perpendicular endcaps for AA lines,
3699 * but that requires implementing line stippling in the pixel
3700 * shader. SC can only do line stippling with axis-aligned
3701 * endcaps.
3702 */
3703 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3704 unsigned sc_aa_config = 0;
3705
3706 if (coverage_samples > 1) {
3707 /* distance from the pixel center, indexed by log2(nr_samples) */
3708 static unsigned max_dist[] = {
3709 0, /* unused */
3710 4, /* 2x MSAA */
3711 6, /* 4x MSAA */
3712 7, /* 8x MSAA */
3713 8, /* 16x MSAA */
3714 };
3715 unsigned log_samples = util_logbase2(coverage_samples);
3716 unsigned log_z_samples = util_logbase2(z_samples);
3717 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3718 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3719
3720 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3721 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3722 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3723 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3724
3725 if (sctx->framebuffer.nr_samples > 1) {
3726 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3727 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3728 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3729 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3730 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3731 } else if (sctx->smoothing_enabled) {
3732 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3733 }
3734 }
3735
3736 unsigned initial_cdw = cs->current.cdw;
3737
3738 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3739 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3740 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3741 sc_aa_config);
3742 /* R_028804_DB_EQAA */
3743 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3744 db_eqaa);
3745 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3746 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3747 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3748
3749 if (initial_cdw != cs->current.cdw) {
3750 sctx->context_roll = true;
3751
3752 /* GFX9: Flush DFSM when the AA mode changes. */
3753 if (sctx->screen->dfsm_allowed) {
3754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3755 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3756 }
3757 }
3758 }
3759
3760 void si_update_ps_iter_samples(struct si_context *sctx)
3761 {
3762 if (sctx->framebuffer.nr_samples > 1)
3763 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3764 if (sctx->screen->dpbb_allowed)
3765 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3766 }
3767
3768 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3769 {
3770 struct si_context *sctx = (struct si_context *)ctx;
3771
3772 /* The hardware can only do sample shading with 2^n samples. */
3773 min_samples = util_next_power_of_two(min_samples);
3774
3775 if (sctx->ps_iter_samples == min_samples)
3776 return;
3777
3778 sctx->ps_iter_samples = min_samples;
3779 sctx->do_update_shaders = true;
3780
3781 si_update_ps_iter_samples(sctx);
3782 }
3783
3784 /*
3785 * Samplers
3786 */
3787
3788 /**
3789 * Build the sampler view descriptor for a buffer texture.
3790 * @param state 256-bit descriptor; only the high 128 bits are filled in
3791 */
3792 void
3793 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3794 enum pipe_format format,
3795 unsigned offset, unsigned size,
3796 uint32_t *state)
3797 {
3798 const struct util_format_description *desc;
3799 unsigned stride;
3800 unsigned num_records;
3801
3802 desc = util_format_description(format);
3803 stride = desc->block.bits / 8;
3804
3805 num_records = size / stride;
3806 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3807
3808 /* The NUM_RECORDS field has a different meaning depending on the chip,
3809 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3810 *
3811 * GFX6-7,10:
3812 * - If STRIDE == 0, it's in byte units.
3813 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3814 *
3815 * GFX8:
3816 * - For SMEM and STRIDE == 0, it's in byte units.
3817 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3818 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3819 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3820 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3821 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3822 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3823 * That way the same descriptor can be used by both SMEM and VMEM.
3824 *
3825 * GFX9:
3826 * - For SMEM and STRIDE == 0, it's in byte units.
3827 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3828 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3829 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3830 */
3831 if (screen->info.chip_class == GFX8)
3832 num_records *= stride;
3833
3834 state[4] = 0;
3835 state[5] = S_008F04_STRIDE(stride);
3836 state[6] = num_records;
3837 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3838 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3839 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3840 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3841
3842 if (screen->info.chip_class >= GFX10) {
3843 const struct gfx10_format *fmt = &gfx10_format_table[format];
3844
3845 /* OOB_SELECT chooses the out-of-bounds check:
3846 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3847 * - 1: index >= NUM_RECORDS
3848 * - 2: NUM_RECORDS == 0
3849 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3850 * else: swizzle_address >= NUM_RECORDS
3851 */
3852 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3853 S_008F0C_OOB_SELECT(0) |
3854 S_008F0C_RESOURCE_LEVEL(1);
3855 } else {
3856 int first_non_void;
3857 unsigned num_format, data_format;
3858
3859 first_non_void = util_format_get_first_non_void_channel(format);
3860 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3861 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3862
3863 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3864 S_008F0C_DATA_FORMAT(data_format);
3865 }
3866 }
3867
3868 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3869 {
3870 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3871
3872 if (swizzle[3] == PIPE_SWIZZLE_X) {
3873 /* For the pre-defined border color values (white, opaque
3874 * black, transparent black), the only thing that matters is
3875 * that the alpha channel winds up in the correct place
3876 * (because the RGB channels are all the same) so either of
3877 * these enumerations will work.
3878 */
3879 if (swizzle[2] == PIPE_SWIZZLE_Y)
3880 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3881 else
3882 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3883 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3884 if (swizzle[1] == PIPE_SWIZZLE_Y)
3885 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3886 else
3887 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3888 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3889 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3890 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3891 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3892 }
3893
3894 return bc_swizzle;
3895 }
3896
3897 /**
3898 * Build the sampler view descriptor for a texture.
3899 */
3900 static void
3901 gfx10_make_texture_descriptor(struct si_screen *screen,
3902 struct si_texture *tex,
3903 bool sampler,
3904 enum pipe_texture_target target,
3905 enum pipe_format pipe_format,
3906 const unsigned char state_swizzle[4],
3907 unsigned first_level, unsigned last_level,
3908 unsigned first_layer, unsigned last_layer,
3909 unsigned width, unsigned height, unsigned depth,
3910 uint32_t *state,
3911 uint32_t *fmask_state)
3912 {
3913 struct pipe_resource *res = &tex->buffer.b.b;
3914 const struct util_format_description *desc;
3915 unsigned img_format;
3916 unsigned char swizzle[4];
3917 unsigned type;
3918 uint64_t va;
3919
3920 desc = util_format_description(pipe_format);
3921 img_format = gfx10_format_table[pipe_format].img_format;
3922
3923 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3924 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3925 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3926 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3927 bool is_stencil = false;
3928
3929 switch (pipe_format) {
3930 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3931 case PIPE_FORMAT_X32_S8X24_UINT:
3932 case PIPE_FORMAT_X8Z24_UNORM:
3933 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3934 is_stencil = true;
3935 break;
3936 case PIPE_FORMAT_X24S8_UINT:
3937 /*
3938 * X24S8 is implemented as an 8_8_8_8 data format, to
3939 * fix texture gathers. This affects at least
3940 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3941 */
3942 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3943 is_stencil = true;
3944 break;
3945 default:
3946 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3947 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3948 }
3949
3950 if (tex->upgraded_depth && !is_stencil) {
3951 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3952 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3953 }
3954 } else {
3955 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3956 }
3957
3958 if (!sampler &&
3959 (res->target == PIPE_TEXTURE_CUBE ||
3960 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3961 /* For the purpose of shader images, treat cube maps as 2D
3962 * arrays.
3963 */
3964 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3965 } else {
3966 type = si_tex_dim(screen, tex, target, res->nr_samples);
3967 }
3968
3969 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3970 height = 1;
3971 depth = res->array_size;
3972 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3973 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3974 if (sampler || res->target != PIPE_TEXTURE_3D)
3975 depth = res->array_size;
3976 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3977 depth = res->array_size / 6;
3978
3979 state[0] = 0;
3980 state[1] = S_00A004_FORMAT(img_format) |
3981 S_00A004_WIDTH_LO(width - 1);
3982 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3983 S_00A008_HEIGHT(height - 1) |
3984 S_00A008_RESOURCE_LEVEL(1);
3985 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3986 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3987 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3988 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3989 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3990 0 : first_level) |
3991 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3992 util_logbase2(res->nr_samples) :
3993 last_level) |
3994 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3995 S_00A00C_TYPE(type);
3996 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3997 * to know the total number of layers.
3998 */
3999 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
4000 ? depth - 1 : last_layer) |
4001 S_00A010_BASE_ARRAY(first_layer);
4002 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
4003 S_00A014_MAX_MIP(res->nr_samples > 1 ?
4004 util_logbase2(res->nr_samples) :
4005 tex->buffer.b.b.last_level) |
4006 S_00A014_PERF_MOD(4);
4007 state[6] = 0;
4008 state[7] = 0;
4009
4010 if (tex->surface.dcc_offset) {
4011 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
4012 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
4013 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4014 }
4015
4016 /* Initialize the sampler view for FMASK. */
4017 if (tex->surface.fmask_offset) {
4018 uint32_t format;
4019
4020 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4021
4022 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4023 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4024 case FMASK(2,1):
4025 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4026 break;
4027 case FMASK(2,2):
4028 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4029 break;
4030 case FMASK(4,1):
4031 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4032 break;
4033 case FMASK(4,2):
4034 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4035 break;
4036 case FMASK(4,4):
4037 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4038 break;
4039 case FMASK(8,1):
4040 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4041 break;
4042 case FMASK(8,2):
4043 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4044 break;
4045 case FMASK(8,4):
4046 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4047 break;
4048 case FMASK(8,8):
4049 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4050 break;
4051 case FMASK(16,1):
4052 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4053 break;
4054 case FMASK(16,2):
4055 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4056 break;
4057 case FMASK(16,4):
4058 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4059 break;
4060 case FMASK(16,8):
4061 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4062 break;
4063 default:
4064 unreachable("invalid nr_samples");
4065 }
4066 #undef FMASK
4067 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4068 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4069 S_00A004_FORMAT(format) |
4070 S_00A004_WIDTH_LO(width - 1);
4071 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4072 S_00A008_HEIGHT(height - 1) |
4073 S_00A008_RESOURCE_LEVEL(1);
4074 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4075 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4076 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4077 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4078 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4079 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4080 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4081 S_00A010_BASE_ARRAY(first_layer);
4082 fmask_state[5] = 0;
4083 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4084 fmask_state[7] = 0;
4085 }
4086 }
4087
4088 /**
4089 * Build the sampler view descriptor for a texture (SI-GFX9).
4090 */
4091 static void
4092 si_make_texture_descriptor(struct si_screen *screen,
4093 struct si_texture *tex,
4094 bool sampler,
4095 enum pipe_texture_target target,
4096 enum pipe_format pipe_format,
4097 const unsigned char state_swizzle[4],
4098 unsigned first_level, unsigned last_level,
4099 unsigned first_layer, unsigned last_layer,
4100 unsigned width, unsigned height, unsigned depth,
4101 uint32_t *state,
4102 uint32_t *fmask_state)
4103 {
4104 struct pipe_resource *res = &tex->buffer.b.b;
4105 const struct util_format_description *desc;
4106 unsigned char swizzle[4];
4107 int first_non_void;
4108 unsigned num_format, data_format, type, num_samples;
4109 uint64_t va;
4110
4111 desc = util_format_description(pipe_format);
4112
4113 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4114 MAX2(1, res->nr_samples) :
4115 MAX2(1, res->nr_storage_samples);
4116
4117 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4118 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4119 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4120 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4121
4122 switch (pipe_format) {
4123 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4124 case PIPE_FORMAT_X32_S8X24_UINT:
4125 case PIPE_FORMAT_X8Z24_UNORM:
4126 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4127 break;
4128 case PIPE_FORMAT_X24S8_UINT:
4129 /*
4130 * X24S8 is implemented as an 8_8_8_8 data format, to
4131 * fix texture gathers. This affects at least
4132 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4133 */
4134 if (screen->info.chip_class <= GFX8)
4135 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4136 else
4137 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4138 break;
4139 default:
4140 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4141 }
4142 } else {
4143 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4144 }
4145
4146 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4147
4148 switch (pipe_format) {
4149 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4150 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4151 break;
4152 default:
4153 if (first_non_void < 0) {
4154 if (util_format_is_compressed(pipe_format)) {
4155 switch (pipe_format) {
4156 case PIPE_FORMAT_DXT1_SRGB:
4157 case PIPE_FORMAT_DXT1_SRGBA:
4158 case PIPE_FORMAT_DXT3_SRGBA:
4159 case PIPE_FORMAT_DXT5_SRGBA:
4160 case PIPE_FORMAT_BPTC_SRGBA:
4161 case PIPE_FORMAT_ETC2_SRGB8:
4162 case PIPE_FORMAT_ETC2_SRGB8A1:
4163 case PIPE_FORMAT_ETC2_SRGBA8:
4164 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4165 break;
4166 case PIPE_FORMAT_RGTC1_SNORM:
4167 case PIPE_FORMAT_LATC1_SNORM:
4168 case PIPE_FORMAT_RGTC2_SNORM:
4169 case PIPE_FORMAT_LATC2_SNORM:
4170 case PIPE_FORMAT_ETC2_R11_SNORM:
4171 case PIPE_FORMAT_ETC2_RG11_SNORM:
4172 /* implies float, so use SNORM/UNORM to determine
4173 whether data is signed or not */
4174 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4175 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4176 break;
4177 default:
4178 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4179 break;
4180 }
4181 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4182 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4183 } else {
4184 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4185 }
4186 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4187 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4188 } else {
4189 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4190
4191 switch (desc->channel[first_non_void].type) {
4192 case UTIL_FORMAT_TYPE_FLOAT:
4193 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4194 break;
4195 case UTIL_FORMAT_TYPE_SIGNED:
4196 if (desc->channel[first_non_void].normalized)
4197 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4198 else if (desc->channel[first_non_void].pure_integer)
4199 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4200 else
4201 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4202 break;
4203 case UTIL_FORMAT_TYPE_UNSIGNED:
4204 if (desc->channel[first_non_void].normalized)
4205 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4206 else if (desc->channel[first_non_void].pure_integer)
4207 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4208 else
4209 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4210 }
4211 }
4212 }
4213
4214 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4215 if (data_format == ~0) {
4216 data_format = 0;
4217 }
4218
4219 /* S8 with Z32 HTILE needs a special format. */
4220 if (screen->info.chip_class == GFX9 &&
4221 pipe_format == PIPE_FORMAT_S8_UINT &&
4222 tex->tc_compatible_htile)
4223 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4224
4225 if (!sampler &&
4226 (res->target == PIPE_TEXTURE_CUBE ||
4227 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4228 (screen->info.chip_class <= GFX8 &&
4229 res->target == PIPE_TEXTURE_3D))) {
4230 /* For the purpose of shader images, treat cube maps and 3D
4231 * textures as 2D arrays. For 3D textures, the address
4232 * calculations for mipmaps are different, so we rely on the
4233 * caller to effectively disable mipmaps.
4234 */
4235 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4236
4237 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4238 } else {
4239 type = si_tex_dim(screen, tex, target, num_samples);
4240 }
4241
4242 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4243 height = 1;
4244 depth = res->array_size;
4245 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4246 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4247 if (sampler || res->target != PIPE_TEXTURE_3D)
4248 depth = res->array_size;
4249 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4250 depth = res->array_size / 6;
4251
4252 state[0] = 0;
4253 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4254 S_008F14_NUM_FORMAT(num_format));
4255 state[2] = (S_008F18_WIDTH(width - 1) |
4256 S_008F18_HEIGHT(height - 1) |
4257 S_008F18_PERF_MOD(4));
4258 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4259 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4260 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4261 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4262 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4263 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4264 util_logbase2(num_samples) :
4265 last_level) |
4266 S_008F1C_TYPE(type));
4267 state[4] = 0;
4268 state[5] = S_008F24_BASE_ARRAY(first_layer);
4269 state[6] = 0;
4270 state[7] = 0;
4271
4272 if (screen->info.chip_class == GFX9) {
4273 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4274
4275 /* Depth is the the last accessible layer on Gfx9.
4276 * The hw doesn't need to know the total number of layers.
4277 */
4278 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4279 state[4] |= S_008F20_DEPTH(depth - 1);
4280 else
4281 state[4] |= S_008F20_DEPTH(last_layer);
4282
4283 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4284 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4285 util_logbase2(num_samples) :
4286 tex->buffer.b.b.last_level);
4287 } else {
4288 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4289 state[4] |= S_008F20_DEPTH(depth - 1);
4290 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4291 }
4292
4293 if (tex->surface.dcc_offset) {
4294 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4295 } else {
4296 /* The last dword is unused by hw. The shader uses it to clear
4297 * bits in the first dword of sampler state.
4298 */
4299 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4300 if (first_level == last_level)
4301 state[7] = C_008F30_MAX_ANISO_RATIO;
4302 else
4303 state[7] = 0xffffffff;
4304 }
4305 }
4306
4307 /* Initialize the sampler view for FMASK. */
4308 if (tex->surface.fmask_offset) {
4309 uint32_t data_format, num_format;
4310
4311 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4312
4313 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4314 if (screen->info.chip_class == GFX9) {
4315 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4316 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4317 case FMASK(2,1):
4318 num_format = V_008F14_IMG_FMASK_8_2_1;
4319 break;
4320 case FMASK(2,2):
4321 num_format = V_008F14_IMG_FMASK_8_2_2;
4322 break;
4323 case FMASK(4,1):
4324 num_format = V_008F14_IMG_FMASK_8_4_1;
4325 break;
4326 case FMASK(4,2):
4327 num_format = V_008F14_IMG_FMASK_8_4_2;
4328 break;
4329 case FMASK(4,4):
4330 num_format = V_008F14_IMG_FMASK_8_4_4;
4331 break;
4332 case FMASK(8,1):
4333 num_format = V_008F14_IMG_FMASK_8_8_1;
4334 break;
4335 case FMASK(8,2):
4336 num_format = V_008F14_IMG_FMASK_16_8_2;
4337 break;
4338 case FMASK(8,4):
4339 num_format = V_008F14_IMG_FMASK_32_8_4;
4340 break;
4341 case FMASK(8,8):
4342 num_format = V_008F14_IMG_FMASK_32_8_8;
4343 break;
4344 case FMASK(16,1):
4345 num_format = V_008F14_IMG_FMASK_16_16_1;
4346 break;
4347 case FMASK(16,2):
4348 num_format = V_008F14_IMG_FMASK_32_16_2;
4349 break;
4350 case FMASK(16,4):
4351 num_format = V_008F14_IMG_FMASK_64_16_4;
4352 break;
4353 case FMASK(16,8):
4354 num_format = V_008F14_IMG_FMASK_64_16_8;
4355 break;
4356 default:
4357 unreachable("invalid nr_samples");
4358 }
4359 } else {
4360 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4361 case FMASK(2,1):
4362 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4363 break;
4364 case FMASK(2,2):
4365 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4366 break;
4367 case FMASK(4,1):
4368 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4369 break;
4370 case FMASK(4,2):
4371 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4372 break;
4373 case FMASK(4,4):
4374 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4375 break;
4376 case FMASK(8,1):
4377 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4378 break;
4379 case FMASK(8,2):
4380 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4381 break;
4382 case FMASK(8,4):
4383 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4384 break;
4385 case FMASK(8,8):
4386 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4387 break;
4388 case FMASK(16,1):
4389 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4390 break;
4391 case FMASK(16,2):
4392 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4393 break;
4394 case FMASK(16,4):
4395 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4396 break;
4397 case FMASK(16,8):
4398 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4399 break;
4400 default:
4401 unreachable("invalid nr_samples");
4402 }
4403 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4404 }
4405 #undef FMASK
4406
4407 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4408 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4409 S_008F14_DATA_FORMAT(data_format) |
4410 S_008F14_NUM_FORMAT(num_format);
4411 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4412 S_008F18_HEIGHT(height - 1);
4413 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4414 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4415 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4416 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4417 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4418 fmask_state[4] = 0;
4419 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4420 fmask_state[6] = 0;
4421 fmask_state[7] = 0;
4422
4423 if (screen->info.chip_class == GFX9) {
4424 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4425 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4426 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4427 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4428 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4429 } else {
4430 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4431 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4432 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4433 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4434 }
4435 }
4436 }
4437
4438 /**
4439 * Create a sampler view.
4440 *
4441 * @param ctx context
4442 * @param texture texture
4443 * @param state sampler view template
4444 * @param width0 width0 override (for compressed textures as int)
4445 * @param height0 height0 override (for compressed textures as int)
4446 * @param force_level set the base address to the level (for compressed textures)
4447 */
4448 struct pipe_sampler_view *
4449 si_create_sampler_view_custom(struct pipe_context *ctx,
4450 struct pipe_resource *texture,
4451 const struct pipe_sampler_view *state,
4452 unsigned width0, unsigned height0,
4453 unsigned force_level)
4454 {
4455 struct si_context *sctx = (struct si_context*)ctx;
4456 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4457 struct si_texture *tex = (struct si_texture*)texture;
4458 unsigned base_level, first_level, last_level;
4459 unsigned char state_swizzle[4];
4460 unsigned height, depth, width;
4461 unsigned last_layer = state->u.tex.last_layer;
4462 enum pipe_format pipe_format;
4463 const struct legacy_surf_level *surflevel;
4464
4465 if (!view)
4466 return NULL;
4467
4468 /* initialize base object */
4469 view->base = *state;
4470 view->base.texture = NULL;
4471 view->base.reference.count = 1;
4472 view->base.context = ctx;
4473
4474 assert(texture);
4475 pipe_resource_reference(&view->base.texture, texture);
4476
4477 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4478 state->format == PIPE_FORMAT_S8X24_UINT ||
4479 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4480 state->format == PIPE_FORMAT_S8_UINT)
4481 view->is_stencil_sampler = true;
4482
4483 /* Buffer resource. */
4484 if (texture->target == PIPE_BUFFER) {
4485 si_make_buffer_descriptor(sctx->screen,
4486 si_resource(texture),
4487 state->format,
4488 state->u.buf.offset,
4489 state->u.buf.size,
4490 view->state);
4491 return &view->base;
4492 }
4493
4494 state_swizzle[0] = state->swizzle_r;
4495 state_swizzle[1] = state->swizzle_g;
4496 state_swizzle[2] = state->swizzle_b;
4497 state_swizzle[3] = state->swizzle_a;
4498
4499 base_level = 0;
4500 first_level = state->u.tex.first_level;
4501 last_level = state->u.tex.last_level;
4502 width = width0;
4503 height = height0;
4504 depth = texture->depth0;
4505
4506 if (sctx->chip_class <= GFX8 && force_level) {
4507 assert(force_level == first_level &&
4508 force_level == last_level);
4509 base_level = force_level;
4510 first_level = 0;
4511 last_level = 0;
4512 width = u_minify(width, force_level);
4513 height = u_minify(height, force_level);
4514 depth = u_minify(depth, force_level);
4515 }
4516
4517 /* This is not needed if state trackers set last_layer correctly. */
4518 if (state->target == PIPE_TEXTURE_1D ||
4519 state->target == PIPE_TEXTURE_2D ||
4520 state->target == PIPE_TEXTURE_RECT ||
4521 state->target == PIPE_TEXTURE_CUBE)
4522 last_layer = state->u.tex.first_layer;
4523
4524 /* Texturing with separate depth and stencil. */
4525 pipe_format = state->format;
4526
4527 /* Depth/stencil texturing sometimes needs separate texture. */
4528 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4529 if (!tex->flushed_depth_texture &&
4530 !si_init_flushed_depth_texture(ctx, texture)) {
4531 pipe_resource_reference(&view->base.texture, NULL);
4532 FREE(view);
4533 return NULL;
4534 }
4535
4536 assert(tex->flushed_depth_texture);
4537
4538 /* Override format for the case where the flushed texture
4539 * contains only Z or only S.
4540 */
4541 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4542 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4543
4544 tex = tex->flushed_depth_texture;
4545 }
4546
4547 surflevel = tex->surface.u.legacy.level;
4548
4549 if (tex->db_compatible) {
4550 if (!view->is_stencil_sampler)
4551 pipe_format = tex->db_render_format;
4552
4553 switch (pipe_format) {
4554 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4555 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4556 break;
4557 case PIPE_FORMAT_X8Z24_UNORM:
4558 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4559 /* Z24 is always stored like this for DB
4560 * compatibility.
4561 */
4562 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4563 break;
4564 case PIPE_FORMAT_X24S8_UINT:
4565 case PIPE_FORMAT_S8X24_UINT:
4566 case PIPE_FORMAT_X32_S8X24_UINT:
4567 pipe_format = PIPE_FORMAT_S8_UINT;
4568 surflevel = tex->surface.u.legacy.stencil_level;
4569 break;
4570 default:;
4571 }
4572 }
4573
4574 view->dcc_incompatible =
4575 vi_dcc_formats_are_incompatible(texture,
4576 state->u.tex.first_level,
4577 state->format);
4578
4579 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4580 state->target, pipe_format, state_swizzle,
4581 first_level, last_level,
4582 state->u.tex.first_layer, last_layer,
4583 width, height, depth,
4584 view->state, view->fmask_state);
4585
4586 const struct util_format_description *desc = util_format_description(pipe_format);
4587 view->is_integer = false;
4588
4589 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4590 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4591 continue;
4592
4593 /* Whether the number format is {U,S}{SCALED,INT} */
4594 view->is_integer =
4595 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4596 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4597 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4598 break;
4599 }
4600
4601 view->base_level_info = &surflevel[base_level];
4602 view->base_level = base_level;
4603 view->block_width = util_format_get_blockwidth(pipe_format);
4604 return &view->base;
4605 }
4606
4607 static struct pipe_sampler_view *
4608 si_create_sampler_view(struct pipe_context *ctx,
4609 struct pipe_resource *texture,
4610 const struct pipe_sampler_view *state)
4611 {
4612 return si_create_sampler_view_custom(ctx, texture, state,
4613 texture ? texture->width0 : 0,
4614 texture ? texture->height0 : 0, 0);
4615 }
4616
4617 static void si_sampler_view_destroy(struct pipe_context *ctx,
4618 struct pipe_sampler_view *state)
4619 {
4620 struct si_sampler_view *view = (struct si_sampler_view *)state;
4621
4622 pipe_resource_reference(&state->texture, NULL);
4623 FREE(view);
4624 }
4625
4626 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4627 {
4628 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4629 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4630 (linear_filter &&
4631 (wrap == PIPE_TEX_WRAP_CLAMP ||
4632 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4633 }
4634
4635 static uint32_t si_translate_border_color(struct si_context *sctx,
4636 const struct pipe_sampler_state *state,
4637 const union pipe_color_union *color,
4638 bool is_integer)
4639 {
4640 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4641 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4642
4643 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4644 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4645 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4646 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4647
4648 #define simple_border_types(elt) \
4649 do { \
4650 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4651 color->elt[2] == 0 && color->elt[3] == 0) \
4652 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4653 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4654 color->elt[2] == 0 && color->elt[3] == 1) \
4655 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4656 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4657 color->elt[2] == 1 && color->elt[3] == 1) \
4658 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4659 } while (false)
4660
4661 if (is_integer)
4662 simple_border_types(ui);
4663 else
4664 simple_border_types(f);
4665
4666 #undef simple_border_types
4667
4668 int i;
4669
4670 /* Check if the border has been uploaded already. */
4671 for (i = 0; i < sctx->border_color_count; i++)
4672 if (memcmp(&sctx->border_color_table[i], color,
4673 sizeof(*color)) == 0)
4674 break;
4675
4676 if (i >= SI_MAX_BORDER_COLORS) {
4677 /* Getting 4096 unique border colors is very unlikely. */
4678 fprintf(stderr, "radeonsi: The border color table is full. "
4679 "Any new border colors will be just black. "
4680 "Please file a bug.\n");
4681 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4682 }
4683
4684 if (i == sctx->border_color_count) {
4685 /* Upload a new border color. */
4686 memcpy(&sctx->border_color_table[i], color,
4687 sizeof(*color));
4688 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4689 color, sizeof(*color));
4690 sctx->border_color_count++;
4691 }
4692
4693 return S_008F3C_BORDER_COLOR_PTR(i) |
4694 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4695 }
4696
4697 static inline int S_FIXED(float value, unsigned frac_bits)
4698 {
4699 return value * (1 << frac_bits);
4700 }
4701
4702 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4703 {
4704 if (filter == PIPE_TEX_FILTER_LINEAR)
4705 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4706 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4707 else
4708 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4709 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4710 }
4711
4712 static inline unsigned si_tex_aniso_filter(unsigned filter)
4713 {
4714 if (filter < 2)
4715 return 0;
4716 if (filter < 4)
4717 return 1;
4718 if (filter < 8)
4719 return 2;
4720 if (filter < 16)
4721 return 3;
4722 return 4;
4723 }
4724
4725 static void *si_create_sampler_state(struct pipe_context *ctx,
4726 const struct pipe_sampler_state *state)
4727 {
4728 struct si_context *sctx = (struct si_context *)ctx;
4729 struct si_screen *sscreen = sctx->screen;
4730 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4731 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4732 : state->max_anisotropy;
4733 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4734 union pipe_color_union clamped_border_color;
4735
4736 if (!rstate) {
4737 return NULL;
4738 }
4739
4740 #ifndef NDEBUG
4741 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4742 #endif
4743 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4744 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4745 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4746 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4747 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4748 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4749 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4750 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4751 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4752 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4753 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4754 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4755 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4756 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4757 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4758 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4759 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4760 S_008F38_MIP_POINT_PRECLAMP(0));
4761 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4762
4763 if (sscreen->info.chip_class >= GFX10) {
4764 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4765 } else {
4766 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4767 S_008F38_FILTER_PREC_FIX(1) |
4768 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4769 }
4770
4771 /* Create sampler resource for integer textures. */
4772 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4773 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4774
4775 /* Create sampler resource for upgraded depth textures. */
4776 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4777
4778 for (unsigned i = 0; i < 4; ++i) {
4779 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4780 * when the border color is 1.0. */
4781 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4782 }
4783
4784 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4785 if (sscreen->info.chip_class <= GFX9)
4786 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4787 } else {
4788 rstate->upgraded_depth_val[3] =
4789 si_translate_border_color(sctx, state, &clamped_border_color, false);
4790 }
4791
4792 return rstate;
4793 }
4794
4795 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4796 {
4797 struct si_context *sctx = (struct si_context *)ctx;
4798
4799 if (sctx->sample_mask == (uint16_t)sample_mask)
4800 return;
4801
4802 sctx->sample_mask = sample_mask;
4803 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4804 }
4805
4806 static void si_emit_sample_mask(struct si_context *sctx)
4807 {
4808 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4809 unsigned mask = sctx->sample_mask;
4810
4811 /* Needed for line and polygon smoothing as well as for the Polaris
4812 * small primitive filter. We expect the state tracker to take care of
4813 * this for us.
4814 */
4815 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4816 (mask & 1 && sctx->blitter->running));
4817
4818 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4819 radeon_emit(cs, mask | (mask << 16));
4820 radeon_emit(cs, mask | (mask << 16));
4821 }
4822
4823 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4824 {
4825 #ifndef NDEBUG
4826 struct si_sampler_state *s = state;
4827
4828 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4829 s->magic = 0;
4830 #endif
4831 free(state);
4832 }
4833
4834 /*
4835 * Vertex elements & buffers
4836 */
4837
4838 struct si_fast_udiv_info32
4839 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4840 {
4841 struct util_fast_udiv_info info =
4842 util_compute_fast_udiv_info(D, num_bits, 32);
4843
4844 struct si_fast_udiv_info32 result = {
4845 info.multiplier,
4846 info.pre_shift,
4847 info.post_shift,
4848 info.increment,
4849 };
4850 return result;
4851 }
4852
4853 static void *si_create_vertex_elements(struct pipe_context *ctx,
4854 unsigned count,
4855 const struct pipe_vertex_element *elements)
4856 {
4857 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4858 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4859 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4860 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4861 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4862 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4863 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4864 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4865 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4866 int i;
4867
4868 assert(count <= SI_MAX_ATTRIBS);
4869 if (!v)
4870 return NULL;
4871
4872 v->count = count;
4873 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4874
4875 for (i = 0; i < count; ++i) {
4876 const struct util_format_description *desc;
4877 const struct util_format_channel_description *channel;
4878 int first_non_void;
4879 unsigned vbo_index = elements[i].vertex_buffer_index;
4880
4881 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4882 FREE(v);
4883 return NULL;
4884 }
4885
4886 unsigned instance_divisor = elements[i].instance_divisor;
4887 if (instance_divisor) {
4888 v->uses_instance_divisors = true;
4889
4890 if (instance_divisor == 1) {
4891 v->instance_divisor_is_one |= 1u << i;
4892 } else {
4893 v->instance_divisor_is_fetched |= 1u << i;
4894 divisor_factors[i] =
4895 si_compute_fast_udiv_info32(instance_divisor, 32);
4896 }
4897 }
4898
4899 if (!used[vbo_index]) {
4900 v->first_vb_use_mask |= 1 << i;
4901 used[vbo_index] = true;
4902 }
4903
4904 desc = util_format_description(elements[i].src_format);
4905 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4906 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4907
4908 v->format_size[i] = desc->block.bits / 8;
4909 v->src_offset[i] = elements[i].src_offset;
4910 v->vertex_buffer_index[i] = vbo_index;
4911
4912 bool always_fix = false;
4913 union si_vs_fix_fetch fix_fetch;
4914 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4915
4916 fix_fetch.bits = 0;
4917 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4918
4919 if (channel) {
4920 switch (channel->type) {
4921 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4922 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4923 case UTIL_FORMAT_TYPE_SIGNED: {
4924 if (channel->pure_integer)
4925 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4926 else if (channel->normalized)
4927 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4928 else
4929 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4930 break;
4931 }
4932 case UTIL_FORMAT_TYPE_UNSIGNED: {
4933 if (channel->pure_integer)
4934 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4935 else if (channel->normalized)
4936 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4937 else
4938 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4939 break;
4940 }
4941 default: unreachable("bad format type");
4942 }
4943 } else {
4944 switch (elements[i].src_format) {
4945 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4946 default: unreachable("bad other format");
4947 }
4948 }
4949
4950 if (desc->channel[0].size == 10) {
4951 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4952 log_hw_load_size = 2;
4953
4954 /* The hardware always treats the 2-bit alpha channel as
4955 * unsigned, so a shader workaround is needed. The affected
4956 * chips are GFX8 and older except Stoney (GFX8.1).
4957 */
4958 always_fix = sscreen->info.chip_class <= GFX8 &&
4959 sscreen->info.family != CHIP_STONEY &&
4960 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4961 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4962 fix_fetch.u.log_size = 3; /* special encoding */
4963 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4964 log_hw_load_size = 2;
4965 } else {
4966 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4967 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4968
4969 /* Always fix up:
4970 * - doubles (multiple loads + truncate to float)
4971 * - 32-bit requiring a conversion
4972 */
4973 always_fix =
4974 (fix_fetch.u.log_size == 3) ||
4975 (fix_fetch.u.log_size == 2 &&
4976 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4977 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4978 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4979
4980 /* Also fixup 8_8_8 and 16_16_16. */
4981 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4982 always_fix = true;
4983 log_hw_load_size = fix_fetch.u.log_size;
4984 }
4985 }
4986
4987 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4988 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4989 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4990 fix_fetch.u.reverse = 1;
4991 }
4992
4993 /* Force the workaround for unaligned access here already if the
4994 * offset relative to the vertex buffer base is unaligned.
4995 *
4996 * There is a theoretical case in which this is too conservative:
4997 * if the vertex buffer's offset is also unaligned in just the
4998 * right way, we end up with an aligned address after all.
4999 * However, this case should be extremely rare in practice (it
5000 * won't happen in well-behaved applications), and taking it
5001 * into account would complicate the fast path (where everything
5002 * is nicely aligned).
5003 */
5004 bool check_alignment =
5005 log_hw_load_size >= 1 &&
5006 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
5007 bool opencode = sscreen->options.vs_fetch_always_opencode;
5008
5009 if (check_alignment &&
5010 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
5011 opencode = true;
5012
5013 if (always_fix || check_alignment || opencode)
5014 v->fix_fetch[i] = fix_fetch.bits;
5015
5016 if (opencode)
5017 v->fix_fetch_opencode |= 1 << i;
5018 if (opencode || always_fix)
5019 v->fix_fetch_always |= 1 << i;
5020
5021 if (check_alignment && !opencode) {
5022 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5023
5024 v->fix_fetch_unaligned |= 1 << i;
5025 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5026 v->vb_alignment_check_mask |= 1 << vbo_index;
5027 }
5028
5029 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5030 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5031 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5032 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5033
5034 if (sscreen->info.chip_class >= GFX10) {
5035 const struct gfx10_format *fmt =
5036 &gfx10_format_table[elements[i].src_format];
5037 assert(fmt->img_format != 0 && fmt->img_format < 128);
5038 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5039 S_008F0C_RESOURCE_LEVEL(1);
5040 } else {
5041 unsigned data_format, num_format;
5042 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5043 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5044 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5045 S_008F0C_DATA_FORMAT(data_format);
5046 }
5047 }
5048
5049 if (v->instance_divisor_is_fetched) {
5050 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5051
5052 v->instance_divisor_factor_buffer =
5053 (struct si_resource*)
5054 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5055 num_divisors * sizeof(divisor_factors[0]));
5056 if (!v->instance_divisor_factor_buffer) {
5057 FREE(v);
5058 return NULL;
5059 }
5060 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5061 NULL, PIPE_TRANSFER_WRITE);
5062 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5063 }
5064 return v;
5065 }
5066
5067 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5068 {
5069 struct si_context *sctx = (struct si_context *)ctx;
5070 struct si_vertex_elements *old = sctx->vertex_elements;
5071 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5072
5073 sctx->vertex_elements = v;
5074 sctx->vertex_buffers_dirty = true;
5075
5076 if (v &&
5077 (!old ||
5078 old->count != v->count ||
5079 old->uses_instance_divisors != v->uses_instance_divisors ||
5080 /* we don't check which divisors changed */
5081 v->uses_instance_divisors ||
5082 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5083 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5084 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5085 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5086 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5087 * functions of fix_fetch and the src_offset alignment.
5088 * If they change and fix_fetch doesn't, it must be due to different
5089 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5090 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5091 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5092 sctx->do_update_shaders = true;
5093
5094 if (v && v->instance_divisor_is_fetched) {
5095 struct pipe_constant_buffer cb;
5096
5097 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5098 cb.user_buffer = NULL;
5099 cb.buffer_offset = 0;
5100 cb.buffer_size = 0xffffffff;
5101 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5102 }
5103 }
5104
5105 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5106 {
5107 struct si_context *sctx = (struct si_context *)ctx;
5108 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5109
5110 if (sctx->vertex_elements == state)
5111 sctx->vertex_elements = NULL;
5112 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5113 FREE(state);
5114 }
5115
5116 static void si_set_vertex_buffers(struct pipe_context *ctx,
5117 unsigned start_slot, unsigned count,
5118 const struct pipe_vertex_buffer *buffers)
5119 {
5120 struct si_context *sctx = (struct si_context *)ctx;
5121 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5122 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5123 uint32_t unaligned = orig_unaligned;
5124 int i;
5125
5126 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5127
5128 if (buffers) {
5129 for (i = 0; i < count; i++) {
5130 const struct pipe_vertex_buffer *src = buffers + i;
5131 struct pipe_vertex_buffer *dsti = dst + i;
5132 struct pipe_resource *buf = src->buffer.resource;
5133
5134 pipe_resource_reference(&dsti->buffer.resource, buf);
5135 dsti->buffer_offset = src->buffer_offset;
5136 dsti->stride = src->stride;
5137 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5138 unaligned |= 1 << (start_slot + i);
5139 else
5140 unaligned &= ~(1 << (start_slot + i));
5141
5142 si_context_add_resource_size(sctx, buf);
5143 if (buf)
5144 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5145 }
5146 } else {
5147 for (i = 0; i < count; i++) {
5148 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5149 }
5150 unaligned &= ~u_bit_consecutive(start_slot, count);
5151 }
5152 sctx->vertex_buffers_dirty = true;
5153 sctx->vertex_buffer_unaligned = unaligned;
5154
5155 /* Check whether alignment may have changed in a way that requires
5156 * shader changes. This check is conservative: a vertex buffer can only
5157 * trigger a shader change if the misalignment amount changes (e.g.
5158 * from byte-aligned to short-aligned), but we only keep track of
5159 * whether buffers are at least dword-aligned, since that should always
5160 * be the case in well-behaved applications anyway.
5161 */
5162 if (sctx->vertex_elements &&
5163 (sctx->vertex_elements->vb_alignment_check_mask &
5164 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5165 sctx->do_update_shaders = true;
5166 }
5167
5168 /*
5169 * Misc
5170 */
5171
5172 static void si_set_tess_state(struct pipe_context *ctx,
5173 const float default_outer_level[4],
5174 const float default_inner_level[2])
5175 {
5176 struct si_context *sctx = (struct si_context *)ctx;
5177 struct pipe_constant_buffer cb;
5178 float array[8];
5179
5180 memcpy(array, default_outer_level, sizeof(float) * 4);
5181 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5182
5183 cb.buffer = NULL;
5184 cb.user_buffer = NULL;
5185 cb.buffer_size = sizeof(array);
5186
5187 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5188 (void*)array, sizeof(array),
5189 &cb.buffer_offset);
5190
5191 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5192 pipe_resource_reference(&cb.buffer, NULL);
5193 }
5194
5195 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5196 {
5197 struct si_context *sctx = (struct si_context *)ctx;
5198
5199 si_update_fb_dirtiness_after_rendering(sctx);
5200
5201 /* Multisample surfaces are flushed in si_decompress_textures. */
5202 if (sctx->framebuffer.uncompressed_cb_mask) {
5203 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5204 sctx->framebuffer.CB_has_shader_readable_metadata,
5205 sctx->framebuffer.all_DCC_pipe_aligned);
5206 }
5207 }
5208
5209 /* This only ensures coherency for shader image/buffer stores. */
5210 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5211 {
5212 struct si_context *sctx = (struct si_context *)ctx;
5213
5214 if (!(flags & ~PIPE_BARRIER_UPDATE))
5215 return;
5216
5217 /* Subsequent commands must wait for all shader invocations to
5218 * complete. */
5219 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5220 SI_CONTEXT_CS_PARTIAL_FLUSH;
5221
5222 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5223 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5224 SI_CONTEXT_INV_VCACHE;
5225
5226 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5227 PIPE_BARRIER_SHADER_BUFFER |
5228 PIPE_BARRIER_TEXTURE |
5229 PIPE_BARRIER_IMAGE |
5230 PIPE_BARRIER_STREAMOUT_BUFFER |
5231 PIPE_BARRIER_GLOBAL_BUFFER)) {
5232 /* As far as I can tell, L1 contents are written back to L2
5233 * automatically at end of shader, but the contents of other
5234 * L1 caches might still be stale. */
5235 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5236 }
5237
5238 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5239 /* Indices are read through TC L2 since GFX8.
5240 * L1 isn't used.
5241 */
5242 if (sctx->screen->info.chip_class <= GFX7)
5243 sctx->flags |= SI_CONTEXT_WB_L2;
5244 }
5245
5246 /* MSAA color, any depth and any stencil are flushed in
5247 * si_decompress_textures when needed.
5248 */
5249 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5250 sctx->framebuffer.uncompressed_cb_mask) {
5251 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5252
5253 if (sctx->chip_class <= GFX8)
5254 sctx->flags |= SI_CONTEXT_WB_L2;
5255 }
5256
5257 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5258 if (sctx->screen->info.chip_class <= GFX8 &&
5259 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5260 sctx->flags |= SI_CONTEXT_WB_L2;
5261 }
5262
5263 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5264 {
5265 struct pipe_blend_state blend;
5266
5267 memset(&blend, 0, sizeof(blend));
5268 blend.independent_blend_enable = true;
5269 blend.rt[0].colormask = 0xf;
5270 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5271 }
5272
5273 static void si_init_config(struct si_context *sctx);
5274
5275 void si_init_state_compute_functions(struct si_context *sctx)
5276 {
5277 sctx->b.create_sampler_state = si_create_sampler_state;
5278 sctx->b.delete_sampler_state = si_delete_sampler_state;
5279 sctx->b.create_sampler_view = si_create_sampler_view;
5280 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5281 sctx->b.memory_barrier = si_memory_barrier;
5282 }
5283
5284 void si_init_state_functions(struct si_context *sctx)
5285 {
5286 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5287 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5288 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5289 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5290 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5291 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5292 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5293 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5294 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5295 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5296 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5297
5298 sctx->b.create_blend_state = si_create_blend_state;
5299 sctx->b.bind_blend_state = si_bind_blend_state;
5300 sctx->b.delete_blend_state = si_delete_blend_state;
5301 sctx->b.set_blend_color = si_set_blend_color;
5302
5303 sctx->b.create_rasterizer_state = si_create_rs_state;
5304 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5305 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5306
5307 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5308 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5309 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5310
5311 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5312 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5313 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5314 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5315 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5316
5317 sctx->b.set_clip_state = si_set_clip_state;
5318 sctx->b.set_stencil_ref = si_set_stencil_ref;
5319
5320 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5321
5322 sctx->b.set_sample_mask = si_set_sample_mask;
5323
5324 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5325 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5326 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5327 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5328
5329 sctx->b.texture_barrier = si_texture_barrier;
5330 sctx->b.set_min_samples = si_set_min_samples;
5331 sctx->b.set_tess_state = si_set_tess_state;
5332
5333 sctx->b.set_active_query_state = si_set_active_query_state;
5334
5335 si_init_config(sctx);
5336 }
5337
5338 void si_init_screen_state_functions(struct si_screen *sscreen)
5339 {
5340 sscreen->b.is_format_supported = si_is_format_supported;
5341
5342 if (sscreen->info.chip_class >= GFX10) {
5343 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5344 } else {
5345 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5346 }
5347 }
5348
5349 static void si_set_grbm_gfx_index(struct si_context *sctx,
5350 struct si_pm4_state *pm4, unsigned value)
5351 {
5352 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5353 R_00802C_GRBM_GFX_INDEX;
5354 si_pm4_set_reg(pm4, reg, value);
5355 }
5356
5357 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5358 struct si_pm4_state *pm4, unsigned se)
5359 {
5360 assert(se == ~0 || se < sctx->screen->info.max_se);
5361 si_set_grbm_gfx_index(sctx, pm4,
5362 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5363 S_030800_SE_INDEX(se)) |
5364 S_030800_SH_BROADCAST_WRITES(1) |
5365 S_030800_INSTANCE_BROADCAST_WRITES(1));
5366 }
5367
5368 static void
5369 si_write_harvested_raster_configs(struct si_context *sctx,
5370 struct si_pm4_state *pm4,
5371 unsigned raster_config,
5372 unsigned raster_config_1)
5373 {
5374 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5375 unsigned raster_config_se[4];
5376 unsigned se;
5377
5378 ac_get_harvested_configs(&sctx->screen->info,
5379 raster_config,
5380 &raster_config_1,
5381 raster_config_se);
5382
5383 for (se = 0; se < num_se; se++) {
5384 si_set_grbm_gfx_index_se(sctx, pm4, se);
5385 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5386 }
5387 si_set_grbm_gfx_index(sctx, pm4, ~0);
5388
5389 if (sctx->chip_class >= GFX7) {
5390 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5391 }
5392 }
5393
5394 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5395 {
5396 struct si_screen *sscreen = sctx->screen;
5397 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5398 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5399 unsigned raster_config = sscreen->pa_sc_raster_config;
5400 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5401
5402 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5403 /* Always use the default config when all backends are enabled
5404 * (or when we failed to determine the enabled backends).
5405 */
5406 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5407 raster_config);
5408 if (sctx->chip_class >= GFX7)
5409 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5410 raster_config_1);
5411 } else {
5412 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5413 }
5414 }
5415
5416 static void si_init_config(struct si_context *sctx)
5417 {
5418 struct si_screen *sscreen = sctx->screen;
5419 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5420 bool has_clear_state = sscreen->info.has_clear_state;
5421 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5422
5423 if (!pm4)
5424 return;
5425
5426 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5427 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5428 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5429 si_pm4_cmd_end(pm4, false);
5430
5431 if (has_clear_state) {
5432 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5433 si_pm4_cmd_add(pm4, 0);
5434 si_pm4_cmd_end(pm4, false);
5435 }
5436
5437 if (sctx->chip_class <= GFX8)
5438 si_set_raster_config(sctx, pm4);
5439
5440 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5441 if (!has_clear_state)
5442 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5443
5444 /* FIXME calculate these values somehow ??? */
5445 if (sctx->chip_class <= GFX8) {
5446 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5447 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5448 }
5449
5450 if (!has_clear_state) {
5451 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5452 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5453 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5454 }
5455
5456 if (sscreen->info.chip_class <= GFX9)
5457 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5458 if (!has_clear_state)
5459 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5460 if (sctx->chip_class < GFX7)
5461 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5462 S_008A14_CLIP_VTX_REORDER_ENA(1));
5463
5464 /* CLEAR_STATE doesn't restore these correctly. */
5465 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5466 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5467 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5468
5469 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5470 * I don't know why. Deduced by trial and error.
5471 */
5472 if (sctx->chip_class <= GFX7 || !has_clear_state) {
5473 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5474 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5475 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5476 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5477 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5478 }
5479
5480 if (!has_clear_state) {
5481 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5482 S_028230_ER_TRI(0xA) |
5483 S_028230_ER_POINT(0xA) |
5484 S_028230_ER_RECT(0xA) |
5485 /* Required by DX10_DIAMOND_TEST_ENA: */
5486 S_028230_ER_LINE_LR(0x1A) |
5487 S_028230_ER_LINE_RL(0x26) |
5488 S_028230_ER_LINE_TB(0xA) |
5489 S_028230_ER_LINE_BT(0xA));
5490 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5491 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5492 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5493 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5494 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5495 }
5496
5497 if (sctx->chip_class >= GFX10) {
5498 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5499 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5500 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5501 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5502 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5503 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5504 } else if (sctx->chip_class == GFX9) {
5505 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5506 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5507 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5508 } else {
5509 /* These registers, when written, also overwrite the CLEAR_STATE
5510 * context, so we can't rely on CLEAR_STATE setting them.
5511 * It would be an issue if there was another UMD changing them.
5512 */
5513 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5514 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5515 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5516 }
5517
5518 if (sctx->chip_class >= GFX7) {
5519 if (sctx->chip_class >= GFX10) {
5520 /* Logical CUs 16 - 31 */
5521 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5522 S_00B404_CU_EN(0xffff));
5523 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5524 S_00B104_CU_EN(0xffff));
5525 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5526 S_00B004_CU_EN(0xffff));
5527 }
5528
5529 if (sctx->chip_class >= GFX9) {
5530 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5531 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5532 } else {
5533 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5534 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5535 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5536 S_00B41C_WAVE_LIMIT(0x3F));
5537 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5538 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5539
5540 /* If this is 0, Bonaire can hang even if GS isn't being used.
5541 * Other chips are unaffected. These are suboptimal values,
5542 * but we don't use on-chip GS.
5543 */
5544 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5545 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5546 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5547 }
5548
5549 /* Compute LATE_ALLOC_VS.LIMIT. */
5550 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5551 unsigned late_alloc_limit; /* The limit is per SH. */
5552
5553 if (sctx->family == CHIP_KABINI) {
5554 late_alloc_limit = 0; /* Potential hang on Kabini. */
5555 } else if (num_cu_per_sh <= 4) {
5556 /* Too few available compute units per SH. Disallowing
5557 * VS to run on one CU could hurt us more than late VS
5558 * allocation would help.
5559 *
5560 * 2 is the highest safe number that allows us to keep
5561 * all CUs enabled.
5562 */
5563 late_alloc_limit = 2;
5564 } else {
5565 /* This is a good initial value, allowing 1 late_alloc
5566 * wave per SIMD on num_cu - 2.
5567 */
5568 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5569 }
5570
5571 unsigned late_alloc_limit_gs = late_alloc_limit;
5572 unsigned cu_mask_vs = 0xffff;
5573 unsigned cu_mask_gs = 0xffff;
5574
5575 if (late_alloc_limit > 2) {
5576 if (sctx->chip_class >= GFX10) {
5577 /* CU2 & CU3 disabled because of the dual CU design */
5578 cu_mask_vs = 0xfff3;
5579 cu_mask_gs = 0xfff3; /* NGG only */
5580 } else {
5581 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5582 }
5583 }
5584
5585 /* Don't use late alloc for NGG on Navi14 due to a hw bug.
5586 * If NGG is never used, enable all CUs.
5587 */
5588 if (!sscreen->use_ngg || sctx->family == CHIP_NAVI14) {
5589 late_alloc_limit_gs = 0;
5590 cu_mask_gs = 0xffff;
5591 }
5592
5593 /* VS can't execute on one CU if the limit is > 2. */
5594 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5595 S_00B118_CU_EN(cu_mask_vs) |
5596 S_00B118_WAVE_LIMIT(0x3F));
5597 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5598 S_00B11C_LIMIT(late_alloc_limit));
5599
5600 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5601 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5602
5603 if (sctx->chip_class >= GFX10) {
5604 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5605 S_00B204_CU_EN(0xffff) |
5606 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
5607 }
5608
5609 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5610 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5611 }
5612
5613 if (sctx->chip_class >= GFX10) {
5614 /* Break up a pixel wave if it contains deallocs for more than
5615 * half the parameter cache.
5616 *
5617 * To avoid a deadlock where pixel waves aren't launched
5618 * because they're waiting for more pixels while the frontend
5619 * is stuck waiting for PC space, the maximum allowed value is
5620 * the size of the PC minus the largest possible allocation for
5621 * a single primitive shader subgroup.
5622 */
5623 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5624 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5625 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5626
5627 if (!has_clear_state) {
5628 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5629 sscreen->info.pa_sc_tile_steering_override);
5630 }
5631
5632 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5633 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5634 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5635 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5636 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5637 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5638 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5639 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
5640
5641 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5642 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5643 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5644 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5645 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5646 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5647 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5648 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
5649 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5650 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5651
5652 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5653 S_00B0C0_SOFT_GROUPING_EN(1) |
5654 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5655 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5656
5657 if (sctx->family == CHIP_NAVI10 ||
5658 sctx->family == CHIP_NAVI12 ||
5659 sctx->family == CHIP_NAVI14) {
5660 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
5661 si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
5662 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
5663 si_pm4_cmd_end(pm4, false);
5664 }
5665 /* TODO: For culling, replace 128 with 256. */
5666 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
5667 S_030980_OVERSUB_EN(1) |
5668 S_030980_NUM_PC_LINES(128 * sscreen->info.max_se - 1));
5669 }
5670
5671 if (sctx->chip_class >= GFX8) {
5672 unsigned vgt_tess_distribution;
5673
5674 vgt_tess_distribution =
5675 S_028B50_ACCUM_ISOLINE(32) |
5676 S_028B50_ACCUM_TRI(11) |
5677 S_028B50_ACCUM_QUAD(11) |
5678 S_028B50_DONUT_SPLIT(16);
5679
5680 /* Testing with Unigine Heaven extreme tesselation yielded best results
5681 * with TRAP_SPLIT = 3.
5682 */
5683 if (sctx->family == CHIP_FIJI ||
5684 sctx->family >= CHIP_POLARIS10)
5685 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5686
5687 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5688 } else if (!has_clear_state) {
5689 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5690 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5691 }
5692
5693 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5694 if (sctx->chip_class >= GFX7) {
5695 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5696 S_028084_ADDRESS(border_color_va >> 40));
5697 }
5698 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5699 RADEON_PRIO_BORDER_COLORS);
5700
5701 if (sctx->chip_class >= GFX9) {
5702 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5703 S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
5704 S_028C48_MAX_PRIM_PER_BATCH(1023));
5705 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5706 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5707 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5708 }
5709
5710 si_pm4_upload_indirect_buffer(sctx, pm4);
5711 sctx->init_config = pm4;
5712 }