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radeonsi: move invariant regs to si_init_config
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "radeonsi_pipe.h"
38 #include "radeonsi_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(uint32_t nbanks)
44 {
45 switch (nbanks) {
46 case 2:
47 return V_02803C_ADDR_SURF_2_BANK;
48 case 4:
49 return V_02803C_ADDR_SURF_4_BANK;
50 case 8:
51 default:
52 return V_02803C_ADDR_SURF_8_BANK;
53 case 16:
54 return V_02803C_ADDR_SURF_16_BANK;
55 }
56 }
57
58
59 static unsigned cik_tile_split(unsigned tile_split)
60 {
61 switch (tile_split) {
62 case 64:
63 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
64 break;
65 case 128:
66 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
67 break;
68 case 256:
69 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
70 break;
71 case 512:
72 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
73 break;
74 default:
75 case 1024:
76 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
77 break;
78 case 2048:
79 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
80 break;
81 case 4096:
82 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
83 break;
84 }
85 return tile_split;
86 }
87
88 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
89 {
90 switch (macro_tile_aspect) {
91 default:
92 case 1:
93 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
94 break;
95 case 2:
96 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
97 break;
98 case 4:
99 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
100 break;
101 case 8:
102 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
103 break;
104 }
105 return macro_tile_aspect;
106 }
107
108 static unsigned cik_bank_wh(unsigned bankwh)
109 {
110 switch (bankwh) {
111 default:
112 case 1:
113 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
114 break;
115 case 2:
116 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
117 break;
118 case 4:
119 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
120 break;
121 case 8:
122 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
123 break;
124 }
125 return bankwh;
126 }
127
128 static unsigned cik_db_pipe_config(unsigned tile_pipes,
129 unsigned num_rbs)
130 {
131 unsigned pipe_config;
132
133 switch (tile_pipes) {
134 case 8:
135 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
136 break;
137 case 4:
138 default:
139 if (num_rbs == 4)
140 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
141 else
142 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
143 break;
144 case 2:
145 pipe_config = V_02803C_ADDR_SURF_P2;
146 break;
147 }
148 return pipe_config;
149 }
150
151 /*
152 * inferred framebuffer and blender state
153 */
154 static void si_update_fb_blend_state(struct r600_context *rctx)
155 {
156 struct si_pm4_state *pm4;
157 struct si_state_blend *blend = rctx->queued.named.blend;
158 uint32_t mask;
159
160 if (blend == NULL)
161 return;
162
163 pm4 = si_pm4_alloc_state(rctx);
164 if (pm4 == NULL)
165 return;
166
167 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
168 mask &= blend->cb_target_mask;
169 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
170
171 si_pm4_set_state(rctx, fb_blend, pm4);
172 }
173
174 /*
175 * Blender functions
176 */
177
178 static uint32_t si_translate_blend_function(int blend_func)
179 {
180 switch (blend_func) {
181 case PIPE_BLEND_ADD:
182 return V_028780_COMB_DST_PLUS_SRC;
183 case PIPE_BLEND_SUBTRACT:
184 return V_028780_COMB_SRC_MINUS_DST;
185 case PIPE_BLEND_REVERSE_SUBTRACT:
186 return V_028780_COMB_DST_MINUS_SRC;
187 case PIPE_BLEND_MIN:
188 return V_028780_COMB_MIN_DST_SRC;
189 case PIPE_BLEND_MAX:
190 return V_028780_COMB_MAX_DST_SRC;
191 default:
192 R600_ERR("Unknown blend function %d\n", blend_func);
193 assert(0);
194 break;
195 }
196 return 0;
197 }
198
199 static uint32_t si_translate_blend_factor(int blend_fact)
200 {
201 switch (blend_fact) {
202 case PIPE_BLENDFACTOR_ONE:
203 return V_028780_BLEND_ONE;
204 case PIPE_BLENDFACTOR_SRC_COLOR:
205 return V_028780_BLEND_SRC_COLOR;
206 case PIPE_BLENDFACTOR_SRC_ALPHA:
207 return V_028780_BLEND_SRC_ALPHA;
208 case PIPE_BLENDFACTOR_DST_ALPHA:
209 return V_028780_BLEND_DST_ALPHA;
210 case PIPE_BLENDFACTOR_DST_COLOR:
211 return V_028780_BLEND_DST_COLOR;
212 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
213 return V_028780_BLEND_SRC_ALPHA_SATURATE;
214 case PIPE_BLENDFACTOR_CONST_COLOR:
215 return V_028780_BLEND_CONSTANT_COLOR;
216 case PIPE_BLENDFACTOR_CONST_ALPHA:
217 return V_028780_BLEND_CONSTANT_ALPHA;
218 case PIPE_BLENDFACTOR_ZERO:
219 return V_028780_BLEND_ZERO;
220 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
221 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
222 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
223 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
224 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
225 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
226 case PIPE_BLENDFACTOR_INV_DST_COLOR:
227 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
228 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
229 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
230 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
231 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
232 case PIPE_BLENDFACTOR_SRC1_COLOR:
233 return V_028780_BLEND_SRC1_COLOR;
234 case PIPE_BLENDFACTOR_SRC1_ALPHA:
235 return V_028780_BLEND_SRC1_ALPHA;
236 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
237 return V_028780_BLEND_INV_SRC1_COLOR;
238 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
239 return V_028780_BLEND_INV_SRC1_ALPHA;
240 default:
241 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
242 assert(0);
243 break;
244 }
245 return 0;
246 }
247
248 static void *si_create_blend_state_mode(struct pipe_context *ctx,
249 const struct pipe_blend_state *state,
250 unsigned mode)
251 {
252 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
253 struct si_pm4_state *pm4 = &blend->pm4;
254
255 uint32_t color_control;
256
257 if (blend == NULL)
258 return NULL;
259
260 blend->alpha_to_one = state->alpha_to_one;
261
262 color_control = S_028808_MODE(mode);
263 if (state->logicop_enable) {
264 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
265 } else {
266 color_control |= S_028808_ROP3(0xcc);
267 }
268 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
269
270 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
271 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
272 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
275 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
276
277 blend->cb_target_mask = 0;
278 for (int i = 0; i < 8; i++) {
279 /* state->rt entries > 0 only written if independent blending */
280 const int j = state->independent_blend_enable ? i : 0;
281
282 unsigned eqRGB = state->rt[j].rgb_func;
283 unsigned srcRGB = state->rt[j].rgb_src_factor;
284 unsigned dstRGB = state->rt[j].rgb_dst_factor;
285 unsigned eqA = state->rt[j].alpha_func;
286 unsigned srcA = state->rt[j].alpha_src_factor;
287 unsigned dstA = state->rt[j].alpha_dst_factor;
288
289 unsigned blend_cntl = 0;
290
291 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
292 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
293
294 if (!state->rt[j].blend_enable) {
295 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
296 continue;
297 }
298
299 blend_cntl |= S_028780_ENABLE(1);
300 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
301 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
302 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
303
304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
305 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
306 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
307 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
308 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
309 }
310 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
311 }
312
313 return blend;
314 }
315
316 static void *si_create_blend_state(struct pipe_context *ctx,
317 const struct pipe_blend_state *state)
318 {
319 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
320 }
321
322 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
323 {
324 struct r600_context *rctx = (struct r600_context *)ctx;
325 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
326 si_update_fb_blend_state(rctx);
327 }
328
329 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
330 {
331 struct r600_context *rctx = (struct r600_context *)ctx;
332 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
333 }
334
335 static void si_set_blend_color(struct pipe_context *ctx,
336 const struct pipe_blend_color *state)
337 {
338 struct r600_context *rctx = (struct r600_context *)ctx;
339 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
340
341 if (pm4 == NULL)
342 return;
343
344 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
345 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
346 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
347 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
348
349 si_pm4_set_state(rctx, blend_color, pm4);
350 }
351
352 /*
353 * Clipping, scissors and viewport
354 */
355
356 static void si_set_clip_state(struct pipe_context *ctx,
357 const struct pipe_clip_state *state)
358 {
359 struct r600_context *rctx = (struct r600_context *)ctx;
360 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
361 struct pipe_constant_buffer cb;
362
363 if (pm4 == NULL)
364 return;
365
366 for (int i = 0; i < 6; i++) {
367 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
368 fui(state->ucp[i][0]));
369 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
370 fui(state->ucp[i][1]));
371 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
372 fui(state->ucp[i][2]));
373 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
374 fui(state->ucp[i][3]));
375 }
376
377 cb.buffer = NULL;
378 cb.user_buffer = state->ucp;
379 cb.buffer_offset = 0;
380 cb.buffer_size = 4*4*8;
381 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
382 pipe_resource_reference(&cb.buffer, NULL);
383
384 si_pm4_set_state(rctx, clip, pm4);
385 }
386
387 static void si_set_scissor_states(struct pipe_context *ctx,
388 unsigned start_slot,
389 unsigned num_scissors,
390 const struct pipe_scissor_state *state)
391 {
392 struct r600_context *rctx = (struct r600_context *)ctx;
393 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
394 uint32_t tl, br;
395
396 if (pm4 == NULL)
397 return;
398
399 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
400 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
401 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
402 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
403 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
404 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
405 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
406 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
407 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
408 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
409
410 si_pm4_set_state(rctx, scissor, pm4);
411 }
412
413 static void si_set_viewport_states(struct pipe_context *ctx,
414 unsigned start_slot,
415 unsigned num_viewports,
416 const struct pipe_viewport_state *state)
417 {
418 struct r600_context *rctx = (struct r600_context *)ctx;
419 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
420 struct si_pm4_state *pm4 = &viewport->pm4;
421
422 if (viewport == NULL)
423 return;
424
425 viewport->viewport = *state;
426 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
427 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
428 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
429 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
430 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
431 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
432
433 si_pm4_set_state(rctx, viewport, viewport);
434 }
435
436 /*
437 * inferred state between framebuffer and rasterizer
438 */
439 static void si_update_fb_rs_state(struct r600_context *rctx)
440 {
441 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
442 struct si_pm4_state *pm4;
443 unsigned offset_db_fmt_cntl = 0, depth;
444 float offset_units;
445
446 if (!rs || !rctx->framebuffer.zsbuf)
447 return;
448
449 offset_units = rctx->queued.named.rasterizer->offset_units;
450 switch (rctx->framebuffer.zsbuf->texture->format) {
451 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
452 case PIPE_FORMAT_X8Z24_UNORM:
453 case PIPE_FORMAT_Z24X8_UNORM:
454 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
455 depth = -24;
456 offset_units *= 2.0f;
457 break;
458 case PIPE_FORMAT_Z32_FLOAT:
459 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
460 depth = -23;
461 offset_units *= 1.0f;
462 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
463 break;
464 case PIPE_FORMAT_Z16_UNORM:
465 depth = -16;
466 offset_units *= 4.0f;
467 break;
468 default:
469 return;
470 }
471
472 pm4 = si_pm4_alloc_state(rctx);
473
474 if (pm4 == NULL)
475 return;
476
477 /* FIXME some of those reg can be computed with cso */
478 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
479 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
480 fui(rctx->queued.named.rasterizer->offset_scale));
481 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
482 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
483 fui(rctx->queued.named.rasterizer->offset_scale));
484 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
485 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
486
487 si_pm4_set_state(rctx, fb_rs, pm4);
488 }
489
490 /*
491 * Rasterizer
492 */
493
494 static uint32_t si_translate_fill(uint32_t func)
495 {
496 switch(func) {
497 case PIPE_POLYGON_MODE_FILL:
498 return V_028814_X_DRAW_TRIANGLES;
499 case PIPE_POLYGON_MODE_LINE:
500 return V_028814_X_DRAW_LINES;
501 case PIPE_POLYGON_MODE_POINT:
502 return V_028814_X_DRAW_POINTS;
503 default:
504 assert(0);
505 return V_028814_X_DRAW_POINTS;
506 }
507 }
508
509 static void *si_create_rs_state(struct pipe_context *ctx,
510 const struct pipe_rasterizer_state *state)
511 {
512 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
513 struct si_pm4_state *pm4 = &rs->pm4;
514 unsigned tmp;
515 unsigned prov_vtx = 1, polygon_dual_mode;
516 unsigned clip_rule;
517 float psize_min, psize_max;
518
519 if (rs == NULL) {
520 return NULL;
521 }
522
523 rs->two_side = state->light_twoside;
524 rs->multisample_enable = state->multisample;
525 rs->clip_plane_enable = state->clip_plane_enable;
526 rs->line_stipple_enable = state->line_stipple_enable;
527
528 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
529 state->fill_back != PIPE_POLYGON_MODE_FILL);
530
531 if (state->flatshade_first)
532 prov_vtx = 0;
533
534 rs->flatshade = state->flatshade;
535 rs->sprite_coord_enable = state->sprite_coord_enable;
536 rs->pa_sc_line_stipple = state->line_stipple_enable ?
537 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
538 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
539 rs->pa_su_sc_mode_cntl =
540 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
541 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
542 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
547 S_028814_POLY_MODE(polygon_dual_mode) |
548 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
549 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
550 rs->pa_cl_clip_cntl =
551 S_028810_PS_UCP_MODE(3) |
552 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
553 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
554 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
555 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
556
557 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
558
559 /* offset */
560 rs->offset_units = state->offset_units;
561 rs->offset_scale = state->offset_scale * 12.0f;
562
563 tmp = S_0286D4_FLAT_SHADE_ENA(1);
564 if (state->sprite_coord_enable) {
565 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
566 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
567 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
568 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
569 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
570 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
571 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
572 }
573 }
574 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
575
576 /* point size 12.4 fixed point */
577 tmp = (unsigned)(state->point_size * 8.0);
578 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
579
580 if (state->point_size_per_vertex) {
581 psize_min = util_get_min_point_size(state);
582 psize_max = 8192;
583 } else {
584 /* Force the point size to be as if the vertex output was disabled. */
585 psize_min = state->point_size;
586 psize_max = state->point_size;
587 }
588 /* Divide by two, because 0.5 = 1 pixel. */
589 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
590 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
591 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
592
593 tmp = (unsigned)state->line_width * 8;
594 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
595 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
596 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
597 S_028A48_MSAA_ENABLE(state->multisample));
598
599 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
600 S_028BE4_PIX_CENTER(state->half_pixel_center) |
601 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
602
603 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
604 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
605
606 return rs;
607 }
608
609 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
610 {
611 struct r600_context *rctx = (struct r600_context *)ctx;
612 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
613
614 if (state == NULL)
615 return;
616
617 // TODO
618 rctx->sprite_coord_enable = rs->sprite_coord_enable;
619 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
620 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
621
622 si_pm4_bind_state(rctx, rasterizer, rs);
623 si_update_fb_rs_state(rctx);
624 }
625
626 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
627 {
628 struct r600_context *rctx = (struct r600_context *)ctx;
629 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
630 }
631
632 /*
633 * infeered state between dsa and stencil ref
634 */
635 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
636 {
637 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
638 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
639 struct si_state_dsa *dsa = rctx->queued.named.dsa;
640
641 if (pm4 == NULL)
642 return;
643
644 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
645 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
646 S_028430_STENCILMASK(dsa->valuemask[0]) |
647 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
648 S_028430_STENCILOPVAL(1));
649 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
650 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
651 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
652 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
653 S_028434_STENCILOPVAL_BF(1));
654
655 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
656 }
657
658 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
659 const struct pipe_stencil_ref *state)
660 {
661 struct r600_context *rctx = (struct r600_context *)ctx;
662 rctx->stencil_ref = *state;
663 si_update_dsa_stencil_ref(rctx);
664 }
665
666
667 /*
668 * DSA
669 */
670
671 static uint32_t si_translate_stencil_op(int s_op)
672 {
673 switch (s_op) {
674 case PIPE_STENCIL_OP_KEEP:
675 return V_02842C_STENCIL_KEEP;
676 case PIPE_STENCIL_OP_ZERO:
677 return V_02842C_STENCIL_ZERO;
678 case PIPE_STENCIL_OP_REPLACE:
679 return V_02842C_STENCIL_REPLACE_TEST;
680 case PIPE_STENCIL_OP_INCR:
681 return V_02842C_STENCIL_ADD_CLAMP;
682 case PIPE_STENCIL_OP_DECR:
683 return V_02842C_STENCIL_SUB_CLAMP;
684 case PIPE_STENCIL_OP_INCR_WRAP:
685 return V_02842C_STENCIL_ADD_WRAP;
686 case PIPE_STENCIL_OP_DECR_WRAP:
687 return V_02842C_STENCIL_SUB_WRAP;
688 case PIPE_STENCIL_OP_INVERT:
689 return V_02842C_STENCIL_INVERT;
690 default:
691 R600_ERR("Unknown stencil op %d", s_op);
692 assert(0);
693 break;
694 }
695 return 0;
696 }
697
698 static void *si_create_dsa_state(struct pipe_context *ctx,
699 const struct pipe_depth_stencil_alpha_state *state)
700 {
701 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
702 struct si_pm4_state *pm4 = &dsa->pm4;
703 unsigned db_depth_control;
704 unsigned db_render_control;
705 uint32_t db_stencil_control = 0;
706
707 if (dsa == NULL) {
708 return NULL;
709 }
710
711 dsa->valuemask[0] = state->stencil[0].valuemask;
712 dsa->valuemask[1] = state->stencil[1].valuemask;
713 dsa->writemask[0] = state->stencil[0].writemask;
714 dsa->writemask[1] = state->stencil[1].writemask;
715
716 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
717 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
718 S_028800_ZFUNC(state->depth.func);
719
720 /* stencil */
721 if (state->stencil[0].enabled) {
722 db_depth_control |= S_028800_STENCIL_ENABLE(1);
723 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
724 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
725 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
726 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
727
728 if (state->stencil[1].enabled) {
729 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
730 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
731 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
732 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
733 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
734 }
735 }
736
737 /* alpha */
738 if (state->alpha.enabled) {
739 dsa->alpha_func = state->alpha.func;
740 dsa->alpha_ref = state->alpha.ref_value;
741
742 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
743 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
744 } else {
745 dsa->alpha_func = PIPE_FUNC_ALWAYS;
746 }
747
748 /* misc */
749 db_render_control = 0;
750 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
751 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
752 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
753
754 return dsa;
755 }
756
757 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
758 {
759 struct r600_context *rctx = (struct r600_context *)ctx;
760 struct si_state_dsa *dsa = state;
761
762 if (state == NULL)
763 return;
764
765 si_pm4_bind_state(rctx, dsa, dsa);
766 si_update_dsa_stencil_ref(rctx);
767 }
768
769 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
770 {
771 struct r600_context *rctx = (struct r600_context *)ctx;
772 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
773 }
774
775 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
776 bool copy_stencil, int sample)
777 {
778 struct pipe_depth_stencil_alpha_state dsa;
779 struct si_state_dsa *state;
780
781 memset(&dsa, 0, sizeof(dsa));
782
783 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
784 if (copy_depth || copy_stencil) {
785 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
786 S_028000_DEPTH_COPY(copy_depth) |
787 S_028000_STENCIL_COPY(copy_stencil) |
788 S_028000_COPY_CENTROID(1) |
789 S_028000_COPY_SAMPLE(sample));
790 } else {
791 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
792 S_028000_DEPTH_COMPRESS_DISABLE(1) |
793 S_028000_STENCIL_COMPRESS_DISABLE(1));
794 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
795 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
796 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
797 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
798 S_02800C_DISABLE_TILE_RATE_TILES(1));
799 }
800
801 return state;
802 }
803
804 /*
805 * format translation
806 */
807 static uint32_t si_translate_colorformat(enum pipe_format format)
808 {
809 const struct util_format_description *desc = util_format_description(format);
810
811 #define HAS_SIZE(x,y,z,w) \
812 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
813 desc->channel[2].size == (z) && desc->channel[3].size == (w))
814
815 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
816 return V_028C70_COLOR_10_11_11;
817
818 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
819 return V_028C70_COLOR_INVALID;
820
821 switch (desc->nr_channels) {
822 case 1:
823 switch (desc->channel[0].size) {
824 case 8:
825 return V_028C70_COLOR_8;
826 case 16:
827 return V_028C70_COLOR_16;
828 case 32:
829 return V_028C70_COLOR_32;
830 }
831 break;
832 case 2:
833 if (desc->channel[0].size == desc->channel[1].size) {
834 switch (desc->channel[0].size) {
835 case 8:
836 return V_028C70_COLOR_8_8;
837 case 16:
838 return V_028C70_COLOR_16_16;
839 case 32:
840 return V_028C70_COLOR_32_32;
841 }
842 } else if (HAS_SIZE(8,24,0,0)) {
843 return V_028C70_COLOR_24_8;
844 } else if (HAS_SIZE(24,8,0,0)) {
845 return V_028C70_COLOR_8_24;
846 }
847 break;
848 case 3:
849 if (HAS_SIZE(5,6,5,0)) {
850 return V_028C70_COLOR_5_6_5;
851 } else if (HAS_SIZE(32,8,24,0)) {
852 return V_028C70_COLOR_X24_8_32_FLOAT;
853 }
854 break;
855 case 4:
856 if (desc->channel[0].size == desc->channel[1].size &&
857 desc->channel[0].size == desc->channel[2].size &&
858 desc->channel[0].size == desc->channel[3].size) {
859 switch (desc->channel[0].size) {
860 case 4:
861 return V_028C70_COLOR_4_4_4_4;
862 case 8:
863 return V_028C70_COLOR_8_8_8_8;
864 case 16:
865 return V_028C70_COLOR_16_16_16_16;
866 case 32:
867 return V_028C70_COLOR_32_32_32_32;
868 }
869 } else if (HAS_SIZE(5,5,5,1)) {
870 return V_028C70_COLOR_1_5_5_5;
871 } else if (HAS_SIZE(10,10,10,2)) {
872 return V_028C70_COLOR_2_10_10_10;
873 }
874 break;
875 }
876 return V_028C70_COLOR_INVALID;
877 }
878
879 static uint32_t si_translate_colorswap(enum pipe_format format)
880 {
881 const struct util_format_description *desc = util_format_description(format);
882
883 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
884
885 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
886 return V_028C70_SWAP_STD;
887
888 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
889 return ~0;
890
891 switch (desc->nr_channels) {
892 case 1:
893 if (HAS_SWIZZLE(0,X))
894 return V_028C70_SWAP_STD; /* X___ */
895 else if (HAS_SWIZZLE(3,X))
896 return V_028C70_SWAP_ALT_REV; /* ___X */
897 break;
898 case 2:
899 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
900 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
901 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
902 return V_028C70_SWAP_STD; /* XY__ */
903 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
904 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
905 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
906 return V_028C70_SWAP_STD_REV; /* YX__ */
907 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
908 return V_028C70_SWAP_ALT; /* X__Y */
909 break;
910 case 3:
911 if (HAS_SWIZZLE(0,X))
912 return V_028C70_SWAP_STD; /* XYZ */
913 else if (HAS_SWIZZLE(0,Z))
914 return V_028C70_SWAP_STD_REV; /* ZYX */
915 break;
916 case 4:
917 /* check the middle channels, the 1st and 4th channel can be NONE */
918 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
919 return V_028C70_SWAP_STD; /* XYZW */
920 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
921 return V_028C70_SWAP_STD_REV; /* WZYX */
922 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
923 return V_028C70_SWAP_ALT; /* ZYXW */
924 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
925 return V_028C70_SWAP_ALT_REV; /* WXYZ */
926 break;
927 }
928 return ~0U;
929 }
930
931 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
932 {
933 if (R600_BIG_ENDIAN) {
934 switch(colorformat) {
935 /* 8-bit buffers. */
936 case V_028C70_COLOR_8:
937 return V_028C70_ENDIAN_NONE;
938
939 /* 16-bit buffers. */
940 case V_028C70_COLOR_5_6_5:
941 case V_028C70_COLOR_1_5_5_5:
942 case V_028C70_COLOR_4_4_4_4:
943 case V_028C70_COLOR_16:
944 case V_028C70_COLOR_8_8:
945 return V_028C70_ENDIAN_8IN16;
946
947 /* 32-bit buffers. */
948 case V_028C70_COLOR_8_8_8_8:
949 case V_028C70_COLOR_2_10_10_10:
950 case V_028C70_COLOR_8_24:
951 case V_028C70_COLOR_24_8:
952 case V_028C70_COLOR_16_16:
953 return V_028C70_ENDIAN_8IN32;
954
955 /* 64-bit buffers. */
956 case V_028C70_COLOR_16_16_16_16:
957 return V_028C70_ENDIAN_8IN16;
958
959 case V_028C70_COLOR_32_32:
960 return V_028C70_ENDIAN_8IN32;
961
962 /* 128-bit buffers. */
963 case V_028C70_COLOR_32_32_32_32:
964 return V_028C70_ENDIAN_8IN32;
965 default:
966 return V_028C70_ENDIAN_NONE; /* Unsupported. */
967 }
968 } else {
969 return V_028C70_ENDIAN_NONE;
970 }
971 }
972
973 /* Returns the size in bits of the widest component of a CB format */
974 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
975 {
976 switch(colorformat) {
977 case V_028C70_COLOR_4_4_4_4:
978 return 4;
979
980 case V_028C70_COLOR_1_5_5_5:
981 case V_028C70_COLOR_5_5_5_1:
982 return 5;
983
984 case V_028C70_COLOR_5_6_5:
985 return 6;
986
987 case V_028C70_COLOR_8:
988 case V_028C70_COLOR_8_8:
989 case V_028C70_COLOR_8_8_8_8:
990 return 8;
991
992 case V_028C70_COLOR_10_10_10_2:
993 case V_028C70_COLOR_2_10_10_10:
994 return 10;
995
996 case V_028C70_COLOR_10_11_11:
997 case V_028C70_COLOR_11_11_10:
998 return 11;
999
1000 case V_028C70_COLOR_16:
1001 case V_028C70_COLOR_16_16:
1002 case V_028C70_COLOR_16_16_16_16:
1003 return 16;
1004
1005 case V_028C70_COLOR_8_24:
1006 case V_028C70_COLOR_24_8:
1007 return 24;
1008
1009 case V_028C70_COLOR_32:
1010 case V_028C70_COLOR_32_32:
1011 case V_028C70_COLOR_32_32_32_32:
1012 case V_028C70_COLOR_X24_8_32_FLOAT:
1013 return 32;
1014 }
1015
1016 assert(!"Unknown maximum component size");
1017 return 0;
1018 }
1019
1020 static uint32_t si_translate_dbformat(enum pipe_format format)
1021 {
1022 switch (format) {
1023 case PIPE_FORMAT_Z16_UNORM:
1024 return V_028040_Z_16;
1025 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1026 case PIPE_FORMAT_X8Z24_UNORM:
1027 case PIPE_FORMAT_Z24X8_UNORM:
1028 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1029 return V_028040_Z_24; /* deprecated on SI */
1030 case PIPE_FORMAT_Z32_FLOAT:
1031 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1032 return V_028040_Z_32_FLOAT;
1033 default:
1034 return V_028040_Z_INVALID;
1035 }
1036 }
1037
1038 /*
1039 * Texture translation
1040 */
1041
1042 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1043 enum pipe_format format,
1044 const struct util_format_description *desc,
1045 int first_non_void)
1046 {
1047 struct r600_screen *rscreen = (struct r600_screen*)screen;
1048 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1049 boolean uniform = TRUE;
1050 int i;
1051
1052 /* Colorspace (return non-RGB formats directly). */
1053 switch (desc->colorspace) {
1054 /* Depth stencil formats */
1055 case UTIL_FORMAT_COLORSPACE_ZS:
1056 switch (format) {
1057 case PIPE_FORMAT_Z16_UNORM:
1058 return V_008F14_IMG_DATA_FORMAT_16;
1059 case PIPE_FORMAT_X24S8_UINT:
1060 case PIPE_FORMAT_Z24X8_UNORM:
1061 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1062 return V_008F14_IMG_DATA_FORMAT_8_24;
1063 case PIPE_FORMAT_X8Z24_UNORM:
1064 case PIPE_FORMAT_S8X24_UINT:
1065 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1066 return V_008F14_IMG_DATA_FORMAT_24_8;
1067 case PIPE_FORMAT_S8_UINT:
1068 return V_008F14_IMG_DATA_FORMAT_8;
1069 case PIPE_FORMAT_Z32_FLOAT:
1070 return V_008F14_IMG_DATA_FORMAT_32;
1071 case PIPE_FORMAT_X32_S8X24_UINT:
1072 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1073 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1074 default:
1075 goto out_unknown;
1076 }
1077
1078 case UTIL_FORMAT_COLORSPACE_YUV:
1079 goto out_unknown; /* TODO */
1080
1081 case UTIL_FORMAT_COLORSPACE_SRGB:
1082 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1083 goto out_unknown;
1084 break;
1085
1086 default:
1087 break;
1088 }
1089
1090 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1091 if (!enable_s3tc)
1092 goto out_unknown;
1093
1094 switch (format) {
1095 case PIPE_FORMAT_RGTC1_SNORM:
1096 case PIPE_FORMAT_LATC1_SNORM:
1097 case PIPE_FORMAT_RGTC1_UNORM:
1098 case PIPE_FORMAT_LATC1_UNORM:
1099 return V_008F14_IMG_DATA_FORMAT_BC4;
1100 case PIPE_FORMAT_RGTC2_SNORM:
1101 case PIPE_FORMAT_LATC2_SNORM:
1102 case PIPE_FORMAT_RGTC2_UNORM:
1103 case PIPE_FORMAT_LATC2_UNORM:
1104 return V_008F14_IMG_DATA_FORMAT_BC5;
1105 default:
1106 goto out_unknown;
1107 }
1108 }
1109
1110 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1111
1112 if (!enable_s3tc)
1113 goto out_unknown;
1114
1115 if (!util_format_s3tc_enabled) {
1116 goto out_unknown;
1117 }
1118
1119 switch (format) {
1120 case PIPE_FORMAT_DXT1_RGB:
1121 case PIPE_FORMAT_DXT1_RGBA:
1122 case PIPE_FORMAT_DXT1_SRGB:
1123 case PIPE_FORMAT_DXT1_SRGBA:
1124 return V_008F14_IMG_DATA_FORMAT_BC1;
1125 case PIPE_FORMAT_DXT3_RGBA:
1126 case PIPE_FORMAT_DXT3_SRGBA:
1127 return V_008F14_IMG_DATA_FORMAT_BC2;
1128 case PIPE_FORMAT_DXT5_RGBA:
1129 case PIPE_FORMAT_DXT5_SRGBA:
1130 return V_008F14_IMG_DATA_FORMAT_BC3;
1131 default:
1132 goto out_unknown;
1133 }
1134 }
1135
1136 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1137 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1138 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1139 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1140 }
1141
1142 /* R8G8Bx_SNORM - TODO CxV8U8 */
1143
1144 /* See whether the components are of the same size. */
1145 for (i = 1; i < desc->nr_channels; i++) {
1146 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1147 }
1148
1149 /* Non-uniform formats. */
1150 if (!uniform) {
1151 switch(desc->nr_channels) {
1152 case 3:
1153 if (desc->channel[0].size == 5 &&
1154 desc->channel[1].size == 6 &&
1155 desc->channel[2].size == 5) {
1156 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1157 }
1158 goto out_unknown;
1159 case 4:
1160 if (desc->channel[0].size == 5 &&
1161 desc->channel[1].size == 5 &&
1162 desc->channel[2].size == 5 &&
1163 desc->channel[3].size == 1) {
1164 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1165 }
1166 if (desc->channel[0].size == 10 &&
1167 desc->channel[1].size == 10 &&
1168 desc->channel[2].size == 10 &&
1169 desc->channel[3].size == 2) {
1170 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1171 }
1172 goto out_unknown;
1173 }
1174 goto out_unknown;
1175 }
1176
1177 if (first_non_void < 0 || first_non_void > 3)
1178 goto out_unknown;
1179
1180 /* uniform formats */
1181 switch (desc->channel[first_non_void].size) {
1182 case 4:
1183 switch (desc->nr_channels) {
1184 #if 0 /* Not supported for render targets */
1185 case 2:
1186 return V_008F14_IMG_DATA_FORMAT_4_4;
1187 #endif
1188 case 4:
1189 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1190 }
1191 break;
1192 case 8:
1193 switch (desc->nr_channels) {
1194 case 1:
1195 return V_008F14_IMG_DATA_FORMAT_8;
1196 case 2:
1197 return V_008F14_IMG_DATA_FORMAT_8_8;
1198 case 4:
1199 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1200 }
1201 break;
1202 case 16:
1203 switch (desc->nr_channels) {
1204 case 1:
1205 return V_008F14_IMG_DATA_FORMAT_16;
1206 case 2:
1207 return V_008F14_IMG_DATA_FORMAT_16_16;
1208 case 4:
1209 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1210 }
1211 break;
1212 case 32:
1213 switch (desc->nr_channels) {
1214 case 1:
1215 return V_008F14_IMG_DATA_FORMAT_32;
1216 case 2:
1217 return V_008F14_IMG_DATA_FORMAT_32_32;
1218 #if 0 /* Not supported for render targets */
1219 case 3:
1220 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1221 #endif
1222 case 4:
1223 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1224 }
1225 }
1226
1227 out_unknown:
1228 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1229 return ~0;
1230 }
1231
1232 static unsigned si_tex_wrap(unsigned wrap)
1233 {
1234 switch (wrap) {
1235 default:
1236 case PIPE_TEX_WRAP_REPEAT:
1237 return V_008F30_SQ_TEX_WRAP;
1238 case PIPE_TEX_WRAP_CLAMP:
1239 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1240 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1241 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1242 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1243 return V_008F30_SQ_TEX_CLAMP_BORDER;
1244 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1245 return V_008F30_SQ_TEX_MIRROR;
1246 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1247 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1248 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1249 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1250 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1251 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1252 }
1253 }
1254
1255 static unsigned si_tex_filter(unsigned filter)
1256 {
1257 switch (filter) {
1258 default:
1259 case PIPE_TEX_FILTER_NEAREST:
1260 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1261 case PIPE_TEX_FILTER_LINEAR:
1262 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1263 }
1264 }
1265
1266 static unsigned si_tex_mipfilter(unsigned filter)
1267 {
1268 switch (filter) {
1269 case PIPE_TEX_MIPFILTER_NEAREST:
1270 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1271 case PIPE_TEX_MIPFILTER_LINEAR:
1272 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1273 default:
1274 case PIPE_TEX_MIPFILTER_NONE:
1275 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1276 }
1277 }
1278
1279 static unsigned si_tex_compare(unsigned compare)
1280 {
1281 switch (compare) {
1282 default:
1283 case PIPE_FUNC_NEVER:
1284 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1285 case PIPE_FUNC_LESS:
1286 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1287 case PIPE_FUNC_EQUAL:
1288 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1289 case PIPE_FUNC_LEQUAL:
1290 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1291 case PIPE_FUNC_GREATER:
1292 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1293 case PIPE_FUNC_NOTEQUAL:
1294 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1295 case PIPE_FUNC_GEQUAL:
1296 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1297 case PIPE_FUNC_ALWAYS:
1298 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1299 }
1300 }
1301
1302 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1303 {
1304 switch (dim) {
1305 default:
1306 case PIPE_TEXTURE_1D:
1307 return V_008F1C_SQ_RSRC_IMG_1D;
1308 case PIPE_TEXTURE_1D_ARRAY:
1309 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1310 case PIPE_TEXTURE_2D:
1311 case PIPE_TEXTURE_RECT:
1312 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1313 V_008F1C_SQ_RSRC_IMG_2D;
1314 case PIPE_TEXTURE_2D_ARRAY:
1315 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1316 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1317 case PIPE_TEXTURE_3D:
1318 return V_008F1C_SQ_RSRC_IMG_3D;
1319 case PIPE_TEXTURE_CUBE:
1320 return V_008F1C_SQ_RSRC_IMG_CUBE;
1321 }
1322 }
1323
1324 /*
1325 * Format support testing
1326 */
1327
1328 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1329 {
1330 return si_translate_texformat(screen, format, util_format_description(format),
1331 util_format_get_first_non_void_channel(format)) != ~0U;
1332 }
1333
1334 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1335 const struct util_format_description *desc,
1336 int first_non_void)
1337 {
1338 unsigned type = desc->channel[first_non_void].type;
1339 int i;
1340
1341 if (type == UTIL_FORMAT_TYPE_FIXED)
1342 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1343
1344 if (desc->nr_channels == 4 &&
1345 desc->channel[0].size == 10 &&
1346 desc->channel[1].size == 10 &&
1347 desc->channel[2].size == 10 &&
1348 desc->channel[3].size == 2)
1349 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1350
1351 /* See whether the components are of the same size. */
1352 for (i = 0; i < desc->nr_channels; i++) {
1353 if (desc->channel[first_non_void].size != desc->channel[i].size)
1354 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1355 }
1356
1357 switch (desc->channel[first_non_void].size) {
1358 case 8:
1359 switch (desc->nr_channels) {
1360 case 1:
1361 return V_008F0C_BUF_DATA_FORMAT_8;
1362 case 2:
1363 return V_008F0C_BUF_DATA_FORMAT_8_8;
1364 case 3:
1365 case 4:
1366 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1367 }
1368 break;
1369 case 16:
1370 switch (desc->nr_channels) {
1371 case 1:
1372 return V_008F0C_BUF_DATA_FORMAT_16;
1373 case 2:
1374 return V_008F0C_BUF_DATA_FORMAT_16_16;
1375 case 3:
1376 case 4:
1377 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1378 }
1379 break;
1380 case 32:
1381 /* From the Southern Islands ISA documentation about MTBUF:
1382 * 'Memory reads of data in memory that is 32 or 64 bits do not
1383 * undergo any format conversion.'
1384 */
1385 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1386 !desc->channel[first_non_void].pure_integer)
1387 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1388
1389 switch (desc->nr_channels) {
1390 case 1:
1391 return V_008F0C_BUF_DATA_FORMAT_32;
1392 case 2:
1393 return V_008F0C_BUF_DATA_FORMAT_32_32;
1394 case 3:
1395 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1396 case 4:
1397 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1398 }
1399 break;
1400 }
1401
1402 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1403 }
1404
1405 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1406 const struct util_format_description *desc,
1407 int first_non_void)
1408 {
1409 switch (desc->channel[first_non_void].type) {
1410 case UTIL_FORMAT_TYPE_SIGNED:
1411 if (desc->channel[first_non_void].normalized)
1412 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1413 else if (desc->channel[first_non_void].pure_integer)
1414 return V_008F0C_BUF_NUM_FORMAT_SINT;
1415 else
1416 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1417 break;
1418 case UTIL_FORMAT_TYPE_UNSIGNED:
1419 if (desc->channel[first_non_void].normalized)
1420 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1421 else if (desc->channel[first_non_void].pure_integer)
1422 return V_008F0C_BUF_NUM_FORMAT_UINT;
1423 else
1424 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1425 break;
1426 case UTIL_FORMAT_TYPE_FLOAT:
1427 default:
1428 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1429 }
1430 }
1431
1432 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1433 {
1434 const struct util_format_description *desc;
1435 int first_non_void;
1436 unsigned data_format;
1437
1438 desc = util_format_description(format);
1439 first_non_void = util_format_get_first_non_void_channel(format);
1440 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1441 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1442 }
1443
1444 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1445 {
1446 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1447 si_translate_colorswap(format) != ~0U;
1448 }
1449
1450 static bool si_is_zs_format_supported(enum pipe_format format)
1451 {
1452 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1453 }
1454
1455 boolean si_is_format_supported(struct pipe_screen *screen,
1456 enum pipe_format format,
1457 enum pipe_texture_target target,
1458 unsigned sample_count,
1459 unsigned usage)
1460 {
1461 struct r600_screen *rscreen = (struct r600_screen *)screen;
1462 unsigned retval = 0;
1463
1464 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1465 R600_ERR("r600: unsupported texture type %d\n", target);
1466 return FALSE;
1467 }
1468
1469 if (!util_format_is_supported(format, usage))
1470 return FALSE;
1471
1472 if (sample_count > 1) {
1473 if (HAVE_LLVM < 0x0304)
1474 return FALSE;
1475
1476 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1477 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1478 return FALSE;
1479
1480 switch (sample_count) {
1481 case 2:
1482 case 4:
1483 case 8:
1484 break;
1485 default:
1486 return FALSE;
1487 }
1488 }
1489
1490 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1491 if (target == PIPE_BUFFER) {
1492 if (si_is_vertex_format_supported(screen, format))
1493 retval |= PIPE_BIND_SAMPLER_VIEW;
1494 } else {
1495 if (si_is_sampler_format_supported(screen, format))
1496 retval |= PIPE_BIND_SAMPLER_VIEW;
1497 }
1498 }
1499
1500 if ((usage & (PIPE_BIND_RENDER_TARGET |
1501 PIPE_BIND_DISPLAY_TARGET |
1502 PIPE_BIND_SCANOUT |
1503 PIPE_BIND_SHARED)) &&
1504 si_is_colorbuffer_format_supported(format)) {
1505 retval |= usage &
1506 (PIPE_BIND_RENDER_TARGET |
1507 PIPE_BIND_DISPLAY_TARGET |
1508 PIPE_BIND_SCANOUT |
1509 PIPE_BIND_SHARED);
1510 }
1511
1512 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1513 si_is_zs_format_supported(format)) {
1514 retval |= PIPE_BIND_DEPTH_STENCIL;
1515 }
1516
1517 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1518 si_is_vertex_format_supported(screen, format)) {
1519 retval |= PIPE_BIND_VERTEX_BUFFER;
1520 }
1521
1522 if (usage & PIPE_BIND_TRANSFER_READ)
1523 retval |= PIPE_BIND_TRANSFER_READ;
1524 if (usage & PIPE_BIND_TRANSFER_WRITE)
1525 retval |= PIPE_BIND_TRANSFER_WRITE;
1526
1527 return retval == usage;
1528 }
1529
1530 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1531 {
1532 unsigned tile_mode_index = 0;
1533
1534 if (stencil) {
1535 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1536 } else {
1537 tile_mode_index = rtex->surface.tiling_index[level];
1538 }
1539 return tile_mode_index;
1540 }
1541
1542 /*
1543 * framebuffer handling
1544 */
1545
1546 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1547 const struct pipe_framebuffer_state *state, int cb)
1548 {
1549 struct r600_texture *rtex;
1550 struct r600_surface *surf;
1551 unsigned level = state->cbufs[cb]->u.tex.level;
1552 unsigned pitch, slice;
1553 unsigned color_info, color_attrib, color_pitch, color_view;
1554 unsigned tile_mode_index;
1555 unsigned format, swap, ntype, endian;
1556 uint64_t offset;
1557 const struct util_format_description *desc;
1558 int i;
1559 unsigned blend_clamp = 0, blend_bypass = 0;
1560 unsigned max_comp_size;
1561
1562 surf = (struct r600_surface *)state->cbufs[cb];
1563 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1564
1565 offset = rtex->surface.level[level].offset;
1566
1567 /* Layered rendering doesn't work with LINEAR_GENERAL.
1568 * (LINEAR_ALIGNED and others work) */
1569 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1570 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1571 offset += rtex->surface.level[level].slice_size *
1572 state->cbufs[cb]->u.tex.first_layer;
1573 color_view = 0;
1574 } else {
1575 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1576 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1577 }
1578
1579 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1580 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1581 if (slice) {
1582 slice = slice - 1;
1583 }
1584
1585 tile_mode_index = si_tile_mode_index(rtex, level, false);
1586
1587 desc = util_format_description(surf->base.format);
1588 for (i = 0; i < 4; i++) {
1589 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1590 break;
1591 }
1592 }
1593 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1594 ntype = V_028C70_NUMBER_FLOAT;
1595 } else {
1596 ntype = V_028C70_NUMBER_UNORM;
1597 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1598 ntype = V_028C70_NUMBER_SRGB;
1599 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1600 if (desc->channel[i].pure_integer) {
1601 ntype = V_028C70_NUMBER_SINT;
1602 } else {
1603 assert(desc->channel[i].normalized);
1604 ntype = V_028C70_NUMBER_SNORM;
1605 }
1606 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1607 if (desc->channel[i].pure_integer) {
1608 ntype = V_028C70_NUMBER_UINT;
1609 } else {
1610 assert(desc->channel[i].normalized);
1611 ntype = V_028C70_NUMBER_UNORM;
1612 }
1613 }
1614 }
1615
1616 format = si_translate_colorformat(surf->base.format);
1617 if (format == V_028C70_COLOR_INVALID) {
1618 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1619 }
1620 assert(format != V_028C70_COLOR_INVALID);
1621 swap = si_translate_colorswap(surf->base.format);
1622 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1623 endian = V_028C70_ENDIAN_NONE;
1624 } else {
1625 endian = si_colorformat_endian_swap(format);
1626 }
1627
1628 /* blend clamp should be set for all NORM/SRGB types */
1629 if (ntype == V_028C70_NUMBER_UNORM ||
1630 ntype == V_028C70_NUMBER_SNORM ||
1631 ntype == V_028C70_NUMBER_SRGB)
1632 blend_clamp = 1;
1633
1634 /* set blend bypass according to docs if SINT/UINT or
1635 8/24 COLOR variants */
1636 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1637 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1638 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1639 blend_clamp = 0;
1640 blend_bypass = 1;
1641 }
1642
1643 color_info = S_028C70_FORMAT(format) |
1644 S_028C70_COMP_SWAP(swap) |
1645 S_028C70_BLEND_CLAMP(blend_clamp) |
1646 S_028C70_BLEND_BYPASS(blend_bypass) |
1647 S_028C70_NUMBER_TYPE(ntype) |
1648 S_028C70_ENDIAN(endian);
1649
1650 color_pitch = S_028C64_TILE_MAX(pitch);
1651
1652 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1653 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1654
1655 if (rtex->resource.b.b.nr_samples > 1) {
1656 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1657
1658 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1659 S_028C74_NUM_FRAGMENTS(log_samples);
1660
1661 if (rtex->fmask.size) {
1662 color_info |= S_028C70_COMPRESSION(1);
1663 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1664
1665 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1666
1667 if (rctx->b.chip_class == SI) {
1668 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1669 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1670 }
1671 if (rctx->b.chip_class >= CIK) {
1672 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1673 }
1674 }
1675 }
1676
1677 if (rtex->cmask.size) {
1678 color_info |= S_028C70_FAST_CLEAR(1);
1679 }
1680
1681 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1682 offset >>= 8;
1683
1684 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1685 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1686 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1687 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1688 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1689 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1690 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1691
1692 if (rtex->cmask.size) {
1693 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1694 offset + (rtex->cmask.offset >> 8));
1695 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1696 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1697 }
1698 if (rtex->fmask.size) {
1699 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1700 offset + (rtex->fmask.offset >> 8));
1701 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1702 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1703 }
1704
1705 /* set CB_COLOR1_INFO for possible dual-src blending */
1706 if (state->nr_cbufs == 1) {
1707 assert(cb == 0);
1708 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1709 }
1710
1711 /* Determine pixel shader export format */
1712 max_comp_size = si_colorformat_max_comp_size(format);
1713 if (ntype == V_028C70_NUMBER_SRGB ||
1714 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1715 max_comp_size <= 10) ||
1716 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1717 rctx->export_16bpc |= 1 << cb;
1718 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1719 if (state->nr_cbufs == 1)
1720 rctx->export_16bpc |= 1 << 1;
1721 }
1722 }
1723
1724 /* Update register(s) containing depth buffer and draw state. */
1725 void si_update_db_draw_state(struct r600_context *rctx, struct r600_surface *zsbuf)
1726 {
1727 struct si_pm4_state *pm4;
1728 uint32_t db_render_override;
1729 boolean hiz_enable = false;
1730
1731 pm4 = si_pm4_alloc_state(rctx);
1732 if (pm4 == NULL) {
1733 return;
1734 }
1735
1736 /* db */
1737
1738 /* TODO HiS aka stencil buffer htile goes here */
1739 db_render_override = S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1740 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1741
1742 /* HiZ aka depth buffer htile */
1743 if (zsbuf && zsbuf->base.texture) {
1744 struct r600_texture *rtex = (struct r600_texture*)zsbuf->base.texture;
1745 uint level = zsbuf->base.u.tex.level;
1746 /* use htile only for first level */
1747 hiz_enable = rtex->htile_buffer && !level;
1748 }
1749 if (hiz_enable) {
1750 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1751 } else {
1752 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1753 }
1754
1755 /* draw */
1756
1757 if (rctx->num_cs_dw_nontimer_queries_suspend) {
1758 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1759 }
1760
1761 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1762 si_pm4_set_state(rctx, db_draw, pm4);
1763 }
1764
1765 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1766 const struct pipe_framebuffer_state *state)
1767 {
1768 struct r600_screen *rscreen = rctx->screen;
1769 struct r600_texture *rtex;
1770 struct r600_surface *surf;
1771 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1772 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1773 uint32_t z_info, s_info, db_depth_info;
1774 uint64_t z_offs, s_offs;
1775 uint32_t db_htile_data_base, db_htile_surface;
1776
1777 if (state->zsbuf == NULL) {
1778 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1779 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1780 return;
1781 }
1782
1783 surf = (struct r600_surface *)state->zsbuf;
1784 level = surf->base.u.tex.level;
1785 rtex = (struct r600_texture*)surf->base.texture;
1786
1787 format = si_translate_dbformat(rtex->resource.b.b.format);
1788
1789 if (format == V_028040_Z_INVALID) {
1790 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1791 }
1792 assert(format != V_028040_Z_INVALID);
1793
1794 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1795 z_offs += rtex->surface.level[level].offset;
1796 s_offs += rtex->surface.stencil_level[level].offset;
1797
1798 z_offs >>= 8;
1799 s_offs >>= 8;
1800
1801 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1802 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1803 if (slice) {
1804 slice = slice - 1;
1805 }
1806
1807 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1808
1809 z_info = S_028040_FORMAT(format);
1810 if (rtex->resource.b.b.nr_samples > 1) {
1811 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1812 }
1813
1814 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1815 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1816 else
1817 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1818
1819 if (rctx->b.chip_class >= CIK) {
1820 switch (rtex->surface.level[level].mode) {
1821 case RADEON_SURF_MODE_2D:
1822 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1823 break;
1824 case RADEON_SURF_MODE_1D:
1825 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1826 case RADEON_SURF_MODE_LINEAR:
1827 default:
1828 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1829 break;
1830 }
1831 tile_split = rtex->surface.tile_split;
1832 stile_split = rtex->surface.stencil_tile_split;
1833 macro_aspect = rtex->surface.mtilea;
1834 bankw = rtex->surface.bankw;
1835 bankh = rtex->surface.bankh;
1836 tile_split = cik_tile_split(tile_split);
1837 stile_split = cik_tile_split(stile_split);
1838 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1839 bankw = cik_bank_wh(bankw);
1840 bankh = cik_bank_wh(bankh);
1841 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1842 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1843 rscreen->b.info.r600_num_backends);
1844
1845 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1846 S_02803C_PIPE_CONFIG(pipe_config) |
1847 S_02803C_BANK_WIDTH(bankw) |
1848 S_02803C_BANK_HEIGHT(bankh) |
1849 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1850 S_02803C_NUM_BANKS(nbanks);
1851 z_info |= S_028040_TILE_SPLIT(tile_split);
1852 s_info |= S_028044_TILE_SPLIT(stile_split);
1853 } else {
1854 tile_mode_index = si_tile_mode_index(rtex, level, false);
1855 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1856 tile_mode_index = si_tile_mode_index(rtex, level, true);
1857 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1858 }
1859
1860 /* HiZ aka depth buffer htile */
1861 /* use htile only for first level */
1862 if (rtex->htile_buffer && !level) {
1863 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1864 /* Force off means no force, DB_SHADER_CONTROL decides */
1865 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1866 db_htile_data_base = va >> 8;
1867 db_htile_surface = S_028ABC_FULL_CACHE(1);
1868 } else {
1869 db_htile_data_base = 0;
1870 db_htile_surface = 0;
1871 }
1872
1873 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1874 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1875 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1876 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1877
1878 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1879 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1880 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1881
1882 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1883 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1884 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1885 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1886 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1887
1888 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1889 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1890
1891 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1892 }
1893
1894 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1895 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1896 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1897 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1898 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1899
1900 /* 2xMSAA
1901 * There are two locations (-4, 4), (4, -4). */
1902 static uint32_t sample_locs_2x[] = {
1903 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1904 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1905 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1906 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1907 };
1908 static unsigned max_dist_2x = 4;
1909 /* 4xMSAA
1910 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1911 static uint32_t sample_locs_4x[] = {
1912 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1913 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1914 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1915 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1916 };
1917 static unsigned max_dist_4x = 6;
1918 /* Cayman/SI 8xMSAA */
1919 static uint32_t cm_sample_locs_8x[] = {
1920 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1921 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1922 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1923 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1924 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1925 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1926 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1927 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1928 };
1929 static unsigned cm_max_dist_8x = 8;
1930 /* Cayman/SI 16xMSAA */
1931 static uint32_t cm_sample_locs_16x[] = {
1932 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1933 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1934 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1935 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1936 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1937 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1938 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1939 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1940 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1941 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1942 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1943 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1944 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1945 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1946 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1947 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1948 };
1949 static unsigned cm_max_dist_16x = 8;
1950
1951 static void si_get_sample_position(struct pipe_context *ctx,
1952 unsigned sample_count,
1953 unsigned sample_index,
1954 float *out_value)
1955 {
1956 int offset, index;
1957 struct {
1958 int idx:4;
1959 } val;
1960 switch (sample_count) {
1961 case 1:
1962 default:
1963 out_value[0] = out_value[1] = 0.5;
1964 break;
1965 case 2:
1966 offset = 4 * (sample_index * 2);
1967 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1968 out_value[0] = (float)(val.idx + 8) / 16.0f;
1969 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1970 out_value[1] = (float)(val.idx + 8) / 16.0f;
1971 break;
1972 case 4:
1973 offset = 4 * (sample_index * 2);
1974 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1975 out_value[0] = (float)(val.idx + 8) / 16.0f;
1976 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1977 out_value[1] = (float)(val.idx + 8) / 16.0f;
1978 break;
1979 case 8:
1980 offset = 4 * (sample_index % 4 * 2);
1981 index = (sample_index / 4) * 4;
1982 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1983 out_value[0] = (float)(val.idx + 8) / 16.0f;
1984 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1985 out_value[1] = (float)(val.idx + 8) / 16.0f;
1986 break;
1987 case 16:
1988 offset = 4 * (sample_index % 4 * 2);
1989 index = (sample_index / 4) * 4;
1990 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1991 out_value[0] = (float)(val.idx + 8) / 16.0f;
1992 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1993 out_value[1] = (float)(val.idx + 8) / 16.0f;
1994 break;
1995 }
1996 }
1997
1998 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1999 {
2000 unsigned max_dist = 0;
2001
2002 switch (nr_samples) {
2003 default:
2004 nr_samples = 0;
2005 break;
2006 case 2:
2007 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2008 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2009 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2010 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2011 max_dist = max_dist_2x;
2012 break;
2013 case 4:
2014 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2015 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2016 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2017 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2018 max_dist = max_dist_4x;
2019 break;
2020 case 8:
2021 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2022 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2023 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2024 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2025 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2026 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2027 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2028 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2029 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2030 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2031 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2032 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2033 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2034 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2035 max_dist = cm_max_dist_8x;
2036 break;
2037 case 16:
2038 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2039 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2040 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2041 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2042 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2043 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2044 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2045 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2046 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2047 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2048 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2049 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2050 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2051 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2052 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2053 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2054 max_dist = cm_max_dist_16x;
2055 break;
2056 }
2057
2058 if (nr_samples > 1) {
2059 unsigned log_samples = util_logbase2(nr_samples);
2060
2061 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2062 S_028BDC_LAST_PIXEL(1) |
2063 S_028BDC_EXPAND_LINE_WIDTH(1));
2064 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2065 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2066 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2067 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2068
2069 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2070 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2071 S_028804_PS_ITER_SAMPLES(log_samples) |
2072 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2073 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2074 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2075 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2076 } else {
2077 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2078 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2079
2080 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2081 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2082 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2083 }
2084 }
2085
2086 static void si_set_framebuffer_state(struct pipe_context *ctx,
2087 const struct pipe_framebuffer_state *state)
2088 {
2089 struct r600_context *rctx = (struct r600_context *)ctx;
2090 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2091 uint32_t tl, br;
2092 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2093
2094 if (pm4 == NULL)
2095 return;
2096
2097 if (rctx->framebuffer.nr_cbufs) {
2098 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2099 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2100 }
2101 if (rctx->framebuffer.zsbuf) {
2102 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2103 }
2104
2105 util_copy_framebuffer_state(&rctx->framebuffer, state);
2106
2107 /* build states */
2108 rctx->export_16bpc = 0;
2109 rctx->fb_compressed_cb_mask = 0;
2110 for (i = 0; i < state->nr_cbufs; i++) {
2111 struct r600_texture *rtex =
2112 (struct r600_texture*)state->cbufs[i]->texture;
2113
2114 si_cb(rctx, pm4, state, i);
2115
2116 if (rtex->fmask.size || rtex->cmask.size) {
2117 rctx->fb_compressed_cb_mask |= 1 << i;
2118 }
2119 }
2120 for (; i < 8; i++) {
2121 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2122 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2123 }
2124
2125 assert(!(rctx->export_16bpc & ~0xff));
2126 si_db(rctx, pm4, state);
2127
2128 tl_x = 0;
2129 tl_y = 0;
2130 br_x = state->width;
2131 br_y = state->height;
2132
2133 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2134 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2135
2136 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2137 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2138 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2139 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2140 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2141 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2142 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2143 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2144
2145 if (state->nr_cbufs)
2146 nr_samples = state->cbufs[0]->texture->nr_samples;
2147 else if (state->zsbuf)
2148 nr_samples = state->zsbuf->texture->nr_samples;
2149 else
2150 nr_samples = 0;
2151
2152 si_set_msaa_state(rctx, pm4, nr_samples);
2153 rctx->fb_log_samples = util_logbase2(nr_samples);
2154 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2155 util_format_is_pure_integer(state->cbufs[0]->format);
2156
2157 si_pm4_set_state(rctx, framebuffer, pm4);
2158 si_update_fb_rs_state(rctx);
2159 si_update_fb_blend_state(rctx);
2160 si_update_db_draw_state(rctx, (struct r600_surface *)state->zsbuf);
2161 }
2162
2163 /*
2164 * shaders
2165 */
2166
2167 /* Compute the key for the hw shader variant */
2168 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2169 struct si_pipe_shader_selector *sel,
2170 union si_shader_key *key)
2171 {
2172 struct r600_context *rctx = (struct r600_context *)ctx;
2173 memset(key, 0, sizeof(*key));
2174
2175 if (sel->type == PIPE_SHADER_VERTEX) {
2176 unsigned i;
2177 if (!rctx->vertex_elements)
2178 return;
2179
2180 for (i = 0; i < rctx->vertex_elements->count; ++i)
2181 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2182
2183 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2184 key->vs.ucps_enabled |= 0x2;
2185 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2186 key->vs.ucps_enabled |= 0x1;
2187 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2188 if (sel->fs_write_all)
2189 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2190 key->ps.export_16bpc = rctx->export_16bpc;
2191
2192 if (rctx->queued.named.rasterizer) {
2193 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2194 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2195
2196 if (rctx->queued.named.blend) {
2197 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2198 rctx->queued.named.rasterizer->multisample_enable &&
2199 !rctx->fb_cb0_is_integer;
2200 }
2201 }
2202 if (rctx->queued.named.dsa) {
2203 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2204
2205 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2206 if (rctx->framebuffer.nr_cbufs &&
2207 rctx->framebuffer.cbufs[0] &&
2208 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2209 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2210 } else {
2211 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2212 }
2213 }
2214 }
2215
2216 /* Select the hw shader variant depending on the current state.
2217 * (*dirty) is set to 1 if current variant was changed */
2218 int si_shader_select(struct pipe_context *ctx,
2219 struct si_pipe_shader_selector *sel,
2220 unsigned *dirty)
2221 {
2222 union si_shader_key key;
2223 struct si_pipe_shader * shader = NULL;
2224 int r;
2225
2226 si_shader_selector_key(ctx, sel, &key);
2227
2228 /* Check if we don't need to change anything.
2229 * This path is also used for most shaders that don't need multiple
2230 * variants, it will cost just a computation of the key and this
2231 * test. */
2232 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2233 return 0;
2234 }
2235
2236 /* lookup if we have other variants in the list */
2237 if (sel->num_shaders > 1) {
2238 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2239
2240 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2241 p = c;
2242 c = c->next_variant;
2243 }
2244
2245 if (c) {
2246 p->next_variant = c->next_variant;
2247 shader = c;
2248 }
2249 }
2250
2251 if (unlikely(!shader)) {
2252 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2253 shader->selector = sel;
2254 shader->key = key;
2255
2256 r = si_pipe_shader_create(ctx, shader);
2257 if (unlikely(r)) {
2258 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2259 sel->type, r);
2260 sel->current = NULL;
2261 FREE(shader);
2262 return r;
2263 }
2264 sel->num_shaders++;
2265 }
2266
2267 if (dirty)
2268 *dirty = 1;
2269
2270 shader->next_variant = sel->current;
2271 sel->current = shader;
2272
2273 return 0;
2274 }
2275
2276 static void *si_create_shader_state(struct pipe_context *ctx,
2277 const struct pipe_shader_state *state,
2278 unsigned pipe_shader_type)
2279 {
2280 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2281 int r;
2282 struct tgsi_shader_info info;
2283
2284 tgsi_scan_shader(state->tokens, &info);
2285
2286 sel->type = pipe_shader_type;
2287 sel->tokens = tgsi_dup_tokens(state->tokens);
2288 sel->so = state->stream_output;
2289 sel->fs_write_all = info.color0_writes_all_cbufs;
2290
2291 r = si_shader_select(ctx, sel, NULL);
2292 if (r) {
2293 free(sel);
2294 return NULL;
2295 }
2296
2297 return sel;
2298 }
2299
2300 static void *si_create_fs_state(struct pipe_context *ctx,
2301 const struct pipe_shader_state *state)
2302 {
2303 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2304 }
2305
2306 static void *si_create_vs_state(struct pipe_context *ctx,
2307 const struct pipe_shader_state *state)
2308 {
2309 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2310 }
2311
2312 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2313 {
2314 struct r600_context *rctx = (struct r600_context *)ctx;
2315 struct si_pipe_shader_selector *sel = state;
2316
2317 if (rctx->vs_shader == sel)
2318 return;
2319
2320 if (!sel || !sel->current)
2321 return;
2322
2323 rctx->vs_shader = sel;
2324 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2325 rctx->b.streamout.stride_in_dw = sel->so.stride;
2326 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2327 }
2328
2329 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2330 {
2331 struct r600_context *rctx = (struct r600_context *)ctx;
2332 struct si_pipe_shader_selector *sel = state;
2333
2334 if (rctx->ps_shader == sel)
2335 return;
2336
2337 if (!sel || !sel->current)
2338 sel = rctx->dummy_pixel_shader;
2339
2340 rctx->ps_shader = sel;
2341 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2342 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2343 }
2344
2345 static void si_delete_shader_selector(struct pipe_context *ctx,
2346 struct si_pipe_shader_selector *sel)
2347 {
2348 struct r600_context *rctx = (struct r600_context *)ctx;
2349 struct si_pipe_shader *p = sel->current, *c;
2350
2351 while (p) {
2352 c = p->next_variant;
2353 si_pm4_delete_state(rctx, vs, p->pm4);
2354 si_pipe_shader_destroy(ctx, p);
2355 free(p);
2356 p = c;
2357 }
2358
2359 free(sel->tokens);
2360 free(sel);
2361 }
2362
2363 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2364 {
2365 struct r600_context *rctx = (struct r600_context *)ctx;
2366 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2367
2368 if (rctx->vs_shader == sel) {
2369 rctx->vs_shader = NULL;
2370 }
2371
2372 si_delete_shader_selector(ctx, sel);
2373 }
2374
2375 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2376 {
2377 struct r600_context *rctx = (struct r600_context *)ctx;
2378 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2379
2380 if (rctx->ps_shader == sel) {
2381 rctx->ps_shader = NULL;
2382 }
2383
2384 si_delete_shader_selector(ctx, sel);
2385 }
2386
2387 /*
2388 * Samplers
2389 */
2390
2391 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2392 struct pipe_resource *texture,
2393 const struct pipe_sampler_view *state)
2394 {
2395 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2396 struct r600_texture *tmp = (struct r600_texture*)texture;
2397 const struct util_format_description *desc;
2398 unsigned format, num_format;
2399 uint32_t pitch = 0;
2400 unsigned char state_swizzle[4], swizzle[4];
2401 unsigned height, depth, width;
2402 enum pipe_format pipe_format = state->format;
2403 struct radeon_surface_level *surflevel;
2404 int first_non_void;
2405 uint64_t va;
2406
2407 if (view == NULL)
2408 return NULL;
2409
2410 /* initialize base object */
2411 view->base = *state;
2412 view->base.texture = NULL;
2413 pipe_resource_reference(&view->base.texture, texture);
2414 view->base.reference.count = 1;
2415 view->base.context = ctx;
2416 view->resource = &tmp->resource;
2417
2418 /* Buffer resource. */
2419 if (texture->target == PIPE_BUFFER) {
2420 unsigned stride;
2421
2422 desc = util_format_description(state->format);
2423 first_non_void = util_format_get_first_non_void_channel(state->format);
2424 stride = desc->block.bits / 8;
2425 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2426 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2427 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2428
2429 view->state[0] = va;
2430 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2431 S_008F04_STRIDE(stride);
2432 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2433 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2434 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2435 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2436 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2437 S_008F0C_NUM_FORMAT(num_format) |
2438 S_008F0C_DATA_FORMAT(format);
2439 return &view->base;
2440 }
2441
2442 state_swizzle[0] = state->swizzle_r;
2443 state_swizzle[1] = state->swizzle_g;
2444 state_swizzle[2] = state->swizzle_b;
2445 state_swizzle[3] = state->swizzle_a;
2446
2447 surflevel = tmp->surface.level;
2448
2449 /* Texturing with separate depth and stencil. */
2450 if (tmp->is_depth && !tmp->is_flushing_texture) {
2451 switch (pipe_format) {
2452 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2453 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2454 break;
2455 case PIPE_FORMAT_X8Z24_UNORM:
2456 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2457 /* Z24 is always stored like this. */
2458 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2459 break;
2460 case PIPE_FORMAT_X24S8_UINT:
2461 case PIPE_FORMAT_S8X24_UINT:
2462 case PIPE_FORMAT_X32_S8X24_UINT:
2463 pipe_format = PIPE_FORMAT_S8_UINT;
2464 surflevel = tmp->surface.stencil_level;
2465 break;
2466 default:;
2467 }
2468 }
2469
2470 desc = util_format_description(pipe_format);
2471
2472 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2473 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2474 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2475
2476 switch (pipe_format) {
2477 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2478 case PIPE_FORMAT_X24S8_UINT:
2479 case PIPE_FORMAT_X32_S8X24_UINT:
2480 case PIPE_FORMAT_X8Z24_UNORM:
2481 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2482 break;
2483 default:
2484 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2485 }
2486 } else {
2487 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2488 }
2489
2490 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2491
2492 switch (pipe_format) {
2493 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2494 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2495 break;
2496 default:
2497 if (first_non_void < 0) {
2498 if (util_format_is_compressed(pipe_format)) {
2499 switch (pipe_format) {
2500 case PIPE_FORMAT_DXT1_SRGB:
2501 case PIPE_FORMAT_DXT1_SRGBA:
2502 case PIPE_FORMAT_DXT3_SRGBA:
2503 case PIPE_FORMAT_DXT5_SRGBA:
2504 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2505 break;
2506 case PIPE_FORMAT_RGTC1_SNORM:
2507 case PIPE_FORMAT_LATC1_SNORM:
2508 case PIPE_FORMAT_RGTC2_SNORM:
2509 case PIPE_FORMAT_LATC2_SNORM:
2510 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2511 break;
2512 default:
2513 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2514 break;
2515 }
2516 } else {
2517 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2518 }
2519 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2520 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2521 } else {
2522 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2523
2524 switch (desc->channel[first_non_void].type) {
2525 case UTIL_FORMAT_TYPE_FLOAT:
2526 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2527 break;
2528 case UTIL_FORMAT_TYPE_SIGNED:
2529 if (desc->channel[first_non_void].normalized)
2530 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2531 else if (desc->channel[first_non_void].pure_integer)
2532 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2533 else
2534 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2535 break;
2536 case UTIL_FORMAT_TYPE_UNSIGNED:
2537 if (desc->channel[first_non_void].normalized)
2538 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2539 else if (desc->channel[first_non_void].pure_integer)
2540 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2541 else
2542 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2543 }
2544 }
2545 }
2546
2547 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2548 if (format == ~0) {
2549 format = 0;
2550 }
2551
2552 /* not supported any more */
2553 //endian = si_colorformat_endian_swap(format);
2554
2555 width = surflevel[0].npix_x;
2556 height = surflevel[0].npix_y;
2557 depth = surflevel[0].npix_z;
2558 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2559
2560 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2561 height = 1;
2562 depth = texture->array_size;
2563 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2564 depth = texture->array_size;
2565 }
2566
2567 va = r600_resource_va(ctx->screen, texture);
2568 va += surflevel[0].offset;
2569 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2570 view->state[0] = va >> 8;
2571 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2572 S_008F14_DATA_FORMAT(format) |
2573 S_008F14_NUM_FORMAT(num_format));
2574 view->state[2] = (S_008F18_WIDTH(width - 1) |
2575 S_008F18_HEIGHT(height - 1));
2576 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2577 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2578 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2579 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2580 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2581 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2582 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2583 util_logbase2(texture->nr_samples) :
2584 state->u.tex.last_level - tmp->mipmap_shift) |
2585 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2586 S_008F1C_POW2_PAD(texture->last_level > 0) |
2587 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2588 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2589 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2590 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2591 view->state[6] = 0;
2592 view->state[7] = 0;
2593
2594 /* Initialize the sampler view for FMASK. */
2595 if (tmp->fmask.size) {
2596 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2597 uint32_t fmask_format;
2598
2599 switch (texture->nr_samples) {
2600 case 2:
2601 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2602 break;
2603 case 4:
2604 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2605 break;
2606 case 8:
2607 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2608 break;
2609 default:
2610 assert(0);
2611 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2612 }
2613
2614 view->fmask_state[0] = va >> 8;
2615 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2616 S_008F14_DATA_FORMAT(fmask_format) |
2617 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2618 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2619 S_008F18_HEIGHT(height - 1);
2620 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2621 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2622 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2623 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2624 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2625 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2626 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2627 S_008F20_PITCH(tmp->fmask.pitch - 1);
2628 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2629 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2630 view->fmask_state[6] = 0;
2631 view->fmask_state[7] = 0;
2632 }
2633
2634 return &view->base;
2635 }
2636
2637 static void si_sampler_view_destroy(struct pipe_context *ctx,
2638 struct pipe_sampler_view *state)
2639 {
2640 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2641
2642 pipe_resource_reference(&state->texture, NULL);
2643 FREE(resource);
2644 }
2645
2646 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2647 {
2648 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2649 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2650 (linear_filter &&
2651 (wrap == PIPE_TEX_WRAP_CLAMP ||
2652 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2653 }
2654
2655 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2656 {
2657 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2658 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2659
2660 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2661 state->border_color.ui[2] || state->border_color.ui[3]) &&
2662 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2663 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2664 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2665 }
2666
2667 static void *si_create_sampler_state(struct pipe_context *ctx,
2668 const struct pipe_sampler_state *state)
2669 {
2670 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2671 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2672 unsigned border_color_type;
2673
2674 if (rstate == NULL) {
2675 return NULL;
2676 }
2677
2678 if (sampler_state_needs_border_color(state))
2679 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2680 else
2681 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2682
2683 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2684 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2685 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2686 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2687 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2688 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2689 aniso_flag_offset << 16 | /* XXX */
2690 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2691 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2692 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2693 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2694 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2695 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2696 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2697 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2698
2699 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2700 memcpy(rstate->border_color, state->border_color.ui,
2701 sizeof(rstate->border_color));
2702 }
2703
2704 return rstate;
2705 }
2706
2707 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2708 * the si_set_sampler_view calls. LTO might help too. */
2709 static void si_set_sampler_views(struct pipe_context *ctx,
2710 unsigned shader, unsigned start,
2711 unsigned count,
2712 struct pipe_sampler_view **views)
2713 {
2714 struct r600_context *rctx = (struct r600_context *)ctx;
2715 struct r600_textures_info *samplers = &rctx->samplers[shader];
2716 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2717 int i;
2718
2719 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2720 return;
2721
2722 assert(start == 0);
2723
2724 for (i = 0; i < count; i++) {
2725 if (!views[i]) {
2726 samplers->depth_texture_mask &= ~(1 << i);
2727 samplers->compressed_colortex_mask &= ~(1 << i);
2728 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2729 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2730 NULL, NULL);
2731 continue;
2732 }
2733
2734 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2735
2736 if (views[i]->texture->target != PIPE_BUFFER) {
2737 struct r600_texture *rtex =
2738 (struct r600_texture*)views[i]->texture;
2739
2740 if (rtex->is_depth && !rtex->is_flushing_texture) {
2741 samplers->depth_texture_mask |= 1 << i;
2742 } else {
2743 samplers->depth_texture_mask &= ~(1 << i);
2744 }
2745 if (rtex->cmask.size || rtex->fmask.size) {
2746 samplers->compressed_colortex_mask |= 1 << i;
2747 } else {
2748 samplers->compressed_colortex_mask &= ~(1 << i);
2749 }
2750
2751 if (rtex->fmask.size) {
2752 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2753 views[i], rviews[i]->fmask_state);
2754 } else {
2755 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2756 NULL, NULL);
2757 }
2758 }
2759 }
2760 for (; i < samplers->n_views; i++) {
2761 samplers->depth_texture_mask &= ~(1 << i);
2762 samplers->compressed_colortex_mask &= ~(1 << i);
2763 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2764 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2765 NULL, NULL);
2766 }
2767
2768 samplers->n_views = count;
2769 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2770 }
2771
2772 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2773 void **states,
2774 struct r600_textures_info *samplers,
2775 unsigned user_data_reg)
2776 {
2777 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2778 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2779 uint32_t *border_color_table = NULL;
2780 int i, j;
2781
2782 if (!count)
2783 goto out;
2784
2785 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2786
2787 si_pm4_sh_data_begin(pm4);
2788 for (i = 0; i < count; i++) {
2789 if (rstates[i] &&
2790 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2791 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2792 if (!rctx->border_color_table ||
2793 ((rctx->border_color_offset + count - i) &
2794 C_008F3C_BORDER_COLOR_PTR)) {
2795 r600_resource_reference(&rctx->border_color_table, NULL);
2796 rctx->border_color_offset = 0;
2797
2798 rctx->border_color_table =
2799 r600_resource_create_custom(&rctx->screen->b.b,
2800 PIPE_USAGE_STAGING,
2801 4096 * 4 * 4);
2802 }
2803
2804 if (!border_color_table) {
2805 border_color_table =
2806 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2807 rctx->b.rings.gfx.cs,
2808 PIPE_TRANSFER_WRITE |
2809 PIPE_TRANSFER_UNSYNCHRONIZED);
2810 }
2811
2812 for (j = 0; j < 4; j++) {
2813 border_color_table[4 * rctx->border_color_offset + j] =
2814 util_le32_to_cpu(rstates[i]->border_color[j]);
2815 }
2816
2817 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2818 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2819 }
2820
2821 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2822 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2823 }
2824 }
2825 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2826
2827 if (border_color_table) {
2828 uint64_t va_offset =
2829 r600_resource_va(&rctx->screen->b.b,
2830 (void*)rctx->border_color_table);
2831
2832 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2833 if (rctx->b.chip_class >= CIK)
2834 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2835 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2836 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2837 }
2838
2839 memcpy(samplers->samplers, states, sizeof(void*) * count);
2840
2841 out:
2842 samplers->n_samplers = count;
2843 return pm4;
2844 }
2845
2846 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2847 {
2848 struct r600_context *rctx = (struct r600_context *)ctx;
2849 struct si_pm4_state *pm4;
2850
2851 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2852 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2853 si_pm4_set_state(rctx, vs_sampler, pm4);
2854 }
2855
2856 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2857 {
2858 struct r600_context *rctx = (struct r600_context *)ctx;
2859 struct si_pm4_state *pm4;
2860
2861 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2862 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2863 si_pm4_set_state(rctx, ps_sampler, pm4);
2864 }
2865
2866
2867 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2868 unsigned start, unsigned count,
2869 void **states)
2870 {
2871 assert(start == 0);
2872
2873 switch (shader) {
2874 case PIPE_SHADER_VERTEX:
2875 si_bind_vs_sampler_states(ctx, count, states);
2876 break;
2877 case PIPE_SHADER_FRAGMENT:
2878 si_bind_ps_sampler_states(ctx, count, states);
2879 break;
2880 default:
2881 ;
2882 }
2883 }
2884
2885
2886
2887 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2888 {
2889 struct r600_context *rctx = (struct r600_context *)ctx;
2890 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2891 uint16_t mask = sample_mask;
2892
2893 if (pm4 == NULL)
2894 return;
2895
2896 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2897 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2898
2899 si_pm4_set_state(rctx, sample_mask, pm4);
2900 }
2901
2902 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2903 {
2904 free(state);
2905 }
2906
2907 /*
2908 * Vertex elements & buffers
2909 */
2910
2911 static void *si_create_vertex_elements(struct pipe_context *ctx,
2912 unsigned count,
2913 const struct pipe_vertex_element *elements)
2914 {
2915 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2916 int i;
2917
2918 assert(count < PIPE_MAX_ATTRIBS);
2919 if (!v)
2920 return NULL;
2921
2922 v->count = count;
2923 for (i = 0; i < count; ++i) {
2924 const struct util_format_description *desc;
2925 unsigned data_format, num_format;
2926 int first_non_void;
2927
2928 desc = util_format_description(elements[i].src_format);
2929 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2930 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2931 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2932
2933 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2934 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2935 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2936 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2937 S_008F0C_NUM_FORMAT(num_format) |
2938 S_008F0C_DATA_FORMAT(data_format);
2939 }
2940 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2941
2942 return v;
2943 }
2944
2945 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2946 {
2947 struct r600_context *rctx = (struct r600_context *)ctx;
2948 struct si_vertex_element *v = (struct si_vertex_element*)state;
2949
2950 rctx->vertex_elements = v;
2951 }
2952
2953 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2954 {
2955 struct r600_context *rctx = (struct r600_context *)ctx;
2956
2957 if (rctx->vertex_elements == state)
2958 rctx->vertex_elements = NULL;
2959 FREE(state);
2960 }
2961
2962 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2963 const struct pipe_vertex_buffer *buffers)
2964 {
2965 struct r600_context *rctx = (struct r600_context *)ctx;
2966
2967 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2968 }
2969
2970 static void si_set_index_buffer(struct pipe_context *ctx,
2971 const struct pipe_index_buffer *ib)
2972 {
2973 struct r600_context *rctx = (struct r600_context *)ctx;
2974
2975 if (ib) {
2976 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2977 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2978 } else {
2979 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2980 }
2981 }
2982
2983 /*
2984 * Misc
2985 */
2986 static void si_set_polygon_stipple(struct pipe_context *ctx,
2987 const struct pipe_poly_stipple *state)
2988 {
2989 }
2990
2991 static void si_texture_barrier(struct pipe_context *ctx)
2992 {
2993 struct r600_context *rctx = (struct r600_context *)ctx;
2994
2995 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2996 R600_CONTEXT_FLUSH_AND_INV_CB;
2997 }
2998
2999 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
3000 {
3001 struct pipe_blend_state blend;
3002
3003 memset(&blend, 0, sizeof(blend));
3004 blend.independent_blend_enable = true;
3005 blend.rt[0].colormask = 0xf;
3006 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
3007 }
3008
3009 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
3010 struct pipe_resource *texture,
3011 const struct pipe_surface *surf_tmpl)
3012 {
3013 struct r600_texture *rtex = (struct r600_texture*)texture;
3014 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
3015 unsigned level = surf_tmpl->u.tex.level;
3016
3017 if (surface == NULL)
3018 return NULL;
3019
3020 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3021 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3022
3023 pipe_reference_init(&surface->base.reference, 1);
3024 pipe_resource_reference(&surface->base.texture, texture);
3025 surface->base.context = pipe;
3026 surface->base.format = surf_tmpl->format;
3027 surface->base.width = rtex->surface.level[level].npix_x;
3028 surface->base.height = rtex->surface.level[level].npix_y;
3029 surface->base.texture = texture;
3030 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3031 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3032 surface->base.u.tex.level = level;
3033
3034 return &surface->base;
3035 }
3036
3037 static void r600_surface_destroy(struct pipe_context *pipe,
3038 struct pipe_surface *surface)
3039 {
3040 pipe_resource_reference(&surface->texture, NULL);
3041 FREE(surface);
3042 }
3043
3044 static boolean si_dma_copy(struct pipe_context *ctx,
3045 struct pipe_resource *dst,
3046 unsigned dst_level,
3047 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3048 struct pipe_resource *src,
3049 unsigned src_level,
3050 const struct pipe_box *src_box)
3051 {
3052 /* XXX implement this or share evergreen_dma_blit with r600g */
3053 return FALSE;
3054 }
3055
3056 void si_init_state_functions(struct r600_context *rctx)
3057 {
3058 int i;
3059
3060 rctx->b.b.create_blend_state = si_create_blend_state;
3061 rctx->b.b.bind_blend_state = si_bind_blend_state;
3062 rctx->b.b.delete_blend_state = si_delete_blend_state;
3063 rctx->b.b.set_blend_color = si_set_blend_color;
3064
3065 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3066 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3067 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3068
3069 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3070 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3071 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3072
3073 for (i = 0; i < 8; i++) {
3074 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3075 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3076 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3077 }
3078 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3079 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3080 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3081
3082 rctx->b.b.set_clip_state = si_set_clip_state;
3083 rctx->b.b.set_scissor_states = si_set_scissor_states;
3084 rctx->b.b.set_viewport_states = si_set_viewport_states;
3085 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3086
3087 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3088 rctx->b.b.get_sample_position = si_get_sample_position;
3089
3090 rctx->b.b.create_vs_state = si_create_vs_state;
3091 rctx->b.b.create_fs_state = si_create_fs_state;
3092 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3093 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3094 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3095 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3096
3097 rctx->b.b.create_sampler_state = si_create_sampler_state;
3098 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3099 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3100
3101 rctx->b.b.create_sampler_view = si_create_sampler_view;
3102 rctx->b.b.set_sampler_views = si_set_sampler_views;
3103 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3104
3105 rctx->b.b.set_sample_mask = si_set_sample_mask;
3106
3107 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3108 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3109 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3110 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3111 rctx->b.b.set_index_buffer = si_set_index_buffer;
3112
3113 rctx->b.b.texture_barrier = si_texture_barrier;
3114 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3115 rctx->b.b.create_surface = r600_create_surface;
3116 rctx->b.b.surface_destroy = r600_surface_destroy;
3117 rctx->b.dma_copy = si_dma_copy;
3118
3119 rctx->b.b.draw_vbo = si_draw_vbo;
3120 }
3121
3122 void si_init_config(struct r600_context *rctx)
3123 {
3124 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3125
3126 if (pm4 == NULL)
3127 return;
3128
3129 si_cmd_context_control(pm4);
3130
3131 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3132
3133 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3134 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3135 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3136 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3137 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3138 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3139 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3140 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3141 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3142 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3143 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3144 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3145 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3146 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3147 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3148 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3149 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3150 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3151 if (rctx->b.chip_class == SI) {
3152 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3153 S_028AA8_SWITCH_ON_EOP(1) |
3154 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3155 S_028AA8_PRIMGROUP_SIZE(63));
3156 }
3157 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3158 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3159 if (rctx->b.chip_class < CIK)
3160 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3161 S_008A14_CLIP_VTX_REORDER_ENA(1));
3162
3163 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3164 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3165 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3166
3167 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3168
3169 if (rctx->b.chip_class >= CIK) {
3170 switch (rctx->screen->b.family) {
3171 case CHIP_BONAIRE:
3172 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3173 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3174 break;
3175 case CHIP_HAWAII:
3176 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3177 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3178 break;
3179 case CHIP_KAVERI:
3180 /* XXX todo */
3181 case CHIP_KABINI:
3182 /* XXX todo */
3183 default:
3184 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3185 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3186 break;
3187 }
3188 } else {
3189 switch (rctx->screen->b.family) {
3190 case CHIP_TAHITI:
3191 case CHIP_PITCAIRN:
3192 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3193 break;
3194 case CHIP_VERDE:
3195 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3196 break;
3197 case CHIP_OLAND:
3198 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3199 break;
3200 case CHIP_HAINAN:
3201 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3202 break;
3203 default:
3204 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3205 break;
3206 }
3207 }
3208
3209 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
3210 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3211 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3212 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3213 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3214 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3215 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3216 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3217 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3218 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3219 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3220 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3221 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3222 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3223 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3224 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3225 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3226 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3227 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3228
3229 if (rctx->b.chip_class >= CIK) {
3230 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3231 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3232 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3233 }
3234
3235 si_pm4_set_state(rctx, init, pm4);
3236 }