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radeonsi: various si_translate_*format functions only apply to pre-gfx10
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= GFX8) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == GFX8 ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
117
118 radeon_opt_set_context_reg(
119 sctx, R_028424_CB_DCC_CONTROL,
120 SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
125 }
126
127 /* RB+ register settings. */
128 if (sctx->screen->rbplus_allowed) {
129 unsigned spi_shader_col_format =
130 sctx->ps_shader.cso ?
131 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
132 unsigned sx_ps_downconvert = 0;
133 unsigned sx_blend_opt_epsilon = 0;
134 unsigned sx_blend_opt_control = 0;
135
136 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
137 struct si_surface *surf =
138 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
139 unsigned format, swap, spi_format, colormask;
140 bool has_alpha, has_rgb;
141
142 if (!surf)
143 continue;
144
145 format = G_028C70_FORMAT(surf->cb_color_info);
146 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
147 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
149
150 /* Set if RGB and A are present. */
151 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
152
153 if (format == V_028C70_COLOR_8 ||
154 format == V_028C70_COLOR_16 ||
155 format == V_028C70_COLOR_32)
156 has_rgb = !has_alpha;
157 else
158 has_rgb = true;
159
160 /* Check the colormask and export format. */
161 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
162 has_rgb = false;
163 if (!(colormask & PIPE_MASK_A))
164 has_alpha = false;
165
166 if (spi_format == V_028714_SPI_SHADER_ZERO) {
167 has_rgb = false;
168 has_alpha = false;
169 }
170
171 /* Disable value checking for disabled channels. */
172 if (!has_rgb)
173 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
174 if (!has_alpha)
175 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
176
177 /* Enable down-conversion for 32bpp and smaller formats. */
178 switch (format) {
179 case V_028C70_COLOR_8:
180 case V_028C70_COLOR_8_8:
181 case V_028C70_COLOR_8_8_8_8:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_5_6_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_1_5_5_5:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_4_4_4_4:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_32:
213 if (swap == V_028C70_SWAP_STD &&
214 spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV &&
217 spi_format == V_028714_SPI_SHADER_32_AR)
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
219 break;
220
221 case V_028C70_COLOR_16:
222 case V_028C70_COLOR_16_16:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
227 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
228 if (swap == V_028C70_SWAP_STD ||
229 swap == V_028C70_SWAP_STD_REV)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
231 else
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_10_11_11:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
240 }
241 break;
242
243 case V_028C70_COLOR_2_10_10_10:
244 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
246 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
247 }
248 break;
249 }
250 }
251
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
254 SI_TRACKED_SX_PS_DOWNCONVERT,
255 sx_ps_downconvert, sx_blend_opt_epsilon,
256 sx_blend_opt_control);
257 }
258 if (initial_cdw != cs->current.cdw)
259 sctx->context_roll = true;
260 }
261
262 /*
263 * Blender functions
264 */
265
266 static uint32_t si_translate_blend_function(int blend_func)
267 {
268 switch (blend_func) {
269 case PIPE_BLEND_ADD:
270 return V_028780_COMB_DST_PLUS_SRC;
271 case PIPE_BLEND_SUBTRACT:
272 return V_028780_COMB_SRC_MINUS_DST;
273 case PIPE_BLEND_REVERSE_SUBTRACT:
274 return V_028780_COMB_DST_MINUS_SRC;
275 case PIPE_BLEND_MIN:
276 return V_028780_COMB_MIN_DST_SRC;
277 case PIPE_BLEND_MAX:
278 return V_028780_COMB_MAX_DST_SRC;
279 default:
280 PRINT_ERR("Unknown blend function %d\n", blend_func);
281 assert(0);
282 break;
283 }
284 return 0;
285 }
286
287 static uint32_t si_translate_blend_factor(int blend_fact)
288 {
289 switch (blend_fact) {
290 case PIPE_BLENDFACTOR_ONE:
291 return V_028780_BLEND_ONE;
292 case PIPE_BLENDFACTOR_SRC_COLOR:
293 return V_028780_BLEND_SRC_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA:
295 return V_028780_BLEND_SRC_ALPHA;
296 case PIPE_BLENDFACTOR_DST_ALPHA:
297 return V_028780_BLEND_DST_ALPHA;
298 case PIPE_BLENDFACTOR_DST_COLOR:
299 return V_028780_BLEND_DST_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE;
302 case PIPE_BLENDFACTOR_CONST_COLOR:
303 return V_028780_BLEND_CONSTANT_COLOR;
304 case PIPE_BLENDFACTOR_CONST_ALPHA:
305 return V_028780_BLEND_CONSTANT_ALPHA;
306 case PIPE_BLENDFACTOR_ZERO:
307 return V_028780_BLEND_ZERO;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_SRC1_COLOR:
321 return V_028780_BLEND_SRC1_COLOR;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA:
323 return V_028780_BLEND_SRC1_ALPHA;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
325 return V_028780_BLEND_INV_SRC1_COLOR;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
327 return V_028780_BLEND_INV_SRC1_ALPHA;
328 default:
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
330 assert(0);
331 break;
332 }
333 return 0;
334 }
335
336 static uint32_t si_translate_blend_opt_function(int blend_func)
337 {
338 switch (blend_func) {
339 case PIPE_BLEND_ADD:
340 return V_028760_OPT_COMB_ADD;
341 case PIPE_BLEND_SUBTRACT:
342 return V_028760_OPT_COMB_SUBTRACT;
343 case PIPE_BLEND_REVERSE_SUBTRACT:
344 return V_028760_OPT_COMB_REVSUBTRACT;
345 case PIPE_BLEND_MIN:
346 return V_028760_OPT_COMB_MIN;
347 case PIPE_BLEND_MAX:
348 return V_028760_OPT_COMB_MAX;
349 default:
350 return V_028760_OPT_COMB_BLEND_DISABLED;
351 }
352 }
353
354 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
355 {
356 switch (blend_fact) {
357 case PIPE_BLENDFACTOR_ZERO:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
359 case PIPE_BLENDFACTOR_ONE:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
361 case PIPE_BLENDFACTOR_SRC_COLOR:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
365 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
367 case PIPE_BLENDFACTOR_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
372 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
374 default:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
376 }
377 }
378
379 static void si_blend_check_commutativity(struct si_screen *sscreen,
380 struct si_state_blend *blend,
381 enum pipe_blend_func func,
382 enum pipe_blendfactor src,
383 enum pipe_blendfactor dst,
384 unsigned chanmask)
385 {
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed =
388 (1u << PIPE_BLENDFACTOR_ONE) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_ZERO) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
403
404 if (dst == PIPE_BLENDFACTOR_ONE &&
405 (src_allowed & (1u << src))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
408 * rounding.
409 *
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
413 * setting.
414 */
415 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
416 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
417 blend->commutative_4bit |= chanmask;
418 }
419 }
420
421 /**
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
424 */
425 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
426 unsigned *dst_factor, unsigned expected_dst,
427 unsigned replacement_src)
428 {
429 if (*src_factor == expected_dst &&
430 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
431 *src_factor = PIPE_BLENDFACTOR_ZERO;
432 *dst_factor = replacement_src;
433
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func == PIPE_BLEND_SUBTRACT)
436 *func = PIPE_BLEND_REVERSE_SUBTRACT;
437 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
438 *func = PIPE_BLEND_SUBTRACT;
439 }
440 }
441
442 static bool si_blend_factor_uses_dst(unsigned factor)
443 {
444 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
445 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
446 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
447 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
448 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
449 }
450
451 static void *si_create_blend_state_mode(struct pipe_context *ctx,
452 const struct pipe_blend_state *state,
453 unsigned mode)
454 {
455 struct si_context *sctx = (struct si_context*)ctx;
456 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
457 struct si_pm4_state *pm4 = &blend->pm4;
458 uint32_t sx_mrt_blend_opt[8] = {0};
459 uint32_t color_control = 0;
460
461 if (!blend)
462 return NULL;
463
464 blend->alpha_to_coverage = state->alpha_to_coverage;
465 blend->alpha_to_one = state->alpha_to_one;
466 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
467 blend->logicop_enable = state->logicop_enable;
468
469 if (state->logicop_enable) {
470 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
471 } else {
472 color_control |= S_028808_ROP3(0xcc);
473 }
474
475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
481 S_028B70_OFFSET_ROUND(1));
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < 8; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
506
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i >= 1 && blend->dual_src_blend) {
509 /* Vulkan does this for dual source blending. */
510 if (i == 1)
511 blend_cntl |= S_028780_ENABLE(1);
512
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
519 */
520 if (blend->dual_src_blend &&
521 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
522 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* cb_render_state will disable unused ones */
529 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
530 if (state->rt[j].colormask)
531 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
532
533 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
535 continue;
536 }
537
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
540 si_blend_check_commutativity(sctx->screen, blend,
541 eqA, srcA, dstA, 0x8 << (4 * i));
542
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
545 *
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 */
549 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_COLOR,
554 PIPE_BLENDFACTOR_SRC_COLOR);
555 si_blend_remove_dst(&eqA, &srcA, &dstA,
556 PIPE_BLENDFACTOR_DST_ALPHA,
557 PIPE_BLENDFACTOR_SRC_ALPHA);
558
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
561 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
562 srcA_opt = si_translate_blend_opt_factor(srcA, true);
563 dstA_opt = si_translate_blend_opt_factor(dstA, true);
564
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568 if (si_blend_factor_uses_dst(srcA))
569 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
570
571 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
572 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
574 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
576
577 /* Set the final value. */
578 sx_mrt_blend_opt[i] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt) |
583 S_028760_ALPHA_DST_OPT(dstA_opt) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
585
586 /* Set blend state. */
587 blend_cntl |= S_028780_ENABLE(1);
588 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
589 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
590 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
591
592 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
593 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
595 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
596 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
597 }
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599
600 blend->blend_enable_4bit |= 0xfu << (i * 4);
601
602 /* This is only important for formats without alpha. */
603 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
605 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
607 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
608 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
609 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
610 }
611
612 if (blend->cb_target_mask) {
613 color_control |= S_028808_MODE(mode);
614 } else {
615 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
616 }
617
618 if (sctx->screen->rbplus_allowed) {
619 /* Disable RB+ blend optimizations for dual source blending.
620 * Vulkan does this.
621 */
622 if (blend->dual_src_blend) {
623 for (int i = 0; i < 8; i++) {
624 sx_mrt_blend_opt[i] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
627 }
628 }
629
630 for (int i = 0; i < 8; i++)
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
632 sx_mrt_blend_opt[i]);
633
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend->dual_src_blend || state->logicop_enable ||
636 mode == V_028808_CB_RESOLVE)
637 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
638 }
639
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
641 return blend;
642 }
643
644 static void *si_create_blend_state(struct pipe_context *ctx,
645 const struct pipe_blend_state *state)
646 {
647 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
648 }
649
650 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 struct si_state_blend *old_blend = sctx->queued.named.blend;
654 struct si_state_blend *blend = (struct si_state_blend *)state;
655
656 if (!state)
657 return;
658
659 si_pm4_bind_state(sctx, blend, state);
660
661 if (!old_blend ||
662 old_blend->cb_target_mask != blend->cb_target_mask ||
663 old_blend->dual_src_blend != blend->dual_src_blend ||
664 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
665 sctx->framebuffer.nr_samples >= 2 &&
666 sctx->screen->dcc_msaa_allowed))
667 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
668
669 if (!old_blend ||
670 old_blend->cb_target_mask != blend->cb_target_mask ||
671 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
672 old_blend->alpha_to_one != blend->alpha_to_one ||
673 old_blend->dual_src_blend != blend->dual_src_blend ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
676 sctx->do_update_shaders = true;
677
678 if (sctx->screen->dpbb_allowed &&
679 (!old_blend ||
680 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
681 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
682 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
683 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
684
685 if (sctx->screen->has_out_of_order_rast &&
686 (!old_blend ||
687 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
688 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
689 old_blend->commutative_4bit != blend->commutative_4bit ||
690 old_blend->logicop_enable != blend->logicop_enable)))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
692 }
693
694 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
698 }
699
700 static void si_set_blend_color(struct pipe_context *ctx,
701 const struct pipe_blend_color *state)
702 {
703 struct si_context *sctx = (struct si_context *)ctx;
704 static const struct pipe_blend_color zeros;
705
706 sctx->blend_color.state = *state;
707 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
708 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
709 }
710
711 static void si_emit_blend_color(struct si_context *sctx)
712 {
713 struct radeon_cmdbuf *cs = sctx->gfx_cs;
714
715 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
716 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
717 }
718
719 /*
720 * Clipping
721 */
722
723 static void si_set_clip_state(struct pipe_context *ctx,
724 const struct pipe_clip_state *state)
725 {
726 struct si_context *sctx = (struct si_context *)ctx;
727 struct pipe_constant_buffer cb;
728 static const struct pipe_clip_state zeros;
729
730 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
731 return;
732
733 sctx->clip_state.state = *state;
734 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
735 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
736
737 cb.buffer = NULL;
738 cb.user_buffer = state->ucp;
739 cb.buffer_offset = 0;
740 cb.buffer_size = 4*4*8;
741 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
742 pipe_resource_reference(&cb.buffer, NULL);
743 }
744
745 static void si_emit_clip_state(struct si_context *sctx)
746 {
747 struct radeon_cmdbuf *cs = sctx->gfx_cs;
748
749 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
750 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
751 }
752
753 static void si_emit_clip_regs(struct si_context *sctx)
754 {
755 struct si_shader *vs = si_get_vs_state(sctx);
756 struct si_shader_selector *vs_sel = vs->selector;
757 struct tgsi_shader_info *info = &vs_sel->info;
758 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
759 unsigned window_space =
760 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
761 unsigned clipdist_mask = vs_sel->clipdist_mask;
762 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
763 unsigned culldist_mask = vs_sel->culldist_mask;
764 unsigned total_mask;
765
766 if (vs->key.opt.clip_disable) {
767 assert(!info->culldist_writemask);
768 clipdist_mask = 0;
769 culldist_mask = 0;
770 }
771 total_mask = clipdist_mask | culldist_mask;
772
773 /* Clip distances on points have no effect, so need to be implemented
774 * as cull distances. This applies for the clipvertex case as well.
775 *
776 * Setting this for primitives other than points should have no adverse
777 * effects.
778 */
779 clipdist_mask &= rs->clip_plane_enable;
780 culldist_mask |= clipdist_mask;
781
782 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
783 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
784 SI_TRACKED_PA_CL_VS_OUT_CNTL,
785 vs_sel->pa_cl_vs_out_cntl |
786 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
787 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
788 clipdist_mask | (culldist_mask << 8));
789 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
790 SI_TRACKED_PA_CL_CLIP_CNTL,
791 rs->pa_cl_clip_cntl |
792 ucp_mask |
793 S_028810_CLIP_DISABLE(window_space));
794
795 if (initial_cdw != sctx->gfx_cs->current.cdw)
796 sctx->context_roll = true;
797 }
798
799 /*
800 * inferred state between framebuffer and rasterizer
801 */
802 static void si_update_poly_offset_state(struct si_context *sctx)
803 {
804 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
805
806 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
807 si_pm4_bind_state(sctx, poly_offset, NULL);
808 return;
809 }
810
811 /* Use the user format, not db_render_format, so that the polygon
812 * offset behaves as expected by applications.
813 */
814 switch (sctx->framebuffer.state.zsbuf->texture->format) {
815 case PIPE_FORMAT_Z16_UNORM:
816 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
817 break;
818 default: /* 24-bit */
819 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
820 break;
821 case PIPE_FORMAT_Z32_FLOAT:
822 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
823 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
824 break;
825 }
826 }
827
828 /*
829 * Rasterizer
830 */
831
832 static uint32_t si_translate_fill(uint32_t func)
833 {
834 switch(func) {
835 case PIPE_POLYGON_MODE_FILL:
836 return V_028814_X_DRAW_TRIANGLES;
837 case PIPE_POLYGON_MODE_LINE:
838 return V_028814_X_DRAW_LINES;
839 case PIPE_POLYGON_MODE_POINT:
840 return V_028814_X_DRAW_POINTS;
841 default:
842 assert(0);
843 return V_028814_X_DRAW_POINTS;
844 }
845 }
846
847 static void *si_create_rs_state(struct pipe_context *ctx,
848 const struct pipe_rasterizer_state *state)
849 {
850 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
851 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
852 struct si_pm4_state *pm4 = &rs->pm4;
853 unsigned tmp, i;
854 float psize_min, psize_max;
855
856 if (!rs) {
857 return NULL;
858 }
859
860 if (!state->front_ccw) {
861 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
862 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
863 } else {
864 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
865 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
866 }
867 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
868 rs->provoking_vertex_first = state->flatshade_first;
869 rs->scissor_enable = state->scissor;
870 rs->clip_halfz = state->clip_halfz;
871 rs->two_side = state->light_twoside;
872 rs->multisample_enable = state->multisample;
873 rs->force_persample_interp = state->force_persample_interp;
874 rs->clip_plane_enable = state->clip_plane_enable;
875 rs->half_pixel_center = state->half_pixel_center;
876 rs->line_stipple_enable = state->line_stipple_enable;
877 rs->poly_stipple_enable = state->poly_stipple_enable;
878 rs->line_smooth = state->line_smooth;
879 rs->line_width = state->line_width;
880 rs->poly_smooth = state->poly_smooth;
881 rs->uses_poly_offset = state->offset_point || state->offset_line ||
882 state->offset_tri;
883 rs->clamp_fragment_color = state->clamp_fragment_color;
884 rs->clamp_vertex_color = state->clamp_vertex_color;
885 rs->flatshade = state->flatshade;
886 rs->sprite_coord_enable = state->sprite_coord_enable;
887 rs->rasterizer_discard = state->rasterizer_discard;
888 rs->pa_sc_line_stipple = state->line_stipple_enable ?
889 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
890 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
891 rs->pa_cl_clip_cntl =
892 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
893 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
894 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
895 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
896 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
897
898 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
899 S_0286D4_FLAT_SHADE_ENA(1) |
900 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
901 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
902 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
903 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
904 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
905 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
906
907 /* point size 12.4 fixed point */
908 tmp = (unsigned)(state->point_size * 8.0);
909 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
910
911 if (state->point_size_per_vertex) {
912 psize_min = util_get_min_point_size(state);
913 psize_max = SI_MAX_POINT_SIZE;
914 } else {
915 /* Force the point size to be as if the vertex output was disabled. */
916 psize_min = state->point_size;
917 psize_max = state->point_size;
918 }
919 rs->max_point_size = psize_max;
920
921 /* Divide by two, because 0.5 = 1 pixel. */
922 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
923 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
924 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
925
926 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
927 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
928 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
929 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
930 S_028A48_MSAA_ENABLE(state->multisample ||
931 state->poly_smooth ||
932 state->line_smooth) |
933 S_028A48_VPORT_SCISSOR_ENABLE(1) |
934 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
935
936 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
937 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
938 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
939 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
940 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
941 S_028814_FACE(!state->front_ccw) |
942 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
943 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
944 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
945 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
946 state->fill_back != PIPE_POLYGON_MODE_FILL) |
947 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
948 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
949
950 if (!rs->uses_poly_offset)
951 return rs;
952
953 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
954 if (!rs->pm4_poly_offset) {
955 FREE(rs);
956 return NULL;
957 }
958
959 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
960 for (i = 0; i < 3; i++) {
961 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
962 float offset_units = state->offset_units;
963 float offset_scale = state->offset_scale * 16.0f;
964 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
965
966 if (!state->offset_units_unscaled) {
967 switch (i) {
968 case 0: /* 16-bit zbuffer */
969 offset_units *= 4.0f;
970 pa_su_poly_offset_db_fmt_cntl =
971 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
972 break;
973 case 1: /* 24-bit zbuffer */
974 offset_units *= 2.0f;
975 pa_su_poly_offset_db_fmt_cntl =
976 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
977 break;
978 case 2: /* 32-bit zbuffer */
979 offset_units *= 1.0f;
980 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
981 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
982 break;
983 }
984 }
985
986 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
987 fui(offset_scale));
988 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
989 fui(offset_units));
990 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
991 fui(offset_scale));
992 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
993 fui(offset_units));
994 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
995 pa_su_poly_offset_db_fmt_cntl);
996 }
997
998 return rs;
999 }
1000
1001 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1002 {
1003 struct si_context *sctx = (struct si_context *)ctx;
1004 struct si_state_rasterizer *old_rs =
1005 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1006 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1007
1008 if (!state)
1009 return;
1010
1011 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1012 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1013
1014 /* Update the small primitive filter workaround if necessary. */
1015 if (sctx->screen->has_msaa_sample_loc_bug &&
1016 sctx->framebuffer.nr_samples > 1)
1017 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1018 }
1019
1020 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1021 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1022
1023 si_pm4_bind_state(sctx, rasterizer, rs);
1024 si_update_poly_offset_state(sctx);
1025
1026 if (!old_rs ||
1027 old_rs->scissor_enable != rs->scissor_enable)
1028 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1029
1030 if (!old_rs ||
1031 old_rs->line_width != rs->line_width ||
1032 old_rs->max_point_size != rs->max_point_size ||
1033 old_rs->half_pixel_center != rs->half_pixel_center)
1034 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1035
1036 if (!old_rs ||
1037 old_rs->clip_halfz != rs->clip_halfz)
1038 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1039
1040 if (!old_rs ||
1041 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1042 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1043 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1044
1045 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1046 rs->line_stipple_enable;
1047
1048 if (!old_rs ||
1049 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1050 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1051 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1052 old_rs->flatshade != rs->flatshade ||
1053 old_rs->two_side != rs->two_side ||
1054 old_rs->multisample_enable != rs->multisample_enable ||
1055 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1056 old_rs->poly_smooth != rs->poly_smooth ||
1057 old_rs->line_smooth != rs->line_smooth ||
1058 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1059 old_rs->force_persample_interp != rs->force_persample_interp)
1060 sctx->do_update_shaders = true;
1061 }
1062
1063 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1064 {
1065 struct si_context *sctx = (struct si_context *)ctx;
1066 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1067
1068 if (sctx->queued.named.rasterizer == state)
1069 si_pm4_bind_state(sctx, poly_offset, NULL);
1070
1071 FREE(rs->pm4_poly_offset);
1072 si_pm4_delete_state(sctx, rasterizer, rs);
1073 }
1074
1075 /*
1076 * infeered state between dsa and stencil ref
1077 */
1078 static void si_emit_stencil_ref(struct si_context *sctx)
1079 {
1080 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1081 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1082 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1083
1084 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1085 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1086 S_028430_STENCILMASK(dsa->valuemask[0]) |
1087 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1088 S_028430_STENCILOPVAL(1));
1089 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1090 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1091 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1092 S_028434_STENCILOPVAL_BF(1));
1093 }
1094
1095 static void si_set_stencil_ref(struct pipe_context *ctx,
1096 const struct pipe_stencil_ref *state)
1097 {
1098 struct si_context *sctx = (struct si_context *)ctx;
1099
1100 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1101 return;
1102
1103 sctx->stencil_ref.state = *state;
1104 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1105 }
1106
1107
1108 /*
1109 * DSA
1110 */
1111
1112 static uint32_t si_translate_stencil_op(int s_op)
1113 {
1114 switch (s_op) {
1115 case PIPE_STENCIL_OP_KEEP:
1116 return V_02842C_STENCIL_KEEP;
1117 case PIPE_STENCIL_OP_ZERO:
1118 return V_02842C_STENCIL_ZERO;
1119 case PIPE_STENCIL_OP_REPLACE:
1120 return V_02842C_STENCIL_REPLACE_TEST;
1121 case PIPE_STENCIL_OP_INCR:
1122 return V_02842C_STENCIL_ADD_CLAMP;
1123 case PIPE_STENCIL_OP_DECR:
1124 return V_02842C_STENCIL_SUB_CLAMP;
1125 case PIPE_STENCIL_OP_INCR_WRAP:
1126 return V_02842C_STENCIL_ADD_WRAP;
1127 case PIPE_STENCIL_OP_DECR_WRAP:
1128 return V_02842C_STENCIL_SUB_WRAP;
1129 case PIPE_STENCIL_OP_INVERT:
1130 return V_02842C_STENCIL_INVERT;
1131 default:
1132 PRINT_ERR("Unknown stencil op %d", s_op);
1133 assert(0);
1134 break;
1135 }
1136 return 0;
1137 }
1138
1139 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1140 {
1141 return s->enabled && s->writemask &&
1142 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1143 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1144 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1145 }
1146
1147 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1148 {
1149 /* REPLACE is normally order invariant, except when the stencil
1150 * reference value is written by the fragment shader. Tracking this
1151 * interaction does not seem worth the effort, so be conservative. */
1152 return op != PIPE_STENCIL_OP_INCR &&
1153 op != PIPE_STENCIL_OP_DECR &&
1154 op != PIPE_STENCIL_OP_REPLACE;
1155 }
1156
1157 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1158 * invariant in the sense that the set of passing fragments as well as the
1159 * final stencil buffer result does not depend on the order of fragments. */
1160 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1161 {
1162 return !state->enabled || !state->writemask ||
1163 /* The following assumes that Z writes are disabled. */
1164 (state->func == PIPE_FUNC_ALWAYS &&
1165 si_order_invariant_stencil_op(state->zpass_op) &&
1166 si_order_invariant_stencil_op(state->zfail_op)) ||
1167 (state->func == PIPE_FUNC_NEVER &&
1168 si_order_invariant_stencil_op(state->fail_op));
1169 }
1170
1171 static void *si_create_dsa_state(struct pipe_context *ctx,
1172 const struct pipe_depth_stencil_alpha_state *state)
1173 {
1174 struct si_context *sctx = (struct si_context *)ctx;
1175 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1176 struct si_pm4_state *pm4 = &dsa->pm4;
1177 unsigned db_depth_control;
1178 uint32_t db_stencil_control = 0;
1179
1180 if (!dsa) {
1181 return NULL;
1182 }
1183
1184 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1185 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1186 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1187 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1188
1189 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1190 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1191 S_028800_ZFUNC(state->depth.func) |
1192 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1193
1194 /* stencil */
1195 if (state->stencil[0].enabled) {
1196 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1197 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1198 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1199 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1200 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1201
1202 if (state->stencil[1].enabled) {
1203 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1204 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1205 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1206 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1207 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1208 }
1209 }
1210
1211 /* alpha */
1212 if (state->alpha.enabled) {
1213 dsa->alpha_func = state->alpha.func;
1214
1215 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1216 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1217 } else {
1218 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1219 }
1220
1221 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1222 if (state->stencil[0].enabled)
1223 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1224 if (state->depth.bounds_test) {
1225 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1226 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1227 }
1228
1229 dsa->depth_enabled = state->depth.enabled;
1230 dsa->depth_write_enabled = state->depth.enabled &&
1231 state->depth.writemask;
1232 dsa->stencil_enabled = state->stencil[0].enabled;
1233 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1234 (si_dsa_writes_stencil(&state->stencil[0]) ||
1235 si_dsa_writes_stencil(&state->stencil[1]));
1236 dsa->db_can_write = dsa->depth_write_enabled ||
1237 dsa->stencil_write_enabled;
1238
1239 bool zfunc_is_ordered =
1240 state->depth.func == PIPE_FUNC_NEVER ||
1241 state->depth.func == PIPE_FUNC_LESS ||
1242 state->depth.func == PIPE_FUNC_LEQUAL ||
1243 state->depth.func == PIPE_FUNC_GREATER ||
1244 state->depth.func == PIPE_FUNC_GEQUAL;
1245
1246 bool nozwrite_and_order_invariant_stencil =
1247 !dsa->db_can_write ||
1248 (!dsa->depth_write_enabled &&
1249 si_order_invariant_stencil_state(&state->stencil[0]) &&
1250 si_order_invariant_stencil_state(&state->stencil[1]));
1251
1252 dsa->order_invariance[1].zs =
1253 nozwrite_and_order_invariant_stencil ||
1254 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1255 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1256
1257 dsa->order_invariance[1].pass_set =
1258 nozwrite_and_order_invariant_stencil ||
1259 (!dsa->stencil_write_enabled &&
1260 (state->depth.func == PIPE_FUNC_ALWAYS ||
1261 state->depth.func == PIPE_FUNC_NEVER));
1262 dsa->order_invariance[0].pass_set =
1263 !dsa->depth_write_enabled ||
1264 (state->depth.func == PIPE_FUNC_ALWAYS ||
1265 state->depth.func == PIPE_FUNC_NEVER);
1266
1267 dsa->order_invariance[1].pass_last =
1268 sctx->screen->assume_no_z_fights &&
1269 !dsa->stencil_write_enabled &&
1270 dsa->depth_write_enabled && zfunc_is_ordered;
1271 dsa->order_invariance[0].pass_last =
1272 sctx->screen->assume_no_z_fights &&
1273 dsa->depth_write_enabled && zfunc_is_ordered;
1274
1275 return dsa;
1276 }
1277
1278 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1279 {
1280 struct si_context *sctx = (struct si_context *)ctx;
1281 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1282 struct si_state_dsa *dsa = state;
1283
1284 if (!state)
1285 return;
1286
1287 si_pm4_bind_state(sctx, dsa, dsa);
1288
1289 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1290 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1291 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1292 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1293 }
1294
1295 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1296 sctx->do_update_shaders = true;
1297
1298 if (sctx->screen->dpbb_allowed &&
1299 (!old_dsa ||
1300 (old_dsa->depth_enabled != dsa->depth_enabled ||
1301 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1302 old_dsa->db_can_write != dsa->db_can_write)))
1303 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1304
1305 if (sctx->screen->has_out_of_order_rast &&
1306 (!old_dsa ||
1307 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1308 sizeof(old_dsa->order_invariance))))
1309 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1310 }
1311
1312 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1313 {
1314 struct si_context *sctx = (struct si_context *)ctx;
1315 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1316 }
1317
1318 static void *si_create_db_flush_dsa(struct si_context *sctx)
1319 {
1320 struct pipe_depth_stencil_alpha_state dsa = {};
1321
1322 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1323 }
1324
1325 /* DB RENDER STATE */
1326
1327 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1328 {
1329 struct si_context *sctx = (struct si_context*)ctx;
1330
1331 /* Pipeline stat & streamout queries. */
1332 if (enable) {
1333 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1334 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1335 } else {
1336 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1337 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1338 }
1339
1340 /* Occlusion queries. */
1341 if (sctx->occlusion_queries_disabled != !enable) {
1342 sctx->occlusion_queries_disabled = !enable;
1343 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1344 }
1345 }
1346
1347 void si_set_occlusion_query_state(struct si_context *sctx,
1348 bool old_perfect_enable)
1349 {
1350 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1351
1352 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1353
1354 if (perfect_enable != old_perfect_enable)
1355 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1356 }
1357
1358 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1359 {
1360 st->saved_compute = sctx->cs_shader_state.program;
1361
1362 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1363 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1364
1365 st->saved_ssbo_writable_mask = 0;
1366
1367 for (unsigned i = 0; i < 3; i++) {
1368 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1369 (1u << si_get_shaderbuf_slot(i)))
1370 st->saved_ssbo_writable_mask |= 1 << i;
1371 }
1372 }
1373
1374 static void si_emit_db_render_state(struct si_context *sctx)
1375 {
1376 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1377 unsigned db_shader_control, db_render_control, db_count_control;
1378 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1379
1380 /* DB_RENDER_CONTROL */
1381 if (sctx->dbcb_depth_copy_enabled ||
1382 sctx->dbcb_stencil_copy_enabled) {
1383 db_render_control =
1384 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1385 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1386 S_028000_COPY_CENTROID(1) |
1387 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1388 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1389 db_render_control =
1390 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1391 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1392 } else {
1393 db_render_control =
1394 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1395 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1396 }
1397
1398 /* DB_COUNT_CONTROL (occlusion queries) */
1399 if (sctx->num_occlusion_queries > 0 &&
1400 !sctx->occlusion_queries_disabled) {
1401 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1402
1403 if (sctx->chip_class >= GFX7) {
1404 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1405
1406 /* Stoney doesn't increment occlusion query counters
1407 * if the sample rate is 16x. Use 8x sample rate instead.
1408 */
1409 if (sctx->family == CHIP_STONEY)
1410 log_sample_rate = MIN2(log_sample_rate, 3);
1411
1412 db_count_control =
1413 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1414 S_028004_SAMPLE_RATE(log_sample_rate) |
1415 S_028004_ZPASS_ENABLE(1) |
1416 S_028004_SLICE_EVEN_ENABLE(1) |
1417 S_028004_SLICE_ODD_ENABLE(1);
1418 } else {
1419 db_count_control =
1420 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1421 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1422 }
1423 } else {
1424 /* Disable occlusion queries. */
1425 if (sctx->chip_class >= GFX7) {
1426 db_count_control = 0;
1427 } else {
1428 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1429 }
1430 }
1431
1432 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1433 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1434 db_count_control);
1435
1436 /* DB_RENDER_OVERRIDE2 */
1437 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1438 SI_TRACKED_DB_RENDER_OVERRIDE2,
1439 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1440 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1441 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1442
1443 db_shader_control = sctx->ps_db_shader_control;
1444
1445 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1446 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1447 db_shader_control &= C_02880C_Z_ORDER;
1448 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1449 }
1450
1451 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1452 if (!rs->multisample_enable)
1453 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1454
1455 if (sctx->screen->has_rbplus &&
1456 !sctx->screen->rbplus_allowed)
1457 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1458
1459 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1460 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1461
1462 if (initial_cdw != sctx->gfx_cs->current.cdw)
1463 sctx->context_roll = true;
1464 }
1465
1466 /*
1467 * format translation
1468 */
1469 static uint32_t si_translate_colorformat(enum pipe_format format)
1470 {
1471 const struct util_format_description *desc = util_format_description(format);
1472 if (!desc)
1473 return V_028C70_COLOR_INVALID;
1474
1475 #define HAS_SIZE(x,y,z,w) \
1476 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1477 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1478
1479 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1480 return V_028C70_COLOR_10_11_11;
1481
1482 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1483 return V_028C70_COLOR_INVALID;
1484
1485 /* hw cannot support mixed formats (except depth/stencil, since
1486 * stencil is not written to). */
1487 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1488 return V_028C70_COLOR_INVALID;
1489
1490 switch (desc->nr_channels) {
1491 case 1:
1492 switch (desc->channel[0].size) {
1493 case 8:
1494 return V_028C70_COLOR_8;
1495 case 16:
1496 return V_028C70_COLOR_16;
1497 case 32:
1498 return V_028C70_COLOR_32;
1499 }
1500 break;
1501 case 2:
1502 if (desc->channel[0].size == desc->channel[1].size) {
1503 switch (desc->channel[0].size) {
1504 case 8:
1505 return V_028C70_COLOR_8_8;
1506 case 16:
1507 return V_028C70_COLOR_16_16;
1508 case 32:
1509 return V_028C70_COLOR_32_32;
1510 }
1511 } else if (HAS_SIZE(8,24,0,0)) {
1512 return V_028C70_COLOR_24_8;
1513 } else if (HAS_SIZE(24,8,0,0)) {
1514 return V_028C70_COLOR_8_24;
1515 }
1516 break;
1517 case 3:
1518 if (HAS_SIZE(5,6,5,0)) {
1519 return V_028C70_COLOR_5_6_5;
1520 } else if (HAS_SIZE(32,8,24,0)) {
1521 return V_028C70_COLOR_X24_8_32_FLOAT;
1522 }
1523 break;
1524 case 4:
1525 if (desc->channel[0].size == desc->channel[1].size &&
1526 desc->channel[0].size == desc->channel[2].size &&
1527 desc->channel[0].size == desc->channel[3].size) {
1528 switch (desc->channel[0].size) {
1529 case 4:
1530 return V_028C70_COLOR_4_4_4_4;
1531 case 8:
1532 return V_028C70_COLOR_8_8_8_8;
1533 case 16:
1534 return V_028C70_COLOR_16_16_16_16;
1535 case 32:
1536 return V_028C70_COLOR_32_32_32_32;
1537 }
1538 } else if (HAS_SIZE(5,5,5,1)) {
1539 return V_028C70_COLOR_1_5_5_5;
1540 } else if (HAS_SIZE(1,5,5,5)) {
1541 return V_028C70_COLOR_5_5_5_1;
1542 } else if (HAS_SIZE(10,10,10,2)) {
1543 return V_028C70_COLOR_2_10_10_10;
1544 }
1545 break;
1546 }
1547 return V_028C70_COLOR_INVALID;
1548 }
1549
1550 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1551 {
1552 if (SI_BIG_ENDIAN) {
1553 switch(colorformat) {
1554 /* 8-bit buffers. */
1555 case V_028C70_COLOR_8:
1556 return V_028C70_ENDIAN_NONE;
1557
1558 /* 16-bit buffers. */
1559 case V_028C70_COLOR_5_6_5:
1560 case V_028C70_COLOR_1_5_5_5:
1561 case V_028C70_COLOR_4_4_4_4:
1562 case V_028C70_COLOR_16:
1563 case V_028C70_COLOR_8_8:
1564 return V_028C70_ENDIAN_8IN16;
1565
1566 /* 32-bit buffers. */
1567 case V_028C70_COLOR_8_8_8_8:
1568 case V_028C70_COLOR_2_10_10_10:
1569 case V_028C70_COLOR_8_24:
1570 case V_028C70_COLOR_24_8:
1571 case V_028C70_COLOR_16_16:
1572 return V_028C70_ENDIAN_8IN32;
1573
1574 /* 64-bit buffers. */
1575 case V_028C70_COLOR_16_16_16_16:
1576 return V_028C70_ENDIAN_8IN16;
1577
1578 case V_028C70_COLOR_32_32:
1579 return V_028C70_ENDIAN_8IN32;
1580
1581 /* 128-bit buffers. */
1582 case V_028C70_COLOR_32_32_32_32:
1583 return V_028C70_ENDIAN_8IN32;
1584 default:
1585 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1586 }
1587 } else {
1588 return V_028C70_ENDIAN_NONE;
1589 }
1590 }
1591
1592 static uint32_t si_translate_dbformat(enum pipe_format format)
1593 {
1594 switch (format) {
1595 case PIPE_FORMAT_Z16_UNORM:
1596 return V_028040_Z_16;
1597 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1598 case PIPE_FORMAT_X8Z24_UNORM:
1599 case PIPE_FORMAT_Z24X8_UNORM:
1600 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1601 return V_028040_Z_24; /* deprecated on AMD GCN */
1602 case PIPE_FORMAT_Z32_FLOAT:
1603 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1604 return V_028040_Z_32_FLOAT;
1605 default:
1606 return V_028040_Z_INVALID;
1607 }
1608 }
1609
1610 /*
1611 * Texture translation
1612 */
1613
1614 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1615 enum pipe_format format,
1616 const struct util_format_description *desc,
1617 int first_non_void)
1618 {
1619 struct si_screen *sscreen = (struct si_screen*)screen;
1620 bool uniform = true;
1621 int i;
1622
1623 assert(sscreen->info.chip_class <= GFX9);
1624
1625 /* Colorspace (return non-RGB formats directly). */
1626 switch (desc->colorspace) {
1627 /* Depth stencil formats */
1628 case UTIL_FORMAT_COLORSPACE_ZS:
1629 switch (format) {
1630 case PIPE_FORMAT_Z16_UNORM:
1631 return V_008F14_IMG_DATA_FORMAT_16;
1632 case PIPE_FORMAT_X24S8_UINT:
1633 case PIPE_FORMAT_S8X24_UINT:
1634 /*
1635 * Implemented as an 8_8_8_8 data format to fix texture
1636 * gathers in stencil sampling. This affects at least
1637 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1638 */
1639 if (sscreen->info.chip_class <= GFX8)
1640 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1641
1642 if (format == PIPE_FORMAT_X24S8_UINT)
1643 return V_008F14_IMG_DATA_FORMAT_8_24;
1644 else
1645 return V_008F14_IMG_DATA_FORMAT_24_8;
1646 case PIPE_FORMAT_Z24X8_UNORM:
1647 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1648 return V_008F14_IMG_DATA_FORMAT_8_24;
1649 case PIPE_FORMAT_X8Z24_UNORM:
1650 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1651 return V_008F14_IMG_DATA_FORMAT_24_8;
1652 case PIPE_FORMAT_S8_UINT:
1653 return V_008F14_IMG_DATA_FORMAT_8;
1654 case PIPE_FORMAT_Z32_FLOAT:
1655 return V_008F14_IMG_DATA_FORMAT_32;
1656 case PIPE_FORMAT_X32_S8X24_UINT:
1657 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1658 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1659 default:
1660 goto out_unknown;
1661 }
1662
1663 case UTIL_FORMAT_COLORSPACE_YUV:
1664 goto out_unknown; /* TODO */
1665
1666 case UTIL_FORMAT_COLORSPACE_SRGB:
1667 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1668 goto out_unknown;
1669 break;
1670
1671 default:
1672 break;
1673 }
1674
1675 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1676 if (!sscreen->info.has_format_bc1_through_bc7)
1677 goto out_unknown;
1678
1679 switch (format) {
1680 case PIPE_FORMAT_RGTC1_SNORM:
1681 case PIPE_FORMAT_LATC1_SNORM:
1682 case PIPE_FORMAT_RGTC1_UNORM:
1683 case PIPE_FORMAT_LATC1_UNORM:
1684 return V_008F14_IMG_DATA_FORMAT_BC4;
1685 case PIPE_FORMAT_RGTC2_SNORM:
1686 case PIPE_FORMAT_LATC2_SNORM:
1687 case PIPE_FORMAT_RGTC2_UNORM:
1688 case PIPE_FORMAT_LATC2_UNORM:
1689 return V_008F14_IMG_DATA_FORMAT_BC5;
1690 default:
1691 goto out_unknown;
1692 }
1693 }
1694
1695 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1696 (sscreen->info.family == CHIP_STONEY ||
1697 sscreen->info.family == CHIP_VEGA10 ||
1698 sscreen->info.family == CHIP_RAVEN)) {
1699 switch (format) {
1700 case PIPE_FORMAT_ETC1_RGB8:
1701 case PIPE_FORMAT_ETC2_RGB8:
1702 case PIPE_FORMAT_ETC2_SRGB8:
1703 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1704 case PIPE_FORMAT_ETC2_RGB8A1:
1705 case PIPE_FORMAT_ETC2_SRGB8A1:
1706 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1707 case PIPE_FORMAT_ETC2_RGBA8:
1708 case PIPE_FORMAT_ETC2_SRGBA8:
1709 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1710 case PIPE_FORMAT_ETC2_R11_UNORM:
1711 case PIPE_FORMAT_ETC2_R11_SNORM:
1712 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1713 case PIPE_FORMAT_ETC2_RG11_UNORM:
1714 case PIPE_FORMAT_ETC2_RG11_SNORM:
1715 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1716 default:
1717 goto out_unknown;
1718 }
1719 }
1720
1721 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1722 if (!sscreen->info.has_format_bc1_through_bc7)
1723 goto out_unknown;
1724
1725 switch (format) {
1726 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1727 case PIPE_FORMAT_BPTC_SRGBA:
1728 return V_008F14_IMG_DATA_FORMAT_BC7;
1729 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1730 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1731 return V_008F14_IMG_DATA_FORMAT_BC6;
1732 default:
1733 goto out_unknown;
1734 }
1735 }
1736
1737 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1738 switch (format) {
1739 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1740 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1741 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1742 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1743 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1744 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1745 default:
1746 goto out_unknown;
1747 }
1748 }
1749
1750 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1751 if (!sscreen->info.has_format_bc1_through_bc7)
1752 goto out_unknown;
1753
1754 switch (format) {
1755 case PIPE_FORMAT_DXT1_RGB:
1756 case PIPE_FORMAT_DXT1_RGBA:
1757 case PIPE_FORMAT_DXT1_SRGB:
1758 case PIPE_FORMAT_DXT1_SRGBA:
1759 return V_008F14_IMG_DATA_FORMAT_BC1;
1760 case PIPE_FORMAT_DXT3_RGBA:
1761 case PIPE_FORMAT_DXT3_SRGBA:
1762 return V_008F14_IMG_DATA_FORMAT_BC2;
1763 case PIPE_FORMAT_DXT5_RGBA:
1764 case PIPE_FORMAT_DXT5_SRGBA:
1765 return V_008F14_IMG_DATA_FORMAT_BC3;
1766 default:
1767 goto out_unknown;
1768 }
1769 }
1770
1771 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1772 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1773 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1774 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1775 }
1776
1777 /* R8G8Bx_SNORM - TODO CxV8U8 */
1778
1779 /* hw cannot support mixed formats (except depth/stencil, since only
1780 * depth is read).*/
1781 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1782 goto out_unknown;
1783
1784 /* See whether the components are of the same size. */
1785 for (i = 1; i < desc->nr_channels; i++) {
1786 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1787 }
1788
1789 /* Non-uniform formats. */
1790 if (!uniform) {
1791 switch(desc->nr_channels) {
1792 case 3:
1793 if (desc->channel[0].size == 5 &&
1794 desc->channel[1].size == 6 &&
1795 desc->channel[2].size == 5) {
1796 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1797 }
1798 goto out_unknown;
1799 case 4:
1800 if (desc->channel[0].size == 5 &&
1801 desc->channel[1].size == 5 &&
1802 desc->channel[2].size == 5 &&
1803 desc->channel[3].size == 1) {
1804 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1805 }
1806 if (desc->channel[0].size == 1 &&
1807 desc->channel[1].size == 5 &&
1808 desc->channel[2].size == 5 &&
1809 desc->channel[3].size == 5) {
1810 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1811 }
1812 if (desc->channel[0].size == 10 &&
1813 desc->channel[1].size == 10 &&
1814 desc->channel[2].size == 10 &&
1815 desc->channel[3].size == 2) {
1816 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1817 }
1818 goto out_unknown;
1819 }
1820 goto out_unknown;
1821 }
1822
1823 if (first_non_void < 0 || first_non_void > 3)
1824 goto out_unknown;
1825
1826 /* uniform formats */
1827 switch (desc->channel[first_non_void].size) {
1828 case 4:
1829 switch (desc->nr_channels) {
1830 #if 0 /* Not supported for render targets */
1831 case 2:
1832 return V_008F14_IMG_DATA_FORMAT_4_4;
1833 #endif
1834 case 4:
1835 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1836 }
1837 break;
1838 case 8:
1839 switch (desc->nr_channels) {
1840 case 1:
1841 return V_008F14_IMG_DATA_FORMAT_8;
1842 case 2:
1843 return V_008F14_IMG_DATA_FORMAT_8_8;
1844 case 4:
1845 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1846 }
1847 break;
1848 case 16:
1849 switch (desc->nr_channels) {
1850 case 1:
1851 return V_008F14_IMG_DATA_FORMAT_16;
1852 case 2:
1853 return V_008F14_IMG_DATA_FORMAT_16_16;
1854 case 4:
1855 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1856 }
1857 break;
1858 case 32:
1859 switch (desc->nr_channels) {
1860 case 1:
1861 return V_008F14_IMG_DATA_FORMAT_32;
1862 case 2:
1863 return V_008F14_IMG_DATA_FORMAT_32_32;
1864 #if 0 /* Not supported for render targets */
1865 case 3:
1866 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1867 #endif
1868 case 4:
1869 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1870 }
1871 }
1872
1873 out_unknown:
1874 return ~0;
1875 }
1876
1877 static unsigned si_tex_wrap(unsigned wrap)
1878 {
1879 switch (wrap) {
1880 default:
1881 case PIPE_TEX_WRAP_REPEAT:
1882 return V_008F30_SQ_TEX_WRAP;
1883 case PIPE_TEX_WRAP_CLAMP:
1884 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1885 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1886 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1887 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1888 return V_008F30_SQ_TEX_CLAMP_BORDER;
1889 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1890 return V_008F30_SQ_TEX_MIRROR;
1891 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1892 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1893 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1894 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1895 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1896 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1897 }
1898 }
1899
1900 static unsigned si_tex_mipfilter(unsigned filter)
1901 {
1902 switch (filter) {
1903 case PIPE_TEX_MIPFILTER_NEAREST:
1904 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1905 case PIPE_TEX_MIPFILTER_LINEAR:
1906 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1907 default:
1908 case PIPE_TEX_MIPFILTER_NONE:
1909 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1910 }
1911 }
1912
1913 static unsigned si_tex_compare(unsigned compare)
1914 {
1915 switch (compare) {
1916 default:
1917 case PIPE_FUNC_NEVER:
1918 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1919 case PIPE_FUNC_LESS:
1920 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1921 case PIPE_FUNC_EQUAL:
1922 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1923 case PIPE_FUNC_LEQUAL:
1924 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1925 case PIPE_FUNC_GREATER:
1926 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1927 case PIPE_FUNC_NOTEQUAL:
1928 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1929 case PIPE_FUNC_GEQUAL:
1930 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1931 case PIPE_FUNC_ALWAYS:
1932 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1933 }
1934 }
1935
1936 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1937 unsigned view_target, unsigned nr_samples)
1938 {
1939 unsigned res_target = tex->buffer.b.b.target;
1940
1941 if (view_target == PIPE_TEXTURE_CUBE ||
1942 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1943 res_target = view_target;
1944 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1945 else if (res_target == PIPE_TEXTURE_CUBE ||
1946 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1947 res_target = PIPE_TEXTURE_2D_ARRAY;
1948
1949 /* GFX9 allocates 1D textures as 2D. */
1950 if ((res_target == PIPE_TEXTURE_1D ||
1951 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1952 sscreen->info.chip_class >= GFX9 &&
1953 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1954 if (res_target == PIPE_TEXTURE_1D)
1955 res_target = PIPE_TEXTURE_2D;
1956 else
1957 res_target = PIPE_TEXTURE_2D_ARRAY;
1958 }
1959
1960 switch (res_target) {
1961 default:
1962 case PIPE_TEXTURE_1D:
1963 return V_008F1C_SQ_RSRC_IMG_1D;
1964 case PIPE_TEXTURE_1D_ARRAY:
1965 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1966 case PIPE_TEXTURE_2D:
1967 case PIPE_TEXTURE_RECT:
1968 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1969 V_008F1C_SQ_RSRC_IMG_2D;
1970 case PIPE_TEXTURE_2D_ARRAY:
1971 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1972 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1973 case PIPE_TEXTURE_3D:
1974 return V_008F1C_SQ_RSRC_IMG_3D;
1975 case PIPE_TEXTURE_CUBE:
1976 case PIPE_TEXTURE_CUBE_ARRAY:
1977 return V_008F1C_SQ_RSRC_IMG_CUBE;
1978 }
1979 }
1980
1981 /*
1982 * Format support testing
1983 */
1984
1985 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1986 {
1987 const struct util_format_description *desc = util_format_description(format);
1988 if (!desc)
1989 return false;
1990
1991 return si_translate_texformat(screen, format, desc,
1992 util_format_get_first_non_void_channel(format)) != ~0U;
1993 }
1994
1995 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1996 const struct util_format_description *desc,
1997 int first_non_void)
1998 {
1999 int i;
2000
2001 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2002
2003 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2004 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2005
2006 assert(first_non_void >= 0);
2007
2008 if (desc->nr_channels == 4 &&
2009 desc->channel[0].size == 10 &&
2010 desc->channel[1].size == 10 &&
2011 desc->channel[2].size == 10 &&
2012 desc->channel[3].size == 2)
2013 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2014
2015 /* See whether the components are of the same size. */
2016 for (i = 0; i < desc->nr_channels; i++) {
2017 if (desc->channel[first_non_void].size != desc->channel[i].size)
2018 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2019 }
2020
2021 switch (desc->channel[first_non_void].size) {
2022 case 8:
2023 switch (desc->nr_channels) {
2024 case 1:
2025 case 3: /* 3 loads */
2026 return V_008F0C_BUF_DATA_FORMAT_8;
2027 case 2:
2028 return V_008F0C_BUF_DATA_FORMAT_8_8;
2029 case 4:
2030 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2031 }
2032 break;
2033 case 16:
2034 switch (desc->nr_channels) {
2035 case 1:
2036 case 3: /* 3 loads */
2037 return V_008F0C_BUF_DATA_FORMAT_16;
2038 case 2:
2039 return V_008F0C_BUF_DATA_FORMAT_16_16;
2040 case 4:
2041 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2042 }
2043 break;
2044 case 32:
2045 switch (desc->nr_channels) {
2046 case 1:
2047 return V_008F0C_BUF_DATA_FORMAT_32;
2048 case 2:
2049 return V_008F0C_BUF_DATA_FORMAT_32_32;
2050 case 3:
2051 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2052 case 4:
2053 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2054 }
2055 break;
2056 case 64:
2057 /* Legacy double formats. */
2058 switch (desc->nr_channels) {
2059 case 1: /* 1 load */
2060 return V_008F0C_BUF_DATA_FORMAT_32_32;
2061 case 2: /* 1 load */
2062 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2063 case 3: /* 3 loads */
2064 return V_008F0C_BUF_DATA_FORMAT_32_32;
2065 case 4: /* 2 loads */
2066 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2067 }
2068 break;
2069 }
2070
2071 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2072 }
2073
2074 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2075 const struct util_format_description *desc,
2076 int first_non_void)
2077 {
2078 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2079
2080 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2081 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2082
2083 assert(first_non_void >= 0);
2084
2085 switch (desc->channel[first_non_void].type) {
2086 case UTIL_FORMAT_TYPE_SIGNED:
2087 case UTIL_FORMAT_TYPE_FIXED:
2088 if (desc->channel[first_non_void].size >= 32 ||
2089 desc->channel[first_non_void].pure_integer)
2090 return V_008F0C_BUF_NUM_FORMAT_SINT;
2091 else if (desc->channel[first_non_void].normalized)
2092 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2093 else
2094 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2095 break;
2096 case UTIL_FORMAT_TYPE_UNSIGNED:
2097 if (desc->channel[first_non_void].size >= 32 ||
2098 desc->channel[first_non_void].pure_integer)
2099 return V_008F0C_BUF_NUM_FORMAT_UINT;
2100 else if (desc->channel[first_non_void].normalized)
2101 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2102 else
2103 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2104 break;
2105 case UTIL_FORMAT_TYPE_FLOAT:
2106 default:
2107 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2108 }
2109 }
2110
2111 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2112 enum pipe_format format,
2113 unsigned usage)
2114 {
2115 const struct util_format_description *desc;
2116 int first_non_void;
2117 unsigned data_format;
2118
2119 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2120 PIPE_BIND_SAMPLER_VIEW |
2121 PIPE_BIND_VERTEX_BUFFER)) == 0);
2122
2123 desc = util_format_description(format);
2124 if (!desc)
2125 return 0;
2126
2127 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2128 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2129 * for read-only access (with caveats surrounding bounds checks), but
2130 * obviously fails for write access which we have to implement for
2131 * shader images. Luckily, OpenGL doesn't expect this to be supported
2132 * anyway, and so the only impact is on PBO uploads / downloads, which
2133 * shouldn't be expected to be fast for GL_RGB anyway.
2134 */
2135 if (desc->block.bits == 3 * 8 ||
2136 desc->block.bits == 3 * 16) {
2137 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2138 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2139 if (!usage)
2140 return 0;
2141 }
2142 }
2143
2144 first_non_void = util_format_get_first_non_void_channel(format);
2145 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2146 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2147 return 0;
2148
2149 return usage;
2150 }
2151
2152 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2153 {
2154 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2155 si_translate_colorswap(format, false) != ~0U;
2156 }
2157
2158 static bool si_is_zs_format_supported(enum pipe_format format)
2159 {
2160 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2161 }
2162
2163 static boolean si_is_format_supported(struct pipe_screen *screen,
2164 enum pipe_format format,
2165 enum pipe_texture_target target,
2166 unsigned sample_count,
2167 unsigned storage_sample_count,
2168 unsigned usage)
2169 {
2170 struct si_screen *sscreen = (struct si_screen *)screen;
2171 unsigned retval = 0;
2172
2173 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2174 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2175 return false;
2176 }
2177
2178 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2179 return false;
2180
2181 if (sample_count > 1) {
2182 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2183 return false;
2184
2185 if (usage & PIPE_BIND_SHADER_IMAGE)
2186 return false;
2187
2188 /* Only power-of-two sample counts are supported. */
2189 if (!util_is_power_of_two_or_zero(sample_count) ||
2190 !util_is_power_of_two_or_zero(storage_sample_count))
2191 return false;
2192
2193 /* MSAA support without framebuffer attachments. */
2194 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2195 return true;
2196
2197 if (!sscreen->info.has_eqaa_surface_allocator ||
2198 util_format_is_depth_or_stencil(format)) {
2199 /* Color without EQAA or depth/stencil. */
2200 if (sample_count > 8 ||
2201 sample_count != storage_sample_count)
2202 return false;
2203 } else {
2204 /* Color with EQAA. */
2205 if (sample_count > 16 ||
2206 storage_sample_count > 8)
2207 return false;
2208 }
2209 }
2210
2211 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2212 PIPE_BIND_SHADER_IMAGE)) {
2213 if (target == PIPE_BUFFER) {
2214 retval |= si_is_vertex_format_supported(
2215 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2216 PIPE_BIND_SHADER_IMAGE));
2217 } else {
2218 if (si_is_sampler_format_supported(screen, format))
2219 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2220 PIPE_BIND_SHADER_IMAGE);
2221 }
2222 }
2223
2224 if ((usage & (PIPE_BIND_RENDER_TARGET |
2225 PIPE_BIND_DISPLAY_TARGET |
2226 PIPE_BIND_SCANOUT |
2227 PIPE_BIND_SHARED |
2228 PIPE_BIND_BLENDABLE)) &&
2229 si_is_colorbuffer_format_supported(format)) {
2230 retval |= usage &
2231 (PIPE_BIND_RENDER_TARGET |
2232 PIPE_BIND_DISPLAY_TARGET |
2233 PIPE_BIND_SCANOUT |
2234 PIPE_BIND_SHARED);
2235 if (!util_format_is_pure_integer(format) &&
2236 !util_format_is_depth_or_stencil(format))
2237 retval |= usage & PIPE_BIND_BLENDABLE;
2238 }
2239
2240 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2241 si_is_zs_format_supported(format)) {
2242 retval |= PIPE_BIND_DEPTH_STENCIL;
2243 }
2244
2245 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2246 retval |= si_is_vertex_format_supported(screen, format,
2247 PIPE_BIND_VERTEX_BUFFER);
2248 }
2249
2250 if ((usage & PIPE_BIND_LINEAR) &&
2251 !util_format_is_compressed(format) &&
2252 !(usage & PIPE_BIND_DEPTH_STENCIL))
2253 retval |= PIPE_BIND_LINEAR;
2254
2255 return retval == usage;
2256 }
2257
2258 /*
2259 * framebuffer handling
2260 */
2261
2262 static void si_choose_spi_color_formats(struct si_surface *surf,
2263 unsigned format, unsigned swap,
2264 unsigned ntype, bool is_depth)
2265 {
2266 /* Alpha is needed for alpha-to-coverage.
2267 * Blending may be with or without alpha.
2268 */
2269 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2270 unsigned alpha = 0; /* exports alpha, but may not support blending */
2271 unsigned blend = 0; /* supports blending, but may not export alpha */
2272 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2273
2274 /* Choose the SPI color formats. These are required values for RB+.
2275 * Other chips have multiple choices, though they are not necessarily better.
2276 */
2277 switch (format) {
2278 case V_028C70_COLOR_5_6_5:
2279 case V_028C70_COLOR_1_5_5_5:
2280 case V_028C70_COLOR_5_5_5_1:
2281 case V_028C70_COLOR_4_4_4_4:
2282 case V_028C70_COLOR_10_11_11:
2283 case V_028C70_COLOR_11_11_10:
2284 case V_028C70_COLOR_8:
2285 case V_028C70_COLOR_8_8:
2286 case V_028C70_COLOR_8_8_8_8:
2287 case V_028C70_COLOR_10_10_10_2:
2288 case V_028C70_COLOR_2_10_10_10:
2289 if (ntype == V_028C70_NUMBER_UINT)
2290 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2291 else if (ntype == V_028C70_NUMBER_SINT)
2292 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2293 else
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2295 break;
2296
2297 case V_028C70_COLOR_16:
2298 case V_028C70_COLOR_16_16:
2299 case V_028C70_COLOR_16_16_16_16:
2300 if (ntype == V_028C70_NUMBER_UNORM ||
2301 ntype == V_028C70_NUMBER_SNORM) {
2302 /* UNORM16 and SNORM16 don't support blending */
2303 if (ntype == V_028C70_NUMBER_UNORM)
2304 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2305 else
2306 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2307
2308 /* Use 32 bits per channel for blending. */
2309 if (format == V_028C70_COLOR_16) {
2310 if (swap == V_028C70_SWAP_STD) { /* R */
2311 blend = V_028714_SPI_SHADER_32_R;
2312 blend_alpha = V_028714_SPI_SHADER_32_AR;
2313 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2314 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2315 else
2316 assert(0);
2317 } else if (format == V_028C70_COLOR_16_16) {
2318 if (swap == V_028C70_SWAP_STD) { /* RG */
2319 blend = V_028714_SPI_SHADER_32_GR;
2320 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2321 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2322 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2323 else
2324 assert(0);
2325 } else /* 16_16_16_16 */
2326 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2327 } else if (ntype == V_028C70_NUMBER_UINT)
2328 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2329 else if (ntype == V_028C70_NUMBER_SINT)
2330 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2331 else if (ntype == V_028C70_NUMBER_FLOAT)
2332 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2333 else
2334 assert(0);
2335 break;
2336
2337 case V_028C70_COLOR_32:
2338 if (swap == V_028C70_SWAP_STD) { /* R */
2339 blend = normal = V_028714_SPI_SHADER_32_R;
2340 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2341 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2342 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2343 else
2344 assert(0);
2345 break;
2346
2347 case V_028C70_COLOR_32_32:
2348 if (swap == V_028C70_SWAP_STD) { /* RG */
2349 blend = normal = V_028714_SPI_SHADER_32_GR;
2350 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2351 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2352 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2353 else
2354 assert(0);
2355 break;
2356
2357 case V_028C70_COLOR_32_32_32_32:
2358 case V_028C70_COLOR_8_24:
2359 case V_028C70_COLOR_24_8:
2360 case V_028C70_COLOR_X24_8_32_FLOAT:
2361 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2362 break;
2363
2364 default:
2365 assert(0);
2366 return;
2367 }
2368
2369 /* The DB->CB copy needs 32_ABGR. */
2370 if (is_depth)
2371 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2372
2373 surf->spi_shader_col_format = normal;
2374 surf->spi_shader_col_format_alpha = alpha;
2375 surf->spi_shader_col_format_blend = blend;
2376 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2377 }
2378
2379 static void si_initialize_color_surface(struct si_context *sctx,
2380 struct si_surface *surf)
2381 {
2382 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2383 unsigned color_info, color_attrib;
2384 unsigned format, swap, ntype, endian;
2385 const struct util_format_description *desc;
2386 int firstchan;
2387 unsigned blend_clamp = 0, blend_bypass = 0;
2388
2389 desc = util_format_description(surf->base.format);
2390 for (firstchan = 0; firstchan < 4; firstchan++) {
2391 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2392 break;
2393 }
2394 }
2395 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2396 ntype = V_028C70_NUMBER_FLOAT;
2397 } else {
2398 ntype = V_028C70_NUMBER_UNORM;
2399 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2400 ntype = V_028C70_NUMBER_SRGB;
2401 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2402 if (desc->channel[firstchan].pure_integer) {
2403 ntype = V_028C70_NUMBER_SINT;
2404 } else {
2405 assert(desc->channel[firstchan].normalized);
2406 ntype = V_028C70_NUMBER_SNORM;
2407 }
2408 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2409 if (desc->channel[firstchan].pure_integer) {
2410 ntype = V_028C70_NUMBER_UINT;
2411 } else {
2412 assert(desc->channel[firstchan].normalized);
2413 ntype = V_028C70_NUMBER_UNORM;
2414 }
2415 }
2416 }
2417
2418 format = si_translate_colorformat(surf->base.format);
2419 if (format == V_028C70_COLOR_INVALID) {
2420 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2421 }
2422 assert(format != V_028C70_COLOR_INVALID);
2423 swap = si_translate_colorswap(surf->base.format, false);
2424 endian = si_colorformat_endian_swap(format);
2425
2426 /* blend clamp should be set for all NORM/SRGB types */
2427 if (ntype == V_028C70_NUMBER_UNORM ||
2428 ntype == V_028C70_NUMBER_SNORM ||
2429 ntype == V_028C70_NUMBER_SRGB)
2430 blend_clamp = 1;
2431
2432 /* set blend bypass according to docs if SINT/UINT or
2433 8/24 COLOR variants */
2434 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2435 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2436 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2437 blend_clamp = 0;
2438 blend_bypass = 1;
2439 }
2440
2441 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2442 if (format == V_028C70_COLOR_8 ||
2443 format == V_028C70_COLOR_8_8 ||
2444 format == V_028C70_COLOR_8_8_8_8)
2445 surf->color_is_int8 = true;
2446 else if (format == V_028C70_COLOR_10_10_10_2 ||
2447 format == V_028C70_COLOR_2_10_10_10)
2448 surf->color_is_int10 = true;
2449 }
2450
2451 color_info = S_028C70_FORMAT(format) |
2452 S_028C70_COMP_SWAP(swap) |
2453 S_028C70_BLEND_CLAMP(blend_clamp) |
2454 S_028C70_BLEND_BYPASS(blend_bypass) |
2455 S_028C70_SIMPLE_FLOAT(1) |
2456 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2457 ntype != V_028C70_NUMBER_SNORM &&
2458 ntype != V_028C70_NUMBER_SRGB &&
2459 format != V_028C70_COLOR_8_24 &&
2460 format != V_028C70_COLOR_24_8) |
2461 S_028C70_NUMBER_TYPE(ntype) |
2462 S_028C70_ENDIAN(endian);
2463
2464 /* Intensity is implemented as Red, so treat it that way. */
2465 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2466 util_format_is_intensity(surf->base.format));
2467
2468 if (tex->buffer.b.b.nr_samples > 1) {
2469 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2470 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2471
2472 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2473 S_028C74_NUM_FRAGMENTS(log_fragments);
2474
2475 if (tex->fmask_offset) {
2476 color_info |= S_028C70_COMPRESSION(1);
2477 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2478
2479 if (sctx->chip_class == GFX6) {
2480 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2481 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2482 }
2483 }
2484 }
2485
2486 if (sctx->chip_class >= GFX8) {
2487 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2488 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2489
2490 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2491 64 for APU because all of our APUs to date use DIMMs which have
2492 a request granularity size of 64B while all other chips have a
2493 32B request size */
2494 if (!sctx->screen->info.has_dedicated_vram)
2495 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2496
2497 if (tex->buffer.b.b.nr_storage_samples > 1) {
2498 if (tex->surface.bpe == 1)
2499 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2500 else if (tex->surface.bpe == 2)
2501 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2502 }
2503
2504 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2505 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2506 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2507 }
2508
2509 /* This must be set for fast clear to work without FMASK. */
2510 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2511 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2512 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2513 }
2514
2515 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2516 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2517
2518 if (sctx->chip_class >= GFX9) {
2519 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2520
2521 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2522 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2523 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2524 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2525 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2526 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2527 }
2528
2529 surf->cb_color_view = color_view;
2530 surf->cb_color_info = color_info;
2531 surf->cb_color_attrib = color_attrib;
2532
2533 /* Determine pixel shader export format */
2534 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2535
2536 surf->color_initialized = true;
2537 }
2538
2539 static void si_init_depth_surface(struct si_context *sctx,
2540 struct si_surface *surf)
2541 {
2542 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2543 unsigned level = surf->base.u.tex.level;
2544 unsigned format, stencil_format;
2545 uint32_t z_info, s_info;
2546
2547 format = si_translate_dbformat(tex->db_render_format);
2548 stencil_format = tex->surface.has_stencil ?
2549 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2550
2551 assert(format != V_028040_Z_INVALID);
2552 if (format == V_028040_Z_INVALID)
2553 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2554
2555 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2556 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2557 surf->db_htile_data_base = 0;
2558 surf->db_htile_surface = 0;
2559
2560 if (sctx->chip_class >= GFX9) {
2561 assert(tex->surface.u.gfx9.surf_offset == 0);
2562 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2563 surf->db_stencil_base = (tex->buffer.gpu_address +
2564 tex->surface.u.gfx9.stencil_offset) >> 8;
2565 z_info = S_028038_FORMAT(format) |
2566 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2567 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2568 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2569 s_info = S_02803C_FORMAT(stencil_format) |
2570 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2571 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2572 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2573 surf->db_depth_view |= S_028008_MIPID(level);
2574 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2575 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2576
2577 if (si_htile_enabled(tex, level)) {
2578 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2579 S_028038_ALLOW_EXPCLEAR(1);
2580
2581 if (tex->tc_compatible_htile) {
2582 unsigned max_zplanes = 4;
2583
2584 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2585 tex->buffer.b.b.nr_samples > 1)
2586 max_zplanes = 2;
2587
2588 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2589 S_028038_ITERATE_FLUSH(1);
2590 s_info |= S_02803C_ITERATE_FLUSH(1);
2591 }
2592
2593 if (tex->surface.has_stencil) {
2594 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2595 * See that for explanation.
2596 */
2597 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2598 } else {
2599 /* Use all HTILE for depth if there's no stencil. */
2600 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2601 }
2602
2603 surf->db_htile_data_base = (tex->buffer.gpu_address +
2604 tex->htile_offset) >> 8;
2605 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2606 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2607 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2608 }
2609 } else {
2610 /* GFX6-GFX8 */
2611 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2612
2613 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2614
2615 surf->db_depth_base = (tex->buffer.gpu_address +
2616 tex->surface.u.legacy.level[level].offset) >> 8;
2617 surf->db_stencil_base = (tex->buffer.gpu_address +
2618 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2619
2620 z_info = S_028040_FORMAT(format) |
2621 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2622 s_info = S_028044_FORMAT(stencil_format);
2623 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2624
2625 if (sctx->chip_class >= GFX7) {
2626 struct radeon_info *info = &sctx->screen->info;
2627 unsigned index = tex->surface.u.legacy.tiling_index[level];
2628 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2629 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2630 unsigned tile_mode = info->si_tile_mode_array[index];
2631 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2632 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2633
2634 surf->db_depth_info |=
2635 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2636 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2637 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2638 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2639 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2640 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2641 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2642 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2643 } else {
2644 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2645 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2646 tile_mode_index = si_tile_mode_index(tex, level, true);
2647 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2648 }
2649
2650 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2651 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2652 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2653 levelinfo->nblk_y) / 64 - 1);
2654
2655 if (si_htile_enabled(tex, level)) {
2656 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2657 S_028040_ALLOW_EXPCLEAR(1);
2658
2659 if (tex->surface.has_stencil) {
2660 /* Workaround: For a not yet understood reason, the
2661 * combination of MSAA, fast stencil clear and stencil
2662 * decompress messes with subsequent stencil buffer
2663 * uses. Problem was reproduced on Verde, Bonaire,
2664 * Tonga, and Carrizo.
2665 *
2666 * Disabling EXPCLEAR works around the problem.
2667 *
2668 * Check piglit's arb_texture_multisample-stencil-clear
2669 * test if you want to try changing this.
2670 */
2671 if (tex->buffer.b.b.nr_samples <= 1)
2672 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2673 } else if (!tex->tc_compatible_htile) {
2674 /* Use all of the htile_buffer for depth if there's no stencil.
2675 * This must not be set when TC-compatible HTILE is enabled
2676 * due to a hw bug.
2677 */
2678 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2679 }
2680
2681 surf->db_htile_data_base = (tex->buffer.gpu_address +
2682 tex->htile_offset) >> 8;
2683 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2684
2685 if (tex->tc_compatible_htile) {
2686 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2687
2688 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2689 if (tex->buffer.b.b.nr_samples <= 1)
2690 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2691 else if (tex->buffer.b.b.nr_samples <= 4)
2692 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2693 else
2694 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2695 }
2696 }
2697 }
2698
2699 surf->db_z_info = z_info;
2700 surf->db_stencil_info = s_info;
2701
2702 surf->depth_initialized = true;
2703 }
2704
2705 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2706 {
2707 if (sctx->decompression_enabled)
2708 return;
2709
2710 if (sctx->framebuffer.state.zsbuf) {
2711 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2712 struct si_texture *tex = (struct si_texture *)surf->texture;
2713
2714 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2715
2716 if (tex->surface.has_stencil)
2717 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2718 }
2719
2720 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2721 while (compressed_cb_mask) {
2722 unsigned i = u_bit_scan(&compressed_cb_mask);
2723 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2724 struct si_texture *tex = (struct si_texture*)surf->texture;
2725
2726 if (tex->fmask_offset)
2727 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2728 if (tex->dcc_gather_statistics)
2729 tex->separate_dcc_dirty = true;
2730 }
2731 }
2732
2733 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2734 {
2735 for (int i = 0; i < state->nr_cbufs; ++i) {
2736 struct si_surface *surf = NULL;
2737 struct si_texture *tex;
2738
2739 if (!state->cbufs[i])
2740 continue;
2741 surf = (struct si_surface*)state->cbufs[i];
2742 tex = (struct si_texture*)surf->base.texture;
2743
2744 p_atomic_dec(&tex->framebuffers_bound);
2745 }
2746 }
2747
2748 static void si_set_framebuffer_state(struct pipe_context *ctx,
2749 const struct pipe_framebuffer_state *state)
2750 {
2751 struct si_context *sctx = (struct si_context *)ctx;
2752 struct si_surface *surf = NULL;
2753 struct si_texture *tex;
2754 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2755 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2756 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2757 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2758 bool old_has_stencil =
2759 old_has_zsbuf &&
2760 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2761 bool unbound = false;
2762 int i;
2763
2764 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2765 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2766 * We could implement the full workaround here, but it's a useless case.
2767 */
2768 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2769 unreachable("the framebuffer shouldn't have zero area");
2770 return;
2771 }
2772
2773 si_update_fb_dirtiness_after_rendering(sctx);
2774
2775 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2776 if (!sctx->framebuffer.state.cbufs[i])
2777 continue;
2778
2779 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2780 if (tex->dcc_gather_statistics)
2781 vi_separate_dcc_stop_query(sctx, tex);
2782 }
2783
2784 /* Disable DCC if the formats are incompatible. */
2785 for (i = 0; i < state->nr_cbufs; i++) {
2786 if (!state->cbufs[i])
2787 continue;
2788
2789 surf = (struct si_surface*)state->cbufs[i];
2790 tex = (struct si_texture*)surf->base.texture;
2791
2792 if (!surf->dcc_incompatible)
2793 continue;
2794
2795 /* Since the DCC decompression calls back into set_framebuffer-
2796 * _state, we need to unbind the framebuffer, so that
2797 * vi_separate_dcc_stop_query isn't called twice with the same
2798 * color buffer.
2799 */
2800 if (!unbound) {
2801 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2802 unbound = true;
2803 }
2804
2805 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2806 if (!si_texture_disable_dcc(sctx, tex))
2807 si_decompress_dcc(sctx, tex);
2808
2809 surf->dcc_incompatible = false;
2810 }
2811
2812 /* Only flush TC when changing the framebuffer state, because
2813 * the only client not using TC that can change textures is
2814 * the framebuffer.
2815 *
2816 * Wait for compute shaders because of possible transitions:
2817 * - FB write -> shader read
2818 * - shader write -> FB read
2819 *
2820 * DB caches are flushed on demand (using si_decompress_textures).
2821 *
2822 * When MSAA is enabled, CB and TC caches are flushed on demand
2823 * (after FMASK decompression). Shader write -> FB read transitions
2824 * cannot happen for MSAA textures, because MSAA shader images are
2825 * not supported.
2826 *
2827 * Only flush and wait for CB if there is actually a bound color buffer.
2828 */
2829 if (sctx->framebuffer.uncompressed_cb_mask) {
2830 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2831 sctx->framebuffer.CB_has_shader_readable_metadata,
2832 sctx->framebuffer.all_DCC_pipe_aligned);
2833 }
2834
2835 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2836
2837 /* u_blitter doesn't invoke depth decompression when it does multiple
2838 * blits in a row, but the only case when it matters for DB is when
2839 * doing generate_mipmap. So here we flush DB manually between
2840 * individual generate_mipmap blits.
2841 * Note that lower mipmap levels aren't compressed.
2842 */
2843 if (sctx->generate_mipmap_for_depth) {
2844 si_make_DB_shader_coherent(sctx, 1, false,
2845 sctx->framebuffer.DB_has_shader_readable_metadata);
2846 } else if (sctx->chip_class == GFX9) {
2847 /* It appears that DB metadata "leaks" in a sequence of:
2848 * - depth clear
2849 * - DCC decompress for shader image writes (with DB disabled)
2850 * - render with DEPTH_BEFORE_SHADER=1
2851 * Flushing DB metadata works around the problem.
2852 */
2853 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2854 }
2855
2856 /* Take the maximum of the old and new count. If the new count is lower,
2857 * dirtying is needed to disable the unbound colorbuffers.
2858 */
2859 sctx->framebuffer.dirty_cbufs |=
2860 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2861 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2862
2863 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2864 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2865
2866 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2867 sctx->framebuffer.spi_shader_col_format = 0;
2868 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2869 sctx->framebuffer.spi_shader_col_format_blend = 0;
2870 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2871 sctx->framebuffer.color_is_int8 = 0;
2872 sctx->framebuffer.color_is_int10 = 0;
2873
2874 sctx->framebuffer.compressed_cb_mask = 0;
2875 sctx->framebuffer.uncompressed_cb_mask = 0;
2876 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2877 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2878 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2879 sctx->framebuffer.any_dst_linear = false;
2880 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2881 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2882 sctx->framebuffer.all_DCC_pipe_aligned = true;
2883 unsigned num_bpp64_colorbufs = 0;
2884
2885 for (i = 0; i < state->nr_cbufs; i++) {
2886 if (!state->cbufs[i])
2887 continue;
2888
2889 surf = (struct si_surface*)state->cbufs[i];
2890 tex = (struct si_texture*)surf->base.texture;
2891
2892 if (!surf->color_initialized) {
2893 si_initialize_color_surface(sctx, surf);
2894 }
2895
2896 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2897 sctx->framebuffer.spi_shader_col_format |=
2898 surf->spi_shader_col_format << (i * 4);
2899 sctx->framebuffer.spi_shader_col_format_alpha |=
2900 surf->spi_shader_col_format_alpha << (i * 4);
2901 sctx->framebuffer.spi_shader_col_format_blend |=
2902 surf->spi_shader_col_format_blend << (i * 4);
2903 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2904 surf->spi_shader_col_format_blend_alpha << (i * 4);
2905
2906 if (surf->color_is_int8)
2907 sctx->framebuffer.color_is_int8 |= 1 << i;
2908 if (surf->color_is_int10)
2909 sctx->framebuffer.color_is_int10 |= 1 << i;
2910
2911 if (tex->fmask_offset)
2912 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2913 else
2914 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2915
2916 /* Don't update nr_color_samples for non-AA buffers.
2917 * (e.g. destination of MSAA resolve)
2918 */
2919 if (tex->buffer.b.b.nr_samples >= 2 &&
2920 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2921 sctx->framebuffer.nr_color_samples =
2922 MIN2(sctx->framebuffer.nr_color_samples,
2923 tex->buffer.b.b.nr_storage_samples);
2924 sctx->framebuffer.nr_color_samples =
2925 MAX2(1, sctx->framebuffer.nr_color_samples);
2926 }
2927
2928 if (tex->surface.is_linear)
2929 sctx->framebuffer.any_dst_linear = true;
2930 if (tex->surface.bpe >= 8)
2931 num_bpp64_colorbufs++;
2932
2933 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2934 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2935
2936 if (sctx->chip_class >= GFX9 &&
2937 !tex->surface.u.gfx9.dcc.pipe_aligned)
2938 sctx->framebuffer.all_DCC_pipe_aligned = false;
2939 }
2940
2941 si_context_add_resource_size(sctx, surf->base.texture);
2942
2943 p_atomic_inc(&tex->framebuffers_bound);
2944
2945 if (tex->dcc_gather_statistics) {
2946 /* Dirty tracking must be enabled for DCC usage analysis. */
2947 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2948 vi_separate_dcc_start_query(sctx, tex);
2949 }
2950 }
2951
2952 /* For optimal DCC performance. */
2953 if (sctx->chip_class == GFX8)
2954 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2955 else if (num_bpp64_colorbufs >= 5)
2956 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2957 else
2958 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2959
2960 struct si_texture *zstex = NULL;
2961
2962 if (state->zsbuf) {
2963 surf = (struct si_surface*)state->zsbuf;
2964 zstex = (struct si_texture*)surf->base.texture;
2965
2966 if (!surf->depth_initialized) {
2967 si_init_depth_surface(sctx, surf);
2968 }
2969
2970 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2971 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2972
2973 si_context_add_resource_size(sctx, surf->base.texture);
2974 }
2975
2976 si_update_ps_colorbuf0_slot(sctx);
2977 si_update_poly_offset_state(sctx);
2978 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2979 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2980
2981 if (sctx->screen->dpbb_allowed)
2982 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2983
2984 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2985 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2986
2987 if (sctx->screen->has_out_of_order_rast &&
2988 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2989 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2990 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2991 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2992
2993 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2994 struct pipe_constant_buffer constbuf = {0};
2995
2996 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2997 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2998
2999 constbuf.buffer = sctx->sample_pos_buffer;
3000
3001 /* Set sample locations as fragment shader constants. */
3002 switch (sctx->framebuffer.nr_samples) {
3003 case 1:
3004 constbuf.buffer_offset = 0;
3005 break;
3006 case 2:
3007 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3008 (ubyte*)sctx->sample_positions.x1;
3009 break;
3010 case 4:
3011 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3012 (ubyte*)sctx->sample_positions.x1;
3013 break;
3014 case 8:
3015 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3016 (ubyte*)sctx->sample_positions.x1;
3017 break;
3018 case 16:
3019 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3020 (ubyte*)sctx->sample_positions.x1;
3021 break;
3022 default:
3023 PRINT_ERR("Requested an invalid number of samples %i.\n",
3024 sctx->framebuffer.nr_samples);
3025 assert(0);
3026 }
3027 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3028 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3029
3030 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3031 }
3032
3033 sctx->do_update_shaders = true;
3034
3035 if (!sctx->decompression_enabled) {
3036 /* Prevent textures decompression when the framebuffer state
3037 * changes come from the decompression passes themselves.
3038 */
3039 sctx->need_check_render_feedback = true;
3040 }
3041 }
3042
3043 static void si_emit_framebuffer_state(struct si_context *sctx)
3044 {
3045 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3046 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3047 unsigned i, nr_cbufs = state->nr_cbufs;
3048 struct si_texture *tex = NULL;
3049 struct si_surface *cb = NULL;
3050 unsigned cb_color_info = 0;
3051
3052 /* Colorbuffers. */
3053 for (i = 0; i < nr_cbufs; i++) {
3054 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3055 unsigned cb_color_attrib;
3056
3057 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3058 continue;
3059
3060 cb = (struct si_surface*)state->cbufs[i];
3061 if (!cb) {
3062 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3063 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3064 continue;
3065 }
3066
3067 tex = (struct si_texture *)cb->base.texture;
3068 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3069 &tex->buffer, RADEON_USAGE_READWRITE,
3070 tex->buffer.b.b.nr_samples > 1 ?
3071 RADEON_PRIO_COLOR_BUFFER_MSAA :
3072 RADEON_PRIO_COLOR_BUFFER);
3073
3074 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3075 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3076 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3077 RADEON_PRIO_SEPARATE_META);
3078 }
3079
3080 if (tex->dcc_separate_buffer)
3081 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3082 tex->dcc_separate_buffer,
3083 RADEON_USAGE_READWRITE,
3084 RADEON_PRIO_SEPARATE_META);
3085
3086 /* Compute mutable surface parameters. */
3087 cb_color_base = tex->buffer.gpu_address >> 8;
3088 cb_color_fmask = 0;
3089 cb_color_cmask = tex->cmask_base_address_reg;
3090 cb_dcc_base = 0;
3091 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3092 cb_color_attrib = cb->cb_color_attrib;
3093
3094 if (cb->base.u.tex.level > 0)
3095 cb_color_info &= C_028C70_FAST_CLEAR;
3096
3097 if (tex->fmask_offset) {
3098 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3099 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3100 }
3101
3102 /* Set up DCC. */
3103 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3104 bool is_msaa_resolve_dst = state->cbufs[0] &&
3105 state->cbufs[0]->texture->nr_samples > 1 &&
3106 state->cbufs[1] == &cb->base &&
3107 state->cbufs[1]->texture->nr_samples <= 1;
3108
3109 if (!is_msaa_resolve_dst)
3110 cb_color_info |= S_028C70_DCC_ENABLE(1);
3111
3112 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3113 tex->dcc_offset) >> 8;
3114 cb_dcc_base |= tex->surface.tile_swizzle;
3115 }
3116
3117 if (sctx->chip_class >= GFX9) {
3118 struct gfx9_surf_meta_flags meta;
3119
3120 if (tex->dcc_offset)
3121 meta = tex->surface.u.gfx9.dcc;
3122 else
3123 meta = tex->surface.u.gfx9.cmask;
3124
3125 /* Set mutable surface parameters. */
3126 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3127 cb_color_base |= tex->surface.tile_swizzle;
3128 if (!tex->fmask_offset)
3129 cb_color_fmask = cb_color_base;
3130 if (cb->base.u.tex.level > 0)
3131 cb_color_cmask = cb_color_base;
3132 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3133 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3134 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3135 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3136
3137 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3138 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3139 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3140 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3141 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3142 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3143 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3144 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3145 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3146 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3147 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3148 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3149 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3150 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3151 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3152 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3153
3154 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3155 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3156 } else {
3157 /* Compute mutable surface parameters (GFX6-GFX8). */
3158 const struct legacy_surf_level *level_info =
3159 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3160 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3161 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3162
3163 cb_color_base += level_info->offset >> 8;
3164 /* Only macrotiled modes can set tile swizzle. */
3165 if (level_info->mode == RADEON_SURF_MODE_2D)
3166 cb_color_base |= tex->surface.tile_swizzle;
3167
3168 if (!tex->fmask_offset)
3169 cb_color_fmask = cb_color_base;
3170 if (cb->base.u.tex.level > 0)
3171 cb_color_cmask = cb_color_base;
3172 if (cb_dcc_base)
3173 cb_dcc_base += level_info->dcc_offset >> 8;
3174
3175 pitch_tile_max = level_info->nblk_x / 8 - 1;
3176 slice_tile_max = level_info->nblk_x *
3177 level_info->nblk_y / 64 - 1;
3178 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3179
3180 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3181 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3182 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3183
3184 if (tex->fmask_offset) {
3185 if (sctx->chip_class >= GFX7)
3186 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3187 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3188 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3189 } else {
3190 /* This must be set for fast clear to work without FMASK. */
3191 if (sctx->chip_class >= GFX7)
3192 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3193 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3194 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3195 }
3196
3197 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3198 sctx->chip_class >= GFX8 ? 14 : 13);
3199 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3200 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3201 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3202 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3203 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3204 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3205 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3206 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3207 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3208 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3209 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3210 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3211 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3212
3213 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3214 radeon_emit(cs, cb_dcc_base);
3215 }
3216 }
3217 for (; i < 8 ; i++)
3218 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3219 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3220
3221 /* ZS buffer. */
3222 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3223 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3224 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3225
3226 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3227 &tex->buffer, RADEON_USAGE_READWRITE,
3228 zb->base.texture->nr_samples > 1 ?
3229 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3230 RADEON_PRIO_DEPTH_BUFFER);
3231
3232 if (sctx->chip_class >= GFX9) {
3233 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3234 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3235 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3236 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3237
3238 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3239 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3240 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3241 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3242 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3243 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3244 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3245 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3246 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3247 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3248 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3249 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3250
3251 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3252 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3253 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3254 } else {
3255 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3256
3257 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3258 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3259 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3260 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3261 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3262 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3263 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3264 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3265 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3266 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3267 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3268 }
3269
3270 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3271 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3272 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3273
3274 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3275 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3276 } else if (sctx->framebuffer.dirty_zsbuf) {
3277 if (sctx->chip_class >= GFX9)
3278 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3279 else
3280 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3281
3282 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3283 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3284 }
3285
3286 /* Framebuffer dimensions. */
3287 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3288 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3289 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3290
3291 if (sctx->screen->dfsm_allowed) {
3292 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3293 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3294 }
3295
3296 sctx->framebuffer.dirty_cbufs = 0;
3297 sctx->framebuffer.dirty_zsbuf = false;
3298 }
3299
3300 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3301 {
3302 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3303 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3304 unsigned nr_samples = sctx->framebuffer.nr_samples;
3305 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3306
3307 /* Smoothing (only possible with nr_samples == 1) uses the same
3308 * sample locations as the MSAA it simulates.
3309 */
3310 if (nr_samples <= 1 && sctx->smoothing_enabled)
3311 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3312
3313 /* On Polaris, the small primitive filter uses the sample locations
3314 * even when MSAA is off, so we need to make sure they're set to 0.
3315 */
3316 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3317 nr_samples != sctx->sample_locs_num_samples) {
3318 sctx->sample_locs_num_samples = nr_samples;
3319 si_emit_sample_locations(cs, nr_samples);
3320 }
3321
3322 if (sctx->family >= CHIP_POLARIS10) {
3323 unsigned small_prim_filter_cntl =
3324 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3325 /* line bug */
3326 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3327
3328 /* The alternative of setting sample locations to 0 would
3329 * require a DB flush to avoid Z errors, see
3330 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3331 */
3332 if (has_msaa_sample_loc_bug &&
3333 sctx->framebuffer.nr_samples > 1 &&
3334 !rs->multisample_enable)
3335 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3336
3337 radeon_opt_set_context_reg(sctx,
3338 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3339 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3340 small_prim_filter_cntl);
3341 }
3342
3343 /* The exclusion bits can be set to improve rasterization efficiency
3344 * if no sample lies on the pixel boundary (-8 sample offset).
3345 */
3346 bool exclusion = sctx->chip_class >= GFX7 &&
3347 (!rs->multisample_enable || nr_samples != 16);
3348 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3349 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3350 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3351 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3352 }
3353
3354 static bool si_out_of_order_rasterization(struct si_context *sctx)
3355 {
3356 struct si_state_blend *blend = sctx->queued.named.blend;
3357 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3358
3359 if (!sctx->screen->has_out_of_order_rast)
3360 return false;
3361
3362 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3363
3364 if (blend) {
3365 colormask &= blend->cb_target_enabled_4bit;
3366 } else {
3367 colormask = 0;
3368 }
3369
3370 /* Conservative: No logic op. */
3371 if (colormask && blend->logicop_enable)
3372 return false;
3373
3374 struct si_dsa_order_invariance dsa_order_invariant = {
3375 .zs = true, .pass_set = true, .pass_last = false
3376 };
3377
3378 if (sctx->framebuffer.state.zsbuf) {
3379 struct si_texture *zstex =
3380 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3381 bool has_stencil = zstex->surface.has_stencil;
3382 dsa_order_invariant = dsa->order_invariance[has_stencil];
3383 if (!dsa_order_invariant.zs)
3384 return false;
3385
3386 /* The set of PS invocations is always order invariant,
3387 * except when early Z/S tests are requested. */
3388 if (sctx->ps_shader.cso &&
3389 sctx->ps_shader.cso->info.writes_memory &&
3390 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3391 !dsa_order_invariant.pass_set)
3392 return false;
3393
3394 if (sctx->num_perfect_occlusion_queries != 0 &&
3395 !dsa_order_invariant.pass_set)
3396 return false;
3397 }
3398
3399 if (!colormask)
3400 return true;
3401
3402 unsigned blendmask = colormask & blend->blend_enable_4bit;
3403
3404 if (blendmask) {
3405 /* Only commutative blending. */
3406 if (blendmask & ~blend->commutative_4bit)
3407 return false;
3408
3409 if (!dsa_order_invariant.pass_set)
3410 return false;
3411 }
3412
3413 if (colormask & ~blendmask) {
3414 if (!dsa_order_invariant.pass_last)
3415 return false;
3416 }
3417
3418 return true;
3419 }
3420
3421 static void si_emit_msaa_config(struct si_context *sctx)
3422 {
3423 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3424 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3425 /* 33% faster rendering to linear color buffers */
3426 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3427 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3428 unsigned sc_mode_cntl_1 =
3429 S_028A4C_WALK_SIZE(dst_is_linear) |
3430 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3431 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3432 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3433 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3434 /* always 1: */
3435 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3436 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3437 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3438 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3439 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3440 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3441 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3442 S_028804_INCOHERENT_EQAA_READS(1) |
3443 S_028804_INTERPOLATE_COMP_Z(1) |
3444 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3445 unsigned coverage_samples, color_samples, z_samples;
3446 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3447
3448 /* S: Coverage samples (up to 16x):
3449 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3450 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3451 *
3452 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3453 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3454 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3455 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3456 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3457 * # Z samples).
3458 *
3459 * F: Color samples (up to 8x, must be <= coverage samples):
3460 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3461 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3462 *
3463 * Can be anything between coverage and color samples:
3464 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3465 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3466 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3467 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3468 * # All are currently set the same as coverage samples.
3469 *
3470 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3471 * flag for undefined color samples. A shader-based resolve must handle unknowns
3472 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3473 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3474 * useful. The CB resolve always drops unknowns.
3475 *
3476 * Sensible AA configurations:
3477 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3478 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3479 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3480 * EQAA 8s 8z 8f = 8x MSAA
3481 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3482 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3483 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3484 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3485 * EQAA 4s 4z 4f = 4x MSAA
3486 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3487 * EQAA 2s 2z 2f = 2x MSAA
3488 */
3489 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3490 coverage_samples = sctx->framebuffer.nr_samples;
3491 color_samples = sctx->framebuffer.nr_color_samples;
3492
3493 if (sctx->framebuffer.state.zsbuf) {
3494 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3495 z_samples = MAX2(1, z_samples);
3496 } else {
3497 z_samples = coverage_samples;
3498 }
3499 } else if (sctx->smoothing_enabled) {
3500 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3501 } else {
3502 coverage_samples = color_samples = z_samples = 1;
3503 }
3504
3505 /* Required by OpenGL line rasterization.
3506 *
3507 * TODO: We should also enable perpendicular endcaps for AA lines,
3508 * but that requires implementing line stippling in the pixel
3509 * shader. SC can only do line stippling with axis-aligned
3510 * endcaps.
3511 */
3512 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3513 unsigned sc_aa_config = 0;
3514
3515 if (coverage_samples > 1) {
3516 /* distance from the pixel center, indexed by log2(nr_samples) */
3517 static unsigned max_dist[] = {
3518 0, /* unused */
3519 4, /* 2x MSAA */
3520 6, /* 4x MSAA */
3521 7, /* 8x MSAA */
3522 8, /* 16x MSAA */
3523 };
3524 unsigned log_samples = util_logbase2(coverage_samples);
3525 unsigned log_z_samples = util_logbase2(z_samples);
3526 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3527 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3528
3529 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3530 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3531 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3532 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3533
3534 if (sctx->framebuffer.nr_samples > 1) {
3535 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3536 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3537 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3538 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3539 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3540 } else if (sctx->smoothing_enabled) {
3541 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3542 }
3543 }
3544
3545 unsigned initial_cdw = cs->current.cdw;
3546
3547 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3548 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3549 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3550 sc_aa_config);
3551 /* R_028804_DB_EQAA */
3552 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3553 db_eqaa);
3554 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3555 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3556 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3557
3558 if (initial_cdw != cs->current.cdw) {
3559 sctx->context_roll = true;
3560
3561 /* GFX9: Flush DFSM when the AA mode changes. */
3562 if (sctx->screen->dfsm_allowed) {
3563 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3564 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3565 }
3566 }
3567 }
3568
3569 void si_update_ps_iter_samples(struct si_context *sctx)
3570 {
3571 if (sctx->framebuffer.nr_samples > 1)
3572 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3573 if (sctx->screen->dpbb_allowed)
3574 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3575 }
3576
3577 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3578 {
3579 struct si_context *sctx = (struct si_context *)ctx;
3580
3581 /* The hardware can only do sample shading with 2^n samples. */
3582 min_samples = util_next_power_of_two(min_samples);
3583
3584 if (sctx->ps_iter_samples == min_samples)
3585 return;
3586
3587 sctx->ps_iter_samples = min_samples;
3588 sctx->do_update_shaders = true;
3589
3590 si_update_ps_iter_samples(sctx);
3591 }
3592
3593 /*
3594 * Samplers
3595 */
3596
3597 /**
3598 * Build the sampler view descriptor for a buffer texture.
3599 * @param state 256-bit descriptor; only the high 128 bits are filled in
3600 */
3601 void
3602 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3603 enum pipe_format format,
3604 unsigned offset, unsigned size,
3605 uint32_t *state)
3606 {
3607 const struct util_format_description *desc;
3608 int first_non_void;
3609 unsigned stride;
3610 unsigned num_records;
3611 unsigned num_format, data_format;
3612
3613 desc = util_format_description(format);
3614 first_non_void = util_format_get_first_non_void_channel(format);
3615 stride = desc->block.bits / 8;
3616 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3617 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3618
3619 num_records = size / stride;
3620 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3621
3622 /* The NUM_RECORDS field has a different meaning depending on the chip,
3623 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3624 *
3625 * GFX6-GFX7:
3626 * - If STRIDE == 0, it's in byte units.
3627 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3628 *
3629 * GFX8:
3630 * - For SMEM and STRIDE == 0, it's in byte units.
3631 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3632 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3633 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3634 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3635 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3636 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3637 * That way the same descriptor can be used by both SMEM and VMEM.
3638 *
3639 * GFX9:
3640 * - For SMEM and STRIDE == 0, it's in byte units.
3641 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3642 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3643 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3644 */
3645 if (screen->info.chip_class >= GFX9 && HAVE_LLVM < 0x0800)
3646 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3647 * from STRIDE to bytes. This works around it by setting
3648 * NUM_RECORDS to at least the size of one element, so that
3649 * the first element is readable when IDXEN == 0.
3650 */
3651 num_records = num_records ? MAX2(num_records, stride) : 0;
3652 else if (screen->info.chip_class == GFX8)
3653 num_records *= stride;
3654
3655 state[4] = 0;
3656 state[5] = S_008F04_STRIDE(stride);
3657 state[6] = num_records;
3658 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3659 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3660 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3661 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3662 S_008F0C_NUM_FORMAT(num_format) |
3663 S_008F0C_DATA_FORMAT(data_format);
3664 }
3665
3666 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3667 {
3668 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3669
3670 if (swizzle[3] == PIPE_SWIZZLE_X) {
3671 /* For the pre-defined border color values (white, opaque
3672 * black, transparent black), the only thing that matters is
3673 * that the alpha channel winds up in the correct place
3674 * (because the RGB channels are all the same) so either of
3675 * these enumerations will work.
3676 */
3677 if (swizzle[2] == PIPE_SWIZZLE_Y)
3678 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3679 else
3680 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3681 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3682 if (swizzle[1] == PIPE_SWIZZLE_Y)
3683 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3684 else
3685 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3686 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3687 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3688 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3689 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3690 }
3691
3692 return bc_swizzle;
3693 }
3694
3695 /**
3696 * Build the sampler view descriptor for a texture.
3697 */
3698 void
3699 si_make_texture_descriptor(struct si_screen *screen,
3700 struct si_texture *tex,
3701 bool sampler,
3702 enum pipe_texture_target target,
3703 enum pipe_format pipe_format,
3704 const unsigned char state_swizzle[4],
3705 unsigned first_level, unsigned last_level,
3706 unsigned first_layer, unsigned last_layer,
3707 unsigned width, unsigned height, unsigned depth,
3708 uint32_t *state,
3709 uint32_t *fmask_state)
3710 {
3711 struct pipe_resource *res = &tex->buffer.b.b;
3712 const struct util_format_description *desc;
3713 unsigned char swizzle[4];
3714 int first_non_void;
3715 unsigned num_format, data_format, type, num_samples;
3716 uint64_t va;
3717
3718 desc = util_format_description(pipe_format);
3719
3720 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3721 MAX2(1, res->nr_samples) :
3722 MAX2(1, res->nr_storage_samples);
3723
3724 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3725 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3726 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3727 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3728
3729 switch (pipe_format) {
3730 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3731 case PIPE_FORMAT_X32_S8X24_UINT:
3732 case PIPE_FORMAT_X8Z24_UNORM:
3733 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3734 break;
3735 case PIPE_FORMAT_X24S8_UINT:
3736 /*
3737 * X24S8 is implemented as an 8_8_8_8 data format, to
3738 * fix texture gathers. This affects at least
3739 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3740 */
3741 if (screen->info.chip_class <= GFX8)
3742 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3743 else
3744 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3745 break;
3746 default:
3747 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3748 }
3749 } else {
3750 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3751 }
3752
3753 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3754
3755 switch (pipe_format) {
3756 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3757 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3758 break;
3759 default:
3760 if (first_non_void < 0) {
3761 if (util_format_is_compressed(pipe_format)) {
3762 switch (pipe_format) {
3763 case PIPE_FORMAT_DXT1_SRGB:
3764 case PIPE_FORMAT_DXT1_SRGBA:
3765 case PIPE_FORMAT_DXT3_SRGBA:
3766 case PIPE_FORMAT_DXT5_SRGBA:
3767 case PIPE_FORMAT_BPTC_SRGBA:
3768 case PIPE_FORMAT_ETC2_SRGB8:
3769 case PIPE_FORMAT_ETC2_SRGB8A1:
3770 case PIPE_FORMAT_ETC2_SRGBA8:
3771 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3772 break;
3773 case PIPE_FORMAT_RGTC1_SNORM:
3774 case PIPE_FORMAT_LATC1_SNORM:
3775 case PIPE_FORMAT_RGTC2_SNORM:
3776 case PIPE_FORMAT_LATC2_SNORM:
3777 case PIPE_FORMAT_ETC2_R11_SNORM:
3778 case PIPE_FORMAT_ETC2_RG11_SNORM:
3779 /* implies float, so use SNORM/UNORM to determine
3780 whether data is signed or not */
3781 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3782 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3783 break;
3784 default:
3785 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3786 break;
3787 }
3788 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3789 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3790 } else {
3791 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3792 }
3793 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3794 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3795 } else {
3796 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3797
3798 switch (desc->channel[first_non_void].type) {
3799 case UTIL_FORMAT_TYPE_FLOAT:
3800 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3801 break;
3802 case UTIL_FORMAT_TYPE_SIGNED:
3803 if (desc->channel[first_non_void].normalized)
3804 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3805 else if (desc->channel[first_non_void].pure_integer)
3806 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3807 else
3808 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3809 break;
3810 case UTIL_FORMAT_TYPE_UNSIGNED:
3811 if (desc->channel[first_non_void].normalized)
3812 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3813 else if (desc->channel[first_non_void].pure_integer)
3814 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3815 else
3816 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3817 }
3818 }
3819 }
3820
3821 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3822 if (data_format == ~0) {
3823 data_format = 0;
3824 }
3825
3826 /* S8 with Z32 HTILE needs a special format. */
3827 if (screen->info.chip_class >= GFX9 &&
3828 pipe_format == PIPE_FORMAT_S8_UINT &&
3829 tex->tc_compatible_htile)
3830 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3831
3832 if (!sampler &&
3833 (res->target == PIPE_TEXTURE_CUBE ||
3834 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3835 (screen->info.chip_class <= GFX8 &&
3836 res->target == PIPE_TEXTURE_3D))) {
3837 /* For the purpose of shader images, treat cube maps and 3D
3838 * textures as 2D arrays. For 3D textures, the address
3839 * calculations for mipmaps are different, so we rely on the
3840 * caller to effectively disable mipmaps.
3841 */
3842 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3843
3844 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3845 } else {
3846 type = si_tex_dim(screen, tex, target, num_samples);
3847 }
3848
3849 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3850 height = 1;
3851 depth = res->array_size;
3852 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3853 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3854 if (sampler || res->target != PIPE_TEXTURE_3D)
3855 depth = res->array_size;
3856 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3857 depth = res->array_size / 6;
3858
3859 state[0] = 0;
3860 state[1] = (S_008F14_DATA_FORMAT(data_format) |
3861 S_008F14_NUM_FORMAT(num_format));
3862 state[2] = (S_008F18_WIDTH(width - 1) |
3863 S_008F18_HEIGHT(height - 1) |
3864 S_008F18_PERF_MOD(4));
3865 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3866 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3867 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3868 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3869 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3870 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3871 util_logbase2(num_samples) :
3872 last_level) |
3873 S_008F1C_TYPE(type));
3874 state[4] = 0;
3875 state[5] = S_008F24_BASE_ARRAY(first_layer);
3876 state[6] = 0;
3877 state[7] = 0;
3878
3879 if (screen->info.chip_class >= GFX9) {
3880 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3881
3882 /* Depth is the the last accessible layer on Gfx9.
3883 * The hw doesn't need to know the total number of layers.
3884 */
3885 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3886 state[4] |= S_008F20_DEPTH(depth - 1);
3887 else
3888 state[4] |= S_008F20_DEPTH(last_layer);
3889
3890 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3891 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3892 util_logbase2(num_samples) :
3893 tex->buffer.b.b.last_level);
3894 } else {
3895 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3896 state[4] |= S_008F20_DEPTH(depth - 1);
3897 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3898 }
3899
3900 if (tex->dcc_offset) {
3901 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3902 } else {
3903 /* The last dword is unused by hw. The shader uses it to clear
3904 * bits in the first dword of sampler state.
3905 */
3906 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
3907 if (first_level == last_level)
3908 state[7] = C_008F30_MAX_ANISO_RATIO;
3909 else
3910 state[7] = 0xffffffff;
3911 }
3912 }
3913
3914 /* Initialize the sampler view for FMASK. */
3915 if (tex->fmask_offset) {
3916 uint32_t data_format, num_format;
3917
3918 va = tex->buffer.gpu_address + tex->fmask_offset;
3919
3920 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3921 if (screen->info.chip_class >= GFX9) {
3922 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3923 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3924 case FMASK(2,1):
3925 num_format = V_008F14_IMG_FMASK_8_2_1;
3926 break;
3927 case FMASK(2,2):
3928 num_format = V_008F14_IMG_FMASK_8_2_2;
3929 break;
3930 case FMASK(4,1):
3931 num_format = V_008F14_IMG_FMASK_8_4_1;
3932 break;
3933 case FMASK(4,2):
3934 num_format = V_008F14_IMG_FMASK_8_4_2;
3935 break;
3936 case FMASK(4,4):
3937 num_format = V_008F14_IMG_FMASK_8_4_4;
3938 break;
3939 case FMASK(8,1):
3940 num_format = V_008F14_IMG_FMASK_8_8_1;
3941 break;
3942 case FMASK(8,2):
3943 num_format = V_008F14_IMG_FMASK_16_8_2;
3944 break;
3945 case FMASK(8,4):
3946 num_format = V_008F14_IMG_FMASK_32_8_4;
3947 break;
3948 case FMASK(8,8):
3949 num_format = V_008F14_IMG_FMASK_32_8_8;
3950 break;
3951 case FMASK(16,1):
3952 num_format = V_008F14_IMG_FMASK_16_16_1;
3953 break;
3954 case FMASK(16,2):
3955 num_format = V_008F14_IMG_FMASK_32_16_2;
3956 break;
3957 case FMASK(16,4):
3958 num_format = V_008F14_IMG_FMASK_64_16_4;
3959 break;
3960 case FMASK(16,8):
3961 num_format = V_008F14_IMG_FMASK_64_16_8;
3962 break;
3963 default:
3964 unreachable("invalid nr_samples");
3965 }
3966 } else {
3967 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3968 case FMASK(2,1):
3969 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3970 break;
3971 case FMASK(2,2):
3972 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3973 break;
3974 case FMASK(4,1):
3975 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3976 break;
3977 case FMASK(4,2):
3978 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3979 break;
3980 case FMASK(4,4):
3981 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3982 break;
3983 case FMASK(8,1):
3984 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3985 break;
3986 case FMASK(8,2):
3987 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3988 break;
3989 case FMASK(8,4):
3990 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3991 break;
3992 case FMASK(8,8):
3993 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3994 break;
3995 case FMASK(16,1):
3996 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3997 break;
3998 case FMASK(16,2):
3999 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4000 break;
4001 case FMASK(16,4):
4002 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4003 break;
4004 case FMASK(16,8):
4005 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4006 break;
4007 default:
4008 unreachable("invalid nr_samples");
4009 }
4010 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4011 }
4012 #undef FMASK
4013
4014 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4015 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4016 S_008F14_DATA_FORMAT(data_format) |
4017 S_008F14_NUM_FORMAT(num_format);
4018 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4019 S_008F18_HEIGHT(height - 1);
4020 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4021 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4022 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4023 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4024 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4025 fmask_state[4] = 0;
4026 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4027 fmask_state[6] = 0;
4028 fmask_state[7] = 0;
4029
4030 if (screen->info.chip_class >= GFX9) {
4031 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4032 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4033 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4034 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4035 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4036 } else {
4037 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4038 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4039 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4040 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4041 }
4042 }
4043 }
4044
4045 /**
4046 * Create a sampler view.
4047 *
4048 * @param ctx context
4049 * @param texture texture
4050 * @param state sampler view template
4051 * @param width0 width0 override (for compressed textures as int)
4052 * @param height0 height0 override (for compressed textures as int)
4053 * @param force_level set the base address to the level (for compressed textures)
4054 */
4055 struct pipe_sampler_view *
4056 si_create_sampler_view_custom(struct pipe_context *ctx,
4057 struct pipe_resource *texture,
4058 const struct pipe_sampler_view *state,
4059 unsigned width0, unsigned height0,
4060 unsigned force_level)
4061 {
4062 struct si_context *sctx = (struct si_context*)ctx;
4063 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4064 struct si_texture *tex = (struct si_texture*)texture;
4065 unsigned base_level, first_level, last_level;
4066 unsigned char state_swizzle[4];
4067 unsigned height, depth, width;
4068 unsigned last_layer = state->u.tex.last_layer;
4069 enum pipe_format pipe_format;
4070 const struct legacy_surf_level *surflevel;
4071
4072 if (!view)
4073 return NULL;
4074
4075 /* initialize base object */
4076 view->base = *state;
4077 view->base.texture = NULL;
4078 view->base.reference.count = 1;
4079 view->base.context = ctx;
4080
4081 assert(texture);
4082 pipe_resource_reference(&view->base.texture, texture);
4083
4084 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4085 state->format == PIPE_FORMAT_S8X24_UINT ||
4086 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4087 state->format == PIPE_FORMAT_S8_UINT)
4088 view->is_stencil_sampler = true;
4089
4090 /* Buffer resource. */
4091 if (texture->target == PIPE_BUFFER) {
4092 si_make_buffer_descriptor(sctx->screen,
4093 si_resource(texture),
4094 state->format,
4095 state->u.buf.offset,
4096 state->u.buf.size,
4097 view->state);
4098 return &view->base;
4099 }
4100
4101 state_swizzle[0] = state->swizzle_r;
4102 state_swizzle[1] = state->swizzle_g;
4103 state_swizzle[2] = state->swizzle_b;
4104 state_swizzle[3] = state->swizzle_a;
4105
4106 base_level = 0;
4107 first_level = state->u.tex.first_level;
4108 last_level = state->u.tex.last_level;
4109 width = width0;
4110 height = height0;
4111 depth = texture->depth0;
4112
4113 if (sctx->chip_class <= GFX8 && force_level) {
4114 assert(force_level == first_level &&
4115 force_level == last_level);
4116 base_level = force_level;
4117 first_level = 0;
4118 last_level = 0;
4119 width = u_minify(width, force_level);
4120 height = u_minify(height, force_level);
4121 depth = u_minify(depth, force_level);
4122 }
4123
4124 /* This is not needed if state trackers set last_layer correctly. */
4125 if (state->target == PIPE_TEXTURE_1D ||
4126 state->target == PIPE_TEXTURE_2D ||
4127 state->target == PIPE_TEXTURE_RECT ||
4128 state->target == PIPE_TEXTURE_CUBE)
4129 last_layer = state->u.tex.first_layer;
4130
4131 /* Texturing with separate depth and stencil. */
4132 pipe_format = state->format;
4133
4134 /* Depth/stencil texturing sometimes needs separate texture. */
4135 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4136 if (!tex->flushed_depth_texture &&
4137 !si_init_flushed_depth_texture(ctx, texture)) {
4138 pipe_resource_reference(&view->base.texture, NULL);
4139 FREE(view);
4140 return NULL;
4141 }
4142
4143 assert(tex->flushed_depth_texture);
4144
4145 /* Override format for the case where the flushed texture
4146 * contains only Z or only S.
4147 */
4148 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4149 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4150
4151 tex = tex->flushed_depth_texture;
4152 }
4153
4154 surflevel = tex->surface.u.legacy.level;
4155
4156 if (tex->db_compatible) {
4157 if (!view->is_stencil_sampler)
4158 pipe_format = tex->db_render_format;
4159
4160 switch (pipe_format) {
4161 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4162 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4163 break;
4164 case PIPE_FORMAT_X8Z24_UNORM:
4165 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4166 /* Z24 is always stored like this for DB
4167 * compatibility.
4168 */
4169 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4170 break;
4171 case PIPE_FORMAT_X24S8_UINT:
4172 case PIPE_FORMAT_S8X24_UINT:
4173 case PIPE_FORMAT_X32_S8X24_UINT:
4174 pipe_format = PIPE_FORMAT_S8_UINT;
4175 surflevel = tex->surface.u.legacy.stencil_level;
4176 break;
4177 default:;
4178 }
4179 }
4180
4181 view->dcc_incompatible =
4182 vi_dcc_formats_are_incompatible(texture,
4183 state->u.tex.first_level,
4184 state->format);
4185
4186 si_make_texture_descriptor(sctx->screen, tex, true,
4187 state->target, pipe_format, state_swizzle,
4188 first_level, last_level,
4189 state->u.tex.first_layer, last_layer,
4190 width, height, depth,
4191 view->state, view->fmask_state);
4192
4193 unsigned num_format = G_008F14_NUM_FORMAT(view->state[1]);
4194 view->is_integer =
4195 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4196 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4197 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4198 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4199 view->base_level_info = &surflevel[base_level];
4200 view->base_level = base_level;
4201 view->block_width = util_format_get_blockwidth(pipe_format);
4202 return &view->base;
4203 }
4204
4205 static struct pipe_sampler_view *
4206 si_create_sampler_view(struct pipe_context *ctx,
4207 struct pipe_resource *texture,
4208 const struct pipe_sampler_view *state)
4209 {
4210 return si_create_sampler_view_custom(ctx, texture, state,
4211 texture ? texture->width0 : 0,
4212 texture ? texture->height0 : 0, 0);
4213 }
4214
4215 static void si_sampler_view_destroy(struct pipe_context *ctx,
4216 struct pipe_sampler_view *state)
4217 {
4218 struct si_sampler_view *view = (struct si_sampler_view *)state;
4219
4220 pipe_resource_reference(&state->texture, NULL);
4221 FREE(view);
4222 }
4223
4224 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4225 {
4226 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4227 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4228 (linear_filter &&
4229 (wrap == PIPE_TEX_WRAP_CLAMP ||
4230 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4231 }
4232
4233 static uint32_t si_translate_border_color(struct si_context *sctx,
4234 const struct pipe_sampler_state *state,
4235 const union pipe_color_union *color,
4236 bool is_integer)
4237 {
4238 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4239 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4240
4241 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4242 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4243 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4244 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4245
4246 #define simple_border_types(elt) \
4247 do { \
4248 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4249 color->elt[2] == 0 && color->elt[3] == 0) \
4250 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4251 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4252 color->elt[2] == 0 && color->elt[3] == 1) \
4253 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4254 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4255 color->elt[2] == 1 && color->elt[3] == 1) \
4256 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4257 } while (false)
4258
4259 if (is_integer)
4260 simple_border_types(ui);
4261 else
4262 simple_border_types(f);
4263
4264 #undef simple_border_types
4265
4266 int i;
4267
4268 /* Check if the border has been uploaded already. */
4269 for (i = 0; i < sctx->border_color_count; i++)
4270 if (memcmp(&sctx->border_color_table[i], color,
4271 sizeof(*color)) == 0)
4272 break;
4273
4274 if (i >= SI_MAX_BORDER_COLORS) {
4275 /* Getting 4096 unique border colors is very unlikely. */
4276 fprintf(stderr, "radeonsi: The border color table is full. "
4277 "Any new border colors will be just black. "
4278 "Please file a bug.\n");
4279 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4280 }
4281
4282 if (i == sctx->border_color_count) {
4283 /* Upload a new border color. */
4284 memcpy(&sctx->border_color_table[i], color,
4285 sizeof(*color));
4286 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4287 color, sizeof(*color));
4288 sctx->border_color_count++;
4289 }
4290
4291 return S_008F3C_BORDER_COLOR_PTR(i) |
4292 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4293 }
4294
4295 static inline int S_FIXED(float value, unsigned frac_bits)
4296 {
4297 return value * (1 << frac_bits);
4298 }
4299
4300 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4301 {
4302 if (filter == PIPE_TEX_FILTER_LINEAR)
4303 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4304 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4305 else
4306 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4307 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4308 }
4309
4310 static inline unsigned si_tex_aniso_filter(unsigned filter)
4311 {
4312 if (filter < 2)
4313 return 0;
4314 if (filter < 4)
4315 return 1;
4316 if (filter < 8)
4317 return 2;
4318 if (filter < 16)
4319 return 3;
4320 return 4;
4321 }
4322
4323 static void *si_create_sampler_state(struct pipe_context *ctx,
4324 const struct pipe_sampler_state *state)
4325 {
4326 struct si_context *sctx = (struct si_context *)ctx;
4327 struct si_screen *sscreen = sctx->screen;
4328 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4329 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4330 : state->max_anisotropy;
4331 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4332 union pipe_color_union clamped_border_color;
4333
4334 if (!rstate) {
4335 return NULL;
4336 }
4337
4338 #ifndef NDEBUG
4339 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4340 #endif
4341 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4342 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4343 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4344 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4345 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4346 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4347 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4348 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4349 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4350 S_008F30_COMPAT_MODE(sctx->chip_class >= GFX8));
4351 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4352 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4353 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4354 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4355 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4356 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4357 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4358 S_008F38_MIP_POINT_PRECLAMP(0) |
4359 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4360 S_008F38_FILTER_PREC_FIX(1) |
4361 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= GFX8));
4362 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4363
4364 /* Create sampler resource for integer textures. */
4365 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4366 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4367
4368 /* Create sampler resource for upgraded depth textures. */
4369 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4370
4371 for (unsigned i = 0; i < 4; ++i) {
4372 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4373 * when the border color is 1.0. */
4374 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4375 }
4376
4377 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4378 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4379 else
4380 rstate->upgraded_depth_val[3] =
4381 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4382 S_008F3C_UPGRADED_DEPTH(1);
4383
4384 return rstate;
4385 }
4386
4387 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4388 {
4389 struct si_context *sctx = (struct si_context *)ctx;
4390
4391 if (sctx->sample_mask == (uint16_t)sample_mask)
4392 return;
4393
4394 sctx->sample_mask = sample_mask;
4395 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4396 }
4397
4398 static void si_emit_sample_mask(struct si_context *sctx)
4399 {
4400 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4401 unsigned mask = sctx->sample_mask;
4402
4403 /* Needed for line and polygon smoothing as well as for the Polaris
4404 * small primitive filter. We expect the state tracker to take care of
4405 * this for us.
4406 */
4407 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4408 (mask & 1 && sctx->blitter->running));
4409
4410 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4411 radeon_emit(cs, mask | (mask << 16));
4412 radeon_emit(cs, mask | (mask << 16));
4413 }
4414
4415 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4416 {
4417 #ifndef NDEBUG
4418 struct si_sampler_state *s = state;
4419
4420 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4421 s->magic = 0;
4422 #endif
4423 free(state);
4424 }
4425
4426 /*
4427 * Vertex elements & buffers
4428 */
4429
4430 struct si_fast_udiv_info32
4431 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4432 {
4433 struct util_fast_udiv_info info =
4434 util_compute_fast_udiv_info(D, num_bits, 32);
4435
4436 struct si_fast_udiv_info32 result = {
4437 info.multiplier,
4438 info.pre_shift,
4439 info.post_shift,
4440 info.increment,
4441 };
4442 return result;
4443 }
4444
4445 static void *si_create_vertex_elements(struct pipe_context *ctx,
4446 unsigned count,
4447 const struct pipe_vertex_element *elements)
4448 {
4449 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4450 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4451 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4452 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4453 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4454 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4455 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4456 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4457 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4458 int i;
4459
4460 assert(count <= SI_MAX_ATTRIBS);
4461 if (!v)
4462 return NULL;
4463
4464 v->count = count;
4465 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4466
4467 for (i = 0; i < count; ++i) {
4468 const struct util_format_description *desc;
4469 const struct util_format_channel_description *channel;
4470 int first_non_void;
4471 unsigned vbo_index = elements[i].vertex_buffer_index;
4472
4473 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4474 FREE(v);
4475 return NULL;
4476 }
4477
4478 unsigned instance_divisor = elements[i].instance_divisor;
4479 if (instance_divisor) {
4480 v->uses_instance_divisors = true;
4481
4482 if (instance_divisor == 1) {
4483 v->instance_divisor_is_one |= 1u << i;
4484 } else {
4485 v->instance_divisor_is_fetched |= 1u << i;
4486 divisor_factors[i] =
4487 si_compute_fast_udiv_info32(instance_divisor, 32);
4488 }
4489 }
4490
4491 if (!used[vbo_index]) {
4492 v->first_vb_use_mask |= 1 << i;
4493 used[vbo_index] = true;
4494 }
4495
4496 desc = util_format_description(elements[i].src_format);
4497 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4498 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4499
4500 v->format_size[i] = desc->block.bits / 8;
4501 v->src_offset[i] = elements[i].src_offset;
4502 v->vertex_buffer_index[i] = vbo_index;
4503
4504 bool always_fix = false;
4505 union si_vs_fix_fetch fix_fetch;
4506 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4507
4508 fix_fetch.bits = 0;
4509 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4510
4511 if (channel) {
4512 switch (channel->type) {
4513 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4514 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4515 case UTIL_FORMAT_TYPE_SIGNED: {
4516 if (channel->pure_integer)
4517 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4518 else if (channel->normalized)
4519 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4520 else
4521 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4522 break;
4523 }
4524 case UTIL_FORMAT_TYPE_UNSIGNED: {
4525 if (channel->pure_integer)
4526 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4527 else if (channel->normalized)
4528 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4529 else
4530 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4531 break;
4532 }
4533 default: unreachable("bad format type");
4534 }
4535 } else {
4536 switch (elements[i].src_format) {
4537 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4538 default: unreachable("bad other format");
4539 }
4540 }
4541
4542 if (desc->channel[0].size == 10) {
4543 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4544 log_hw_load_size = 2;
4545
4546 /* The hardware always treats the 2-bit alpha channel as
4547 * unsigned, so a shader workaround is needed. The affected
4548 * chips are GFX8 and older except Stoney (GFX8.1).
4549 */
4550 always_fix = sscreen->info.chip_class <= GFX8 &&
4551 sscreen->info.family != CHIP_STONEY &&
4552 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4553 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4554 fix_fetch.u.log_size = 3; /* special encoding */
4555 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4556 log_hw_load_size = 2;
4557 } else {
4558 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4559 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4560
4561 /* Always fix up:
4562 * - doubles (multiple loads + truncate to float)
4563 * - 32-bit requiring a conversion
4564 */
4565 always_fix =
4566 (fix_fetch.u.log_size == 3) ||
4567 (fix_fetch.u.log_size == 2 &&
4568 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4569 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4570 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4571
4572 /* Also fixup 8_8_8 and 16_16_16. */
4573 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4574 always_fix = true;
4575 log_hw_load_size = fix_fetch.u.log_size;
4576 }
4577 }
4578
4579 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4580 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4581 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4582 fix_fetch.u.reverse = 1;
4583 }
4584
4585 /* Force the workaround for unaligned access here already if the
4586 * offset relative to the vertex buffer base is unaligned.
4587 *
4588 * There is a theoretical case in which this is too conservative:
4589 * if the vertex buffer's offset is also unaligned in just the
4590 * right way, we end up with an aligned address after all.
4591 * However, this case should be extremely rare in practice (it
4592 * won't happen in well-behaved applications), and taking it
4593 * into account would complicate the fast path (where everything
4594 * is nicely aligned).
4595 */
4596 bool check_alignment = log_hw_load_size >= 1 && sscreen->info.chip_class == GFX6;
4597 bool opencode = sscreen->options.vs_fetch_always_opencode;
4598
4599 if (check_alignment &&
4600 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4601 opencode = true;
4602
4603 if (always_fix || check_alignment || opencode)
4604 v->fix_fetch[i] = fix_fetch.bits;
4605
4606 if (opencode)
4607 v->fix_fetch_opencode |= 1 << i;
4608 if (opencode || always_fix)
4609 v->fix_fetch_always |= 1 << i;
4610
4611 if (check_alignment && !opencode) {
4612 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4613
4614 v->fix_fetch_unaligned |= 1 << i;
4615 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4616 v->vb_alignment_check_mask |= 1 << vbo_index;
4617 }
4618
4619 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
4620 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
4621 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
4622 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
4623
4624 unsigned data_format, num_format;
4625 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4626 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4627 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
4628 S_008F0C_DATA_FORMAT(data_format);
4629 }
4630
4631 if (v->instance_divisor_is_fetched) {
4632 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4633
4634 v->instance_divisor_factor_buffer =
4635 (struct si_resource*)
4636 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4637 num_divisors * sizeof(divisor_factors[0]));
4638 if (!v->instance_divisor_factor_buffer) {
4639 FREE(v);
4640 return NULL;
4641 }
4642 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4643 NULL, PIPE_TRANSFER_WRITE);
4644 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4645 }
4646 return v;
4647 }
4648
4649 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4650 {
4651 struct si_context *sctx = (struct si_context *)ctx;
4652 struct si_vertex_elements *old = sctx->vertex_elements;
4653 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4654
4655 sctx->vertex_elements = v;
4656 sctx->vertex_buffers_dirty = true;
4657
4658 if (v &&
4659 (!old ||
4660 old->count != v->count ||
4661 old->uses_instance_divisors != v->uses_instance_divisors ||
4662 /* we don't check which divisors changed */
4663 v->uses_instance_divisors ||
4664 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
4665 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4666 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4667 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
4668 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4669 * functions of fix_fetch and the src_offset alignment.
4670 * If they change and fix_fetch doesn't, it must be due to different
4671 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4672 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4673 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4674 sctx->do_update_shaders = true;
4675
4676 if (v && v->instance_divisor_is_fetched) {
4677 struct pipe_constant_buffer cb;
4678
4679 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4680 cb.user_buffer = NULL;
4681 cb.buffer_offset = 0;
4682 cb.buffer_size = 0xffffffff;
4683 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4684 }
4685 }
4686
4687 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4688 {
4689 struct si_context *sctx = (struct si_context *)ctx;
4690 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4691
4692 if (sctx->vertex_elements == state)
4693 sctx->vertex_elements = NULL;
4694 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4695 FREE(state);
4696 }
4697
4698 static void si_set_vertex_buffers(struct pipe_context *ctx,
4699 unsigned start_slot, unsigned count,
4700 const struct pipe_vertex_buffer *buffers)
4701 {
4702 struct si_context *sctx = (struct si_context *)ctx;
4703 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4704 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
4705 uint32_t unaligned = orig_unaligned;
4706 int i;
4707
4708 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4709
4710 if (buffers) {
4711 for (i = 0; i < count; i++) {
4712 const struct pipe_vertex_buffer *src = buffers + i;
4713 struct pipe_vertex_buffer *dsti = dst + i;
4714 struct pipe_resource *buf = src->buffer.resource;
4715
4716 pipe_resource_reference(&dsti->buffer.resource, buf);
4717 dsti->buffer_offset = src->buffer_offset;
4718 dsti->stride = src->stride;
4719 if (dsti->buffer_offset & 3 || dsti->stride & 3)
4720 unaligned |= 1 << (start_slot + i);
4721 else
4722 unaligned &= ~(1 << (start_slot + i));
4723
4724 si_context_add_resource_size(sctx, buf);
4725 if (buf)
4726 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4727 }
4728 } else {
4729 for (i = 0; i < count; i++) {
4730 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4731 }
4732 unaligned &= ~u_bit_consecutive(start_slot, count);
4733 }
4734 sctx->vertex_buffers_dirty = true;
4735 sctx->vertex_buffer_unaligned = unaligned;
4736
4737 /* Check whether alignment may have changed in a way that requires
4738 * shader changes. This check is conservative: a vertex buffer can only
4739 * trigger a shader change if the misalignment amount changes (e.g.
4740 * from byte-aligned to short-aligned), but we only keep track of
4741 * whether buffers are at least dword-aligned, since that should always
4742 * be the case in well-behaved applications anyway.
4743 */
4744 if (sctx->vertex_elements &&
4745 (sctx->vertex_elements->vb_alignment_check_mask &
4746 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
4747 sctx->do_update_shaders = true;
4748 }
4749
4750 /*
4751 * Misc
4752 */
4753
4754 static void si_set_tess_state(struct pipe_context *ctx,
4755 const float default_outer_level[4],
4756 const float default_inner_level[2])
4757 {
4758 struct si_context *sctx = (struct si_context *)ctx;
4759 struct pipe_constant_buffer cb;
4760 float array[8];
4761
4762 memcpy(array, default_outer_level, sizeof(float) * 4);
4763 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4764
4765 cb.buffer = NULL;
4766 cb.user_buffer = NULL;
4767 cb.buffer_size = sizeof(array);
4768
4769 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
4770 (void*)array, sizeof(array),
4771 &cb.buffer_offset);
4772
4773 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4774 pipe_resource_reference(&cb.buffer, NULL);
4775 }
4776
4777 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4778 {
4779 struct si_context *sctx = (struct si_context *)ctx;
4780
4781 si_update_fb_dirtiness_after_rendering(sctx);
4782
4783 /* Multisample surfaces are flushed in si_decompress_textures. */
4784 if (sctx->framebuffer.uncompressed_cb_mask) {
4785 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4786 sctx->framebuffer.CB_has_shader_readable_metadata,
4787 sctx->framebuffer.all_DCC_pipe_aligned);
4788 }
4789 }
4790
4791 /* This only ensures coherency for shader image/buffer stores. */
4792 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4793 {
4794 struct si_context *sctx = (struct si_context *)ctx;
4795
4796 if (!(flags & ~PIPE_BARRIER_UPDATE))
4797 return;
4798
4799 /* Subsequent commands must wait for all shader invocations to
4800 * complete. */
4801 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4802 SI_CONTEXT_CS_PARTIAL_FLUSH;
4803
4804 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4805 sctx->flags |= SI_CONTEXT_INV_SCACHE |
4806 SI_CONTEXT_INV_VCACHE;
4807
4808 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4809 PIPE_BARRIER_SHADER_BUFFER |
4810 PIPE_BARRIER_TEXTURE |
4811 PIPE_BARRIER_IMAGE |
4812 PIPE_BARRIER_STREAMOUT_BUFFER |
4813 PIPE_BARRIER_GLOBAL_BUFFER)) {
4814 /* As far as I can tell, L1 contents are written back to L2
4815 * automatically at end of shader, but the contents of other
4816 * L1 caches might still be stale. */
4817 sctx->flags |= SI_CONTEXT_INV_VCACHE;
4818 }
4819
4820 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4821 /* Indices are read through TC L2 since GFX8.
4822 * L1 isn't used.
4823 */
4824 if (sctx->screen->info.chip_class <= GFX7)
4825 sctx->flags |= SI_CONTEXT_WB_L2;
4826 }
4827
4828 /* MSAA color, any depth and any stencil are flushed in
4829 * si_decompress_textures when needed.
4830 */
4831 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4832 sctx->framebuffer.uncompressed_cb_mask) {
4833 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4834
4835 if (sctx->chip_class <= GFX8)
4836 sctx->flags |= SI_CONTEXT_WB_L2;
4837 }
4838
4839 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4840 if (sctx->screen->info.chip_class <= GFX8 &&
4841 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4842 sctx->flags |= SI_CONTEXT_WB_L2;
4843 }
4844
4845 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4846 {
4847 struct pipe_blend_state blend;
4848
4849 memset(&blend, 0, sizeof(blend));
4850 blend.independent_blend_enable = true;
4851 blend.rt[0].colormask = 0xf;
4852 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4853 }
4854
4855 static void si_init_config(struct si_context *sctx);
4856
4857 void si_init_state_compute_functions(struct si_context *sctx)
4858 {
4859 sctx->b.create_sampler_state = si_create_sampler_state;
4860 sctx->b.delete_sampler_state = si_delete_sampler_state;
4861 sctx->b.create_sampler_view = si_create_sampler_view;
4862 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4863 sctx->b.memory_barrier = si_memory_barrier;
4864 }
4865
4866 void si_init_state_functions(struct si_context *sctx)
4867 {
4868 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4869 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4870 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4871 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4872 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4873 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4874 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4875 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4876 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4877 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4878 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4879
4880 sctx->b.create_blend_state = si_create_blend_state;
4881 sctx->b.bind_blend_state = si_bind_blend_state;
4882 sctx->b.delete_blend_state = si_delete_blend_state;
4883 sctx->b.set_blend_color = si_set_blend_color;
4884
4885 sctx->b.create_rasterizer_state = si_create_rs_state;
4886 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4887 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4888
4889 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4890 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4891 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4892
4893 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4894 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4895 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4896 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4897 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4898
4899 sctx->b.set_clip_state = si_set_clip_state;
4900 sctx->b.set_stencil_ref = si_set_stencil_ref;
4901
4902 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4903
4904 sctx->b.set_sample_mask = si_set_sample_mask;
4905
4906 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4907 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4908 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4909 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4910
4911 sctx->b.texture_barrier = si_texture_barrier;
4912 sctx->b.set_min_samples = si_set_min_samples;
4913 sctx->b.set_tess_state = si_set_tess_state;
4914
4915 sctx->b.set_active_query_state = si_set_active_query_state;
4916
4917 si_init_config(sctx);
4918 }
4919
4920 void si_init_screen_state_functions(struct si_screen *sscreen)
4921 {
4922 sscreen->b.is_format_supported = si_is_format_supported;
4923 }
4924
4925 static void si_set_grbm_gfx_index(struct si_context *sctx,
4926 struct si_pm4_state *pm4, unsigned value)
4927 {
4928 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
4929 R_00802C_GRBM_GFX_INDEX;
4930 si_pm4_set_reg(pm4, reg, value);
4931 }
4932
4933 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4934 struct si_pm4_state *pm4, unsigned se)
4935 {
4936 assert(se == ~0 || se < sctx->screen->info.max_se);
4937 si_set_grbm_gfx_index(sctx, pm4,
4938 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4939 S_030800_SE_INDEX(se)) |
4940 S_030800_SH_BROADCAST_WRITES(1) |
4941 S_030800_INSTANCE_BROADCAST_WRITES(1));
4942 }
4943
4944 static void
4945 si_write_harvested_raster_configs(struct si_context *sctx,
4946 struct si_pm4_state *pm4,
4947 unsigned raster_config,
4948 unsigned raster_config_1)
4949 {
4950 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4951 unsigned raster_config_se[4];
4952 unsigned se;
4953
4954 ac_get_harvested_configs(&sctx->screen->info,
4955 raster_config,
4956 &raster_config_1,
4957 raster_config_se);
4958
4959 for (se = 0; se < num_se; se++) {
4960 si_set_grbm_gfx_index_se(sctx, pm4, se);
4961 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4962 }
4963 si_set_grbm_gfx_index(sctx, pm4, ~0);
4964
4965 if (sctx->chip_class >= GFX7) {
4966 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4967 }
4968 }
4969
4970 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4971 {
4972 struct si_screen *sscreen = sctx->screen;
4973 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4974 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4975 unsigned raster_config = sscreen->pa_sc_raster_config;
4976 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4977
4978 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4979 /* Always use the default config when all backends are enabled
4980 * (or when we failed to determine the enabled backends).
4981 */
4982 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4983 raster_config);
4984 if (sctx->chip_class >= GFX7)
4985 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4986 raster_config_1);
4987 } else {
4988 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4989 }
4990 }
4991
4992 static void si_init_config(struct si_context *sctx)
4993 {
4994 struct si_screen *sscreen = sctx->screen;
4995 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4996 bool has_clear_state = sscreen->has_clear_state;
4997 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4998
4999 /* GFX6, radeon kernel disabled CLEAR_STATE. */
5000 assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
5001 !sscreen->info.is_amdgpu);
5002
5003 if (!pm4)
5004 return;
5005
5006 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5007 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5008 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5009 si_pm4_cmd_end(pm4, false);
5010
5011 if (has_clear_state) {
5012 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5013 si_pm4_cmd_add(pm4, 0);
5014 si_pm4_cmd_end(pm4, false);
5015 }
5016
5017 if (sctx->chip_class <= GFX8)
5018 si_set_raster_config(sctx, pm4);
5019
5020 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5021 if (!has_clear_state)
5022 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5023
5024 /* FIXME calculate these values somehow ??? */
5025 if (sctx->chip_class <= GFX8) {
5026 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5027 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5028 }
5029
5030 if (!has_clear_state) {
5031 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5032 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5033 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5034 }
5035
5036 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5037 if (!has_clear_state)
5038 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5039 if (sctx->chip_class < GFX7)
5040 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5041 S_008A14_CLIP_VTX_REORDER_ENA(1));
5042
5043 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5044 * I don't know why. Deduced by trial and error.
5045 */
5046 if (sctx->chip_class <= GFX7) {
5047 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5048 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5049 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5050 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5051 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5052 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5053 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5054 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5055 }
5056
5057 if (!has_clear_state) {
5058 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5059 S_028230_ER_TRI(0xA) |
5060 S_028230_ER_POINT(0xA) |
5061 S_028230_ER_RECT(0xA) |
5062 /* Required by DX10_DIAMOND_TEST_ENA: */
5063 S_028230_ER_LINE_LR(0x1A) |
5064 S_028230_ER_LINE_RL(0x26) |
5065 S_028230_ER_LINE_TB(0xA) |
5066 S_028230_ER_LINE_BT(0xA));
5067 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5068 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5069 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5070 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5071 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5072 }
5073
5074 if (sctx->chip_class >= GFX9) {
5075 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5076 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5077 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5078 } else {
5079 /* These registers, when written, also overwrite the CLEAR_STATE
5080 * context, so we can't rely on CLEAR_STATE setting them.
5081 * It would be an issue if there was another UMD changing them.
5082 */
5083 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5084 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5085 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5086 }
5087
5088 if (sctx->chip_class >= GFX7) {
5089 if (sctx->chip_class >= GFX9) {
5090 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5091 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5092 } else {
5093 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5094 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5095 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5096 S_00B41C_WAVE_LIMIT(0x3F));
5097 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5098 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5099
5100 /* If this is 0, Bonaire can hang even if GS isn't being used.
5101 * Other chips are unaffected. These are suboptimal values,
5102 * but we don't use on-chip GS.
5103 */
5104 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5105 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5106 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5107 }
5108 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5109 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5110
5111 /* Compute LATE_ALLOC_VS.LIMIT. */
5112 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5113 unsigned late_alloc_limit; /* The limit is per SH. */
5114
5115 if (sctx->family == CHIP_KABINI) {
5116 late_alloc_limit = 0; /* Potential hang on Kabini. */
5117 } else if (num_cu_per_sh <= 4) {
5118 /* Too few available compute units per SH. Disallowing
5119 * VS to run on one CU could hurt us more than late VS
5120 * allocation would help.
5121 *
5122 * 2 is the highest safe number that allows us to keep
5123 * all CUs enabled.
5124 */
5125 late_alloc_limit = 2;
5126 } else {
5127 /* This is a good initial value, allowing 1 late_alloc
5128 * wave per SIMD on num_cu - 2.
5129 */
5130 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5131
5132 /* The limit is 0-based, so 0 means 1. */
5133 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5134 late_alloc_limit -= 1;
5135 }
5136
5137 /* VS can't execute on one CU if the limit is > 2. */
5138 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5139 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5140 S_00B118_WAVE_LIMIT(0x3F));
5141 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5142 S_00B11C_LIMIT(late_alloc_limit));
5143 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5144 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5145 }
5146
5147 if (sctx->chip_class >= GFX8) {
5148 unsigned vgt_tess_distribution;
5149
5150 vgt_tess_distribution =
5151 S_028B50_ACCUM_ISOLINE(32) |
5152 S_028B50_ACCUM_TRI(11) |
5153 S_028B50_ACCUM_QUAD(11) |
5154 S_028B50_DONUT_SPLIT(16);
5155
5156 /* Testing with Unigine Heaven extreme tesselation yielded best results
5157 * with TRAP_SPLIT = 3.
5158 */
5159 if (sctx->family == CHIP_FIJI ||
5160 sctx->family >= CHIP_POLARIS10)
5161 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5162
5163 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5164 } else if (!has_clear_state) {
5165 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5166 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5167 }
5168
5169 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5170 if (sctx->chip_class >= GFX7) {
5171 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5172 S_028084_ADDRESS(border_color_va >> 40));
5173 }
5174 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5175 RADEON_PRIO_BORDER_COLORS);
5176
5177 if (sctx->chip_class >= GFX9) {
5178 unsigned num_se = sscreen->info.max_se;
5179 unsigned pc_lines = 0;
5180
5181 switch (sctx->family) {
5182 case CHIP_VEGA10:
5183 case CHIP_VEGA12:
5184 case CHIP_VEGA20:
5185 pc_lines = 4096;
5186 break;
5187 case CHIP_RAVEN:
5188 case CHIP_RAVEN2:
5189 pc_lines = 1024;
5190 break;
5191 default:
5192 assert(0);
5193 }
5194
5195 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5196 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5197 S_028C48_MAX_PRIM_PER_BATCH(1023));
5198 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5199 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5200 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5201 }
5202
5203 si_pm4_upload_indirect_buffer(sctx, pm4);
5204 sctx->init_config = pm4;
5205 }