2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
36 #include "gfx10_format_table.h"
38 static unsigned si_map_swizzle(unsigned swizzle
)
42 return V_008F0C_SQ_SEL_Y
;
44 return V_008F0C_SQ_SEL_Z
;
46 return V_008F0C_SQ_SEL_W
;
48 return V_008F0C_SQ_SEL_0
;
50 return V_008F0C_SQ_SEL_1
;
51 default: /* PIPE_SWIZZLE_X */
52 return V_008F0C_SQ_SEL_X
;
56 /* 12.4 fixed-point */
57 static unsigned si_pack_float_12p4(float x
)
59 return x
<= 0 ? 0 : x
>= 4096 ? 0xffff : x
* 16;
63 * Inferred framebuffer and blender state.
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
68 static void si_emit_cb_render_state(struct si_context
*sctx
)
70 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
71 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
& blend
->cb_target_mask
;
77 /* Avoid a hang that happens when dual source blending is enabled
78 * but there is not enough color outputs. This is undefined behavior,
79 * so disable color writes completely.
81 * Reproducible with Unigine Heaven 4.0 and drirc missing.
83 if (blend
->dual_src_blend
&& sctx
->ps_shader
.cso
&&
84 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
87 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
88 * I think we don't have to do anything between IBs.
90 if (sctx
->screen
->dpbb_allowed
&& sctx
->last_cb_target_mask
!= cb_target_mask
) {
91 sctx
->last_cb_target_mask
= cb_target_mask
;
93 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
94 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
97 unsigned initial_cdw
= cs
->current
.cdw
;
98 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
, SI_TRACKED_CB_TARGET_MASK
,
101 if (sctx
->chip_class
>= GFX8
) {
102 /* DCC MSAA workaround.
103 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
104 * COMBINER_DISABLE, but that would be more complicated.
107 blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&& sctx
->framebuffer
.nr_samples
>= 2;
108 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
110 radeon_opt_set_context_reg(
111 sctx
, R_028424_CB_DCC_CONTROL
, SI_TRACKED_CB_DCC_CONTROL
,
112 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
113 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
114 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
115 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
118 /* RB+ register settings. */
119 if (sctx
->screen
->info
.rbplus_allowed
) {
120 unsigned spi_shader_col_format
=
121 sctx
->ps_shader
.cso
? sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
123 unsigned sx_ps_downconvert
= 0;
124 unsigned sx_blend_opt_epsilon
= 0;
125 unsigned sx_blend_opt_control
= 0;
127 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
128 struct si_surface
*surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
129 unsigned format
, swap
, spi_format
, colormask
;
130 bool has_alpha
, has_rgb
;
133 /* If the color buffer is not set, the driver sets 32_R
134 * as the SPI color format, because the hw doesn't allow
135 * holes between color outputs, so also set this to
138 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
142 format
= G_028C70_FORMAT(surf
->cb_color_info
);
143 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
144 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
145 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
147 /* Set if RGB and A are present. */
148 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
150 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_16
||
151 format
== V_028C70_COLOR_32
)
152 has_rgb
= !has_alpha
;
156 /* Check the colormask and export format. */
157 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
159 if (!(colormask
& PIPE_MASK_A
))
162 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
167 /* Disable value checking for disabled channels. */
169 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
171 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
173 /* Enable down-conversion for 32bpp and smaller formats. */
175 case V_028C70_COLOR_8
:
176 case V_028C70_COLOR_8_8
:
177 case V_028C70_COLOR_8_8_8_8
:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
180 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
181 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
182 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
183 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
187 case V_028C70_COLOR_5_6_5
:
188 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
189 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
190 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
194 case V_028C70_COLOR_1_5_5_5
:
195 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
196 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
197 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
201 case V_028C70_COLOR_4_4_4_4
:
202 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
203 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
204 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
208 case V_028C70_COLOR_32
:
209 if (swap
== V_028C70_SWAP_STD
&& spi_format
== V_028714_SPI_SHADER_32_R
)
210 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
211 else if (swap
== V_028C70_SWAP_ALT_REV
&& spi_format
== V_028714_SPI_SHADER_32_AR
)
212 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
215 case V_028C70_COLOR_16
:
216 case V_028C70_COLOR_16_16
:
217 /* For 1-channel formats, use the superset thereof. */
218 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
219 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
220 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
221 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
222 if (swap
== V_028C70_SWAP_STD
|| swap
== V_028C70_SWAP_STD_REV
)
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
225 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
229 case V_028C70_COLOR_10_11_11
:
230 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
234 case V_028C70_COLOR_2_10_10_10
:
235 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
236 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
237 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
241 case V_028C70_COLOR_5_9_9_9
:
242 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
243 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_9_9_9_E5
<< (i
* 4);
248 /* If there are no color outputs, the first color export is
249 * always enabled as 32_R, so also set this to enable RB+.
251 if (!sx_ps_downconvert
)
252 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
254 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
255 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
, SI_TRACKED_SX_PS_DOWNCONVERT
,
256 sx_ps_downconvert
, sx_blend_opt_epsilon
, sx_blend_opt_control
);
258 if (initial_cdw
!= cs
->current
.cdw
)
259 sctx
->context_roll
= true;
266 static uint32_t si_translate_blend_function(int blend_func
)
268 switch (blend_func
) {
270 return V_028780_COMB_DST_PLUS_SRC
;
271 case PIPE_BLEND_SUBTRACT
:
272 return V_028780_COMB_SRC_MINUS_DST
;
273 case PIPE_BLEND_REVERSE_SUBTRACT
:
274 return V_028780_COMB_DST_MINUS_SRC
;
276 return V_028780_COMB_MIN_DST_SRC
;
278 return V_028780_COMB_MAX_DST_SRC
;
280 PRINT_ERR("Unknown blend function %d\n", blend_func
);
287 static uint32_t si_translate_blend_factor(int blend_fact
)
289 switch (blend_fact
) {
290 case PIPE_BLENDFACTOR_ONE
:
291 return V_028780_BLEND_ONE
;
292 case PIPE_BLENDFACTOR_SRC_COLOR
:
293 return V_028780_BLEND_SRC_COLOR
;
294 case PIPE_BLENDFACTOR_SRC_ALPHA
:
295 return V_028780_BLEND_SRC_ALPHA
;
296 case PIPE_BLENDFACTOR_DST_ALPHA
:
297 return V_028780_BLEND_DST_ALPHA
;
298 case PIPE_BLENDFACTOR_DST_COLOR
:
299 return V_028780_BLEND_DST_COLOR
;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
302 case PIPE_BLENDFACTOR_CONST_COLOR
:
303 return V_028780_BLEND_CONSTANT_COLOR
;
304 case PIPE_BLENDFACTOR_CONST_ALPHA
:
305 return V_028780_BLEND_CONSTANT_ALPHA
;
306 case PIPE_BLENDFACTOR_ZERO
:
307 return V_028780_BLEND_ZERO
;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
320 case PIPE_BLENDFACTOR_SRC1_COLOR
:
321 return V_028780_BLEND_SRC1_COLOR
;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
323 return V_028780_BLEND_SRC1_ALPHA
;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
325 return V_028780_BLEND_INV_SRC1_COLOR
;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
327 return V_028780_BLEND_INV_SRC1_ALPHA
;
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
336 static uint32_t si_translate_blend_opt_function(int blend_func
)
338 switch (blend_func
) {
340 return V_028760_OPT_COMB_ADD
;
341 case PIPE_BLEND_SUBTRACT
:
342 return V_028760_OPT_COMB_SUBTRACT
;
343 case PIPE_BLEND_REVERSE_SUBTRACT
:
344 return V_028760_OPT_COMB_REVSUBTRACT
;
346 return V_028760_OPT_COMB_MIN
;
348 return V_028760_OPT_COMB_MAX
;
350 return V_028760_OPT_COMB_BLEND_DISABLED
;
354 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
356 switch (blend_fact
) {
357 case PIPE_BLENDFACTOR_ZERO
:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
359 case PIPE_BLENDFACTOR_ONE
:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
361 case PIPE_BLENDFACTOR_SRC_COLOR
:
362 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
365 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
367 case PIPE_BLENDFACTOR_SRC_ALPHA
:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
372 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
379 static void si_blend_check_commutativity(struct si_screen
*sscreen
, struct si_state_blend
*blend
,
380 enum pipe_blend_func func
, enum pipe_blendfactor src
,
381 enum pipe_blendfactor dst
, unsigned chanmask
)
383 /* Src factor is allowed when it does not depend on Dst */
384 static const uint32_t src_allowed
=
385 (1u << PIPE_BLENDFACTOR_ONE
) | (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
386 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
387 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
389 (1u << PIPE_BLENDFACTOR_ZERO
) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
391 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
394 if (dst
== PIPE_BLENDFACTOR_ONE
&& (src_allowed
& (1u << src
))) {
395 /* Addition is commutative, but floating point addition isn't
396 * associative: subtle changes can be introduced via different
399 * Out-of-order is also non-deterministic, which means that
400 * this breaks OpenGL invariance requirements. So only enable
401 * out-of-order additive blending if explicitly allowed by a
404 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
405 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
406 blend
->commutative_4bit
|= chanmask
;
411 * Get rid of DST in the blend factors by commuting the operands:
412 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
, unsigned *dst_factor
,
415 unsigned expected_dst
, unsigned replacement_src
)
417 if (*src_factor
== expected_dst
&& *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
418 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
419 *dst_factor
= replacement_src
;
421 /* Commuting the operands requires reversing subtractions. */
422 if (*func
== PIPE_BLEND_SUBTRACT
)
423 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
424 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
425 *func
= PIPE_BLEND_SUBTRACT
;
429 static bool si_blend_factor_uses_dst(unsigned factor
)
431 return factor
== PIPE_BLENDFACTOR_DST_COLOR
|| factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
432 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
433 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
|| factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
436 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
437 const struct pipe_blend_state
*state
, unsigned mode
)
439 struct si_context
*sctx
= (struct si_context
*)ctx
;
440 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
441 struct si_pm4_state
*pm4
= &blend
->pm4
;
442 uint32_t sx_mrt_blend_opt
[8] = {0};
443 uint32_t color_control
= 0;
444 bool logicop_enable
= state
->logicop_enable
&& state
->logicop_func
!= PIPE_LOGICOP_COPY
;
449 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
450 blend
->alpha_to_one
= state
->alpha_to_one
;
451 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
452 blend
->logicop_enable
= logicop_enable
;
454 unsigned num_shader_outputs
= state
->max_rt
+ 1; /* estimate */
455 if (blend
->dual_src_blend
)
456 num_shader_outputs
= MAX2(num_shader_outputs
, 2);
458 if (logicop_enable
) {
459 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
461 color_control
|= S_028808_ROP3(0xcc);
464 if (state
->alpha_to_coverage
&& state
->alpha_to_coverage_dither
) {
465 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
468 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
469 S_028B70_OFFSET_ROUND(1));
471 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
472 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
473 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
475 S_028B70_OFFSET_ROUND(0));
478 if (state
->alpha_to_coverage
)
479 blend
->need_src_alpha_4bit
|= 0xf;
481 blend
->cb_target_mask
= 0;
482 blend
->cb_target_enabled_4bit
= 0;
484 for (int i
= 0; i
< num_shader_outputs
; i
++) {
485 /* state->rt entries > 0 only written if independent blending */
486 const int j
= state
->independent_blend_enable
? i
: 0;
488 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
489 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
490 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
491 unsigned eqA
= state
->rt
[j
].alpha_func
;
492 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
493 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
495 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
496 unsigned blend_cntl
= 0;
498 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
499 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
501 /* Only set dual source blending for MRT0 to avoid a hang. */
502 if (i
>= 1 && blend
->dual_src_blend
) {
503 /* Vulkan does this for dual source blending. */
505 blend_cntl
|= S_028780_ENABLE(1);
507 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
511 /* Only addition and subtraction equations are supported with
512 * dual source blending.
514 if (blend
->dual_src_blend
&& (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
515 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
521 /* cb_render_state will disable unused ones */
522 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
523 if (state
->rt
[j
].colormask
)
524 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
526 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
527 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
531 si_blend_check_commutativity(sctx
->screen
, blend
, eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
532 si_blend_check_commutativity(sctx
->screen
, blend
, eqA
, srcA
, dstA
, 0x8 << (4 * i
));
534 /* Blending optimizations for RB+.
535 * These transformations don't change the behavior.
537 * First, get rid of DST in the blend factors:
538 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
540 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
, PIPE_BLENDFACTOR_DST_COLOR
,
541 PIPE_BLENDFACTOR_SRC_COLOR
);
542 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_COLOR
,
543 PIPE_BLENDFACTOR_SRC_COLOR
);
544 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_ALPHA
,
545 PIPE_BLENDFACTOR_SRC_ALPHA
);
547 /* Look up the ideal settings from tables. */
548 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
549 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
550 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
551 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
553 /* Handle interdependencies. */
554 if (si_blend_factor_uses_dst(srcRGB
))
555 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
556 if (si_blend_factor_uses_dst(srcA
))
557 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
559 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
560 (dstRGB
== PIPE_BLENDFACTOR_ZERO
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
561 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
562 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
564 /* Set the final value. */
565 sx_mrt_blend_opt
[i
] = S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
566 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
567 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
568 S_028760_ALPHA_SRC_OPT(srcA_opt
) | S_028760_ALPHA_DST_OPT(dstA_opt
) |
569 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
571 /* Set blend state. */
572 blend_cntl
|= S_028780_ENABLE(1);
573 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
574 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
575 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
577 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
578 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
579 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
580 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
581 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
583 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
585 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
587 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
)
588 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
590 /* This is only important for formats without alpha. */
591 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
592 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
593 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
594 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
595 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
598 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
&& logicop_enable
)
599 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
601 if (blend
->cb_target_mask
) {
602 color_control
|= S_028808_MODE(mode
);
604 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
607 if (sctx
->screen
->info
.rbplus_allowed
) {
608 /* Disable RB+ blend optimizations for dual source blending.
611 if (blend
->dual_src_blend
) {
612 for (int i
= 0; i
< num_shader_outputs
; i
++) {
613 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
614 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
618 for (int i
= 0; i
< num_shader_outputs
; i
++)
619 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4, sx_mrt_blend_opt
[i
]);
621 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
622 if (blend
->dual_src_blend
|| logicop_enable
|| mode
== V_028808_CB_RESOLVE
)
623 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
626 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
630 static void *si_create_blend_state(struct pipe_context
*ctx
, const struct pipe_blend_state
*state
)
632 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
635 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
637 struct si_context
*sctx
= (struct si_context
*)ctx
;
638 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
639 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
642 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
644 si_pm4_bind_state(sctx
, blend
, blend
);
646 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
647 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
648 (old_blend
->dcc_msaa_corruption_4bit
!= blend
->dcc_msaa_corruption_4bit
&&
649 sctx
->framebuffer
.nr_samples
>= 2 && sctx
->screen
->dcc_msaa_allowed
))
650 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
652 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
653 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
654 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
655 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
656 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
657 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
658 sctx
->do_update_shaders
= true;
660 if (sctx
->screen
->dpbb_allowed
&&
661 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
662 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
663 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
664 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
666 if (sctx
->screen
->has_out_of_order_rast
&&
667 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
668 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
669 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
670 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
671 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
674 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
676 struct si_context
*sctx
= (struct si_context
*)ctx
;
678 if (sctx
->queued
.named
.blend
== state
)
679 si_bind_blend_state(ctx
, sctx
->noop_blend
);
681 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
684 static void si_set_blend_color(struct pipe_context
*ctx
, const struct pipe_blend_color
*state
)
686 struct si_context
*sctx
= (struct si_context
*)ctx
;
687 static const struct pipe_blend_color zeros
;
689 sctx
->blend_color
.state
= *state
;
690 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
691 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
694 static void si_emit_blend_color(struct si_context
*sctx
)
696 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
698 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
699 radeon_emit_array(cs
, (uint32_t *)sctx
->blend_color
.state
.color
, 4);
706 static void si_set_clip_state(struct pipe_context
*ctx
, const struct pipe_clip_state
*state
)
708 struct si_context
*sctx
= (struct si_context
*)ctx
;
709 struct pipe_constant_buffer cb
;
710 static const struct pipe_clip_state zeros
;
712 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
715 sctx
->clip_state
.state
= *state
;
716 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
717 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
720 cb
.user_buffer
= state
->ucp
;
721 cb
.buffer_offset
= 0;
722 cb
.buffer_size
= 4 * 4 * 8;
723 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
724 pipe_resource_reference(&cb
.buffer
, NULL
);
727 static void si_emit_clip_state(struct si_context
*sctx
)
729 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
731 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6 * 4);
732 radeon_emit_array(cs
, (uint32_t *)sctx
->clip_state
.state
.ucp
, 6 * 4);
735 static void si_emit_clip_regs(struct si_context
*sctx
)
737 struct si_shader
*vs
= si_get_vs_state(sctx
);
738 struct si_shader_selector
*vs_sel
= vs
->selector
;
739 struct si_shader_info
*info
= &vs_sel
->info
;
740 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
741 unsigned window_space
= info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
742 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
743 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
744 unsigned culldist_mask
= vs_sel
->culldist_mask
;
747 if (vs
->key
.opt
.clip_disable
) {
748 assert(!info
->culldist_writemask
);
752 total_mask
= clipdist_mask
| culldist_mask
;
754 /* Clip distances on points have no effect, so need to be implemented
755 * as cull distances. This applies for the clipvertex case as well.
757 * Setting this for primitives other than points should have no adverse
760 clipdist_mask
&= rs
->clip_plane_enable
;
761 culldist_mask
|= clipdist_mask
;
763 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
764 unsigned pa_cl_cntl
= S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
765 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
766 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(sctx
->chip_class
>= GFX10_3
) |
767 clipdist_mask
| (culldist_mask
<< 8);
769 if (sctx
->chip_class
>= GFX10
) {
770 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
771 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
, pa_cl_cntl
,
772 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
774 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
775 vs_sel
->pa_cl_vs_out_cntl
| pa_cl_cntl
);
777 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
, SI_TRACKED_PA_CL_CLIP_CNTL
,
778 rs
->pa_cl_clip_cntl
| ucp_mask
| S_028810_CLIP_DISABLE(window_space
));
780 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
781 sctx
->context_roll
= true;
785 * inferred state between framebuffer and rasterizer
787 static void si_update_poly_offset_state(struct si_context
*sctx
)
789 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
791 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
792 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
796 /* Use the user format, not db_render_format, so that the polygon
797 * offset behaves as expected by applications.
799 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
800 case PIPE_FORMAT_Z16_UNORM
:
801 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
803 default: /* 24-bit */
804 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
806 case PIPE_FORMAT_Z32_FLOAT
:
807 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
808 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
817 static uint32_t si_translate_fill(uint32_t func
)
820 case PIPE_POLYGON_MODE_FILL
:
821 return V_028814_X_DRAW_TRIANGLES
;
822 case PIPE_POLYGON_MODE_LINE
:
823 return V_028814_X_DRAW_LINES
;
824 case PIPE_POLYGON_MODE_POINT
:
825 return V_028814_X_DRAW_POINTS
;
828 return V_028814_X_DRAW_POINTS
;
832 static void *si_create_rs_state(struct pipe_context
*ctx
, const struct pipe_rasterizer_state
*state
)
834 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
835 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
836 struct si_pm4_state
*pm4
= &rs
->pm4
;
838 float psize_min
, psize_max
;
844 if (!state
->front_ccw
) {
845 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
846 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
848 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
849 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
851 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
852 rs
->provoking_vertex_first
= state
->flatshade_first
;
853 rs
->scissor_enable
= state
->scissor
;
854 rs
->clip_halfz
= state
->clip_halfz
;
855 rs
->two_side
= state
->light_twoside
;
856 rs
->multisample_enable
= state
->multisample
;
857 rs
->force_persample_interp
= state
->force_persample_interp
;
858 rs
->clip_plane_enable
= state
->clip_plane_enable
;
859 rs
->half_pixel_center
= state
->half_pixel_center
;
860 rs
->line_stipple_enable
= state
->line_stipple_enable
;
861 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
862 rs
->line_smooth
= state
->line_smooth
;
863 rs
->line_width
= state
->line_width
;
864 rs
->poly_smooth
= state
->poly_smooth
;
865 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
866 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
867 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
868 rs
->flatshade
= state
->flatshade
;
869 rs
->flatshade_first
= state
->flatshade_first
;
870 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
871 rs
->rasterizer_discard
= state
->rasterizer_discard
;
872 rs
->polygon_mode_enabled
=
873 (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
874 (state
->fill_back
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_BACK
));
875 rs
->polygon_mode_is_lines
=
876 (state
->fill_front
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
877 (state
->fill_back
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_BACK
));
878 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
879 ? S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
880 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
)
882 rs
->pa_cl_clip_cntl
= S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
883 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
884 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
885 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
886 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
889 pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
890 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
891 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
892 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
893 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
894 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
895 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
897 /* point size 12.4 fixed point */
898 tmp
= (unsigned)(state
->point_size
* 8.0);
899 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
901 if (state
->point_size_per_vertex
) {
902 psize_min
= util_get_min_point_size(state
);
903 psize_max
= SI_MAX_POINT_SIZE
;
905 /* Force the point size to be as if the vertex output was disabled. */
906 psize_min
= state
->point_size
;
907 psize_max
= state
->point_size
;
909 rs
->max_point_size
= psize_max
;
911 /* Divide by two, because 0.5 = 1 pixel. */
912 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
913 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/ 2)) |
914 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/ 2)));
916 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
917 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/ 2)));
919 pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
920 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
921 S_028A48_MSAA_ENABLE(state
->multisample
|| state
->poly_smooth
|| state
->line_smooth
) |
922 S_028A48_VPORT_SCISSOR_ENABLE(1) |
923 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
925 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
926 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
927 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
928 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
929 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
930 S_028814_FACE(!state
->front_ccw
) |
931 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
932 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
933 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
934 S_028814_POLY_MODE(rs
->polygon_mode_enabled
) |
935 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
936 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
938 if (!rs
->uses_poly_offset
)
941 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
942 if (!rs
->pm4_poly_offset
) {
947 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
948 for (i
= 0; i
< 3; i
++) {
949 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
950 float offset_units
= state
->offset_units
;
951 float offset_scale
= state
->offset_scale
* 16.0f
;
952 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
954 if (!state
->offset_units_unscaled
) {
956 case 0: /* 16-bit zbuffer */
957 offset_units
*= 4.0f
;
958 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
960 case 1: /* 24-bit zbuffer */
961 offset_units
*= 2.0f
;
962 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
964 case 2: /* 32-bit zbuffer */
965 offset_units
*= 1.0f
;
966 pa_su_poly_offset_db_fmt_cntl
=
967 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
972 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, fui(offset_scale
));
973 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
974 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, fui(offset_scale
));
975 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
976 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, pa_su_poly_offset_db_fmt_cntl
);
982 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
984 struct si_context
*sctx
= (struct si_context
*)ctx
;
985 struct si_state_rasterizer
*old_rs
= (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
986 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
989 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
991 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
992 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
994 /* Update the small primitive filter workaround if necessary. */
995 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1)
996 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
999 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1000 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1002 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1003 si_update_poly_offset_state(sctx
);
1005 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1006 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1008 if (old_rs
->line_width
!= rs
->line_width
|| old_rs
->max_point_size
!= rs
->max_point_size
||
1009 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1010 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1012 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1013 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1015 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1016 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1017 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1019 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1020 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1021 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1022 old_rs
->flatshade
!= rs
->flatshade
|| old_rs
->two_side
!= rs
->two_side
||
1023 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1024 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1025 old_rs
->poly_smooth
!= rs
->poly_smooth
|| old_rs
->line_smooth
!= rs
->line_smooth
||
1026 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1027 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1028 sctx
->do_update_shaders
= true;
1031 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1033 struct si_context
*sctx
= (struct si_context
*)ctx
;
1034 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1036 if (sctx
->queued
.named
.rasterizer
== state
)
1037 si_bind_rs_state(ctx
, sctx
->discard_rasterizer_state
);
1039 FREE(rs
->pm4_poly_offset
);
1040 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1044 * infeered state between dsa and stencil ref
1046 static void si_emit_stencil_ref(struct si_context
*sctx
)
1048 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1049 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1050 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1052 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1053 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1054 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1055 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) | S_028430_STENCILOPVAL(1));
1056 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1057 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1058 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1059 S_028434_STENCILOPVAL_BF(1));
1062 static void si_set_stencil_ref(struct pipe_context
*ctx
, const struct pipe_stencil_ref
*state
)
1064 struct si_context
*sctx
= (struct si_context
*)ctx
;
1066 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1069 sctx
->stencil_ref
.state
= *state
;
1070 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1077 static uint32_t si_translate_stencil_op(int s_op
)
1080 case PIPE_STENCIL_OP_KEEP
:
1081 return V_02842C_STENCIL_KEEP
;
1082 case PIPE_STENCIL_OP_ZERO
:
1083 return V_02842C_STENCIL_ZERO
;
1084 case PIPE_STENCIL_OP_REPLACE
:
1085 return V_02842C_STENCIL_REPLACE_TEST
;
1086 case PIPE_STENCIL_OP_INCR
:
1087 return V_02842C_STENCIL_ADD_CLAMP
;
1088 case PIPE_STENCIL_OP_DECR
:
1089 return V_02842C_STENCIL_SUB_CLAMP
;
1090 case PIPE_STENCIL_OP_INCR_WRAP
:
1091 return V_02842C_STENCIL_ADD_WRAP
;
1092 case PIPE_STENCIL_OP_DECR_WRAP
:
1093 return V_02842C_STENCIL_SUB_WRAP
;
1094 case PIPE_STENCIL_OP_INVERT
:
1095 return V_02842C_STENCIL_INVERT
;
1097 PRINT_ERR("Unknown stencil op %d", s_op
);
1104 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1106 return s
->enabled
&& s
->writemask
&&
1107 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
|| s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1108 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1111 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1113 /* REPLACE is normally order invariant, except when the stencil
1114 * reference value is written by the fragment shader. Tracking this
1115 * interaction does not seem worth the effort, so be conservative. */
1116 return op
!= PIPE_STENCIL_OP_INCR
&& op
!= PIPE_STENCIL_OP_DECR
&& op
!= PIPE_STENCIL_OP_REPLACE
;
1119 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1120 * invariant in the sense that the set of passing fragments as well as the
1121 * final stencil buffer result does not depend on the order of fragments. */
1122 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1124 return !state
->enabled
|| !state
->writemask
||
1125 /* The following assumes that Z writes are disabled. */
1126 (state
->func
== PIPE_FUNC_ALWAYS
&& si_order_invariant_stencil_op(state
->zpass_op
) &&
1127 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1128 (state
->func
== PIPE_FUNC_NEVER
&& si_order_invariant_stencil_op(state
->fail_op
));
1131 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1132 const struct pipe_depth_stencil_alpha_state
*state
)
1134 struct si_context
*sctx
= (struct si_context
*)ctx
;
1135 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1136 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1137 unsigned db_depth_control
;
1138 uint32_t db_stencil_control
= 0;
1144 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1145 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1146 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1147 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1150 S_028800_Z_ENABLE(state
->depth
.enabled
) | S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1151 S_028800_ZFUNC(state
->depth
.func
) | S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1154 if (state
->stencil
[0].enabled
) {
1155 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1156 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1157 db_stencil_control
|=
1158 S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1159 db_stencil_control
|=
1160 S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1161 db_stencil_control
|=
1162 S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1164 if (state
->stencil
[1].enabled
) {
1165 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1166 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1167 db_stencil_control
|=
1168 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1169 db_stencil_control
|=
1170 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1171 db_stencil_control
|=
1172 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1177 if (state
->alpha
.enabled
) {
1178 dsa
->alpha_func
= state
->alpha
.func
;
1180 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+ SI_SGPR_ALPHA_REF
* 4,
1181 fui(state
->alpha
.ref_value
));
1183 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1186 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1187 if (state
->stencil
[0].enabled
)
1188 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1189 if (state
->depth
.bounds_test
) {
1190 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1191 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1194 dsa
->depth_enabled
= state
->depth
.enabled
;
1195 dsa
->depth_write_enabled
= state
->depth
.enabled
&& state
->depth
.writemask
;
1196 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1197 dsa
->stencil_write_enabled
=
1198 state
->stencil
[0].enabled
&&
1199 (si_dsa_writes_stencil(&state
->stencil
[0]) || si_dsa_writes_stencil(&state
->stencil
[1]));
1200 dsa
->db_can_write
= dsa
->depth_write_enabled
|| dsa
->stencil_write_enabled
;
1202 bool zfunc_is_ordered
=
1203 state
->depth
.func
== PIPE_FUNC_NEVER
|| state
->depth
.func
== PIPE_FUNC_LESS
||
1204 state
->depth
.func
== PIPE_FUNC_LEQUAL
|| state
->depth
.func
== PIPE_FUNC_GREATER
||
1205 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1207 bool nozwrite_and_order_invariant_stencil
=
1208 !dsa
->db_can_write
||
1209 (!dsa
->depth_write_enabled
&& si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1210 si_order_invariant_stencil_state(&state
->stencil
[1]));
1212 dsa
->order_invariance
[1].zs
=
1213 nozwrite_and_order_invariant_stencil
|| (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1214 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1216 dsa
->order_invariance
[1].pass_set
=
1217 nozwrite_and_order_invariant_stencil
||
1218 (!dsa
->stencil_write_enabled
&&
1219 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
));
1220 dsa
->order_invariance
[0].pass_set
=
1221 !dsa
->depth_write_enabled
||
1222 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
);
1224 dsa
->order_invariance
[1].pass_last
= sctx
->screen
->assume_no_z_fights
&&
1225 !dsa
->stencil_write_enabled
&& dsa
->depth_write_enabled
&&
1227 dsa
->order_invariance
[0].pass_last
=
1228 sctx
->screen
->assume_no_z_fights
&& dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1233 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1235 struct si_context
*sctx
= (struct si_context
*)ctx
;
1236 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1237 struct si_state_dsa
*dsa
= state
;
1240 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1242 si_pm4_bind_state(sctx
, dsa
, dsa
);
1244 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1245 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1246 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1247 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1250 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1251 sctx
->do_update_shaders
= true;
1253 if (sctx
->screen
->dpbb_allowed
&& ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1254 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1255 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1256 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1258 if (sctx
->screen
->has_out_of_order_rast
&&
1259 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1260 sizeof(old_dsa
->order_invariance
))))
1261 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1264 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1266 struct si_context
*sctx
= (struct si_context
*)ctx
;
1268 if (sctx
->queued
.named
.dsa
== state
)
1269 si_bind_dsa_state(ctx
, sctx
->noop_dsa
);
1271 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1274 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1276 struct pipe_depth_stencil_alpha_state dsa
= {};
1278 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1281 /* DB RENDER STATE */
1283 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1285 struct si_context
*sctx
= (struct si_context
*)ctx
;
1287 /* Pipeline stat & streamout queries. */
1289 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1290 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1292 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1293 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1296 /* Occlusion queries. */
1297 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1298 sctx
->occlusion_queries_disabled
= !enable
;
1299 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1303 void si_set_occlusion_query_state(struct si_context
*sctx
, bool old_perfect_enable
)
1305 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1307 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1309 if (perfect_enable
!= old_perfect_enable
)
1310 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1313 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1315 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1317 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1318 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1320 st
->saved_ssbo_writable_mask
= 0;
1322 for (unsigned i
= 0; i
< 3; i
++) {
1323 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1324 (1u << si_get_shaderbuf_slot(i
)))
1325 st
->saved_ssbo_writable_mask
|= 1 << i
;
1329 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1331 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1333 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1334 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1336 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1337 st
->saved_ssbo_writable_mask
);
1338 for (unsigned i
= 0; i
< 3; ++i
)
1339 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1342 static void si_emit_db_render_state(struct si_context
*sctx
)
1344 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1345 unsigned db_shader_control
, db_render_control
, db_count_control
;
1346 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1348 /* DB_RENDER_CONTROL */
1349 if (sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
) {
1350 db_render_control
= S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1351 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1352 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1353 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1354 db_render_control
= S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1355 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1357 db_render_control
= S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1358 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1361 /* DB_COUNT_CONTROL (occlusion queries) */
1362 if (sctx
->num_occlusion_queries
> 0 && !sctx
->occlusion_queries_disabled
) {
1363 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1364 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1366 if (sctx
->chip_class
>= GFX7
) {
1367 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1369 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1370 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1371 S_028004_SAMPLE_RATE(log_sample_rate
) | S_028004_ZPASS_ENABLE(1) |
1372 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1374 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1375 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1378 /* Disable occlusion queries. */
1379 if (sctx
->chip_class
>= GFX7
) {
1380 db_count_control
= 0;
1382 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1386 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
, SI_TRACKED_DB_RENDER_CONTROL
,
1387 db_render_control
, db_count_control
);
1389 /* DB_RENDER_OVERRIDE2 */
1390 radeon_opt_set_context_reg(
1391 sctx
, R_028010_DB_RENDER_OVERRIDE2
, SI_TRACKED_DB_RENDER_OVERRIDE2
,
1392 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1393 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1394 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4) |
1395 S_028010_CENTROID_COMPUTATION_MODE_GFX103(sctx
->chip_class
>= GFX10_3
? 2 : 0));
1397 db_shader_control
= sctx
->ps_db_shader_control
;
1399 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1400 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1401 db_shader_control
&= C_02880C_Z_ORDER
;
1402 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1405 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1406 if (!rs
->multisample_enable
)
1407 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1409 if (sctx
->screen
->info
.has_rbplus
&& !sctx
->screen
->info
.rbplus_allowed
)
1410 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1412 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
, SI_TRACKED_DB_SHADER_CONTROL
,
1415 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1416 sctx
->context_roll
= true;
1420 * format translation
1422 static uint32_t si_translate_colorformat(enum chip_class chip_class
,
1423 enum pipe_format format
)
1425 const struct util_format_description
*desc
= util_format_description(format
);
1427 return V_028C70_COLOR_INVALID
;
1429 #define HAS_SIZE(x, y, z, w) \
1430 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1431 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1433 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1434 return V_028C70_COLOR_10_11_11
;
1436 if (chip_class
>= GFX10_3
&&
1437 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) /* isn't plain */
1438 return V_028C70_COLOR_5_9_9_9
;
1440 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1441 return V_028C70_COLOR_INVALID
;
1443 /* hw cannot support mixed formats (except depth/stencil, since
1444 * stencil is not written to). */
1445 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1446 return V_028C70_COLOR_INVALID
;
1448 switch (desc
->nr_channels
) {
1450 switch (desc
->channel
[0].size
) {
1452 return V_028C70_COLOR_8
;
1454 return V_028C70_COLOR_16
;
1456 return V_028C70_COLOR_32
;
1460 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1461 switch (desc
->channel
[0].size
) {
1463 return V_028C70_COLOR_8_8
;
1465 return V_028C70_COLOR_16_16
;
1467 return V_028C70_COLOR_32_32
;
1469 } else if (HAS_SIZE(8, 24, 0, 0)) {
1470 return V_028C70_COLOR_24_8
;
1471 } else if (HAS_SIZE(24, 8, 0, 0)) {
1472 return V_028C70_COLOR_8_24
;
1476 if (HAS_SIZE(5, 6, 5, 0)) {
1477 return V_028C70_COLOR_5_6_5
;
1478 } else if (HAS_SIZE(32, 8, 24, 0)) {
1479 return V_028C70_COLOR_X24_8_32_FLOAT
;
1483 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1484 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1485 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1486 switch (desc
->channel
[0].size
) {
1488 return V_028C70_COLOR_4_4_4_4
;
1490 return V_028C70_COLOR_8_8_8_8
;
1492 return V_028C70_COLOR_16_16_16_16
;
1494 return V_028C70_COLOR_32_32_32_32
;
1496 } else if (HAS_SIZE(5, 5, 5, 1)) {
1497 return V_028C70_COLOR_1_5_5_5
;
1498 } else if (HAS_SIZE(1, 5, 5, 5)) {
1499 return V_028C70_COLOR_5_5_5_1
;
1500 } else if (HAS_SIZE(10, 10, 10, 2)) {
1501 return V_028C70_COLOR_2_10_10_10
;
1505 return V_028C70_COLOR_INVALID
;
1508 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1510 if (SI_BIG_ENDIAN
) {
1511 switch (colorformat
) {
1512 /* 8-bit buffers. */
1513 case V_028C70_COLOR_8
:
1514 return V_028C70_ENDIAN_NONE
;
1516 /* 16-bit buffers. */
1517 case V_028C70_COLOR_5_6_5
:
1518 case V_028C70_COLOR_1_5_5_5
:
1519 case V_028C70_COLOR_4_4_4_4
:
1520 case V_028C70_COLOR_16
:
1521 case V_028C70_COLOR_8_8
:
1522 return V_028C70_ENDIAN_8IN16
;
1524 /* 32-bit buffers. */
1525 case V_028C70_COLOR_8_8_8_8
:
1526 case V_028C70_COLOR_2_10_10_10
:
1527 case V_028C70_COLOR_8_24
:
1528 case V_028C70_COLOR_24_8
:
1529 case V_028C70_COLOR_16_16
:
1530 return V_028C70_ENDIAN_8IN32
;
1532 /* 64-bit buffers. */
1533 case V_028C70_COLOR_16_16_16_16
:
1534 return V_028C70_ENDIAN_8IN16
;
1536 case V_028C70_COLOR_32_32
:
1537 return V_028C70_ENDIAN_8IN32
;
1539 /* 128-bit buffers. */
1540 case V_028C70_COLOR_32_32_32_32
:
1541 return V_028C70_ENDIAN_8IN32
;
1543 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1546 return V_028C70_ENDIAN_NONE
;
1550 static uint32_t si_translate_dbformat(enum pipe_format format
)
1553 case PIPE_FORMAT_Z16_UNORM
:
1554 return V_028040_Z_16
;
1555 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1556 case PIPE_FORMAT_X8Z24_UNORM
:
1557 case PIPE_FORMAT_Z24X8_UNORM
:
1558 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1559 return V_028040_Z_24
; /* deprecated on AMD GCN */
1560 case PIPE_FORMAT_Z32_FLOAT
:
1561 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1562 return V_028040_Z_32_FLOAT
;
1564 return V_028040_Z_INVALID
;
1569 * Texture translation
1572 static uint32_t si_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
1573 const struct util_format_description
*desc
,
1576 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1577 bool uniform
= true;
1580 assert(sscreen
->info
.chip_class
<= GFX9
);
1582 /* Colorspace (return non-RGB formats directly). */
1583 switch (desc
->colorspace
) {
1584 /* Depth stencil formats */
1585 case UTIL_FORMAT_COLORSPACE_ZS
:
1587 case PIPE_FORMAT_Z16_UNORM
:
1588 return V_008F14_IMG_DATA_FORMAT_16
;
1589 case PIPE_FORMAT_X24S8_UINT
:
1590 case PIPE_FORMAT_S8X24_UINT
:
1592 * Implemented as an 8_8_8_8 data format to fix texture
1593 * gathers in stencil sampling. This affects at least
1594 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1596 if (sscreen
->info
.chip_class
<= GFX8
)
1597 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1599 if (format
== PIPE_FORMAT_X24S8_UINT
)
1600 return V_008F14_IMG_DATA_FORMAT_8_24
;
1602 return V_008F14_IMG_DATA_FORMAT_24_8
;
1603 case PIPE_FORMAT_Z24X8_UNORM
:
1604 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1605 return V_008F14_IMG_DATA_FORMAT_8_24
;
1606 case PIPE_FORMAT_X8Z24_UNORM
:
1607 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1608 return V_008F14_IMG_DATA_FORMAT_24_8
;
1609 case PIPE_FORMAT_S8_UINT
:
1610 return V_008F14_IMG_DATA_FORMAT_8
;
1611 case PIPE_FORMAT_Z32_FLOAT
:
1612 return V_008F14_IMG_DATA_FORMAT_32
;
1613 case PIPE_FORMAT_X32_S8X24_UINT
:
1614 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1615 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1620 case UTIL_FORMAT_COLORSPACE_YUV
:
1621 goto out_unknown
; /* TODO */
1623 case UTIL_FORMAT_COLORSPACE_SRGB
:
1624 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1632 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1633 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1637 case PIPE_FORMAT_RGTC1_SNORM
:
1638 case PIPE_FORMAT_LATC1_SNORM
:
1639 case PIPE_FORMAT_RGTC1_UNORM
:
1640 case PIPE_FORMAT_LATC1_UNORM
:
1641 return V_008F14_IMG_DATA_FORMAT_BC4
;
1642 case PIPE_FORMAT_RGTC2_SNORM
:
1643 case PIPE_FORMAT_LATC2_SNORM
:
1644 case PIPE_FORMAT_RGTC2_UNORM
:
1645 case PIPE_FORMAT_LATC2_UNORM
:
1646 return V_008F14_IMG_DATA_FORMAT_BC5
;
1652 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1653 (sscreen
->info
.family
== CHIP_STONEY
|| sscreen
->info
.family
== CHIP_VEGA10
||
1654 sscreen
->info
.family
== CHIP_RAVEN
)) {
1656 case PIPE_FORMAT_ETC1_RGB8
:
1657 case PIPE_FORMAT_ETC2_RGB8
:
1658 case PIPE_FORMAT_ETC2_SRGB8
:
1659 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1660 case PIPE_FORMAT_ETC2_RGB8A1
:
1661 case PIPE_FORMAT_ETC2_SRGB8A1
:
1662 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1663 case PIPE_FORMAT_ETC2_RGBA8
:
1664 case PIPE_FORMAT_ETC2_SRGBA8
:
1665 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1666 case PIPE_FORMAT_ETC2_R11_UNORM
:
1667 case PIPE_FORMAT_ETC2_R11_SNORM
:
1668 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1669 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1670 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1671 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1677 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1678 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1682 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1683 case PIPE_FORMAT_BPTC_SRGBA
:
1684 return V_008F14_IMG_DATA_FORMAT_BC7
;
1685 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1686 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1687 return V_008F14_IMG_DATA_FORMAT_BC6
;
1693 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1695 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1696 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1697 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1698 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1699 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1700 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1706 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1707 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1711 case PIPE_FORMAT_DXT1_RGB
:
1712 case PIPE_FORMAT_DXT1_RGBA
:
1713 case PIPE_FORMAT_DXT1_SRGB
:
1714 case PIPE_FORMAT_DXT1_SRGBA
:
1715 return V_008F14_IMG_DATA_FORMAT_BC1
;
1716 case PIPE_FORMAT_DXT3_RGBA
:
1717 case PIPE_FORMAT_DXT3_SRGBA
:
1718 return V_008F14_IMG_DATA_FORMAT_BC2
;
1719 case PIPE_FORMAT_DXT5_RGBA
:
1720 case PIPE_FORMAT_DXT5_SRGBA
:
1721 return V_008F14_IMG_DATA_FORMAT_BC3
;
1727 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1728 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1729 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1730 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1733 /* R8G8Bx_SNORM - TODO CxV8U8 */
1735 /* hw cannot support mixed formats (except depth/stencil, since only
1737 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1740 /* See whether the components are of the same size. */
1741 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1742 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1745 /* Non-uniform formats. */
1747 switch (desc
->nr_channels
) {
1749 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 6 &&
1750 desc
->channel
[2].size
== 5) {
1751 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1755 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 5 &&
1756 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 1) {
1757 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1759 if (desc
->channel
[0].size
== 1 && desc
->channel
[1].size
== 5 &&
1760 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 5) {
1761 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1763 if (desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1764 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2) {
1765 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1772 if (first_non_void
< 0 || first_non_void
> 3)
1775 /* uniform formats */
1776 switch (desc
->channel
[first_non_void
].size
) {
1778 switch (desc
->nr_channels
) {
1779 #if 0 /* Not supported for render targets */
1781 return V_008F14_IMG_DATA_FORMAT_4_4
;
1784 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1788 switch (desc
->nr_channels
) {
1790 return V_008F14_IMG_DATA_FORMAT_8
;
1792 return V_008F14_IMG_DATA_FORMAT_8_8
;
1794 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1798 switch (desc
->nr_channels
) {
1800 return V_008F14_IMG_DATA_FORMAT_16
;
1802 return V_008F14_IMG_DATA_FORMAT_16_16
;
1804 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1808 switch (desc
->nr_channels
) {
1810 return V_008F14_IMG_DATA_FORMAT_32
;
1812 return V_008F14_IMG_DATA_FORMAT_32_32
;
1813 #if 0 /* Not supported for render targets */
1815 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1818 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1826 static unsigned si_tex_wrap(unsigned wrap
)
1830 case PIPE_TEX_WRAP_REPEAT
:
1831 return V_008F30_SQ_TEX_WRAP
;
1832 case PIPE_TEX_WRAP_CLAMP
:
1833 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1834 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1835 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1836 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1837 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1838 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1839 return V_008F30_SQ_TEX_MIRROR
;
1840 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1841 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1842 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1843 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1844 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1845 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1849 static unsigned si_tex_mipfilter(unsigned filter
)
1852 case PIPE_TEX_MIPFILTER_NEAREST
:
1853 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1854 case PIPE_TEX_MIPFILTER_LINEAR
:
1855 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1857 case PIPE_TEX_MIPFILTER_NONE
:
1858 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1862 static unsigned si_tex_compare(unsigned compare
)
1866 case PIPE_FUNC_NEVER
:
1867 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1868 case PIPE_FUNC_LESS
:
1869 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1870 case PIPE_FUNC_EQUAL
:
1871 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1872 case PIPE_FUNC_LEQUAL
:
1873 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1874 case PIPE_FUNC_GREATER
:
1875 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1876 case PIPE_FUNC_NOTEQUAL
:
1877 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1878 case PIPE_FUNC_GEQUAL
:
1879 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1880 case PIPE_FUNC_ALWAYS
:
1881 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1885 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
, unsigned view_target
,
1886 unsigned nr_samples
)
1888 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1890 if (view_target
== PIPE_TEXTURE_CUBE
|| view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1891 res_target
= view_target
;
1892 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1893 else if (res_target
== PIPE_TEXTURE_CUBE
|| res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1894 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1896 /* GFX9 allocates 1D textures as 2D. */
1897 if ((res_target
== PIPE_TEXTURE_1D
|| res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1898 sscreen
->info
.chip_class
== GFX9
&&
1899 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1900 if (res_target
== PIPE_TEXTURE_1D
)
1901 res_target
= PIPE_TEXTURE_2D
;
1903 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1906 switch (res_target
) {
1908 case PIPE_TEXTURE_1D
:
1909 return V_008F1C_SQ_RSRC_IMG_1D
;
1910 case PIPE_TEXTURE_1D_ARRAY
:
1911 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1912 case PIPE_TEXTURE_2D
:
1913 case PIPE_TEXTURE_RECT
:
1914 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
: V_008F1C_SQ_RSRC_IMG_2D
;
1915 case PIPE_TEXTURE_2D_ARRAY
:
1916 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1917 case PIPE_TEXTURE_3D
:
1918 return V_008F1C_SQ_RSRC_IMG_3D
;
1919 case PIPE_TEXTURE_CUBE
:
1920 case PIPE_TEXTURE_CUBE_ARRAY
:
1921 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1926 * Format support testing
1929 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1931 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1933 if (sscreen
->info
.chip_class
>= GFX10
) {
1934 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
1935 if (!fmt
->img_format
|| fmt
->buffers_only
)
1940 const struct util_format_description
*desc
= util_format_description(format
);
1944 return si_translate_texformat(screen
, format
, desc
,
1945 util_format_get_first_non_void_channel(format
)) != ~0U;
1948 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1949 const struct util_format_description
*desc
,
1954 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
1956 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1957 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1959 assert(first_non_void
>= 0);
1961 if (desc
->nr_channels
== 4 && desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1962 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2)
1963 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1965 /* See whether the components are of the same size. */
1966 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1967 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1968 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1971 switch (desc
->channel
[first_non_void
].size
) {
1973 switch (desc
->nr_channels
) {
1975 case 3: /* 3 loads */
1976 return V_008F0C_BUF_DATA_FORMAT_8
;
1978 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1980 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1984 switch (desc
->nr_channels
) {
1986 case 3: /* 3 loads */
1987 return V_008F0C_BUF_DATA_FORMAT_16
;
1989 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1991 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1995 switch (desc
->nr_channels
) {
1997 return V_008F0C_BUF_DATA_FORMAT_32
;
1999 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2001 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2003 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2007 /* Legacy double formats. */
2008 switch (desc
->nr_channels
) {
2009 case 1: /* 1 load */
2010 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2011 case 2: /* 1 load */
2012 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2013 case 3: /* 3 loads */
2014 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2015 case 4: /* 2 loads */
2016 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2021 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2024 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2025 const struct util_format_description
*desc
,
2028 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2030 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2031 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2033 assert(first_non_void
>= 0);
2035 switch (desc
->channel
[first_non_void
].type
) {
2036 case UTIL_FORMAT_TYPE_SIGNED
:
2037 case UTIL_FORMAT_TYPE_FIXED
:
2038 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2039 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2040 else if (desc
->channel
[first_non_void
].normalized
)
2041 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2043 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2045 case UTIL_FORMAT_TYPE_UNSIGNED
:
2046 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2047 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2048 else if (desc
->channel
[first_non_void
].normalized
)
2049 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2051 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2053 case UTIL_FORMAT_TYPE_FLOAT
:
2055 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2059 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2062 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2063 const struct util_format_description
*desc
;
2065 unsigned data_format
;
2067 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_VERTEX_BUFFER
)) ==
2070 desc
= util_format_description(format
);
2074 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2075 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2076 * for read-only access (with caveats surrounding bounds checks), but
2077 * obviously fails for write access which we have to implement for
2078 * shader images. Luckily, OpenGL doesn't expect this to be supported
2079 * anyway, and so the only impact is on PBO uploads / downloads, which
2080 * shouldn't be expected to be fast for GL_RGB anyway.
2082 if (desc
->block
.bits
== 3 * 8 || desc
->block
.bits
== 3 * 16) {
2083 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2084 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2090 if (sscreen
->info
.chip_class
>= GFX10
) {
2091 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2092 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2097 first_non_void
= util_format_get_first_non_void_channel(format
);
2098 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2099 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2105 static bool si_is_colorbuffer_format_supported(enum chip_class chip_class
,
2106 enum pipe_format format
)
2108 return si_translate_colorformat(chip_class
, format
) != V_028C70_COLOR_INVALID
&&
2109 si_translate_colorswap(format
, false) != ~0U;
2112 static bool si_is_zs_format_supported(enum pipe_format format
)
2114 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2117 static bool si_is_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2118 enum pipe_texture_target target
, unsigned sample_count
,
2119 unsigned storage_sample_count
, unsigned usage
)
2121 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2122 unsigned retval
= 0;
2124 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2125 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2129 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2132 if (sample_count
> 1) {
2133 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2136 /* Only power-of-two sample counts are supported. */
2137 if (!util_is_power_of_two_or_zero(sample_count
) ||
2138 !util_is_power_of_two_or_zero(storage_sample_count
))
2141 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2142 * so don't expose 16 samples there.
2144 const unsigned max_eqaa_samples
= sscreen
->info
.num_render_backends
== 1 ? 8 : 16;
2145 const unsigned max_samples
= 8;
2147 /* MSAA support without framebuffer attachments. */
2148 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= max_eqaa_samples
)
2151 if (!sscreen
->info
.has_eqaa_surface_allocator
|| util_format_is_depth_or_stencil(format
)) {
2152 /* Color without EQAA or depth/stencil. */
2153 if (sample_count
> max_samples
|| sample_count
!= storage_sample_count
)
2156 /* Color with EQAA. */
2157 if (sample_count
> max_eqaa_samples
|| storage_sample_count
> max_samples
)
2162 if (usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
)) {
2163 if (target
== PIPE_BUFFER
) {
2164 retval
|= si_is_vertex_format_supported(
2165 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
));
2167 if (si_is_sampler_format_supported(screen
, format
))
2168 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
);
2172 if ((usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2173 PIPE_BIND_SHARED
| PIPE_BIND_BLENDABLE
)) &&
2174 si_is_colorbuffer_format_supported(sscreen
->info
.chip_class
, format
)) {
2175 retval
|= usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2177 if (!util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
))
2178 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2181 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) && si_is_zs_format_supported(format
)) {
2182 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2185 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2186 retval
|= si_is_vertex_format_supported(screen
, format
, PIPE_BIND_VERTEX_BUFFER
);
2189 if ((usage
& PIPE_BIND_LINEAR
) && !util_format_is_compressed(format
) &&
2190 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2191 retval
|= PIPE_BIND_LINEAR
;
2193 return retval
== usage
;
2197 * framebuffer handling
2200 static void si_choose_spi_color_formats(struct si_surface
*surf
, unsigned format
, unsigned swap
,
2201 unsigned ntype
, bool is_depth
)
2203 /* Alpha is needed for alpha-to-coverage.
2204 * Blending may be with or without alpha.
2206 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2207 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2208 unsigned blend
= 0; /* supports blending, but may not export alpha */
2209 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2211 /* Choose the SPI color formats. These are required values for RB+.
2212 * Other chips have multiple choices, though they are not necessarily better.
2215 case V_028C70_COLOR_5_6_5
:
2216 case V_028C70_COLOR_1_5_5_5
:
2217 case V_028C70_COLOR_5_5_5_1
:
2218 case V_028C70_COLOR_4_4_4_4
:
2219 case V_028C70_COLOR_10_11_11
:
2220 case V_028C70_COLOR_11_11_10
:
2221 case V_028C70_COLOR_5_9_9_9
:
2222 case V_028C70_COLOR_8
:
2223 case V_028C70_COLOR_8_8
:
2224 case V_028C70_COLOR_8_8_8_8
:
2225 case V_028C70_COLOR_10_10_10_2
:
2226 case V_028C70_COLOR_2_10_10_10
:
2227 if (ntype
== V_028C70_NUMBER_UINT
)
2228 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2229 else if (ntype
== V_028C70_NUMBER_SINT
)
2230 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2232 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2235 case V_028C70_COLOR_16
:
2236 case V_028C70_COLOR_16_16
:
2237 case V_028C70_COLOR_16_16_16_16
:
2238 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) {
2239 /* UNORM16 and SNORM16 don't support blending */
2240 if (ntype
== V_028C70_NUMBER_UNORM
)
2241 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2243 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2245 /* Use 32 bits per channel for blending. */
2246 if (format
== V_028C70_COLOR_16
) {
2247 if (swap
== V_028C70_SWAP_STD
) { /* R */
2248 blend
= V_028714_SPI_SHADER_32_R
;
2249 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2250 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2251 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2254 } else if (format
== V_028C70_COLOR_16_16
) {
2255 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2256 blend
= V_028714_SPI_SHADER_32_GR
;
2257 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2258 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2259 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2262 } else /* 16_16_16_16 */
2263 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2264 } else if (ntype
== V_028C70_NUMBER_UINT
)
2265 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2266 else if (ntype
== V_028C70_NUMBER_SINT
)
2267 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2268 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2269 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2274 case V_028C70_COLOR_32
:
2275 if (swap
== V_028C70_SWAP_STD
) { /* R */
2276 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2277 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2278 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2279 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2284 case V_028C70_COLOR_32_32
:
2285 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2286 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2287 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2288 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2289 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2294 case V_028C70_COLOR_32_32_32_32
:
2295 case V_028C70_COLOR_8_24
:
2296 case V_028C70_COLOR_24_8
:
2297 case V_028C70_COLOR_X24_8_32_FLOAT
:
2298 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2306 /* The DB->CB copy needs 32_ABGR. */
2308 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2310 surf
->spi_shader_col_format
= normal
;
2311 surf
->spi_shader_col_format_alpha
= alpha
;
2312 surf
->spi_shader_col_format_blend
= blend
;
2313 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2316 static void si_initialize_color_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2318 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2319 unsigned color_info
, color_attrib
;
2320 unsigned format
, swap
, ntype
, endian
;
2321 const struct util_format_description
*desc
;
2323 unsigned blend_clamp
= 0, blend_bypass
= 0;
2325 desc
= util_format_description(surf
->base
.format
);
2326 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2327 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2331 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2332 ntype
= V_028C70_NUMBER_FLOAT
;
2334 ntype
= V_028C70_NUMBER_UNORM
;
2335 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2336 ntype
= V_028C70_NUMBER_SRGB
;
2337 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2338 if (desc
->channel
[firstchan
].pure_integer
) {
2339 ntype
= V_028C70_NUMBER_SINT
;
2341 assert(desc
->channel
[firstchan
].normalized
);
2342 ntype
= V_028C70_NUMBER_SNORM
;
2344 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2345 if (desc
->channel
[firstchan
].pure_integer
) {
2346 ntype
= V_028C70_NUMBER_UINT
;
2348 assert(desc
->channel
[firstchan
].normalized
);
2349 ntype
= V_028C70_NUMBER_UNORM
;
2354 format
= si_translate_colorformat(sctx
->chip_class
, surf
->base
.format
);
2355 if (format
== V_028C70_COLOR_INVALID
) {
2356 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2358 assert(format
!= V_028C70_COLOR_INVALID
);
2359 swap
= si_translate_colorswap(surf
->base
.format
, false);
2360 endian
= si_colorformat_endian_swap(format
);
2362 /* blend clamp should be set for all NORM/SRGB types */
2363 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
2364 ntype
== V_028C70_NUMBER_SRGB
)
2367 /* set blend bypass according to docs if SINT/UINT or
2368 8/24 COLOR variants */
2369 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2370 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2371 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2376 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2377 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_8_8
||
2378 format
== V_028C70_COLOR_8_8_8_8
)
2379 surf
->color_is_int8
= true;
2380 else if (format
== V_028C70_COLOR_10_10_10_2
|| format
== V_028C70_COLOR_2_10_10_10
)
2381 surf
->color_is_int10
= true;
2385 S_028C70_FORMAT(format
) | S_028C70_COMP_SWAP(swap
) | S_028C70_BLEND_CLAMP(blend_clamp
) |
2386 S_028C70_BLEND_BYPASS(blend_bypass
) | S_028C70_SIMPLE_FLOAT(1) |
2387 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&& ntype
!= V_028C70_NUMBER_SNORM
&&
2388 ntype
!= V_028C70_NUMBER_SRGB
&& format
!= V_028C70_COLOR_8_24
&&
2389 format
!= V_028C70_COLOR_24_8
) |
2390 S_028C70_NUMBER_TYPE(ntype
) | S_028C70_ENDIAN(endian
);
2392 /* Intensity is implemented as Red, so treat it that way. */
2393 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2394 util_format_is_intensity(surf
->base
.format
));
2396 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2397 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2398 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2400 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) | S_028C74_NUM_FRAGMENTS(log_fragments
);
2402 if (tex
->surface
.fmask_offset
) {
2403 color_info
|= S_028C70_COMPRESSION(1);
2404 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2406 if (sctx
->chip_class
== GFX6
) {
2407 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2408 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2413 if (sctx
->chip_class
>= GFX10
) {
2414 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2416 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2417 64 for APU because all of our APUs to date use DIMMs which have
2418 a request granularity size of 64B while all other chips have a
2420 if (!sctx
->screen
->info
.has_dedicated_vram
)
2421 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2423 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2424 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
2425 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2426 S_028C78_INDEPENDENT_64B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_64B_blocks
) |
2427 S_028C78_INDEPENDENT_128B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_128B_blocks
);
2428 } else if (sctx
->chip_class
>= GFX8
) {
2429 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2430 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2432 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2433 64 for APU because all of our APUs to date use DIMMs which have
2434 a request granularity size of 64B while all other chips have a
2436 if (!sctx
->screen
->info
.has_dedicated_vram
)
2437 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2439 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2440 if (tex
->surface
.bpe
== 1)
2441 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2442 else if (tex
->surface
.bpe
== 2)
2443 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2446 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2447 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2448 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2451 /* This must be set for fast clear to work without FMASK. */
2452 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2453 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2454 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2457 /* GFX10 field has the same base shift as the GFX6 field */
2458 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2459 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2460 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2462 if (sctx
->chip_class
>= GFX10
) {
2463 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2465 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2466 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2467 S_028EE0_RESOURCE_LEVEL(1);
2468 } else if (sctx
->chip_class
== GFX9
) {
2469 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2470 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2471 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2474 if (sctx
->chip_class
>= GFX9
) {
2475 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2476 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2477 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2480 surf
->cb_color_view
= color_view
;
2481 surf
->cb_color_info
= color_info
;
2482 surf
->cb_color_attrib
= color_attrib
;
2484 /* Determine pixel shader export format */
2485 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2487 surf
->color_initialized
= true;
2490 static void si_init_depth_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2492 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2493 unsigned level
= surf
->base
.u
.tex
.level
;
2494 unsigned format
, stencil_format
;
2495 uint32_t z_info
, s_info
;
2497 format
= si_translate_dbformat(tex
->db_render_format
);
2498 stencil_format
= tex
->surface
.has_stencil
? V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2500 assert(format
!= V_028040_Z_INVALID
);
2501 if (format
== V_028040_Z_INVALID
)
2502 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2504 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2505 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2506 surf
->db_htile_data_base
= 0;
2507 surf
->db_htile_surface
= 0;
2509 if (sctx
->chip_class
>= GFX10
) {
2510 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2511 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2514 if (sctx
->chip_class
>= GFX9
) {
2515 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2516 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2517 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2518 z_info
= S_028038_FORMAT(format
) |
2519 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2520 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2521 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2522 s_info
= S_02803C_FORMAT(stencil_format
) |
2523 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2525 if (sctx
->chip_class
== GFX9
) {
2526 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2527 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2529 surf
->db_depth_view
|= S_028008_MIPID(level
);
2530 surf
->db_depth_size
=
2531 S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) | S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2533 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2534 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2536 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2537 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2538 * See that for explanation.
2540 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2542 /* Use all HTILE for depth if there's no stencil. */
2543 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2546 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2547 surf
->db_htile_surface
=
2548 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
2549 if (sctx
->chip_class
== GFX9
) {
2550 surf
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
2555 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2557 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2559 surf
->db_depth_base
=
2560 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2561 surf
->db_stencil_base
=
2562 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2565 S_028040_FORMAT(format
) | S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2566 s_info
= S_028044_FORMAT(stencil_format
);
2567 surf
->db_depth_info
= 0;
2569 if (sctx
->chip_class
>= GFX7
) {
2570 struct radeon_info
*info
= &sctx
->screen
->info
;
2571 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2572 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2573 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2574 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2575 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2576 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2578 surf
->db_depth_info
|= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2579 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2580 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2581 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2582 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2583 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2584 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2585 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2587 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2588 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2589 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2590 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2593 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2594 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2595 surf
->db_depth_slice
=
2596 S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
* levelinfo
->nblk_y
) / 64 - 1);
2598 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2599 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2601 if (tex
->surface
.has_stencil
) {
2602 /* Workaround: For a not yet understood reason, the
2603 * combination of MSAA, fast stencil clear and stencil
2604 * decompress messes with subsequent stencil buffer
2605 * uses. Problem was reproduced on Verde, Bonaire,
2606 * Tonga, and Carrizo.
2608 * Disabling EXPCLEAR works around the problem.
2610 * Check piglit's arb_texture_multisample-stencil-clear
2611 * test if you want to try changing this.
2613 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2614 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2617 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2618 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2622 surf
->db_z_info
= z_info
;
2623 surf
->db_stencil_info
= s_info
;
2625 surf
->depth_initialized
= true;
2628 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2630 if (sctx
->decompression_enabled
)
2633 if (sctx
->framebuffer
.state
.zsbuf
) {
2634 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2635 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2637 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2639 if (tex
->surface
.has_stencil
)
2640 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2643 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2644 while (compressed_cb_mask
) {
2645 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2646 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2647 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2649 if (tex
->surface
.fmask_offset
) {
2650 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2651 tex
->fmask_is_identity
= false;
2653 if (tex
->dcc_gather_statistics
)
2654 tex
->separate_dcc_dirty
= true;
2658 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2660 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2661 struct si_surface
*surf
= NULL
;
2662 struct si_texture
*tex
;
2664 if (!state
->cbufs
[i
])
2666 surf
= (struct si_surface
*)state
->cbufs
[i
];
2667 tex
= (struct si_texture
*)surf
->base
.texture
;
2669 p_atomic_dec(&tex
->framebuffers_bound
);
2673 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2674 const struct pipe_framebuffer_state
*state
)
2676 struct si_context
*sctx
= (struct si_context
*)ctx
;
2677 struct si_surface
*surf
= NULL
;
2678 struct si_texture
*tex
;
2679 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2680 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2681 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2682 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2683 bool old_has_stencil
=
2685 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2686 bool unbound
= false;
2689 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2690 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2691 * We could implement the full workaround here, but it's a useless case.
2693 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2694 unreachable("the framebuffer shouldn't have zero area");
2698 si_update_fb_dirtiness_after_rendering(sctx
);
2700 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2701 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2704 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2705 if (tex
->dcc_gather_statistics
)
2706 vi_separate_dcc_stop_query(sctx
, tex
);
2709 /* Disable DCC if the formats are incompatible. */
2710 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2711 if (!state
->cbufs
[i
])
2714 surf
= (struct si_surface
*)state
->cbufs
[i
];
2715 tex
= (struct si_texture
*)surf
->base
.texture
;
2717 if (!surf
->dcc_incompatible
)
2720 /* Since the DCC decompression calls back into set_framebuffer-
2721 * _state, we need to unbind the framebuffer, so that
2722 * vi_separate_dcc_stop_query isn't called twice with the same
2726 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2730 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2731 if (!si_texture_disable_dcc(sctx
, tex
))
2732 si_decompress_dcc(sctx
, tex
);
2734 surf
->dcc_incompatible
= false;
2737 /* Only flush TC when changing the framebuffer state, because
2738 * the only client not using TC that can change textures is
2741 * Wait for compute shaders because of possible transitions:
2742 * - FB write -> shader read
2743 * - shader write -> FB read
2745 * DB caches are flushed on demand (using si_decompress_textures).
2747 * When MSAA is enabled, CB and TC caches are flushed on demand
2748 * (after FMASK decompression). Shader write -> FB read transitions
2749 * cannot happen for MSAA textures, because MSAA shader images are
2752 * Only flush and wait for CB if there is actually a bound color buffer.
2754 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2755 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2756 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2757 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2760 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2762 /* u_blitter doesn't invoke depth decompression when it does multiple
2763 * blits in a row, but the only case when it matters for DB is when
2764 * doing generate_mipmap. So here we flush DB manually between
2765 * individual generate_mipmap blits.
2766 * Note that lower mipmap levels aren't compressed.
2768 if (sctx
->generate_mipmap_for_depth
) {
2769 si_make_DB_shader_coherent(sctx
, 1, false, sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2770 } else if (sctx
->chip_class
== GFX9
) {
2771 /* It appears that DB metadata "leaks" in a sequence of:
2773 * - DCC decompress for shader image writes (with DB disabled)
2774 * - render with DEPTH_BEFORE_SHADER=1
2775 * Flushing DB metadata works around the problem.
2777 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2780 /* Take the maximum of the old and new count. If the new count is lower,
2781 * dirtying is needed to disable the unbound colorbuffers.
2783 sctx
->framebuffer
.dirty_cbufs
|=
2784 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2785 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2787 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2788 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2790 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2791 sctx
->framebuffer
.spi_shader_col_format
= 0;
2792 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2793 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2794 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2795 sctx
->framebuffer
.color_is_int8
= 0;
2796 sctx
->framebuffer
.color_is_int10
= 0;
2798 sctx
->framebuffer
.compressed_cb_mask
= 0;
2799 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2800 sctx
->framebuffer
.displayable_dcc_cb_mask
= 0;
2801 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2802 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2803 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2804 sctx
->framebuffer
.any_dst_linear
= false;
2805 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2806 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2807 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2808 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2810 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2811 if (!state
->cbufs
[i
])
2814 surf
= (struct si_surface
*)state
->cbufs
[i
];
2815 tex
= (struct si_texture
*)surf
->base
.texture
;
2817 if (!surf
->color_initialized
) {
2818 si_initialize_color_surface(sctx
, surf
);
2821 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2822 sctx
->framebuffer
.spi_shader_col_format
|= surf
->spi_shader_col_format
<< (i
* 4);
2823 sctx
->framebuffer
.spi_shader_col_format_alpha
|= surf
->spi_shader_col_format_alpha
<< (i
* 4);
2824 sctx
->framebuffer
.spi_shader_col_format_blend
|= surf
->spi_shader_col_format_blend
<< (i
* 4);
2825 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|= surf
->spi_shader_col_format_blend_alpha
2828 if (surf
->color_is_int8
)
2829 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2830 if (surf
->color_is_int10
)
2831 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2833 if (tex
->surface
.fmask_offset
)
2834 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2836 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2838 if (tex
->surface
.display_dcc_offset
)
2839 sctx
->framebuffer
.displayable_dcc_cb_mask
|= 1 << i
;
2841 /* Don't update nr_color_samples for non-AA buffers.
2842 * (e.g. destination of MSAA resolve)
2844 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2845 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2846 sctx
->framebuffer
.nr_color_samples
=
2847 MIN2(sctx
->framebuffer
.nr_color_samples
, tex
->buffer
.b
.b
.nr_storage_samples
);
2848 sctx
->framebuffer
.nr_color_samples
= MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2851 if (tex
->surface
.is_linear
)
2852 sctx
->framebuffer
.any_dst_linear
= true;
2854 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
2855 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2857 if (sctx
->chip_class
>= GFX9
&& !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
2858 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
2861 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2863 p_atomic_inc(&tex
->framebuffers_bound
);
2865 if (tex
->dcc_gather_statistics
) {
2866 /* Dirty tracking must be enabled for DCC usage analysis. */
2867 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2868 vi_separate_dcc_start_query(sctx
, tex
);
2871 /* Update the minimum but don't keep 0. */
2872 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2873 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2874 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
2877 /* For optimal DCC performance. */
2878 if (sctx
->chip_class
>= GFX10
)
2879 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2881 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2883 struct si_texture
*zstex
= NULL
;
2886 surf
= (struct si_surface
*)state
->zsbuf
;
2887 zstex
= (struct si_texture
*)surf
->base
.texture
;
2889 if (!surf
->depth_initialized
) {
2890 si_init_depth_surface(sctx
, surf
);
2893 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
, PIPE_MASK_ZS
))
2894 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2896 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2898 /* Update the minimum but don't keep 0. */
2899 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2900 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2901 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
2904 si_update_ps_colorbuf0_slot(sctx
);
2905 si_update_poly_offset_state(sctx
);
2906 si_update_ngg_small_prim_precision(sctx
);
2907 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2908 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2910 if (sctx
->screen
->dpbb_allowed
)
2911 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2913 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2914 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2916 if (sctx
->screen
->has_out_of_order_rast
&&
2917 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2918 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2919 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2920 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2922 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2923 struct pipe_constant_buffer constbuf
= {0};
2925 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2926 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2928 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2930 /* Set sample locations as fragment shader constants. */
2931 switch (sctx
->framebuffer
.nr_samples
) {
2933 constbuf
.buffer_offset
= 0;
2936 constbuf
.buffer_offset
=
2937 (ubyte
*)sctx
->sample_positions
.x2
- (ubyte
*)sctx
->sample_positions
.x1
;
2940 constbuf
.buffer_offset
=
2941 (ubyte
*)sctx
->sample_positions
.x4
- (ubyte
*)sctx
->sample_positions
.x1
;
2944 constbuf
.buffer_offset
=
2945 (ubyte
*)sctx
->sample_positions
.x8
- (ubyte
*)sctx
->sample_positions
.x1
;
2948 constbuf
.buffer_offset
=
2949 (ubyte
*)sctx
->sample_positions
.x16
- (ubyte
*)sctx
->sample_positions
.x1
;
2952 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx
->framebuffer
.nr_samples
);
2955 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2956 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2958 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2961 sctx
->do_update_shaders
= true;
2963 if (!sctx
->decompression_enabled
) {
2964 /* Prevent textures decompression when the framebuffer state
2965 * changes come from the decompression passes themselves.
2967 sctx
->need_check_render_feedback
= true;
2971 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2973 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2974 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2975 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2976 struct si_texture
*tex
= NULL
;
2977 struct si_surface
*cb
= NULL
;
2978 unsigned cb_color_info
= 0;
2980 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
2981 unsigned meta_write_policy
, meta_read_policy
;
2982 /* TODO: investigate whether LRU improves performance on other chips too */
2983 if (sctx
->screen
->info
.num_render_backends
<= 4) {
2984 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
2985 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
2987 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
2988 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
2992 for (i
= 0; i
< nr_cbufs
; i
++) {
2993 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
2994 unsigned cb_color_attrib
;
2996 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2999 cb
= (struct si_surface
*)state
->cbufs
[i
];
3001 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3002 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3006 tex
= (struct si_texture
*)cb
->base
.texture
;
3007 radeon_add_to_buffer_list(
3008 sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3009 tex
->buffer
.b
.b
.nr_samples
> 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA
: RADEON_PRIO_COLOR_BUFFER
);
3011 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3012 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3013 RADEON_PRIO_SEPARATE_META
);
3016 if (tex
->dcc_separate_buffer
)
3017 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->dcc_separate_buffer
,
3018 RADEON_USAGE_READWRITE
, RADEON_PRIO_SEPARATE_META
);
3020 /* Compute mutable surface parameters. */
3021 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3023 cb_color_cmask
= tex
->cmask_base_address_reg
;
3025 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3026 cb_color_attrib
= cb
->cb_color_attrib
;
3028 if (cb
->base
.u
.tex
.level
> 0)
3029 cb_color_info
&= C_028C70_FAST_CLEAR
;
3031 if (tex
->surface
.fmask_offset
) {
3032 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
) >> 8;
3033 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3037 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3038 bool is_msaa_resolve_dst
= state
->cbufs
[0] && state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3039 state
->cbufs
[1] == &cb
->base
&&
3040 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3042 if (!is_msaa_resolve_dst
)
3043 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3046 ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
) >>
3049 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3050 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3051 cb_dcc_base
|= dcc_tile_swizzle
;
3054 if (sctx
->chip_class
>= GFX10
) {
3055 unsigned cb_color_attrib3
;
3057 /* Set mutable surface parameters. */
3058 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3059 cb_color_base
|= tex
->surface
.tile_swizzle
;
3060 if (!tex
->surface
.fmask_offset
)
3061 cb_color_fmask
= cb_color_base
;
3062 if (cb
->base
.u
.tex
.level
> 0)
3063 cb_color_cmask
= cb_color_base
;
3065 cb_color_attrib3
= cb
->cb_color_attrib3
|
3066 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3067 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3068 S_028EE0_CMASK_PIPE_ALIGNED(1) |
3069 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3071 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3072 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3073 radeon_emit(cs
, 0); /* hole */
3074 radeon_emit(cs
, 0); /* hole */
3075 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3076 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3077 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3078 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3079 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3080 radeon_emit(cs
, 0); /* hole */
3081 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3082 radeon_emit(cs
, 0); /* hole */
3083 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3084 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3085 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3087 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4, cb_color_base
>> 32);
3088 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3089 cb_color_cmask
>> 32);
3090 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3091 cb_color_fmask
>> 32);
3092 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4, cb_dcc_base
>> 32);
3093 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4, cb
->cb_color_attrib2
);
3094 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4, cb_color_attrib3
);
3095 } else if (sctx
->chip_class
== GFX9
) {
3096 struct gfx9_surf_meta_flags meta
= {
3101 if (tex
->surface
.dcc_offset
)
3102 meta
= tex
->surface
.u
.gfx9
.dcc
;
3104 /* Set mutable surface parameters. */
3105 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3106 cb_color_base
|= tex
->surface
.tile_swizzle
;
3107 if (!tex
->surface
.fmask_offset
)
3108 cb_color_fmask
= cb_color_base
;
3109 if (cb
->base
.u
.tex
.level
> 0)
3110 cb_color_cmask
= cb_color_base
;
3111 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3112 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3113 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3114 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3116 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3117 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3118 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3119 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3120 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3121 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3122 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3123 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3124 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3125 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3126 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3127 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3128 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3129 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3130 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3131 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3133 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3134 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3136 /* Compute mutable surface parameters (GFX6-GFX8). */
3137 const struct legacy_surf_level
*level_info
=
3138 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3139 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3140 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3142 cb_color_base
+= level_info
->offset
>> 8;
3143 /* Only macrotiled modes can set tile swizzle. */
3144 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3145 cb_color_base
|= tex
->surface
.tile_swizzle
;
3147 if (!tex
->surface
.fmask_offset
)
3148 cb_color_fmask
= cb_color_base
;
3149 if (cb
->base
.u
.tex
.level
> 0)
3150 cb_color_cmask
= cb_color_base
;
3152 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3154 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3155 slice_tile_max
= level_info
->nblk_x
* level_info
->nblk_y
/ 64 - 1;
3156 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3158 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3159 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3160 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3162 if (tex
->surface
.fmask_offset
) {
3163 if (sctx
->chip_class
>= GFX7
)
3165 S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3167 S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3168 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3170 /* This must be set for fast clear to work without FMASK. */
3171 if (sctx
->chip_class
>= GFX7
)
3172 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3173 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3174 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3177 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3178 sctx
->chip_class
>= GFX8
? 14 : 13);
3179 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3180 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3181 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3182 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3183 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3184 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3185 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3186 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3187 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3188 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3189 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3190 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3191 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3193 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3194 radeon_emit(cs
, cb_dcc_base
);
3198 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3199 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3202 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3203 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3204 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3205 unsigned db_z_info
= zb
->db_z_info
;
3206 unsigned db_stencil_info
= zb
->db_stencil_info
;
3207 unsigned db_htile_surface
= zb
->db_htile_surface
;
3209 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3210 zb
->base
.texture
->nr_samples
> 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3211 : RADEON_PRIO_DEPTH_BUFFER
);
3213 /* Set fields dependent on tc_compatile_htile. */
3214 if (sctx
->chip_class
>= GFX9
&&
3215 vi_tc_compat_htile_enabled(tex
, zb
->base
.u
.tex
.level
, PIPE_MASK_ZS
)) {
3216 unsigned max_zplanes
= 4;
3218 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&& tex
->buffer
.b
.b
.nr_samples
> 1)
3221 db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
3223 if (sctx
->chip_class
>= GFX10
) {
3224 db_z_info
|= S_028040_ITERATE_FLUSH(1);
3225 db_stencil_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
3227 db_z_info
|= S_028038_ITERATE_FLUSH(1);
3228 db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
3232 if (sctx
->chip_class
>= GFX10
) {
3233 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3234 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3236 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3237 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3238 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3239 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3240 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3241 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3242 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3243 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3244 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3246 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 6);
3247 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3248 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3249 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3250 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3251 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3252 radeon_emit(cs
, /* DB_RMI_L2_CACHE_CONTROL */
3253 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
3254 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
3255 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
3256 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
3257 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
3258 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
3259 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
3260 } else if (sctx
->chip_class
== GFX9
) {
3261 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3262 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3264 S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3265 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3267 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3268 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3269 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3270 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3271 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3272 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3273 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3274 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3275 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3276 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3277 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3279 S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3281 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3282 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3283 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3286 /* Set fields dependent on tc_compatile_htile. */
3287 if (si_htile_enabled(tex
, zb
->base
.u
.tex
.level
, PIPE_MASK_ZS
)) {
3288 if (!tex
->surface
.has_stencil
&& !tex
->tc_compatible_htile
) {
3289 /* Use all of the htile_buffer for depth if there's no stencil.
3290 * This must not be set when TC-compatible HTILE is enabled
3293 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3296 if (tex
->tc_compatible_htile
) {
3297 db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
3299 /* 0 = full compression. N = only compress up to N-1 Z planes. */
3300 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
3301 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3302 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
3303 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3305 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3309 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3311 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3312 radeon_emit(cs
, zb
->db_depth_info
| /* DB_DEPTH_INFO */
3313 S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
));
3314 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3315 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3316 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3317 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3318 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3319 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3320 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3321 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3322 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3325 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3326 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3327 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3329 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3330 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, db_htile_surface
);
3331 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3332 if (sctx
->chip_class
== GFX9
)
3333 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3335 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3337 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3338 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3341 /* Framebuffer dimensions. */
3342 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3343 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3344 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3347 radeon_set_context_reg(cs
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
3348 S_028410_CMASK_WR_POLICY(meta_write_policy
) |
3349 S_028410_FMASK_WR_POLICY(meta_write_policy
) |
3350 S_028410_DCC_WR_POLICY(meta_write_policy
) |
3351 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
3352 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
3353 S_028410_FMASK_RD_POLICY(meta_read_policy
) |
3354 S_028410_DCC_RD_POLICY(meta_read_policy
) |
3355 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
3358 if (sctx
->screen
->dfsm_allowed
) {
3359 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3360 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3363 sctx
->framebuffer
.dirty_cbufs
= 0;
3364 sctx
->framebuffer
.dirty_zsbuf
= false;
3367 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3369 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3370 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3371 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3372 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3374 /* Smoothing (only possible with nr_samples == 1) uses the same
3375 * sample locations as the MSAA it simulates.
3377 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3378 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3380 /* On Polaris, the small primitive filter uses the sample locations
3381 * even when MSAA is off, so we need to make sure they're set to 0.
3383 * GFX10 uses sample locations unconditionally, so they always need
3386 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
|| sctx
->chip_class
>= GFX10
) &&
3387 nr_samples
!= sctx
->sample_locs_num_samples
) {
3388 sctx
->sample_locs_num_samples
= nr_samples
;
3389 si_emit_sample_locations(cs
, nr_samples
);
3392 if (sctx
->family
>= CHIP_POLARIS10
) {
3393 unsigned small_prim_filter_cntl
=
3394 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3396 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3398 /* The alternative of setting sample locations to 0 would
3399 * require a DB flush to avoid Z errors, see
3400 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3402 if (has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1 && !rs
->multisample_enable
)
3403 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3405 radeon_opt_set_context_reg(sctx
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3406 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
, small_prim_filter_cntl
);
3409 /* The exclusion bits can be set to improve rasterization efficiency
3410 * if no sample lies on the pixel boundary (-8 sample offset).
3412 bool exclusion
= sctx
->chip_class
>= GFX7
&& (!rs
->multisample_enable
|| nr_samples
!= 16);
3413 radeon_opt_set_context_reg(
3414 sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3415 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3418 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3420 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3421 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3423 if (!sctx
->screen
->has_out_of_order_rast
)
3426 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3428 colormask
&= blend
->cb_target_enabled_4bit
;
3430 /* Conservative: No logic op. */
3431 if (colormask
&& blend
->logicop_enable
)
3434 struct si_dsa_order_invariance dsa_order_invariant
= {.zs
= true,
3436 .pass_last
= false};
3438 if (sctx
->framebuffer
.state
.zsbuf
) {
3439 struct si_texture
*zstex
= (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3440 bool has_stencil
= zstex
->surface
.has_stencil
;
3441 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3442 if (!dsa_order_invariant
.zs
)
3445 /* The set of PS invocations is always order invariant,
3446 * except when early Z/S tests are requested. */
3447 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.writes_memory
&&
3448 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3449 !dsa_order_invariant
.pass_set
)
3452 if (sctx
->num_perfect_occlusion_queries
!= 0 && !dsa_order_invariant
.pass_set
)
3459 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3462 /* Only commutative blending. */
3463 if (blendmask
& ~blend
->commutative_4bit
)
3466 if (!dsa_order_invariant
.pass_set
)
3470 if (colormask
& ~blendmask
) {
3471 if (!dsa_order_invariant
.pass_last
)
3478 static void si_emit_msaa_config(struct si_context
*sctx
)
3480 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3481 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3482 /* 33% faster rendering to linear color buffers */
3483 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3484 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3485 unsigned sc_mode_cntl_1
=
3486 S_028A4C_WALK_SIZE(dst_is_linear
) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3487 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3488 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3489 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3491 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3492 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3493 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3494 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) |
3495 S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3496 unsigned coverage_samples
, color_samples
, z_samples
;
3497 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3499 /* S: Coverage samples (up to 16x):
3500 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3501 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3503 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3504 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3505 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3506 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3507 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3510 * F: Color samples (up to 8x, must be <= coverage samples):
3511 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3512 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3514 * Can be anything between coverage and color samples:
3515 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3516 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3517 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3518 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3519 * # All are currently set the same as coverage samples.
3521 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3522 * flag for undefined color samples. A shader-based resolve must handle unknowns
3523 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3524 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3525 * useful. The CB resolve always drops unknowns.
3527 * Sensible AA configurations:
3528 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3529 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3530 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3531 * EQAA 8s 8z 8f = 8x MSAA
3532 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3533 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3534 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3535 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3536 * EQAA 4s 4z 4f = 4x MSAA
3537 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3538 * EQAA 2s 2z 2f = 2x MSAA
3540 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3541 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3542 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3544 if (sctx
->framebuffer
.state
.zsbuf
) {
3545 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3546 z_samples
= MAX2(1, z_samples
);
3548 z_samples
= coverage_samples
;
3550 } else if (sctx
->smoothing_enabled
) {
3551 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3553 coverage_samples
= color_samples
= z_samples
= 1;
3556 /* Required by OpenGL line rasterization.
3558 * TODO: We should also enable perpendicular endcaps for AA lines,
3559 * but that requires implementing line stippling in the pixel
3560 * shader. SC can only do line stippling with axis-aligned
3563 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3564 unsigned sc_aa_config
= 0;
3566 if (coverage_samples
> 1) {
3567 /* distance from the pixel center, indexed by log2(nr_samples) */
3568 static unsigned max_dist
[] = {
3575 unsigned log_samples
= util_logbase2(coverage_samples
);
3576 unsigned log_z_samples
= util_logbase2(z_samples
);
3577 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3578 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3580 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3581 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3582 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3583 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) |
3584 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(sctx
->chip_class
>= GFX10_3
);
3586 if (sctx
->framebuffer
.nr_samples
> 1) {
3587 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3588 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3589 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3590 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3591 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3592 } else if (sctx
->smoothing_enabled
) {
3593 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3597 unsigned initial_cdw
= cs
->current
.cdw
;
3599 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3600 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
, SI_TRACKED_PA_SC_LINE_CNTL
,
3601 sc_line_cntl
, sc_aa_config
);
3602 /* R_028804_DB_EQAA */
3603 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
, db_eqaa
);
3604 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3605 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
, SI_TRACKED_PA_SC_MODE_CNTL_1
,
3608 if (initial_cdw
!= cs
->current
.cdw
) {
3609 sctx
->context_roll
= true;
3611 /* GFX9: Flush DFSM when the AA mode changes. */
3612 if (sctx
->screen
->dfsm_allowed
) {
3613 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3614 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3619 void si_update_ps_iter_samples(struct si_context
*sctx
)
3621 if (sctx
->framebuffer
.nr_samples
> 1)
3622 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3623 if (sctx
->screen
->dpbb_allowed
)
3624 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3627 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3629 struct si_context
*sctx
= (struct si_context
*)ctx
;
3631 /* The hardware can only do sample shading with 2^n samples. */
3632 min_samples
= util_next_power_of_two(min_samples
);
3634 if (sctx
->ps_iter_samples
== min_samples
)
3637 sctx
->ps_iter_samples
= min_samples
;
3638 sctx
->do_update_shaders
= true;
3640 si_update_ps_iter_samples(sctx
);
3648 * Build the sampler view descriptor for a buffer texture.
3649 * @param state 256-bit descriptor; only the high 128 bits are filled in
3651 void si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3652 enum pipe_format format
, unsigned offset
, unsigned size
,
3655 const struct util_format_description
*desc
;
3657 unsigned num_records
;
3659 desc
= util_format_description(format
);
3660 stride
= desc
->block
.bits
/ 8;
3662 num_records
= size
/ stride
;
3663 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3665 /* The NUM_RECORDS field has a different meaning depending on the chip,
3666 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3669 * - If STRIDE == 0, it's in byte units.
3670 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3673 * - For SMEM and STRIDE == 0, it's in byte units.
3674 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3675 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3676 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3677 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3678 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3679 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3680 * That way the same descriptor can be used by both SMEM and VMEM.
3683 * - For SMEM and STRIDE == 0, it's in byte units.
3684 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3685 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3686 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3688 if (screen
->info
.chip_class
== GFX8
)
3689 num_records
*= stride
;
3692 state
[5] = S_008F04_STRIDE(stride
);
3693 state
[6] = num_records
;
3694 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3695 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3696 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3697 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3699 if (screen
->info
.chip_class
>= GFX10
) {
3700 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3702 /* OOB_SELECT chooses the out-of-bounds check:
3703 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3704 * - 1: index >= NUM_RECORDS
3705 * - 2: NUM_RECORDS == 0
3706 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3707 * else: swizzle_address >= NUM_RECORDS
3709 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3710 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET
) |
3711 S_008F0C_RESOURCE_LEVEL(1);
3714 unsigned num_format
, data_format
;
3716 first_non_void
= util_format_get_first_non_void_channel(format
);
3717 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3718 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3720 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
3724 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3726 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3728 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3729 /* For the pre-defined border color values (white, opaque
3730 * black, transparent black), the only thing that matters is
3731 * that the alpha channel winds up in the correct place
3732 * (because the RGB channels are all the same) so either of
3733 * these enumerations will work.
3735 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3736 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3738 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3739 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3740 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3741 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3743 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3744 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3745 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3746 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3747 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3754 * Build the sampler view descriptor for a texture.
3756 static void gfx10_make_texture_descriptor(
3757 struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
, enum pipe_texture_target target
,
3758 enum pipe_format pipe_format
, const unsigned char state_swizzle
[4], unsigned first_level
,
3759 unsigned last_level
, unsigned first_layer
, unsigned last_layer
, unsigned width
, unsigned height
,
3760 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3762 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3763 const struct util_format_description
*desc
;
3764 unsigned img_format
;
3765 unsigned char swizzle
[4];
3769 desc
= util_format_description(pipe_format
);
3770 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3772 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3773 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3774 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3775 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3776 bool is_stencil
= false;
3778 switch (pipe_format
) {
3779 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3780 case PIPE_FORMAT_X32_S8X24_UINT
:
3781 case PIPE_FORMAT_X8Z24_UNORM
:
3782 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3785 case PIPE_FORMAT_X24S8_UINT
:
3787 * X24S8 is implemented as an 8_8_8_8 data format, to
3788 * fix texture gathers. This affects at least
3789 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3791 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3795 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3796 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3799 if (tex
->upgraded_depth
&& !is_stencil
) {
3800 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3801 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3804 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3807 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3808 /* For the purpose of shader images, treat cube maps as 2D
3811 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3813 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3816 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3818 depth
= res
->array_size
;
3819 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3820 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3821 depth
= res
->array_size
;
3822 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3823 depth
= res
->array_size
/ 6;
3826 state
[1] = S_00A004_FORMAT(img_format
) | S_00A004_WIDTH_LO(width
- 1);
3827 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3828 S_00A008_RESOURCE_LEVEL(1);
3830 S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3831 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3832 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3833 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3834 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ? 0 : first_level
) |
3835 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
) : last_level
) |
3836 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) | S_00A00C_TYPE(type
);
3838 if (res
->target
== PIPE_TEXTURE_1D
||
3839 res
->target
== PIPE_TEXTURE_2D
) {
3840 /* 1D, 2D, and 2D_MSAA can set a custom pitch for shader resources
3841 * starting with gfx10.3 (ignored if pitch <= width). Other texture
3842 * targets can't. CB and DB can't set a custom pitch for any target.
3844 if (screen
->info
.chip_class
>= GFX10_3
)
3845 state
[4] = S_00A010_DEPTH(tex
->surface
.u
.gfx9
.surf_pitch
- 1);
3849 /* Depth is the last accessible layer on gfx9+. The hw doesn't need
3850 * to know the total number of layers.
3852 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
) ?
3853 depth
- 1 : last_layer
) |
3854 S_00A010_BASE_ARRAY(first_layer
);
3857 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3858 S_00A014_MAX_MIP(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
)
3859 : tex
->buffer
.b
.b
.last_level
) |
3860 S_00A014_PERF_MOD(4);
3864 if (vi_dcc_enabled(tex
, first_level
)) {
3865 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3866 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
3867 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
3870 /* Initialize the sampler view for FMASK. */
3871 if (tex
->surface
.fmask_offset
) {
3874 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
3876 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3877 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3879 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
3882 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
3885 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
3888 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
3891 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
3894 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
3897 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
3900 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
3903 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
3906 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
3909 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
3912 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
3915 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
3918 unreachable("invalid nr_samples");
3921 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3922 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) | S_00A004_FORMAT(format
) |
3923 S_00A004_WIDTH_LO(width
- 1);
3924 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3925 S_00A008_RESOURCE_LEVEL(1);
3927 S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3928 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3929 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3930 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3931 fmask_state
[4] = S_00A010_DEPTH(last_layer
) | S_00A010_BASE_ARRAY(first_layer
);
3933 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(1);
3939 * Build the sampler view descriptor for a texture (SI-GFX9).
3941 static void si_make_texture_descriptor(struct si_screen
*screen
, struct si_texture
*tex
,
3942 bool sampler
, enum pipe_texture_target target
,
3943 enum pipe_format pipe_format
,
3944 const unsigned char state_swizzle
[4], unsigned first_level
,
3945 unsigned last_level
, unsigned first_layer
,
3946 unsigned last_layer
, unsigned width
, unsigned height
,
3947 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3949 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3950 const struct util_format_description
*desc
;
3951 unsigned char swizzle
[4];
3953 unsigned num_format
, data_format
, type
, num_samples
;
3956 desc
= util_format_description(pipe_format
);
3958 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
? MAX2(1, res
->nr_samples
)
3959 : MAX2(1, res
->nr_storage_samples
);
3961 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3962 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3963 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3964 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3966 switch (pipe_format
) {
3967 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3968 case PIPE_FORMAT_X32_S8X24_UINT
:
3969 case PIPE_FORMAT_X8Z24_UNORM
:
3970 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3972 case PIPE_FORMAT_X24S8_UINT
:
3974 * X24S8 is implemented as an 8_8_8_8 data format, to
3975 * fix texture gathers. This affects at least
3976 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3978 if (screen
->info
.chip_class
<= GFX8
)
3979 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3981 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3984 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3987 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3990 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3992 switch (pipe_format
) {
3993 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3994 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3997 if (first_non_void
< 0) {
3998 if (util_format_is_compressed(pipe_format
)) {
3999 switch (pipe_format
) {
4000 case PIPE_FORMAT_DXT1_SRGB
:
4001 case PIPE_FORMAT_DXT1_SRGBA
:
4002 case PIPE_FORMAT_DXT3_SRGBA
:
4003 case PIPE_FORMAT_DXT5_SRGBA
:
4004 case PIPE_FORMAT_BPTC_SRGBA
:
4005 case PIPE_FORMAT_ETC2_SRGB8
:
4006 case PIPE_FORMAT_ETC2_SRGB8A1
:
4007 case PIPE_FORMAT_ETC2_SRGBA8
:
4008 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4010 case PIPE_FORMAT_RGTC1_SNORM
:
4011 case PIPE_FORMAT_LATC1_SNORM
:
4012 case PIPE_FORMAT_RGTC2_SNORM
:
4013 case PIPE_FORMAT_LATC2_SNORM
:
4014 case PIPE_FORMAT_ETC2_R11_SNORM
:
4015 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4016 /* implies float, so use SNORM/UNORM to determine
4017 whether data is signed or not */
4018 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4019 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4022 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4025 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4026 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4028 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4030 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4031 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4033 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4035 switch (desc
->channel
[first_non_void
].type
) {
4036 case UTIL_FORMAT_TYPE_FLOAT
:
4037 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4039 case UTIL_FORMAT_TYPE_SIGNED
:
4040 if (desc
->channel
[first_non_void
].normalized
)
4041 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4042 else if (desc
->channel
[first_non_void
].pure_integer
)
4043 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4045 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4047 case UTIL_FORMAT_TYPE_UNSIGNED
:
4048 if (desc
->channel
[first_non_void
].normalized
)
4049 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4050 else if (desc
->channel
[first_non_void
].pure_integer
)
4051 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4053 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4058 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4059 if (data_format
== ~0) {
4063 /* S8 with Z32 HTILE needs a special format. */
4064 if (screen
->info
.chip_class
== GFX9
&& pipe_format
== PIPE_FORMAT_S8_UINT
)
4065 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4067 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4068 (screen
->info
.chip_class
<= GFX8
&& res
->target
== PIPE_TEXTURE_3D
))) {
4069 /* For the purpose of shader images, treat cube maps and 3D
4070 * textures as 2D arrays. For 3D textures, the address
4071 * calculations for mipmaps are different, so we rely on the
4072 * caller to effectively disable mipmaps.
4074 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4076 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4078 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4081 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4083 depth
= res
->array_size
;
4084 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4085 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4086 depth
= res
->array_size
;
4087 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4088 depth
= res
->array_size
/ 6;
4091 state
[1] = (S_008F14_DATA_FORMAT(data_format
) | S_008F14_NUM_FORMAT(num_format
));
4092 state
[2] = (S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1) | S_008F18_PERF_MOD(4));
4093 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4094 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4095 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4096 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4097 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4098 S_008F1C_LAST_LEVEL(num_samples
> 1 ? util_logbase2(num_samples
) : last_level
) |
4099 S_008F1C_TYPE(type
));
4101 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4105 if (screen
->info
.chip_class
== GFX9
) {
4106 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4108 /* Depth is the the last accessible layer on Gfx9.
4109 * The hw doesn't need to know the total number of layers.
4111 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4112 state
[4] |= S_008F20_DEPTH(depth
- 1);
4114 state
[4] |= S_008F20_DEPTH(last_layer
);
4116 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4117 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ? util_logbase2(num_samples
)
4118 : tex
->buffer
.b
.b
.last_level
);
4120 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4121 state
[4] |= S_008F20_DEPTH(depth
- 1);
4122 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4125 if (vi_dcc_enabled(tex
, first_level
)) {
4126 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4128 /* The last dword is unused by hw. The shader uses it to clear
4129 * bits in the first dword of sampler state.
4131 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4132 if (first_level
== last_level
)
4133 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4135 state
[7] = 0xffffffff;
4139 /* Initialize the sampler view for FMASK. */
4140 if (tex
->surface
.fmask_offset
) {
4141 uint32_t data_format
, num_format
;
4143 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4145 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4146 if (screen
->info
.chip_class
== GFX9
) {
4147 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4148 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4150 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4153 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4156 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4159 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4162 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4165 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4168 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4171 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4174 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4177 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4180 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4183 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4186 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4189 unreachable("invalid nr_samples");
4192 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4194 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4197 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4200 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4203 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4206 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4209 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4212 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4215 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4218 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4221 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4224 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4227 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4230 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4233 unreachable("invalid nr_samples");
4235 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4239 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4240 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) | S_008F14_DATA_FORMAT(data_format
) |
4241 S_008F14_NUM_FORMAT(num_format
);
4242 fmask_state
[2] = S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1);
4244 S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4245 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4246 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4248 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4252 if (screen
->info
.chip_class
== GFX9
) {
4253 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4255 S_008F20_DEPTH(last_layer
) | S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4256 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(1) |
4257 S_008F24_META_RB_ALIGNED(1);
4259 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4260 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4261 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4262 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4268 * Create a sampler view.
4270 * @param ctx context
4271 * @param texture texture
4272 * @param state sampler view template
4273 * @param width0 width0 override (for compressed textures as int)
4274 * @param height0 height0 override (for compressed textures as int)
4275 * @param force_level set the base address to the level (for compressed textures)
4277 struct pipe_sampler_view
*si_create_sampler_view_custom(struct pipe_context
*ctx
,
4278 struct pipe_resource
*texture
,
4279 const struct pipe_sampler_view
*state
,
4280 unsigned width0
, unsigned height0
,
4281 unsigned force_level
)
4283 struct si_context
*sctx
= (struct si_context
*)ctx
;
4284 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4285 struct si_texture
*tex
= (struct si_texture
*)texture
;
4286 unsigned base_level
, first_level
, last_level
;
4287 unsigned char state_swizzle
[4];
4288 unsigned height
, depth
, width
;
4289 unsigned last_layer
= state
->u
.tex
.last_layer
;
4290 enum pipe_format pipe_format
;
4291 const struct legacy_surf_level
*surflevel
;
4296 /* initialize base object */
4297 view
->base
= *state
;
4298 view
->base
.texture
= NULL
;
4299 view
->base
.reference
.count
= 1;
4300 view
->base
.context
= ctx
;
4303 pipe_resource_reference(&view
->base
.texture
, texture
);
4305 if (state
->format
== PIPE_FORMAT_X24S8_UINT
|| state
->format
== PIPE_FORMAT_S8X24_UINT
||
4306 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
|| state
->format
== PIPE_FORMAT_S8_UINT
)
4307 view
->is_stencil_sampler
= true;
4309 /* Buffer resource. */
4310 if (texture
->target
== PIPE_BUFFER
) {
4311 si_make_buffer_descriptor(sctx
->screen
, si_resource(texture
), state
->format
,
4312 state
->u
.buf
.offset
, state
->u
.buf
.size
, view
->state
);
4316 state_swizzle
[0] = state
->swizzle_r
;
4317 state_swizzle
[1] = state
->swizzle_g
;
4318 state_swizzle
[2] = state
->swizzle_b
;
4319 state_swizzle
[3] = state
->swizzle_a
;
4322 first_level
= state
->u
.tex
.first_level
;
4323 last_level
= state
->u
.tex
.last_level
;
4326 depth
= texture
->depth0
;
4328 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4329 assert(force_level
== first_level
&& force_level
== last_level
);
4330 base_level
= force_level
;
4333 width
= u_minify(width
, force_level
);
4334 height
= u_minify(height
, force_level
);
4335 depth
= u_minify(depth
, force_level
);
4338 /* This is not needed if gallium frontends set last_layer correctly. */
4339 if (state
->target
== PIPE_TEXTURE_1D
|| state
->target
== PIPE_TEXTURE_2D
||
4340 state
->target
== PIPE_TEXTURE_RECT
|| state
->target
== PIPE_TEXTURE_CUBE
)
4341 last_layer
= state
->u
.tex
.first_layer
;
4343 /* Texturing with separate depth and stencil. */
4344 pipe_format
= state
->format
;
4346 /* Depth/stencil texturing sometimes needs separate texture. */
4347 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4348 if (!tex
->flushed_depth_texture
&& !si_init_flushed_depth_texture(ctx
, texture
)) {
4349 pipe_resource_reference(&view
->base
.texture
, NULL
);
4354 assert(tex
->flushed_depth_texture
);
4356 /* Override format for the case where the flushed texture
4357 * contains only Z or only S.
4359 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4360 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4362 tex
= tex
->flushed_depth_texture
;
4365 surflevel
= tex
->surface
.u
.legacy
.level
;
4367 if (tex
->db_compatible
) {
4368 if (!view
->is_stencil_sampler
)
4369 pipe_format
= tex
->db_render_format
;
4371 switch (pipe_format
) {
4372 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4373 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4375 case PIPE_FORMAT_X8Z24_UNORM
:
4376 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4377 /* Z24 is always stored like this for DB
4380 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4382 case PIPE_FORMAT_X24S8_UINT
:
4383 case PIPE_FORMAT_S8X24_UINT
:
4384 case PIPE_FORMAT_X32_S8X24_UINT
:
4385 pipe_format
= PIPE_FORMAT_S8_UINT
;
4386 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4392 view
->dcc_incompatible
=
4393 vi_dcc_formats_are_incompatible(texture
, state
->u
.tex
.first_level
, state
->format
);
4395 sctx
->screen
->make_texture_descriptor(
4396 sctx
->screen
, tex
, true, state
->target
, pipe_format
, state_swizzle
, first_level
, last_level
,
4397 state
->u
.tex
.first_layer
, last_layer
, width
, height
, depth
, view
->state
, view
->fmask_state
);
4399 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4400 view
->is_integer
= false;
4402 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4403 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4406 /* Whether the number format is {U,S}{SCALED,INT} */
4407 view
->is_integer
= (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4408 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4409 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4413 view
->base_level_info
= &surflevel
[base_level
];
4414 view
->base_level
= base_level
;
4415 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4419 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
4420 struct pipe_resource
*texture
,
4421 const struct pipe_sampler_view
*state
)
4423 return si_create_sampler_view_custom(ctx
, texture
, state
, texture
? texture
->width0
: 0,
4424 texture
? texture
->height0
: 0, 0);
4427 static void si_sampler_view_destroy(struct pipe_context
*ctx
, struct pipe_sampler_view
*state
)
4429 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4431 pipe_resource_reference(&state
->texture
, NULL
);
4435 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4437 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4438 (linear_filter
&& (wrap
== PIPE_TEX_WRAP_CLAMP
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4441 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4442 const struct pipe_sampler_state
*state
,
4443 const union pipe_color_union
*color
, bool is_integer
)
4445 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4446 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4448 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4449 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4450 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4451 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4453 #define simple_border_types(elt) \
4455 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4456 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4457 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4458 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4459 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4460 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4464 simple_border_types(ui
);
4466 simple_border_types(f
);
4468 #undef simple_border_types
4472 /* Check if the border has been uploaded already. */
4473 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4474 if (memcmp(&sctx
->border_color_table
[i
], color
, sizeof(*color
)) == 0)
4477 if (i
>= SI_MAX_BORDER_COLORS
) {
4478 /* Getting 4096 unique border colors is very unlikely. */
4479 fprintf(stderr
, "radeonsi: The border color table is full. "
4480 "Any new border colors will be just black. "
4481 "Please file a bug.\n");
4482 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4485 if (i
== sctx
->border_color_count
) {
4486 /* Upload a new border color. */
4487 memcpy(&sctx
->border_color_table
[i
], color
, sizeof(*color
));
4488 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
], color
, sizeof(*color
));
4489 sctx
->border_color_count
++;
4492 return S_008F3C_BORDER_COLOR_PTR(i
) |
4493 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4496 static inline int S_FIXED(float value
, unsigned frac_bits
)
4498 return value
* (1 << frac_bits
);
4501 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4503 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4504 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4505 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4507 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4508 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4511 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4524 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4525 const struct pipe_sampler_state
*state
)
4527 struct si_context
*sctx
= (struct si_context
*)ctx
;
4528 struct si_screen
*sscreen
= sctx
->screen
;
4529 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4530 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
: state
->max_anisotropy
;
4531 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4532 bool trunc_coord
= state
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
&&
4533 state
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
&&
4534 state
->compare_mode
== PIPE_TEX_COMPARE_NONE
;
4535 union pipe_color_union clamped_border_color
;
4542 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4545 (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) | S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4546 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4547 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4548 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4549 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4550 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4551 S_008F30_TRUNC_COORD(trunc_coord
) |
4552 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4553 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4554 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4555 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4556 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4557 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4558 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4559 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4560 S_008F38_MIP_POINT_PRECLAMP(0));
4561 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4563 if (sscreen
->info
.chip_class
>= GFX10
) {
4564 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4566 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4567 S_008F38_FILTER_PREC_FIX(1) |
4568 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4571 /* Create sampler resource for integer textures. */
4572 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4573 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4575 /* Create sampler resource for upgraded depth textures. */
4576 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4578 for (unsigned i
= 0; i
< 4; ++i
) {
4579 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4580 * when the border color is 1.0. */
4581 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4584 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4585 if (sscreen
->info
.chip_class
<= GFX9
)
4586 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4588 rstate
->upgraded_depth_val
[3] =
4589 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4595 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4597 struct si_context
*sctx
= (struct si_context
*)ctx
;
4599 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4602 sctx
->sample_mask
= sample_mask
;
4603 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4606 static void si_emit_sample_mask(struct si_context
*sctx
)
4608 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4609 unsigned mask
= sctx
->sample_mask
;
4611 /* Needed for line and polygon smoothing as well as for the Polaris
4612 * small primitive filter. We expect the gallium frontend to take care of
4615 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4616 (mask
& 1 && sctx
->blitter
->running
));
4618 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4619 radeon_emit(cs
, mask
| (mask
<< 16));
4620 radeon_emit(cs
, mask
| (mask
<< 16));
4623 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4626 struct si_sampler_state
*s
= state
;
4628 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4635 * Vertex elements & buffers
4638 struct si_fast_udiv_info32
si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4640 struct util_fast_udiv_info info
= util_compute_fast_udiv_info(D
, num_bits
, 32);
4642 struct si_fast_udiv_info32 result
= {
4651 static void *si_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
4652 const struct pipe_vertex_element
*elements
)
4654 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4655 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4656 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4657 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4658 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4659 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4660 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4661 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4662 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4665 assert(count
<= SI_MAX_ATTRIBS
);
4671 unsigned alloc_count
=
4672 count
> sscreen
->num_vbos_in_user_sgprs
? count
- sscreen
->num_vbos_in_user_sgprs
: 0;
4673 v
->vb_desc_list_alloc_size
= align(alloc_count
* 16, SI_CPDMA_ALIGNMENT
);
4675 for (i
= 0; i
< count
; ++i
) {
4676 const struct util_format_description
*desc
;
4677 const struct util_format_channel_description
*channel
;
4679 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4681 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4686 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4687 if (instance_divisor
) {
4688 v
->uses_instance_divisors
= true;
4690 if (instance_divisor
== 1) {
4691 v
->instance_divisor_is_one
|= 1u << i
;
4693 v
->instance_divisor_is_fetched
|= 1u << i
;
4694 divisor_factors
[i
] = si_compute_fast_udiv_info32(instance_divisor
, 32);
4698 if (!used
[vbo_index
]) {
4699 v
->first_vb_use_mask
|= 1 << i
;
4700 used
[vbo_index
] = true;
4703 desc
= util_format_description(elements
[i
].src_format
);
4704 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4705 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4707 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4708 v
->src_offset
[i
] = elements
[i
].src_offset
;
4709 v
->vertex_buffer_index
[i
] = vbo_index
;
4711 bool always_fix
= false;
4712 union si_vs_fix_fetch fix_fetch
;
4713 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4716 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4719 switch (channel
->type
) {
4720 case UTIL_FORMAT_TYPE_FLOAT
:
4721 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4723 case UTIL_FORMAT_TYPE_FIXED
:
4724 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4726 case UTIL_FORMAT_TYPE_SIGNED
: {
4727 if (channel
->pure_integer
)
4728 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4729 else if (channel
->normalized
)
4730 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4732 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4735 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4736 if (channel
->pure_integer
)
4737 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4738 else if (channel
->normalized
)
4739 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4741 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4745 unreachable("bad format type");
4748 switch (elements
[i
].src_format
) {
4749 case PIPE_FORMAT_R11G11B10_FLOAT
:
4750 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4753 unreachable("bad other format");
4757 if (desc
->channel
[0].size
== 10) {
4758 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4759 log_hw_load_size
= 2;
4761 /* The hardware always treats the 2-bit alpha channel as
4762 * unsigned, so a shader workaround is needed. The affected
4763 * chips are GFX8 and older except Stoney (GFX8.1).
4765 always_fix
= sscreen
->info
.chip_class
<= GFX8
&& sscreen
->info
.family
!= CHIP_STONEY
&&
4766 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4767 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4768 fix_fetch
.u
.log_size
= 3; /* special encoding */
4769 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4770 log_hw_load_size
= 2;
4772 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4773 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4776 * - doubles (multiple loads + truncate to float)
4777 * - 32-bit requiring a conversion
4779 always_fix
= (fix_fetch
.u
.log_size
== 3) ||
4780 (fix_fetch
.u
.log_size
== 2 && fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4781 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4782 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4784 /* Also fixup 8_8_8 and 16_16_16. */
4785 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4787 log_hw_load_size
= fix_fetch
.u
.log_size
;
4791 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4792 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4793 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4794 fix_fetch
.u
.reverse
= 1;
4797 /* Force the workaround for unaligned access here already if the
4798 * offset relative to the vertex buffer base is unaligned.
4800 * There is a theoretical case in which this is too conservative:
4801 * if the vertex buffer's offset is also unaligned in just the
4802 * right way, we end up with an aligned address after all.
4803 * However, this case should be extremely rare in practice (it
4804 * won't happen in well-behaved applications), and taking it
4805 * into account would complicate the fast path (where everything
4806 * is nicely aligned).
4808 bool check_alignment
=
4809 log_hw_load_size
>= 1 &&
4810 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
>= GFX10
);
4811 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4813 if (check_alignment
&& (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4816 if (always_fix
|| check_alignment
|| opencode
)
4817 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4820 v
->fix_fetch_opencode
|= 1 << i
;
4821 if (opencode
|| always_fix
)
4822 v
->fix_fetch_always
|= 1 << i
;
4824 if (check_alignment
&& !opencode
) {
4825 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4827 v
->fix_fetch_unaligned
|= 1 << i
;
4828 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4829 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
4832 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
4833 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
4834 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
4835 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
4837 if (sscreen
->info
.chip_class
>= GFX10
) {
4838 const struct gfx10_format
*fmt
= &gfx10_format_table
[elements
[i
].src_format
];
4839 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
4840 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) | S_008F0C_RESOURCE_LEVEL(1);
4842 unsigned data_format
, num_format
;
4843 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4844 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4845 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
4849 if (v
->instance_divisor_is_fetched
) {
4850 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4852 v
->instance_divisor_factor_buffer
= (struct si_resource
*)pipe_buffer_create(
4853 &sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, num_divisors
* sizeof(divisor_factors
[0]));
4854 if (!v
->instance_divisor_factor_buffer
) {
4859 sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
4860 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4865 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4867 struct si_context
*sctx
= (struct si_context
*)ctx
;
4868 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4869 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4871 sctx
->vertex_elements
= v
;
4872 sctx
->num_vertex_elements
= v
? v
->count
: 0;
4874 if (sctx
->num_vertex_elements
) {
4875 sctx
->vertex_buffers_dirty
= true;
4877 sctx
->vertex_buffer_pointer_dirty
= false;
4878 sctx
->vertex_buffer_user_sgprs_dirty
= false;
4881 if (v
&& (!old
|| old
->count
!= v
->count
||
4882 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4883 /* we don't check which divisors changed */
4884 v
->uses_instance_divisors
||
4885 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) &
4886 sctx
->vertex_buffer_unaligned
||
4887 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
4888 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
4889 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
4890 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4891 * functions of fix_fetch and the src_offset alignment.
4892 * If they change and fix_fetch doesn't, it must be due to different
4893 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4894 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
4895 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4896 sctx
->do_update_shaders
= true;
4898 if (v
&& v
->instance_divisor_is_fetched
) {
4899 struct pipe_constant_buffer cb
;
4901 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4902 cb
.user_buffer
= NULL
;
4903 cb
.buffer_offset
= 0;
4904 cb
.buffer_size
= 0xffffffff;
4905 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4909 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4911 struct si_context
*sctx
= (struct si_context
*)ctx
;
4912 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4914 if (sctx
->vertex_elements
== state
) {
4915 sctx
->vertex_elements
= NULL
;
4916 sctx
->num_vertex_elements
= 0;
4918 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4922 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
4923 const struct pipe_vertex_buffer
*buffers
)
4925 struct si_context
*sctx
= (struct si_context
*)ctx
;
4926 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4927 unsigned updated_mask
= u_bit_consecutive(start_slot
, count
);
4928 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
4929 uint32_t unaligned
= 0;
4932 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4935 for (i
= 0; i
< count
; i
++) {
4936 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4937 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4938 struct pipe_resource
*buf
= src
->buffer
.resource
;
4939 unsigned slot_bit
= 1 << (start_slot
+ i
);
4941 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4942 dsti
->buffer_offset
= src
->buffer_offset
;
4943 dsti
->stride
= src
->stride
;
4945 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
4946 unaligned
|= slot_bit
;
4948 si_context_add_resource_size(sctx
, buf
);
4950 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4953 for (i
= 0; i
< count
; i
++) {
4954 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4956 unaligned
&= ~updated_mask
;
4958 sctx
->vertex_buffers_dirty
= true;
4959 sctx
->vertex_buffer_unaligned
= (orig_unaligned
& ~updated_mask
) | unaligned
;
4961 /* Check whether alignment may have changed in a way that requires
4962 * shader changes. This check is conservative: a vertex buffer can only
4963 * trigger a shader change if the misalignment amount changes (e.g.
4964 * from byte-aligned to short-aligned), but we only keep track of
4965 * whether buffers are at least dword-aligned, since that should always
4966 * be the case in well-behaved applications anyway.
4968 if (sctx
->vertex_elements
&& (sctx
->vertex_elements
->vb_alignment_check_mask
&
4969 (unaligned
| orig_unaligned
) & updated_mask
))
4970 sctx
->do_update_shaders
= true;
4977 static void si_set_tess_state(struct pipe_context
*ctx
, const float default_outer_level
[4],
4978 const float default_inner_level
[2])
4980 struct si_context
*sctx
= (struct si_context
*)ctx
;
4981 struct pipe_constant_buffer cb
;
4984 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4985 memcpy(array
+ 4, default_inner_level
, sizeof(float) * 2);
4988 cb
.user_buffer
= NULL
;
4989 cb
.buffer_size
= sizeof(array
);
4991 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
, (void *)array
, sizeof(array
),
4994 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4995 pipe_resource_reference(&cb
.buffer
, NULL
);
4998 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5000 struct si_context
*sctx
= (struct si_context
*)ctx
;
5002 si_update_fb_dirtiness_after_rendering(sctx
);
5004 /* Multisample surfaces are flushed in si_decompress_textures. */
5005 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5006 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5007 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5008 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5012 /* This only ensures coherency for shader image/buffer stores. */
5013 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5015 struct si_context
*sctx
= (struct si_context
*)ctx
;
5017 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5020 /* Subsequent commands must wait for all shader invocations to
5022 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
5024 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5025 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
;
5027 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
| PIPE_BARRIER_SHADER_BUFFER
| PIPE_BARRIER_TEXTURE
|
5028 PIPE_BARRIER_IMAGE
| PIPE_BARRIER_STREAMOUT_BUFFER
| PIPE_BARRIER_GLOBAL_BUFFER
)) {
5029 /* As far as I can tell, L1 contents are written back to L2
5030 * automatically at end of shader, but the contents of other
5031 * L1 caches might still be stale. */
5032 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5035 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5036 /* Indices are read through TC L2 since GFX8.
5039 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5040 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5043 /* MSAA color, any depth and any stencil are flushed in
5044 * si_decompress_textures when needed.
5046 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&& sctx
->framebuffer
.uncompressed_cb_mask
) {
5047 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5049 if (sctx
->chip_class
<= GFX8
)
5050 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5053 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5054 if (sctx
->screen
->info
.chip_class
<= GFX8
&& flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5055 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5058 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5060 struct pipe_blend_state blend
;
5062 memset(&blend
, 0, sizeof(blend
));
5063 blend
.independent_blend_enable
= true;
5064 blend
.rt
[0].colormask
= 0xf;
5065 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5068 static void si_init_config(struct si_context
*sctx
);
5070 void si_init_state_compute_functions(struct si_context
*sctx
)
5072 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5073 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5074 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5075 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5076 sctx
->b
.memory_barrier
= si_memory_barrier
;
5079 void si_init_state_functions(struct si_context
*sctx
)
5081 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5082 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5083 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5084 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5085 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5086 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5087 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5088 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5089 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5090 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5091 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5093 sctx
->b
.create_blend_state
= si_create_blend_state
;
5094 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5095 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5096 sctx
->b
.set_blend_color
= si_set_blend_color
;
5098 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5099 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5100 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5102 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5103 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5104 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5106 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5107 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5108 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5109 sctx
->custom_blend_eliminate_fastclear
=
5110 si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5111 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5113 sctx
->b
.set_clip_state
= si_set_clip_state
;
5114 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5116 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5118 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5120 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5121 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5122 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5123 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5125 sctx
->b
.texture_barrier
= si_texture_barrier
;
5126 sctx
->b
.set_min_samples
= si_set_min_samples
;
5127 sctx
->b
.set_tess_state
= si_set_tess_state
;
5129 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5131 si_init_config(sctx
);
5134 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5136 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5138 if (sscreen
->info
.chip_class
>= GFX10
) {
5139 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5141 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5145 static void si_set_grbm_gfx_index(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned value
)
5147 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
: R_00802C_GRBM_GFX_INDEX
;
5148 si_pm4_set_reg(pm4
, reg
, value
);
5151 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned se
)
5153 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5154 si_set_grbm_gfx_index(sctx
, pm4
,
5155 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se
)) |
5156 S_030800_SH_BROADCAST_WRITES(1) |
5157 S_030800_INSTANCE_BROADCAST_WRITES(1));
5160 static void si_write_harvested_raster_configs(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
5161 unsigned raster_config
, unsigned raster_config_1
)
5163 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5164 unsigned raster_config_se
[4];
5167 ac_get_harvested_configs(&sctx
->screen
->info
, raster_config
, &raster_config_1
, raster_config_se
);
5169 for (se
= 0; se
< num_se
; se
++) {
5170 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5171 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5173 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5175 if (sctx
->chip_class
>= GFX7
) {
5176 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5180 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5182 struct si_screen
*sscreen
= sctx
->screen
;
5183 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5184 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5185 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5186 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5188 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5189 /* Always use the default config when all backends are enabled
5190 * (or when we failed to determine the enabled backends).
5192 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config
);
5193 if (sctx
->chip_class
>= GFX7
)
5194 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5196 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5200 static void si_init_config(struct si_context
*sctx
)
5202 struct si_screen
*sscreen
= sctx
->screen
;
5203 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5204 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5205 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5210 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5211 si_pm4_cmd_add(pm4
, CC0_UPDATE_LOAD_ENABLES(1));
5212 si_pm4_cmd_add(pm4
, CC1_UPDATE_SHADOW_ENABLES(1));
5213 si_pm4_cmd_end(pm4
, false);
5215 if (has_clear_state
) {
5216 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5217 si_pm4_cmd_add(pm4
, 0);
5218 si_pm4_cmd_end(pm4
, false);
5221 if (sctx
->chip_class
<= GFX8
)
5222 si_set_raster_config(sctx
, pm4
);
5224 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5225 if (!has_clear_state
)
5226 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5228 /* FIXME calculate these values somehow ??? */
5229 if (sctx
->chip_class
<= GFX8
) {
5230 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5231 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5234 if (!has_clear_state
) {
5235 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5236 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5237 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5240 if (sscreen
->info
.chip_class
<= GFX9
)
5241 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5242 if (!has_clear_state
)
5243 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5244 if (sctx
->chip_class
< GFX7
)
5245 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
,
5246 S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
5248 /* CLEAR_STATE doesn't restore these correctly. */
5249 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5250 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5251 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5253 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5254 * I don't know why. Deduced by trial and error.
5256 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5257 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5258 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5259 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5260 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5261 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5264 if (!has_clear_state
) {
5265 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5266 S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
5267 /* Required by DX10_DIAMOND_TEST_ENA: */
5268 S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
5269 S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
5270 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5271 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5272 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5273 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5274 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5277 if (sctx
->chip_class
>= GFX10
) {
5278 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5279 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5280 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5281 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5282 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5283 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5284 } else if (sctx
->chip_class
== GFX9
) {
5285 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5286 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5287 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5289 /* These registers, when written, also overwrite the CLEAR_STATE
5290 * context, so we can't rely on CLEAR_STATE setting them.
5291 * It would be an issue if there was another UMD changing them.
5293 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5294 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5295 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5298 if (sctx
->chip_class
>= GFX7
) {
5299 if (sctx
->chip_class
>= GFX10
) {
5300 /* Logical CUs 16 - 31 */
5301 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
, S_00B404_CU_EN(0xffff));
5302 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
, S_00B104_CU_EN(0xffff));
5303 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
, S_00B004_CU_EN(0xffff));
5306 if (sctx
->chip_class
>= GFX9
) {
5307 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5308 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5310 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5311 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5312 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_WAVE_LIMIT(0x3F));
5313 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5314 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5316 /* If this is 0, Bonaire can hang even if GS isn't being used.
5317 * Other chips are unaffected. These are suboptimal values,
5318 * but we don't use on-chip GS.
5320 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5321 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
5324 /* Compute LATE_ALLOC_VS.LIMIT. */
5325 unsigned num_cu_per_sh
= sscreen
->info
.min_good_cu_per_sa
;
5326 unsigned late_alloc_wave64
= 0; /* The limit is per SA. */
5327 unsigned cu_mask_vs
= 0xffff;
5328 unsigned cu_mask_gs
= 0xffff;
5330 if (sctx
->chip_class
>= GFX10
) {
5331 /* For Wave32, the hw will launch twice the number of late
5332 * alloc waves, so 1 == 2x wave32.
5334 if (!sscreen
->info
.use_late_alloc
) {
5335 late_alloc_wave64
= 0;
5336 } else if (num_cu_per_sh
<= 6) {
5337 late_alloc_wave64
= num_cu_per_sh
- 2;
5339 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5341 /* CU2 & CU3 disabled because of the dual CU design */
5342 /* Late alloc is not used for NGG on Navi14 due to a hw bug. */
5343 cu_mask_vs
= 0xfff3;
5344 cu_mask_gs
= sscreen
->use_ngg
&& sctx
->family
!= CHIP_NAVI14
? 0xfff3 : 0xffff;
5347 if (!sscreen
->info
.use_late_alloc
) {
5348 late_alloc_wave64
= 0;
5349 } else if (num_cu_per_sh
<= 4) {
5350 /* Too few available compute units per SA. Disallowing
5351 * VS to run on one CU could hurt us more than late VS
5352 * allocation would help.
5354 * 2 is the highest safe number that allows us to keep
5357 late_alloc_wave64
= 2;
5359 /* This is a good initial value, allowing 1 late_alloc
5360 * wave per SIMD on num_cu - 2.
5362 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5365 if (late_alloc_wave64
> 2)
5366 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5369 /* VS can't execute on one CU if the limit is > 2. */
5370 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5371 S_00B118_CU_EN(cu_mask_vs
) | S_00B118_WAVE_LIMIT(0x3F));
5372 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(late_alloc_wave64
));
5374 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5375 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5377 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5378 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5381 if (sctx
->chip_class
>= GFX10
) {
5382 /* Break up a pixel wave if it contains deallocs for more than
5383 * half the parameter cache.
5385 * To avoid a deadlock where pixel waves aren't launched
5386 * because they're waiting for more pixels while the frontend
5387 * is stuck waiting for PC space, the maximum allowed value is
5388 * the size of the PC minus the largest possible allocation for
5389 * a single primitive shader subgroup.
5391 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5392 /* Reuse for legacy (non-NGG) only. */
5393 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5395 if (!has_clear_state
) {
5396 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5397 sscreen
->info
.pa_sc_tile_steering_override
);
5400 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5402 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5403 S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5404 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5406 if (sctx
->chip_class
>= GFX10_3
) {
5407 si_pm4_set_reg(pm4
, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103
, 0xff);
5410 if (sctx
->chip_class
>= GFX9
) {
5411 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
,
5412 S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
5413 S_028B50_DONUT_SPLIT(24) | S_028B50_TRAP_SPLIT(6));
5414 } else if (sctx
->chip_class
>= GFX8
) {
5415 unsigned vgt_tess_distribution
;
5417 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
5418 S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT(16);
5420 /* Testing with Unigine Heaven extreme tesselation yielded best results
5421 * with TRAP_SPLIT = 3.
5423 if (sctx
->family
== CHIP_FIJI
|| sctx
->family
>= CHIP_POLARIS10
)
5424 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5426 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5427 } else if (!has_clear_state
) {
5428 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5429 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5432 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5433 if (sctx
->chip_class
>= GFX7
) {
5434 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, S_028084_ADDRESS(border_color_va
>> 40));
5436 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
, RADEON_PRIO_BORDER_COLORS
);
5438 if (sctx
->chip_class
>= GFX9
) {
5439 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5440 S_028C48_MAX_ALLOC_COUNT(sscreen
->info
.pbb_max_alloc_count
- 1) |
5441 S_028C48_MAX_PRIM_PER_BATCH(1023));
5442 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5443 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5444 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5447 sctx
->init_config
= pm4
;