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util: Move gallium's PIPE_FORMAT utils to /util/format/
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/format/u_format.h"
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit &
86 blend->cb_target_mask;
87 unsigned i;
88
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
92 *
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
94 */
95 if (blend->dual_src_blend &&
96 sctx->ps_shader.cso &&
97 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
98 cb_target_mask = 0;
99
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
102 */
103 if (sctx->screen->dpbb_allowed &&
104 sctx->last_cb_target_mask != cb_target_mask) {
105 sctx->last_cb_target_mask = cb_target_mask;
106
107 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
108 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
109 }
110
111 unsigned initial_cdw = cs->current.cdw;
112 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
113 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
114
115 if (sctx->chip_class >= GFX8) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
119 */
120 bool oc_disable = blend->dcc_msaa_corruption_4bit & cb_target_mask &&
121 sctx->framebuffer.nr_samples >= 2;
122 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
123
124 radeon_opt_set_context_reg(
125 sctx, R_028424_CB_DCC_CONTROL,
126 SI_TRACKED_CB_DCC_CONTROL,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
131 }
132
133 /* RB+ register settings. */
134 if (sctx->screen->info.rbplus_allowed) {
135 unsigned spi_shader_col_format =
136 sctx->ps_shader.cso ?
137 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
138 unsigned sx_ps_downconvert = 0;
139 unsigned sx_blend_opt_epsilon = 0;
140 unsigned sx_blend_opt_control = 0;
141
142 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
143 struct si_surface *surf =
144 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
145 unsigned format, swap, spi_format, colormask;
146 bool has_alpha, has_rgb;
147
148 if (!surf) {
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
152 * enable RB+.
153 */
154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
155 continue;
156 }
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 break;
253
254 case V_028C70_COLOR_2_10_10_10:
255 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
256 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
257 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
258 }
259 break;
260 }
261 }
262
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
265 */
266 if (!sx_ps_downconvert)
267 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
268
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
271 SI_TRACKED_SX_PS_DOWNCONVERT,
272 sx_ps_downconvert, sx_blend_opt_epsilon,
273 sx_blend_opt_control);
274 }
275 if (initial_cdw != cs->current.cdw)
276 sctx->context_roll = true;
277 }
278
279 /*
280 * Blender functions
281 */
282
283 static uint32_t si_translate_blend_function(int blend_func)
284 {
285 switch (blend_func) {
286 case PIPE_BLEND_ADD:
287 return V_028780_COMB_DST_PLUS_SRC;
288 case PIPE_BLEND_SUBTRACT:
289 return V_028780_COMB_SRC_MINUS_DST;
290 case PIPE_BLEND_REVERSE_SUBTRACT:
291 return V_028780_COMB_DST_MINUS_SRC;
292 case PIPE_BLEND_MIN:
293 return V_028780_COMB_MIN_DST_SRC;
294 case PIPE_BLEND_MAX:
295 return V_028780_COMB_MAX_DST_SRC;
296 default:
297 PRINT_ERR("Unknown blend function %d\n", blend_func);
298 assert(0);
299 break;
300 }
301 return 0;
302 }
303
304 static uint32_t si_translate_blend_factor(int blend_fact)
305 {
306 switch (blend_fact) {
307 case PIPE_BLENDFACTOR_ONE:
308 return V_028780_BLEND_ONE;
309 case PIPE_BLENDFACTOR_SRC_COLOR:
310 return V_028780_BLEND_SRC_COLOR;
311 case PIPE_BLENDFACTOR_SRC_ALPHA:
312 return V_028780_BLEND_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_DST_ALPHA:
314 return V_028780_BLEND_DST_ALPHA;
315 case PIPE_BLENDFACTOR_DST_COLOR:
316 return V_028780_BLEND_DST_COLOR;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE;
319 case PIPE_BLENDFACTOR_CONST_COLOR:
320 return V_028780_BLEND_CONSTANT_COLOR;
321 case PIPE_BLENDFACTOR_CONST_ALPHA:
322 return V_028780_BLEND_CONSTANT_ALPHA;
323 case PIPE_BLENDFACTOR_ZERO:
324 return V_028780_BLEND_ZERO;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
337 case PIPE_BLENDFACTOR_SRC1_COLOR:
338 return V_028780_BLEND_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA:
340 return V_028780_BLEND_SRC1_ALPHA;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
342 return V_028780_BLEND_INV_SRC1_COLOR;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
344 return V_028780_BLEND_INV_SRC1_ALPHA;
345 default:
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
347 assert(0);
348 break;
349 }
350 return 0;
351 }
352
353 static uint32_t si_translate_blend_opt_function(int blend_func)
354 {
355 switch (blend_func) {
356 case PIPE_BLEND_ADD:
357 return V_028760_OPT_COMB_ADD;
358 case PIPE_BLEND_SUBTRACT:
359 return V_028760_OPT_COMB_SUBTRACT;
360 case PIPE_BLEND_REVERSE_SUBTRACT:
361 return V_028760_OPT_COMB_REVSUBTRACT;
362 case PIPE_BLEND_MIN:
363 return V_028760_OPT_COMB_MIN;
364 case PIPE_BLEND_MAX:
365 return V_028760_OPT_COMB_MAX;
366 default:
367 return V_028760_OPT_COMB_BLEND_DISABLED;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
372 {
373 switch (blend_fact) {
374 case PIPE_BLENDFACTOR_ZERO:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
376 case PIPE_BLENDFACTOR_ONE:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
378 case PIPE_BLENDFACTOR_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
382 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
384 case PIPE_BLENDFACTOR_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
389 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
391 default:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
393 }
394 }
395
396 static void si_blend_check_commutativity(struct si_screen *sscreen,
397 struct si_state_blend *blend,
398 enum pipe_blend_func func,
399 enum pipe_blendfactor src,
400 enum pipe_blendfactor dst,
401 unsigned chanmask)
402 {
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed =
405 (1u << PIPE_BLENDFACTOR_ONE) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_ZERO) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
420
421 if (dst == PIPE_BLENDFACTOR_ONE &&
422 (src_allowed & (1u << src))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
425 * rounding.
426 *
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
430 * setting.
431 */
432 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
433 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
434 blend->commutative_4bit |= chanmask;
435 }
436 }
437
438 /**
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
441 */
442 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
443 unsigned *dst_factor, unsigned expected_dst,
444 unsigned replacement_src)
445 {
446 if (*src_factor == expected_dst &&
447 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
448 *src_factor = PIPE_BLENDFACTOR_ZERO;
449 *dst_factor = replacement_src;
450
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func == PIPE_BLEND_SUBTRACT)
453 *func = PIPE_BLEND_REVERSE_SUBTRACT;
454 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
455 *func = PIPE_BLEND_SUBTRACT;
456 }
457 }
458
459 static bool si_blend_factor_uses_dst(unsigned factor)
460 {
461 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
462 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
464 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
465 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
466 }
467
468 static void *si_create_blend_state_mode(struct pipe_context *ctx,
469 const struct pipe_blend_state *state,
470 unsigned mode)
471 {
472 struct si_context *sctx = (struct si_context*)ctx;
473 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
474 struct si_pm4_state *pm4 = &blend->pm4;
475 uint32_t sx_mrt_blend_opt[8] = {0};
476 uint32_t color_control = 0;
477 bool logicop_enable = state->logicop_enable &&
478 state->logicop_func != PIPE_LOGICOP_COPY;
479
480 if (!blend)
481 return NULL;
482
483 blend->alpha_to_coverage = state->alpha_to_coverage;
484 blend->alpha_to_one = state->alpha_to_one;
485 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
486 blend->logicop_enable = logicop_enable;
487
488 if (logicop_enable) {
489 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
490 } else {
491 color_control |= S_028808_ROP3(0xcc);
492 }
493
494 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
501
502 if (state->alpha_to_coverage)
503 blend->need_src_alpha_4bit |= 0xf;
504
505 blend->cb_target_mask = 0;
506 blend->cb_target_enabled_4bit = 0;
507
508 for (int i = 0; i < 8; i++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j = state->independent_blend_enable ? i : 0;
511
512 unsigned eqRGB = state->rt[j].rgb_func;
513 unsigned srcRGB = state->rt[j].rgb_src_factor;
514 unsigned dstRGB = state->rt[j].rgb_dst_factor;
515 unsigned eqA = state->rt[j].alpha_func;
516 unsigned srcA = state->rt[j].alpha_src_factor;
517 unsigned dstA = state->rt[j].alpha_dst_factor;
518
519 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
520 unsigned blend_cntl = 0;
521
522 sx_mrt_blend_opt[i] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
525
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i >= 1 && blend->dual_src_blend) {
528 /* Vulkan does this for dual source blending. */
529 if (i == 1)
530 blend_cntl |= S_028780_ENABLE(1);
531
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
538 */
539 if (blend->dual_src_blend &&
540 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
541 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544 continue;
545 }
546
547 /* cb_render_state will disable unused ones */
548 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
549 if (state->rt[j].colormask)
550 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
551
552 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
553 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
554 continue;
555 }
556
557 si_blend_check_commutativity(sctx->screen, blend,
558 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
559 si_blend_check_commutativity(sctx->screen, blend,
560 eqA, srcA, dstA, 0x8 << (4 * i));
561
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
564 *
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
567 */
568 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
569 PIPE_BLENDFACTOR_DST_COLOR,
570 PIPE_BLENDFACTOR_SRC_COLOR);
571 si_blend_remove_dst(&eqA, &srcA, &dstA,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_ALPHA,
576 PIPE_BLENDFACTOR_SRC_ALPHA);
577
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
580 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
581 srcA_opt = si_translate_blend_opt_factor(srcA, true);
582 dstA_opt = si_translate_blend_opt_factor(dstA, true);
583
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB))
586 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
587 if (si_blend_factor_uses_dst(srcA))
588 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
589
590 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
591 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
592 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
594 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
595
596 /* Set the final value. */
597 sx_mrt_blend_opt[i] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt) |
602 S_028760_ALPHA_DST_OPT(dstA_opt) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
604
605 /* Set blend state. */
606 blend_cntl |= S_028780_ENABLE(1);
607 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
608 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
609 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
610
611 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
612 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
614 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
615 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
616 }
617 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
618
619 blend->blend_enable_4bit |= 0xfu << (i * 4);
620
621 if (sctx->family <= CHIP_NAVI14)
622 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (sctx->family <= CHIP_NAVI14 && logicop_enable)
635 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
636
637 if (blend->cb_target_mask) {
638 color_control |= S_028808_MODE(mode);
639 } else {
640 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
641 }
642
643 if (sctx->screen->info.rbplus_allowed) {
644 /* Disable RB+ blend optimizations for dual source blending.
645 * Vulkan does this.
646 */
647 if (blend->dual_src_blend) {
648 for (int i = 0; i < 8; i++) {
649 sx_mrt_blend_opt[i] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
652 }
653 }
654
655 for (int i = 0; i < 8; i++)
656 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
657 sx_mrt_blend_opt[i]);
658
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend->dual_src_blend || logicop_enable ||
661 mode == V_028808_CB_RESOLVE)
662 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
663 }
664
665 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
666 return blend;
667 }
668
669 static void *si_create_blend_state(struct pipe_context *ctx,
670 const struct pipe_blend_state *state)
671 {
672 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
673 }
674
675 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
676 {
677 struct si_context *sctx = (struct si_context *)ctx;
678 struct si_state_blend *old_blend = sctx->queued.named.blend;
679 struct si_state_blend *blend = (struct si_state_blend *)state;
680
681 if (!blend)
682 blend = (struct si_state_blend *)sctx->noop_blend;
683
684 si_pm4_bind_state(sctx, blend, blend);
685
686 if (old_blend->cb_target_mask != blend->cb_target_mask ||
687 old_blend->dual_src_blend != blend->dual_src_blend ||
688 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
689 sctx->framebuffer.nr_samples >= 2 &&
690 sctx->screen->dcc_msaa_allowed))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
692
693 if (old_blend->cb_target_mask != blend->cb_target_mask ||
694 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
695 old_blend->alpha_to_one != blend->alpha_to_one ||
696 old_blend->dual_src_blend != blend->dual_src_blend ||
697 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
698 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
699 sctx->do_update_shaders = true;
700
701 if (sctx->screen->dpbb_allowed &&
702 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
709 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
710 old_blend->commutative_4bit != blend->commutative_4bit ||
711 old_blend->logicop_enable != blend->logicop_enable)))
712 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
713 }
714
715 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718
719 if (sctx->queued.named.blend == state)
720 si_bind_blend_state(ctx, sctx->noop_blend);
721
722 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
723 }
724
725 static void si_set_blend_color(struct pipe_context *ctx,
726 const struct pipe_blend_color *state)
727 {
728 struct si_context *sctx = (struct si_context *)ctx;
729 static const struct pipe_blend_color zeros;
730
731 sctx->blend_color.state = *state;
732 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
733 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
734 }
735
736 static void si_emit_blend_color(struct si_context *sctx)
737 {
738 struct radeon_cmdbuf *cs = sctx->gfx_cs;
739
740 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
741 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
742 }
743
744 /*
745 * Clipping
746 */
747
748 static void si_set_clip_state(struct pipe_context *ctx,
749 const struct pipe_clip_state *state)
750 {
751 struct si_context *sctx = (struct si_context *)ctx;
752 struct pipe_constant_buffer cb;
753 static const struct pipe_clip_state zeros;
754
755 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
756 return;
757
758 sctx->clip_state.state = *state;
759 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
760 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
761
762 cb.buffer = NULL;
763 cb.user_buffer = state->ucp;
764 cb.buffer_offset = 0;
765 cb.buffer_size = 4*4*8;
766 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
767 pipe_resource_reference(&cb.buffer, NULL);
768 }
769
770 static void si_emit_clip_state(struct si_context *sctx)
771 {
772 struct radeon_cmdbuf *cs = sctx->gfx_cs;
773
774 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
775 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
776 }
777
778 static void si_emit_clip_regs(struct si_context *sctx)
779 {
780 struct si_shader *vs = si_get_vs_state(sctx);
781 struct si_shader_selector *vs_sel = vs->selector;
782 struct tgsi_shader_info *info = &vs_sel->info;
783 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
784 unsigned window_space =
785 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
786 unsigned clipdist_mask = vs_sel->clipdist_mask;
787 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
788 unsigned culldist_mask = vs_sel->culldist_mask;
789 unsigned total_mask;
790
791 if (vs->key.opt.clip_disable) {
792 assert(!info->culldist_writemask);
793 clipdist_mask = 0;
794 culldist_mask = 0;
795 }
796 total_mask = clipdist_mask | culldist_mask;
797
798 /* Clip distances on points have no effect, so need to be implemented
799 * as cull distances. This applies for the clipvertex case as well.
800 *
801 * Setting this for primitives other than points should have no adverse
802 * effects.
803 */
804 clipdist_mask &= rs->clip_plane_enable;
805 culldist_mask |= clipdist_mask;
806
807 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
808 unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
810 clipdist_mask | (culldist_mask << 8);
811
812 if (sctx->chip_class >= GFX10) {
813 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
814 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
815 pa_cl_cntl,
816 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
817 } else {
818 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
819 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
820 vs_sel->pa_cl_vs_out_cntl | pa_cl_cntl);
821 }
822 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
823 SI_TRACKED_PA_CL_CLIP_CNTL,
824 rs->pa_cl_clip_cntl |
825 ucp_mask |
826 S_028810_CLIP_DISABLE(window_space));
827
828 if (initial_cdw != sctx->gfx_cs->current.cdw)
829 sctx->context_roll = true;
830 }
831
832 /*
833 * inferred state between framebuffer and rasterizer
834 */
835 static void si_update_poly_offset_state(struct si_context *sctx)
836 {
837 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
838
839 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
840 si_pm4_bind_state(sctx, poly_offset, NULL);
841 return;
842 }
843
844 /* Use the user format, not db_render_format, so that the polygon
845 * offset behaves as expected by applications.
846 */
847 switch (sctx->framebuffer.state.zsbuf->texture->format) {
848 case PIPE_FORMAT_Z16_UNORM:
849 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
850 break;
851 default: /* 24-bit */
852 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
853 break;
854 case PIPE_FORMAT_Z32_FLOAT:
855 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
856 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
857 break;
858 }
859 }
860
861 /*
862 * Rasterizer
863 */
864
865 static uint32_t si_translate_fill(uint32_t func)
866 {
867 switch(func) {
868 case PIPE_POLYGON_MODE_FILL:
869 return V_028814_X_DRAW_TRIANGLES;
870 case PIPE_POLYGON_MODE_LINE:
871 return V_028814_X_DRAW_LINES;
872 case PIPE_POLYGON_MODE_POINT:
873 return V_028814_X_DRAW_POINTS;
874 default:
875 assert(0);
876 return V_028814_X_DRAW_POINTS;
877 }
878 }
879
880 static void *si_create_rs_state(struct pipe_context *ctx,
881 const struct pipe_rasterizer_state *state)
882 {
883 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
884 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
885 struct si_pm4_state *pm4 = &rs->pm4;
886 unsigned tmp, i;
887 float psize_min, psize_max;
888
889 if (!rs) {
890 return NULL;
891 }
892
893 if (!state->front_ccw) {
894 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
895 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
896 } else {
897 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
898 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
899 }
900 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
901 rs->provoking_vertex_first = state->flatshade_first;
902 rs->scissor_enable = state->scissor;
903 rs->clip_halfz = state->clip_halfz;
904 rs->two_side = state->light_twoside;
905 rs->multisample_enable = state->multisample;
906 rs->force_persample_interp = state->force_persample_interp;
907 rs->clip_plane_enable = state->clip_plane_enable;
908 rs->half_pixel_center = state->half_pixel_center;
909 rs->line_stipple_enable = state->line_stipple_enable;
910 rs->poly_stipple_enable = state->poly_stipple_enable;
911 rs->line_smooth = state->line_smooth;
912 rs->line_width = state->line_width;
913 rs->poly_smooth = state->poly_smooth;
914 rs->uses_poly_offset = state->offset_point || state->offset_line ||
915 state->offset_tri;
916 rs->clamp_fragment_color = state->clamp_fragment_color;
917 rs->clamp_vertex_color = state->clamp_vertex_color;
918 rs->flatshade = state->flatshade;
919 rs->flatshade_first = state->flatshade_first;
920 rs->sprite_coord_enable = state->sprite_coord_enable;
921 rs->rasterizer_discard = state->rasterizer_discard;
922 rs->pa_sc_line_stipple = state->line_stipple_enable ?
923 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
924 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
925 rs->pa_cl_clip_cntl =
926 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
927 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
928 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
929 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
930 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
931
932 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
933 S_0286D4_FLAT_SHADE_ENA(1) |
934 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
935 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
936 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
937 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
938 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
939 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
940
941 /* point size 12.4 fixed point */
942 tmp = (unsigned)(state->point_size * 8.0);
943 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
944
945 if (state->point_size_per_vertex) {
946 psize_min = util_get_min_point_size(state);
947 psize_max = SI_MAX_POINT_SIZE;
948 } else {
949 /* Force the point size to be as if the vertex output was disabled. */
950 psize_min = state->point_size;
951 psize_max = state->point_size;
952 }
953 rs->max_point_size = psize_max;
954
955 /* Divide by two, because 0.5 = 1 pixel. */
956 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
957 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
958 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
959
960 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
961 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
962 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
963 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
964 S_028A48_MSAA_ENABLE(state->multisample ||
965 state->poly_smooth ||
966 state->line_smooth) |
967 S_028A48_VPORT_SCISSOR_ENABLE(1) |
968 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
969
970 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
971 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
972 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
973 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
974 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
975 S_028814_FACE(!state->front_ccw) |
976 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
977 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
978 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
979 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
980 state->fill_back != PIPE_POLYGON_MODE_FILL) |
981 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
982 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
983
984 if (!rs->uses_poly_offset)
985 return rs;
986
987 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
988 if (!rs->pm4_poly_offset) {
989 FREE(rs);
990 return NULL;
991 }
992
993 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
994 for (i = 0; i < 3; i++) {
995 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
996 float offset_units = state->offset_units;
997 float offset_scale = state->offset_scale * 16.0f;
998 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
999
1000 if (!state->offset_units_unscaled) {
1001 switch (i) {
1002 case 0: /* 16-bit zbuffer */
1003 offset_units *= 4.0f;
1004 pa_su_poly_offset_db_fmt_cntl =
1005 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1006 break;
1007 case 1: /* 24-bit zbuffer */
1008 offset_units *= 2.0f;
1009 pa_su_poly_offset_db_fmt_cntl =
1010 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1011 break;
1012 case 2: /* 32-bit zbuffer */
1013 offset_units *= 1.0f;
1014 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1015 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1016 break;
1017 }
1018 }
1019
1020 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1021 fui(offset_scale));
1022 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1023 fui(offset_units));
1024 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1025 fui(offset_scale));
1026 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1027 fui(offset_units));
1028 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1029 pa_su_poly_offset_db_fmt_cntl);
1030 }
1031
1032 return rs;
1033 }
1034
1035 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1036 {
1037 struct si_context *sctx = (struct si_context *)ctx;
1038 struct si_state_rasterizer *old_rs =
1039 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1040 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1041
1042 if (!rs)
1043 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1044
1045 if (old_rs->multisample_enable != rs->multisample_enable) {
1046 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1047
1048 /* Update the small primitive filter workaround if necessary. */
1049 if (sctx->screen->info.has_msaa_sample_loc_bug &&
1050 sctx->framebuffer.nr_samples > 1)
1051 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1052 }
1053
1054 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1055 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1056
1057 si_pm4_bind_state(sctx, rasterizer, rs);
1058 si_update_poly_offset_state(sctx);
1059
1060 if (old_rs->scissor_enable != rs->scissor_enable)
1061 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1062
1063 if (old_rs->line_width != rs->line_width ||
1064 old_rs->max_point_size != rs->max_point_size ||
1065 old_rs->half_pixel_center != rs->half_pixel_center)
1066 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1067
1068 if (old_rs->clip_halfz != rs->clip_halfz)
1069 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1070
1071 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1072 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1073 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1074
1075 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1076 rs->line_stipple_enable;
1077
1078 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1079 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1080 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1081 old_rs->flatshade != rs->flatshade ||
1082 old_rs->two_side != rs->two_side ||
1083 old_rs->multisample_enable != rs->multisample_enable ||
1084 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1085 old_rs->poly_smooth != rs->poly_smooth ||
1086 old_rs->line_smooth != rs->line_smooth ||
1087 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1088 old_rs->force_persample_interp != rs->force_persample_interp)
1089 sctx->do_update_shaders = true;
1090 }
1091
1092 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1093 {
1094 struct si_context *sctx = (struct si_context *)ctx;
1095 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1096
1097 if (sctx->queued.named.rasterizer == state)
1098 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1099
1100 FREE(rs->pm4_poly_offset);
1101 si_pm4_delete_state(sctx, rasterizer, rs);
1102 }
1103
1104 /*
1105 * infeered state between dsa and stencil ref
1106 */
1107 static void si_emit_stencil_ref(struct si_context *sctx)
1108 {
1109 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1110 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1111 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1112
1113 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1114 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1115 S_028430_STENCILMASK(dsa->valuemask[0]) |
1116 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1117 S_028430_STENCILOPVAL(1));
1118 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1119 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1120 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1121 S_028434_STENCILOPVAL_BF(1));
1122 }
1123
1124 static void si_set_stencil_ref(struct pipe_context *ctx,
1125 const struct pipe_stencil_ref *state)
1126 {
1127 struct si_context *sctx = (struct si_context *)ctx;
1128
1129 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1130 return;
1131
1132 sctx->stencil_ref.state = *state;
1133 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1134 }
1135
1136
1137 /*
1138 * DSA
1139 */
1140
1141 static uint32_t si_translate_stencil_op(int s_op)
1142 {
1143 switch (s_op) {
1144 case PIPE_STENCIL_OP_KEEP:
1145 return V_02842C_STENCIL_KEEP;
1146 case PIPE_STENCIL_OP_ZERO:
1147 return V_02842C_STENCIL_ZERO;
1148 case PIPE_STENCIL_OP_REPLACE:
1149 return V_02842C_STENCIL_REPLACE_TEST;
1150 case PIPE_STENCIL_OP_INCR:
1151 return V_02842C_STENCIL_ADD_CLAMP;
1152 case PIPE_STENCIL_OP_DECR:
1153 return V_02842C_STENCIL_SUB_CLAMP;
1154 case PIPE_STENCIL_OP_INCR_WRAP:
1155 return V_02842C_STENCIL_ADD_WRAP;
1156 case PIPE_STENCIL_OP_DECR_WRAP:
1157 return V_02842C_STENCIL_SUB_WRAP;
1158 case PIPE_STENCIL_OP_INVERT:
1159 return V_02842C_STENCIL_INVERT;
1160 default:
1161 PRINT_ERR("Unknown stencil op %d", s_op);
1162 assert(0);
1163 break;
1164 }
1165 return 0;
1166 }
1167
1168 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1169 {
1170 return s->enabled && s->writemask &&
1171 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1172 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1173 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1174 }
1175
1176 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1177 {
1178 /* REPLACE is normally order invariant, except when the stencil
1179 * reference value is written by the fragment shader. Tracking this
1180 * interaction does not seem worth the effort, so be conservative. */
1181 return op != PIPE_STENCIL_OP_INCR &&
1182 op != PIPE_STENCIL_OP_DECR &&
1183 op != PIPE_STENCIL_OP_REPLACE;
1184 }
1185
1186 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1187 * invariant in the sense that the set of passing fragments as well as the
1188 * final stencil buffer result does not depend on the order of fragments. */
1189 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1190 {
1191 return !state->enabled || !state->writemask ||
1192 /* The following assumes that Z writes are disabled. */
1193 (state->func == PIPE_FUNC_ALWAYS &&
1194 si_order_invariant_stencil_op(state->zpass_op) &&
1195 si_order_invariant_stencil_op(state->zfail_op)) ||
1196 (state->func == PIPE_FUNC_NEVER &&
1197 si_order_invariant_stencil_op(state->fail_op));
1198 }
1199
1200 static void *si_create_dsa_state(struct pipe_context *ctx,
1201 const struct pipe_depth_stencil_alpha_state *state)
1202 {
1203 struct si_context *sctx = (struct si_context *)ctx;
1204 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1205 struct si_pm4_state *pm4 = &dsa->pm4;
1206 unsigned db_depth_control;
1207 uint32_t db_stencil_control = 0;
1208
1209 if (!dsa) {
1210 return NULL;
1211 }
1212
1213 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1214 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1215 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1216 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1217
1218 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1219 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1220 S_028800_ZFUNC(state->depth.func) |
1221 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1222
1223 /* stencil */
1224 if (state->stencil[0].enabled) {
1225 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1226 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1227 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1228 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1229 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1230
1231 if (state->stencil[1].enabled) {
1232 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1233 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1234 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1235 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1236 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1237 }
1238 }
1239
1240 /* alpha */
1241 if (state->alpha.enabled) {
1242 dsa->alpha_func = state->alpha.func;
1243
1244 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1245 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1246 } else {
1247 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1248 }
1249
1250 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1251 if (state->stencil[0].enabled)
1252 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1253 if (state->depth.bounds_test) {
1254 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1255 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1256 }
1257
1258 dsa->depth_enabled = state->depth.enabled;
1259 dsa->depth_write_enabled = state->depth.enabled &&
1260 state->depth.writemask;
1261 dsa->stencil_enabled = state->stencil[0].enabled;
1262 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1263 (si_dsa_writes_stencil(&state->stencil[0]) ||
1264 si_dsa_writes_stencil(&state->stencil[1]));
1265 dsa->db_can_write = dsa->depth_write_enabled ||
1266 dsa->stencil_write_enabled;
1267
1268 bool zfunc_is_ordered =
1269 state->depth.func == PIPE_FUNC_NEVER ||
1270 state->depth.func == PIPE_FUNC_LESS ||
1271 state->depth.func == PIPE_FUNC_LEQUAL ||
1272 state->depth.func == PIPE_FUNC_GREATER ||
1273 state->depth.func == PIPE_FUNC_GEQUAL;
1274
1275 bool nozwrite_and_order_invariant_stencil =
1276 !dsa->db_can_write ||
1277 (!dsa->depth_write_enabled &&
1278 si_order_invariant_stencil_state(&state->stencil[0]) &&
1279 si_order_invariant_stencil_state(&state->stencil[1]));
1280
1281 dsa->order_invariance[1].zs =
1282 nozwrite_and_order_invariant_stencil ||
1283 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1284 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1285
1286 dsa->order_invariance[1].pass_set =
1287 nozwrite_and_order_invariant_stencil ||
1288 (!dsa->stencil_write_enabled &&
1289 (state->depth.func == PIPE_FUNC_ALWAYS ||
1290 state->depth.func == PIPE_FUNC_NEVER));
1291 dsa->order_invariance[0].pass_set =
1292 !dsa->depth_write_enabled ||
1293 (state->depth.func == PIPE_FUNC_ALWAYS ||
1294 state->depth.func == PIPE_FUNC_NEVER);
1295
1296 dsa->order_invariance[1].pass_last =
1297 sctx->screen->assume_no_z_fights &&
1298 !dsa->stencil_write_enabled &&
1299 dsa->depth_write_enabled && zfunc_is_ordered;
1300 dsa->order_invariance[0].pass_last =
1301 sctx->screen->assume_no_z_fights &&
1302 dsa->depth_write_enabled && zfunc_is_ordered;
1303
1304 return dsa;
1305 }
1306
1307 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1308 {
1309 struct si_context *sctx = (struct si_context *)ctx;
1310 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1311 struct si_state_dsa *dsa = state;
1312
1313 if (!dsa)
1314 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1315
1316 si_pm4_bind_state(sctx, dsa, dsa);
1317
1318 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1319 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1320 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1321 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1322 }
1323
1324 if (old_dsa->alpha_func != dsa->alpha_func)
1325 sctx->do_update_shaders = true;
1326
1327 if (sctx->screen->dpbb_allowed &&
1328 ((old_dsa->depth_enabled != dsa->depth_enabled ||
1329 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1330 old_dsa->db_can_write != dsa->db_can_write)))
1331 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1332
1333 if (sctx->screen->has_out_of_order_rast &&
1334 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1335 sizeof(old_dsa->order_invariance))))
1336 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1337 }
1338
1339 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1340 {
1341 struct si_context *sctx = (struct si_context *)ctx;
1342
1343 if (sctx->queued.named.dsa == state)
1344 si_bind_dsa_state(ctx, sctx->noop_dsa);
1345
1346 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1347 }
1348
1349 static void *si_create_db_flush_dsa(struct si_context *sctx)
1350 {
1351 struct pipe_depth_stencil_alpha_state dsa = {};
1352
1353 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1354 }
1355
1356 /* DB RENDER STATE */
1357
1358 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1359 {
1360 struct si_context *sctx = (struct si_context*)ctx;
1361
1362 /* Pipeline stat & streamout queries. */
1363 if (enable) {
1364 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1365 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1366 } else {
1367 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1368 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1369 }
1370
1371 /* Occlusion queries. */
1372 if (sctx->occlusion_queries_disabled != !enable) {
1373 sctx->occlusion_queries_disabled = !enable;
1374 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1375 }
1376 }
1377
1378 void si_set_occlusion_query_state(struct si_context *sctx,
1379 bool old_perfect_enable)
1380 {
1381 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1382
1383 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1384
1385 if (perfect_enable != old_perfect_enable)
1386 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1387 }
1388
1389 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1390 {
1391 st->saved_compute = sctx->cs_shader_state.program;
1392
1393 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1394 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1395
1396 st->saved_ssbo_writable_mask = 0;
1397
1398 for (unsigned i = 0; i < 3; i++) {
1399 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1400 (1u << si_get_shaderbuf_slot(i)))
1401 st->saved_ssbo_writable_mask |= 1 << i;
1402 }
1403 }
1404
1405 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1406 {
1407 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1408
1409 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1410 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1411
1412 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1413 st->saved_ssbo_writable_mask);
1414 for (unsigned i = 0; i < 3; ++i)
1415 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1416 }
1417
1418 static void si_emit_db_render_state(struct si_context *sctx)
1419 {
1420 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1421 unsigned db_shader_control, db_render_control, db_count_control;
1422 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1423
1424 /* DB_RENDER_CONTROL */
1425 if (sctx->dbcb_depth_copy_enabled ||
1426 sctx->dbcb_stencil_copy_enabled) {
1427 db_render_control =
1428 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1429 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1430 S_028000_COPY_CENTROID(1) |
1431 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1432 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1433 db_render_control =
1434 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1435 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1436 } else {
1437 db_render_control =
1438 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1439 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1440 }
1441
1442 /* DB_COUNT_CONTROL (occlusion queries) */
1443 if (sctx->num_occlusion_queries > 0 &&
1444 !sctx->occlusion_queries_disabled) {
1445 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1446 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1447
1448 if (sctx->chip_class >= GFX7) {
1449 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1450
1451 /* Stoney doesn't increment occlusion query counters
1452 * if the sample rate is 16x. Use 8x sample rate instead.
1453 */
1454 if (sctx->family == CHIP_STONEY)
1455 log_sample_rate = MIN2(log_sample_rate, 3);
1456
1457 db_count_control =
1458 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1459 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1460 S_028004_SAMPLE_RATE(log_sample_rate) |
1461 S_028004_ZPASS_ENABLE(1) |
1462 S_028004_SLICE_EVEN_ENABLE(1) |
1463 S_028004_SLICE_ODD_ENABLE(1);
1464 } else {
1465 db_count_control =
1466 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1467 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1468 }
1469 } else {
1470 /* Disable occlusion queries. */
1471 if (sctx->chip_class >= GFX7) {
1472 db_count_control = 0;
1473 } else {
1474 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1475 }
1476 }
1477
1478 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1479 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1480 db_count_control);
1481
1482 /* DB_RENDER_OVERRIDE2 */
1483 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1484 SI_TRACKED_DB_RENDER_OVERRIDE2,
1485 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1486 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1487 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1488
1489 db_shader_control = sctx->ps_db_shader_control;
1490
1491 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1492 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1493 db_shader_control &= C_02880C_Z_ORDER;
1494 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1495 }
1496
1497 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1498 if (!rs->multisample_enable)
1499 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1500
1501 if (sctx->screen->info.has_rbplus &&
1502 !sctx->screen->info.rbplus_allowed)
1503 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1504
1505 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1506 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1507
1508 if (initial_cdw != sctx->gfx_cs->current.cdw)
1509 sctx->context_roll = true;
1510 }
1511
1512 /*
1513 * format translation
1514 */
1515 static uint32_t si_translate_colorformat(enum pipe_format format)
1516 {
1517 const struct util_format_description *desc = util_format_description(format);
1518 if (!desc)
1519 return V_028C70_COLOR_INVALID;
1520
1521 #define HAS_SIZE(x,y,z,w) \
1522 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1523 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1524
1525 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1526 return V_028C70_COLOR_10_11_11;
1527
1528 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1529 return V_028C70_COLOR_INVALID;
1530
1531 /* hw cannot support mixed formats (except depth/stencil, since
1532 * stencil is not written to). */
1533 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1534 return V_028C70_COLOR_INVALID;
1535
1536 switch (desc->nr_channels) {
1537 case 1:
1538 switch (desc->channel[0].size) {
1539 case 8:
1540 return V_028C70_COLOR_8;
1541 case 16:
1542 return V_028C70_COLOR_16;
1543 case 32:
1544 return V_028C70_COLOR_32;
1545 }
1546 break;
1547 case 2:
1548 if (desc->channel[0].size == desc->channel[1].size) {
1549 switch (desc->channel[0].size) {
1550 case 8:
1551 return V_028C70_COLOR_8_8;
1552 case 16:
1553 return V_028C70_COLOR_16_16;
1554 case 32:
1555 return V_028C70_COLOR_32_32;
1556 }
1557 } else if (HAS_SIZE(8,24,0,0)) {
1558 return V_028C70_COLOR_24_8;
1559 } else if (HAS_SIZE(24,8,0,0)) {
1560 return V_028C70_COLOR_8_24;
1561 }
1562 break;
1563 case 3:
1564 if (HAS_SIZE(5,6,5,0)) {
1565 return V_028C70_COLOR_5_6_5;
1566 } else if (HAS_SIZE(32,8,24,0)) {
1567 return V_028C70_COLOR_X24_8_32_FLOAT;
1568 }
1569 break;
1570 case 4:
1571 if (desc->channel[0].size == desc->channel[1].size &&
1572 desc->channel[0].size == desc->channel[2].size &&
1573 desc->channel[0].size == desc->channel[3].size) {
1574 switch (desc->channel[0].size) {
1575 case 4:
1576 return V_028C70_COLOR_4_4_4_4;
1577 case 8:
1578 return V_028C70_COLOR_8_8_8_8;
1579 case 16:
1580 return V_028C70_COLOR_16_16_16_16;
1581 case 32:
1582 return V_028C70_COLOR_32_32_32_32;
1583 }
1584 } else if (HAS_SIZE(5,5,5,1)) {
1585 return V_028C70_COLOR_1_5_5_5;
1586 } else if (HAS_SIZE(1,5,5,5)) {
1587 return V_028C70_COLOR_5_5_5_1;
1588 } else if (HAS_SIZE(10,10,10,2)) {
1589 return V_028C70_COLOR_2_10_10_10;
1590 }
1591 break;
1592 }
1593 return V_028C70_COLOR_INVALID;
1594 }
1595
1596 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1597 {
1598 if (SI_BIG_ENDIAN) {
1599 switch(colorformat) {
1600 /* 8-bit buffers. */
1601 case V_028C70_COLOR_8:
1602 return V_028C70_ENDIAN_NONE;
1603
1604 /* 16-bit buffers. */
1605 case V_028C70_COLOR_5_6_5:
1606 case V_028C70_COLOR_1_5_5_5:
1607 case V_028C70_COLOR_4_4_4_4:
1608 case V_028C70_COLOR_16:
1609 case V_028C70_COLOR_8_8:
1610 return V_028C70_ENDIAN_8IN16;
1611
1612 /* 32-bit buffers. */
1613 case V_028C70_COLOR_8_8_8_8:
1614 case V_028C70_COLOR_2_10_10_10:
1615 case V_028C70_COLOR_8_24:
1616 case V_028C70_COLOR_24_8:
1617 case V_028C70_COLOR_16_16:
1618 return V_028C70_ENDIAN_8IN32;
1619
1620 /* 64-bit buffers. */
1621 case V_028C70_COLOR_16_16_16_16:
1622 return V_028C70_ENDIAN_8IN16;
1623
1624 case V_028C70_COLOR_32_32:
1625 return V_028C70_ENDIAN_8IN32;
1626
1627 /* 128-bit buffers. */
1628 case V_028C70_COLOR_32_32_32_32:
1629 return V_028C70_ENDIAN_8IN32;
1630 default:
1631 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1632 }
1633 } else {
1634 return V_028C70_ENDIAN_NONE;
1635 }
1636 }
1637
1638 static uint32_t si_translate_dbformat(enum pipe_format format)
1639 {
1640 switch (format) {
1641 case PIPE_FORMAT_Z16_UNORM:
1642 return V_028040_Z_16;
1643 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1644 case PIPE_FORMAT_X8Z24_UNORM:
1645 case PIPE_FORMAT_Z24X8_UNORM:
1646 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1647 return V_028040_Z_24; /* deprecated on AMD GCN */
1648 case PIPE_FORMAT_Z32_FLOAT:
1649 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1650 return V_028040_Z_32_FLOAT;
1651 default:
1652 return V_028040_Z_INVALID;
1653 }
1654 }
1655
1656 /*
1657 * Texture translation
1658 */
1659
1660 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1661 enum pipe_format format,
1662 const struct util_format_description *desc,
1663 int first_non_void)
1664 {
1665 struct si_screen *sscreen = (struct si_screen*)screen;
1666 bool uniform = true;
1667 int i;
1668
1669 assert(sscreen->info.chip_class <= GFX9);
1670
1671 /* Colorspace (return non-RGB formats directly). */
1672 switch (desc->colorspace) {
1673 /* Depth stencil formats */
1674 case UTIL_FORMAT_COLORSPACE_ZS:
1675 switch (format) {
1676 case PIPE_FORMAT_Z16_UNORM:
1677 return V_008F14_IMG_DATA_FORMAT_16;
1678 case PIPE_FORMAT_X24S8_UINT:
1679 case PIPE_FORMAT_S8X24_UINT:
1680 /*
1681 * Implemented as an 8_8_8_8 data format to fix texture
1682 * gathers in stencil sampling. This affects at least
1683 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1684 */
1685 if (sscreen->info.chip_class <= GFX8)
1686 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1687
1688 if (format == PIPE_FORMAT_X24S8_UINT)
1689 return V_008F14_IMG_DATA_FORMAT_8_24;
1690 else
1691 return V_008F14_IMG_DATA_FORMAT_24_8;
1692 case PIPE_FORMAT_Z24X8_UNORM:
1693 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1694 return V_008F14_IMG_DATA_FORMAT_8_24;
1695 case PIPE_FORMAT_X8Z24_UNORM:
1696 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1697 return V_008F14_IMG_DATA_FORMAT_24_8;
1698 case PIPE_FORMAT_S8_UINT:
1699 return V_008F14_IMG_DATA_FORMAT_8;
1700 case PIPE_FORMAT_Z32_FLOAT:
1701 return V_008F14_IMG_DATA_FORMAT_32;
1702 case PIPE_FORMAT_X32_S8X24_UINT:
1703 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1704 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1705 default:
1706 goto out_unknown;
1707 }
1708
1709 case UTIL_FORMAT_COLORSPACE_YUV:
1710 goto out_unknown; /* TODO */
1711
1712 case UTIL_FORMAT_COLORSPACE_SRGB:
1713 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1714 goto out_unknown;
1715 break;
1716
1717 default:
1718 break;
1719 }
1720
1721 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1722 if (!sscreen->info.has_format_bc1_through_bc7)
1723 goto out_unknown;
1724
1725 switch (format) {
1726 case PIPE_FORMAT_RGTC1_SNORM:
1727 case PIPE_FORMAT_LATC1_SNORM:
1728 case PIPE_FORMAT_RGTC1_UNORM:
1729 case PIPE_FORMAT_LATC1_UNORM:
1730 return V_008F14_IMG_DATA_FORMAT_BC4;
1731 case PIPE_FORMAT_RGTC2_SNORM:
1732 case PIPE_FORMAT_LATC2_SNORM:
1733 case PIPE_FORMAT_RGTC2_UNORM:
1734 case PIPE_FORMAT_LATC2_UNORM:
1735 return V_008F14_IMG_DATA_FORMAT_BC5;
1736 default:
1737 goto out_unknown;
1738 }
1739 }
1740
1741 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1742 (sscreen->info.family == CHIP_STONEY ||
1743 sscreen->info.family == CHIP_VEGA10 ||
1744 sscreen->info.family == CHIP_RAVEN)) {
1745 switch (format) {
1746 case PIPE_FORMAT_ETC1_RGB8:
1747 case PIPE_FORMAT_ETC2_RGB8:
1748 case PIPE_FORMAT_ETC2_SRGB8:
1749 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1750 case PIPE_FORMAT_ETC2_RGB8A1:
1751 case PIPE_FORMAT_ETC2_SRGB8A1:
1752 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1753 case PIPE_FORMAT_ETC2_RGBA8:
1754 case PIPE_FORMAT_ETC2_SRGBA8:
1755 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1756 case PIPE_FORMAT_ETC2_R11_UNORM:
1757 case PIPE_FORMAT_ETC2_R11_SNORM:
1758 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1759 case PIPE_FORMAT_ETC2_RG11_UNORM:
1760 case PIPE_FORMAT_ETC2_RG11_SNORM:
1761 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1762 default:
1763 goto out_unknown;
1764 }
1765 }
1766
1767 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1768 if (!sscreen->info.has_format_bc1_through_bc7)
1769 goto out_unknown;
1770
1771 switch (format) {
1772 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1773 case PIPE_FORMAT_BPTC_SRGBA:
1774 return V_008F14_IMG_DATA_FORMAT_BC7;
1775 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1776 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1777 return V_008F14_IMG_DATA_FORMAT_BC6;
1778 default:
1779 goto out_unknown;
1780 }
1781 }
1782
1783 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1784 switch (format) {
1785 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1786 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1787 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1788 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1789 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1790 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1791 default:
1792 goto out_unknown;
1793 }
1794 }
1795
1796 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1797 if (!sscreen->info.has_format_bc1_through_bc7)
1798 goto out_unknown;
1799
1800 switch (format) {
1801 case PIPE_FORMAT_DXT1_RGB:
1802 case PIPE_FORMAT_DXT1_RGBA:
1803 case PIPE_FORMAT_DXT1_SRGB:
1804 case PIPE_FORMAT_DXT1_SRGBA:
1805 return V_008F14_IMG_DATA_FORMAT_BC1;
1806 case PIPE_FORMAT_DXT3_RGBA:
1807 case PIPE_FORMAT_DXT3_SRGBA:
1808 return V_008F14_IMG_DATA_FORMAT_BC2;
1809 case PIPE_FORMAT_DXT5_RGBA:
1810 case PIPE_FORMAT_DXT5_SRGBA:
1811 return V_008F14_IMG_DATA_FORMAT_BC3;
1812 default:
1813 goto out_unknown;
1814 }
1815 }
1816
1817 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1818 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1819 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1820 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1821 }
1822
1823 /* R8G8Bx_SNORM - TODO CxV8U8 */
1824
1825 /* hw cannot support mixed formats (except depth/stencil, since only
1826 * depth is read).*/
1827 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1828 goto out_unknown;
1829
1830 /* See whether the components are of the same size. */
1831 for (i = 1; i < desc->nr_channels; i++) {
1832 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1833 }
1834
1835 /* Non-uniform formats. */
1836 if (!uniform) {
1837 switch(desc->nr_channels) {
1838 case 3:
1839 if (desc->channel[0].size == 5 &&
1840 desc->channel[1].size == 6 &&
1841 desc->channel[2].size == 5) {
1842 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1843 }
1844 goto out_unknown;
1845 case 4:
1846 if (desc->channel[0].size == 5 &&
1847 desc->channel[1].size == 5 &&
1848 desc->channel[2].size == 5 &&
1849 desc->channel[3].size == 1) {
1850 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1851 }
1852 if (desc->channel[0].size == 1 &&
1853 desc->channel[1].size == 5 &&
1854 desc->channel[2].size == 5 &&
1855 desc->channel[3].size == 5) {
1856 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1857 }
1858 if (desc->channel[0].size == 10 &&
1859 desc->channel[1].size == 10 &&
1860 desc->channel[2].size == 10 &&
1861 desc->channel[3].size == 2) {
1862 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1863 }
1864 goto out_unknown;
1865 }
1866 goto out_unknown;
1867 }
1868
1869 if (first_non_void < 0 || first_non_void > 3)
1870 goto out_unknown;
1871
1872 /* uniform formats */
1873 switch (desc->channel[first_non_void].size) {
1874 case 4:
1875 switch (desc->nr_channels) {
1876 #if 0 /* Not supported for render targets */
1877 case 2:
1878 return V_008F14_IMG_DATA_FORMAT_4_4;
1879 #endif
1880 case 4:
1881 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1882 }
1883 break;
1884 case 8:
1885 switch (desc->nr_channels) {
1886 case 1:
1887 return V_008F14_IMG_DATA_FORMAT_8;
1888 case 2:
1889 return V_008F14_IMG_DATA_FORMAT_8_8;
1890 case 4:
1891 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1892 }
1893 break;
1894 case 16:
1895 switch (desc->nr_channels) {
1896 case 1:
1897 return V_008F14_IMG_DATA_FORMAT_16;
1898 case 2:
1899 return V_008F14_IMG_DATA_FORMAT_16_16;
1900 case 4:
1901 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1902 }
1903 break;
1904 case 32:
1905 switch (desc->nr_channels) {
1906 case 1:
1907 return V_008F14_IMG_DATA_FORMAT_32;
1908 case 2:
1909 return V_008F14_IMG_DATA_FORMAT_32_32;
1910 #if 0 /* Not supported for render targets */
1911 case 3:
1912 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1913 #endif
1914 case 4:
1915 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1916 }
1917 }
1918
1919 out_unknown:
1920 return ~0;
1921 }
1922
1923 static unsigned si_tex_wrap(unsigned wrap)
1924 {
1925 switch (wrap) {
1926 default:
1927 case PIPE_TEX_WRAP_REPEAT:
1928 return V_008F30_SQ_TEX_WRAP;
1929 case PIPE_TEX_WRAP_CLAMP:
1930 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1931 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1932 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1933 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1934 return V_008F30_SQ_TEX_CLAMP_BORDER;
1935 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1936 return V_008F30_SQ_TEX_MIRROR;
1937 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1938 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1939 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1940 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1941 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1942 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1943 }
1944 }
1945
1946 static unsigned si_tex_mipfilter(unsigned filter)
1947 {
1948 switch (filter) {
1949 case PIPE_TEX_MIPFILTER_NEAREST:
1950 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1951 case PIPE_TEX_MIPFILTER_LINEAR:
1952 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1953 default:
1954 case PIPE_TEX_MIPFILTER_NONE:
1955 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1956 }
1957 }
1958
1959 static unsigned si_tex_compare(unsigned compare)
1960 {
1961 switch (compare) {
1962 default:
1963 case PIPE_FUNC_NEVER:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1965 case PIPE_FUNC_LESS:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1967 case PIPE_FUNC_EQUAL:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1969 case PIPE_FUNC_LEQUAL:
1970 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1971 case PIPE_FUNC_GREATER:
1972 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1973 case PIPE_FUNC_NOTEQUAL:
1974 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1975 case PIPE_FUNC_GEQUAL:
1976 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1977 case PIPE_FUNC_ALWAYS:
1978 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1979 }
1980 }
1981
1982 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1983 unsigned view_target, unsigned nr_samples)
1984 {
1985 unsigned res_target = tex->buffer.b.b.target;
1986
1987 if (view_target == PIPE_TEXTURE_CUBE ||
1988 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1989 res_target = view_target;
1990 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1991 else if (res_target == PIPE_TEXTURE_CUBE ||
1992 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1993 res_target = PIPE_TEXTURE_2D_ARRAY;
1994
1995 /* GFX9 allocates 1D textures as 2D. */
1996 if ((res_target == PIPE_TEXTURE_1D ||
1997 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1998 sscreen->info.chip_class == GFX9 &&
1999 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2000 if (res_target == PIPE_TEXTURE_1D)
2001 res_target = PIPE_TEXTURE_2D;
2002 else
2003 res_target = PIPE_TEXTURE_2D_ARRAY;
2004 }
2005
2006 switch (res_target) {
2007 default:
2008 case PIPE_TEXTURE_1D:
2009 return V_008F1C_SQ_RSRC_IMG_1D;
2010 case PIPE_TEXTURE_1D_ARRAY:
2011 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2012 case PIPE_TEXTURE_2D:
2013 case PIPE_TEXTURE_RECT:
2014 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2015 V_008F1C_SQ_RSRC_IMG_2D;
2016 case PIPE_TEXTURE_2D_ARRAY:
2017 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2018 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2019 case PIPE_TEXTURE_3D:
2020 return V_008F1C_SQ_RSRC_IMG_3D;
2021 case PIPE_TEXTURE_CUBE:
2022 case PIPE_TEXTURE_CUBE_ARRAY:
2023 return V_008F1C_SQ_RSRC_IMG_CUBE;
2024 }
2025 }
2026
2027 /*
2028 * Format support testing
2029 */
2030
2031 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2032 {
2033 struct si_screen *sscreen = (struct si_screen *)screen;
2034
2035 if (sscreen->info.chip_class >= GFX10) {
2036 const struct gfx10_format *fmt = &gfx10_format_table[format];
2037 if (!fmt->img_format || fmt->buffers_only)
2038 return false;
2039 return true;
2040 }
2041
2042 const struct util_format_description *desc = util_format_description(format);
2043 if (!desc)
2044 return false;
2045
2046 return si_translate_texformat(screen, format, desc,
2047 util_format_get_first_non_void_channel(format)) != ~0U;
2048 }
2049
2050 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2051 const struct util_format_description *desc,
2052 int first_non_void)
2053 {
2054 int i;
2055
2056 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2057
2058 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2059 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2060
2061 assert(first_non_void >= 0);
2062
2063 if (desc->nr_channels == 4 &&
2064 desc->channel[0].size == 10 &&
2065 desc->channel[1].size == 10 &&
2066 desc->channel[2].size == 10 &&
2067 desc->channel[3].size == 2)
2068 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2069
2070 /* See whether the components are of the same size. */
2071 for (i = 0; i < desc->nr_channels; i++) {
2072 if (desc->channel[first_non_void].size != desc->channel[i].size)
2073 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2074 }
2075
2076 switch (desc->channel[first_non_void].size) {
2077 case 8:
2078 switch (desc->nr_channels) {
2079 case 1:
2080 case 3: /* 3 loads */
2081 return V_008F0C_BUF_DATA_FORMAT_8;
2082 case 2:
2083 return V_008F0C_BUF_DATA_FORMAT_8_8;
2084 case 4:
2085 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2086 }
2087 break;
2088 case 16:
2089 switch (desc->nr_channels) {
2090 case 1:
2091 case 3: /* 3 loads */
2092 return V_008F0C_BUF_DATA_FORMAT_16;
2093 case 2:
2094 return V_008F0C_BUF_DATA_FORMAT_16_16;
2095 case 4:
2096 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2097 }
2098 break;
2099 case 32:
2100 switch (desc->nr_channels) {
2101 case 1:
2102 return V_008F0C_BUF_DATA_FORMAT_32;
2103 case 2:
2104 return V_008F0C_BUF_DATA_FORMAT_32_32;
2105 case 3:
2106 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2107 case 4:
2108 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2109 }
2110 break;
2111 case 64:
2112 /* Legacy double formats. */
2113 switch (desc->nr_channels) {
2114 case 1: /* 1 load */
2115 return V_008F0C_BUF_DATA_FORMAT_32_32;
2116 case 2: /* 1 load */
2117 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2118 case 3: /* 3 loads */
2119 return V_008F0C_BUF_DATA_FORMAT_32_32;
2120 case 4: /* 2 loads */
2121 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2122 }
2123 break;
2124 }
2125
2126 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2127 }
2128
2129 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2130 const struct util_format_description *desc,
2131 int first_non_void)
2132 {
2133 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2134
2135 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2136 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2137
2138 assert(first_non_void >= 0);
2139
2140 switch (desc->channel[first_non_void].type) {
2141 case UTIL_FORMAT_TYPE_SIGNED:
2142 case UTIL_FORMAT_TYPE_FIXED:
2143 if (desc->channel[first_non_void].size >= 32 ||
2144 desc->channel[first_non_void].pure_integer)
2145 return V_008F0C_BUF_NUM_FORMAT_SINT;
2146 else if (desc->channel[first_non_void].normalized)
2147 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2148 else
2149 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2150 break;
2151 case UTIL_FORMAT_TYPE_UNSIGNED:
2152 if (desc->channel[first_non_void].size >= 32 ||
2153 desc->channel[first_non_void].pure_integer)
2154 return V_008F0C_BUF_NUM_FORMAT_UINT;
2155 else if (desc->channel[first_non_void].normalized)
2156 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2157 else
2158 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2159 break;
2160 case UTIL_FORMAT_TYPE_FLOAT:
2161 default:
2162 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2163 }
2164 }
2165
2166 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2167 enum pipe_format format,
2168 unsigned usage)
2169 {
2170 struct si_screen *sscreen = (struct si_screen *)screen;
2171 const struct util_format_description *desc;
2172 int first_non_void;
2173 unsigned data_format;
2174
2175 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2176 PIPE_BIND_SAMPLER_VIEW |
2177 PIPE_BIND_VERTEX_BUFFER)) == 0);
2178
2179 desc = util_format_description(format);
2180 if (!desc)
2181 return 0;
2182
2183 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2184 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2185 * for read-only access (with caveats surrounding bounds checks), but
2186 * obviously fails for write access which we have to implement for
2187 * shader images. Luckily, OpenGL doesn't expect this to be supported
2188 * anyway, and so the only impact is on PBO uploads / downloads, which
2189 * shouldn't be expected to be fast for GL_RGB anyway.
2190 */
2191 if (desc->block.bits == 3 * 8 ||
2192 desc->block.bits == 3 * 16) {
2193 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2194 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2195 if (!usage)
2196 return 0;
2197 }
2198 }
2199
2200 if (sscreen->info.chip_class >= GFX10) {
2201 const struct gfx10_format *fmt = &gfx10_format_table[format];
2202 if (!fmt->img_format || fmt->img_format >= 128)
2203 return 0;
2204 return usage;
2205 }
2206
2207 first_non_void = util_format_get_first_non_void_channel(format);
2208 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2209 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2210 return 0;
2211
2212 return usage;
2213 }
2214
2215 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2216 {
2217 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2218 si_translate_colorswap(format, false) != ~0U;
2219 }
2220
2221 static bool si_is_zs_format_supported(enum pipe_format format)
2222 {
2223 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2224 }
2225
2226 static bool si_is_format_supported(struct pipe_screen *screen,
2227 enum pipe_format format,
2228 enum pipe_texture_target target,
2229 unsigned sample_count,
2230 unsigned storage_sample_count,
2231 unsigned usage)
2232 {
2233 struct si_screen *sscreen = (struct si_screen *)screen;
2234 unsigned retval = 0;
2235
2236 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2237 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2238 return false;
2239 }
2240
2241 if (util_format_get_num_planes(format) >= 2) {
2242 return util_format_planar_is_supported(screen, format, target,
2243 sample_count,
2244 storage_sample_count,
2245 usage);
2246 }
2247
2248 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2249 return false;
2250
2251 if (sample_count > 1) {
2252 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2253 return false;
2254
2255 /* Only power-of-two sample counts are supported. */
2256 if (!util_is_power_of_two_or_zero(sample_count) ||
2257 !util_is_power_of_two_or_zero(storage_sample_count))
2258 return false;
2259
2260 /* MSAA support without framebuffer attachments. */
2261 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2262 return true;
2263
2264 if (!sscreen->info.has_eqaa_surface_allocator ||
2265 util_format_is_depth_or_stencil(format)) {
2266 /* Color without EQAA or depth/stencil. */
2267 if (sample_count > 8 ||
2268 sample_count != storage_sample_count)
2269 return false;
2270 } else {
2271 /* Color with EQAA. */
2272 if (sample_count > 16 ||
2273 storage_sample_count > 8)
2274 return false;
2275 }
2276 }
2277
2278 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2279 PIPE_BIND_SHADER_IMAGE)) {
2280 if (target == PIPE_BUFFER) {
2281 retval |= si_is_vertex_format_supported(
2282 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2283 PIPE_BIND_SHADER_IMAGE));
2284 } else {
2285 if (si_is_sampler_format_supported(screen, format))
2286 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2287 PIPE_BIND_SHADER_IMAGE);
2288 }
2289 }
2290
2291 if ((usage & (PIPE_BIND_RENDER_TARGET |
2292 PIPE_BIND_DISPLAY_TARGET |
2293 PIPE_BIND_SCANOUT |
2294 PIPE_BIND_SHARED |
2295 PIPE_BIND_BLENDABLE)) &&
2296 si_is_colorbuffer_format_supported(format)) {
2297 retval |= usage &
2298 (PIPE_BIND_RENDER_TARGET |
2299 PIPE_BIND_DISPLAY_TARGET |
2300 PIPE_BIND_SCANOUT |
2301 PIPE_BIND_SHARED);
2302 if (!util_format_is_pure_integer(format) &&
2303 !util_format_is_depth_or_stencil(format))
2304 retval |= usage & PIPE_BIND_BLENDABLE;
2305 }
2306
2307 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2308 si_is_zs_format_supported(format)) {
2309 retval |= PIPE_BIND_DEPTH_STENCIL;
2310 }
2311
2312 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2313 retval |= si_is_vertex_format_supported(screen, format,
2314 PIPE_BIND_VERTEX_BUFFER);
2315 }
2316
2317 if ((usage & PIPE_BIND_LINEAR) &&
2318 !util_format_is_compressed(format) &&
2319 !(usage & PIPE_BIND_DEPTH_STENCIL))
2320 retval |= PIPE_BIND_LINEAR;
2321
2322 return retval == usage;
2323 }
2324
2325 /*
2326 * framebuffer handling
2327 */
2328
2329 static void si_choose_spi_color_formats(struct si_surface *surf,
2330 unsigned format, unsigned swap,
2331 unsigned ntype, bool is_depth)
2332 {
2333 /* Alpha is needed for alpha-to-coverage.
2334 * Blending may be with or without alpha.
2335 */
2336 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2337 unsigned alpha = 0; /* exports alpha, but may not support blending */
2338 unsigned blend = 0; /* supports blending, but may not export alpha */
2339 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2340
2341 /* Choose the SPI color formats. These are required values for RB+.
2342 * Other chips have multiple choices, though they are not necessarily better.
2343 */
2344 switch (format) {
2345 case V_028C70_COLOR_5_6_5:
2346 case V_028C70_COLOR_1_5_5_5:
2347 case V_028C70_COLOR_5_5_5_1:
2348 case V_028C70_COLOR_4_4_4_4:
2349 case V_028C70_COLOR_10_11_11:
2350 case V_028C70_COLOR_11_11_10:
2351 case V_028C70_COLOR_8:
2352 case V_028C70_COLOR_8_8:
2353 case V_028C70_COLOR_8_8_8_8:
2354 case V_028C70_COLOR_10_10_10_2:
2355 case V_028C70_COLOR_2_10_10_10:
2356 if (ntype == V_028C70_NUMBER_UINT)
2357 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2358 else if (ntype == V_028C70_NUMBER_SINT)
2359 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2360 else
2361 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2362 break;
2363
2364 case V_028C70_COLOR_16:
2365 case V_028C70_COLOR_16_16:
2366 case V_028C70_COLOR_16_16_16_16:
2367 if (ntype == V_028C70_NUMBER_UNORM ||
2368 ntype == V_028C70_NUMBER_SNORM) {
2369 /* UNORM16 and SNORM16 don't support blending */
2370 if (ntype == V_028C70_NUMBER_UNORM)
2371 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2372 else
2373 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2374
2375 /* Use 32 bits per channel for blending. */
2376 if (format == V_028C70_COLOR_16) {
2377 if (swap == V_028C70_SWAP_STD) { /* R */
2378 blend = V_028714_SPI_SHADER_32_R;
2379 blend_alpha = V_028714_SPI_SHADER_32_AR;
2380 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2381 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2382 else
2383 assert(0);
2384 } else if (format == V_028C70_COLOR_16_16) {
2385 if (swap == V_028C70_SWAP_STD) { /* RG */
2386 blend = V_028714_SPI_SHADER_32_GR;
2387 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2388 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2389 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2390 else
2391 assert(0);
2392 } else /* 16_16_16_16 */
2393 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2394 } else if (ntype == V_028C70_NUMBER_UINT)
2395 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2396 else if (ntype == V_028C70_NUMBER_SINT)
2397 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2398 else if (ntype == V_028C70_NUMBER_FLOAT)
2399 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2400 else
2401 assert(0);
2402 break;
2403
2404 case V_028C70_COLOR_32:
2405 if (swap == V_028C70_SWAP_STD) { /* R */
2406 blend = normal = V_028714_SPI_SHADER_32_R;
2407 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2408 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2409 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2410 else
2411 assert(0);
2412 break;
2413
2414 case V_028C70_COLOR_32_32:
2415 if (swap == V_028C70_SWAP_STD) { /* RG */
2416 blend = normal = V_028714_SPI_SHADER_32_GR;
2417 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2418 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2419 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2420 else
2421 assert(0);
2422 break;
2423
2424 case V_028C70_COLOR_32_32_32_32:
2425 case V_028C70_COLOR_8_24:
2426 case V_028C70_COLOR_24_8:
2427 case V_028C70_COLOR_X24_8_32_FLOAT:
2428 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2429 break;
2430
2431 default:
2432 assert(0);
2433 return;
2434 }
2435
2436 /* The DB->CB copy needs 32_ABGR. */
2437 if (is_depth)
2438 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2439
2440 surf->spi_shader_col_format = normal;
2441 surf->spi_shader_col_format_alpha = alpha;
2442 surf->spi_shader_col_format_blend = blend;
2443 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2444 }
2445
2446 static void si_initialize_color_surface(struct si_context *sctx,
2447 struct si_surface *surf)
2448 {
2449 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2450 unsigned color_info, color_attrib;
2451 unsigned format, swap, ntype, endian;
2452 const struct util_format_description *desc;
2453 int firstchan;
2454 unsigned blend_clamp = 0, blend_bypass = 0;
2455
2456 desc = util_format_description(surf->base.format);
2457 for (firstchan = 0; firstchan < 4; firstchan++) {
2458 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2459 break;
2460 }
2461 }
2462 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2463 ntype = V_028C70_NUMBER_FLOAT;
2464 } else {
2465 ntype = V_028C70_NUMBER_UNORM;
2466 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2467 ntype = V_028C70_NUMBER_SRGB;
2468 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2469 if (desc->channel[firstchan].pure_integer) {
2470 ntype = V_028C70_NUMBER_SINT;
2471 } else {
2472 assert(desc->channel[firstchan].normalized);
2473 ntype = V_028C70_NUMBER_SNORM;
2474 }
2475 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2476 if (desc->channel[firstchan].pure_integer) {
2477 ntype = V_028C70_NUMBER_UINT;
2478 } else {
2479 assert(desc->channel[firstchan].normalized);
2480 ntype = V_028C70_NUMBER_UNORM;
2481 }
2482 }
2483 }
2484
2485 format = si_translate_colorformat(surf->base.format);
2486 if (format == V_028C70_COLOR_INVALID) {
2487 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2488 }
2489 assert(format != V_028C70_COLOR_INVALID);
2490 swap = si_translate_colorswap(surf->base.format, false);
2491 endian = si_colorformat_endian_swap(format);
2492
2493 /* blend clamp should be set for all NORM/SRGB types */
2494 if (ntype == V_028C70_NUMBER_UNORM ||
2495 ntype == V_028C70_NUMBER_SNORM ||
2496 ntype == V_028C70_NUMBER_SRGB)
2497 blend_clamp = 1;
2498
2499 /* set blend bypass according to docs if SINT/UINT or
2500 8/24 COLOR variants */
2501 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2502 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2503 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2504 blend_clamp = 0;
2505 blend_bypass = 1;
2506 }
2507
2508 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2509 if (format == V_028C70_COLOR_8 ||
2510 format == V_028C70_COLOR_8_8 ||
2511 format == V_028C70_COLOR_8_8_8_8)
2512 surf->color_is_int8 = true;
2513 else if (format == V_028C70_COLOR_10_10_10_2 ||
2514 format == V_028C70_COLOR_2_10_10_10)
2515 surf->color_is_int10 = true;
2516 }
2517
2518 color_info = S_028C70_FORMAT(format) |
2519 S_028C70_COMP_SWAP(swap) |
2520 S_028C70_BLEND_CLAMP(blend_clamp) |
2521 S_028C70_BLEND_BYPASS(blend_bypass) |
2522 S_028C70_SIMPLE_FLOAT(1) |
2523 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2524 ntype != V_028C70_NUMBER_SNORM &&
2525 ntype != V_028C70_NUMBER_SRGB &&
2526 format != V_028C70_COLOR_8_24 &&
2527 format != V_028C70_COLOR_24_8) |
2528 S_028C70_NUMBER_TYPE(ntype) |
2529 S_028C70_ENDIAN(endian);
2530
2531 /* Intensity is implemented as Red, so treat it that way. */
2532 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2533 util_format_is_intensity(surf->base.format));
2534
2535 if (tex->buffer.b.b.nr_samples > 1) {
2536 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2537 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2538
2539 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2540 S_028C74_NUM_FRAGMENTS(log_fragments);
2541
2542 if (tex->surface.fmask_offset) {
2543 color_info |= S_028C70_COMPRESSION(1);
2544 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2545
2546 if (sctx->chip_class == GFX6) {
2547 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2548 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2549 }
2550 }
2551 }
2552
2553 if (sctx->chip_class >= GFX10) {
2554 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2555
2556 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2557 64 for APU because all of our APUs to date use DIMMs which have
2558 a request granularity size of 64B while all other chips have a
2559 32B request size */
2560 if (!sctx->screen->info.has_dedicated_vram)
2561 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2562
2563 surf->cb_dcc_control =
2564 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2565 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2566 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2567 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2568 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2569 } else if (sctx->chip_class >= GFX8) {
2570 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2571 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2572
2573 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2574 64 for APU because all of our APUs to date use DIMMs which have
2575 a request granularity size of 64B while all other chips have a
2576 32B request size */
2577 if (!sctx->screen->info.has_dedicated_vram)
2578 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2579
2580 if (tex->buffer.b.b.nr_storage_samples > 1) {
2581 if (tex->surface.bpe == 1)
2582 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2583 else if (tex->surface.bpe == 2)
2584 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2585 }
2586
2587 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2588 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2589 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2590 }
2591
2592 /* This must be set for fast clear to work without FMASK. */
2593 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2594 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2595 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2596 }
2597
2598 /* GFX10 field has the same base shift as the GFX6 field */
2599 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2600 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2601 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2602
2603 if (sctx->chip_class >= GFX10) {
2604 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2605
2606 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2607 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2608 S_028EE0_RESOURCE_LEVEL(1);
2609 } else if (sctx->chip_class == GFX9) {
2610 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2611 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2612 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2613 }
2614
2615 if (sctx->chip_class >= GFX9) {
2616 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2617 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2618 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2619 }
2620
2621 surf->cb_color_view = color_view;
2622 surf->cb_color_info = color_info;
2623 surf->cb_color_attrib = color_attrib;
2624
2625 /* Determine pixel shader export format */
2626 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2627
2628 surf->color_initialized = true;
2629 }
2630
2631 static void si_init_depth_surface(struct si_context *sctx,
2632 struct si_surface *surf)
2633 {
2634 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2635 unsigned level = surf->base.u.tex.level;
2636 unsigned format, stencil_format;
2637 uint32_t z_info, s_info;
2638
2639 format = si_translate_dbformat(tex->db_render_format);
2640 stencil_format = tex->surface.has_stencil ?
2641 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2642
2643 assert(format != V_028040_Z_INVALID);
2644 if (format == V_028040_Z_INVALID)
2645 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2646
2647 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2648 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2649 surf->db_htile_data_base = 0;
2650 surf->db_htile_surface = 0;
2651
2652 if (sctx->chip_class >= GFX10) {
2653 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2654 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2655 }
2656
2657 if (sctx->chip_class >= GFX9) {
2658 assert(tex->surface.u.gfx9.surf_offset == 0);
2659 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2660 surf->db_stencil_base = (tex->buffer.gpu_address +
2661 tex->surface.u.gfx9.stencil_offset) >> 8;
2662 z_info = S_028038_FORMAT(format) |
2663 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2664 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2665 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2666 s_info = S_02803C_FORMAT(stencil_format) |
2667 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2668
2669 if (sctx->chip_class == GFX9) {
2670 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2671 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2672 }
2673 surf->db_depth_view |= S_028008_MIPID(level);
2674 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2675 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2676
2677 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2678 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2679 S_028038_ALLOW_EXPCLEAR(1);
2680
2681 if (tex->tc_compatible_htile) {
2682 unsigned max_zplanes = 4;
2683
2684 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2685 tex->buffer.b.b.nr_samples > 1)
2686 max_zplanes = 2;
2687
2688 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2689
2690 if (sctx->chip_class >= GFX10) {
2691 z_info |= S_028040_ITERATE_FLUSH(1);
2692 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2693 } else {
2694 z_info |= S_028038_ITERATE_FLUSH(1);
2695 s_info |= S_02803C_ITERATE_FLUSH(1);
2696 }
2697 }
2698
2699 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2700 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2701 * See that for explanation.
2702 */
2703 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2704 } else {
2705 /* Use all HTILE for depth if there's no stencil. */
2706 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2707 }
2708
2709 surf->db_htile_data_base = (tex->buffer.gpu_address +
2710 tex->surface.htile_offset) >> 8;
2711 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2712 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2713 if (sctx->chip_class == GFX9) {
2714 surf->db_htile_surface |=
2715 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2716 }
2717 }
2718 } else {
2719 /* GFX6-GFX8 */
2720 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2721
2722 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2723
2724 surf->db_depth_base = (tex->buffer.gpu_address +
2725 tex->surface.u.legacy.level[level].offset) >> 8;
2726 surf->db_stencil_base = (tex->buffer.gpu_address +
2727 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2728
2729 z_info = S_028040_FORMAT(format) |
2730 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2731 s_info = S_028044_FORMAT(stencil_format);
2732 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2733
2734 if (sctx->chip_class >= GFX7) {
2735 struct radeon_info *info = &sctx->screen->info;
2736 unsigned index = tex->surface.u.legacy.tiling_index[level];
2737 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2738 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2739 unsigned tile_mode = info->si_tile_mode_array[index];
2740 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2741 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2742
2743 surf->db_depth_info |=
2744 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2745 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2746 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2747 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2748 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2749 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2750 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2751 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2752 } else {
2753 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2754 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2755 tile_mode_index = si_tile_mode_index(tex, level, true);
2756 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2757 }
2758
2759 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2760 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2761 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2762 levelinfo->nblk_y) / 64 - 1);
2763
2764 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2765 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2766 S_028040_ALLOW_EXPCLEAR(1);
2767
2768 if (tex->surface.has_stencil) {
2769 /* Workaround: For a not yet understood reason, the
2770 * combination of MSAA, fast stencil clear and stencil
2771 * decompress messes with subsequent stencil buffer
2772 * uses. Problem was reproduced on Verde, Bonaire,
2773 * Tonga, and Carrizo.
2774 *
2775 * Disabling EXPCLEAR works around the problem.
2776 *
2777 * Check piglit's arb_texture_multisample-stencil-clear
2778 * test if you want to try changing this.
2779 */
2780 if (tex->buffer.b.b.nr_samples <= 1)
2781 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2782 } else if (!tex->tc_compatible_htile) {
2783 /* Use all of the htile_buffer for depth if there's no stencil.
2784 * This must not be set when TC-compatible HTILE is enabled
2785 * due to a hw bug.
2786 */
2787 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2788 }
2789
2790 surf->db_htile_data_base = (tex->buffer.gpu_address +
2791 tex->surface.htile_offset) >> 8;
2792 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2793
2794 if (tex->tc_compatible_htile) {
2795 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2796
2797 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2798 if (tex->buffer.b.b.nr_samples <= 1)
2799 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2800 else if (tex->buffer.b.b.nr_samples <= 4)
2801 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2802 else
2803 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2804 }
2805 }
2806 }
2807
2808 surf->db_z_info = z_info;
2809 surf->db_stencil_info = s_info;
2810
2811 surf->depth_initialized = true;
2812 }
2813
2814 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2815 {
2816 if (sctx->decompression_enabled)
2817 return;
2818
2819 if (sctx->framebuffer.state.zsbuf) {
2820 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2821 struct si_texture *tex = (struct si_texture *)surf->texture;
2822
2823 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2824
2825 if (tex->surface.has_stencil)
2826 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2827 }
2828
2829 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2830 while (compressed_cb_mask) {
2831 unsigned i = u_bit_scan(&compressed_cb_mask);
2832 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2833 struct si_texture *tex = (struct si_texture*)surf->texture;
2834
2835 if (tex->surface.fmask_offset) {
2836 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2837 tex->fmask_is_not_identity = true;
2838 }
2839 if (tex->dcc_gather_statistics)
2840 tex->separate_dcc_dirty = true;
2841 }
2842 }
2843
2844 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2845 {
2846 for (int i = 0; i < state->nr_cbufs; ++i) {
2847 struct si_surface *surf = NULL;
2848 struct si_texture *tex;
2849
2850 if (!state->cbufs[i])
2851 continue;
2852 surf = (struct si_surface*)state->cbufs[i];
2853 tex = (struct si_texture*)surf->base.texture;
2854
2855 p_atomic_dec(&tex->framebuffers_bound);
2856 }
2857 }
2858
2859 static void si_set_framebuffer_state(struct pipe_context *ctx,
2860 const struct pipe_framebuffer_state *state)
2861 {
2862 struct si_context *sctx = (struct si_context *)ctx;
2863 struct si_surface *surf = NULL;
2864 struct si_texture *tex;
2865 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2866 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2867 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2868 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2869 bool old_has_stencil =
2870 old_has_zsbuf &&
2871 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2872 bool unbound = false;
2873 int i;
2874
2875 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2876 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2877 * We could implement the full workaround here, but it's a useless case.
2878 */
2879 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2880 unreachable("the framebuffer shouldn't have zero area");
2881 return;
2882 }
2883
2884 si_update_fb_dirtiness_after_rendering(sctx);
2885
2886 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2887 if (!sctx->framebuffer.state.cbufs[i])
2888 continue;
2889
2890 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2891 if (tex->dcc_gather_statistics)
2892 vi_separate_dcc_stop_query(sctx, tex);
2893 }
2894
2895 /* Disable DCC if the formats are incompatible. */
2896 for (i = 0; i < state->nr_cbufs; i++) {
2897 if (!state->cbufs[i])
2898 continue;
2899
2900 surf = (struct si_surface*)state->cbufs[i];
2901 tex = (struct si_texture*)surf->base.texture;
2902
2903 if (!surf->dcc_incompatible)
2904 continue;
2905
2906 /* Since the DCC decompression calls back into set_framebuffer-
2907 * _state, we need to unbind the framebuffer, so that
2908 * vi_separate_dcc_stop_query isn't called twice with the same
2909 * color buffer.
2910 */
2911 if (!unbound) {
2912 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2913 unbound = true;
2914 }
2915
2916 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2917 if (!si_texture_disable_dcc(sctx, tex))
2918 si_decompress_dcc(sctx, tex);
2919
2920 surf->dcc_incompatible = false;
2921 }
2922
2923 /* Only flush TC when changing the framebuffer state, because
2924 * the only client not using TC that can change textures is
2925 * the framebuffer.
2926 *
2927 * Wait for compute shaders because of possible transitions:
2928 * - FB write -> shader read
2929 * - shader write -> FB read
2930 *
2931 * DB caches are flushed on demand (using si_decompress_textures).
2932 *
2933 * When MSAA is enabled, CB and TC caches are flushed on demand
2934 * (after FMASK decompression). Shader write -> FB read transitions
2935 * cannot happen for MSAA textures, because MSAA shader images are
2936 * not supported.
2937 *
2938 * Only flush and wait for CB if there is actually a bound color buffer.
2939 */
2940 if (sctx->framebuffer.uncompressed_cb_mask) {
2941 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2942 sctx->framebuffer.CB_has_shader_readable_metadata,
2943 sctx->framebuffer.all_DCC_pipe_aligned);
2944 }
2945
2946 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2947
2948 /* u_blitter doesn't invoke depth decompression when it does multiple
2949 * blits in a row, but the only case when it matters for DB is when
2950 * doing generate_mipmap. So here we flush DB manually between
2951 * individual generate_mipmap blits.
2952 * Note that lower mipmap levels aren't compressed.
2953 */
2954 if (sctx->generate_mipmap_for_depth) {
2955 si_make_DB_shader_coherent(sctx, 1, false,
2956 sctx->framebuffer.DB_has_shader_readable_metadata);
2957 } else if (sctx->chip_class == GFX9) {
2958 /* It appears that DB metadata "leaks" in a sequence of:
2959 * - depth clear
2960 * - DCC decompress for shader image writes (with DB disabled)
2961 * - render with DEPTH_BEFORE_SHADER=1
2962 * Flushing DB metadata works around the problem.
2963 */
2964 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2965 }
2966
2967 /* Take the maximum of the old and new count. If the new count is lower,
2968 * dirtying is needed to disable the unbound colorbuffers.
2969 */
2970 sctx->framebuffer.dirty_cbufs |=
2971 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2972 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2973
2974 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2975 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2976
2977 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2978 sctx->framebuffer.spi_shader_col_format = 0;
2979 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2980 sctx->framebuffer.spi_shader_col_format_blend = 0;
2981 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2982 sctx->framebuffer.color_is_int8 = 0;
2983 sctx->framebuffer.color_is_int10 = 0;
2984
2985 sctx->framebuffer.compressed_cb_mask = 0;
2986 sctx->framebuffer.uncompressed_cb_mask = 0;
2987 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2988 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2989 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2990 sctx->framebuffer.any_dst_linear = false;
2991 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2992 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2993 sctx->framebuffer.all_DCC_pipe_aligned = true;
2994 sctx->framebuffer.min_bytes_per_pixel = 0;
2995
2996 for (i = 0; i < state->nr_cbufs; i++) {
2997 if (!state->cbufs[i])
2998 continue;
2999
3000 surf = (struct si_surface*)state->cbufs[i];
3001 tex = (struct si_texture*)surf->base.texture;
3002
3003 if (!surf->color_initialized) {
3004 si_initialize_color_surface(sctx, surf);
3005 }
3006
3007 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
3008 sctx->framebuffer.spi_shader_col_format |=
3009 surf->spi_shader_col_format << (i * 4);
3010 sctx->framebuffer.spi_shader_col_format_alpha |=
3011 surf->spi_shader_col_format_alpha << (i * 4);
3012 sctx->framebuffer.spi_shader_col_format_blend |=
3013 surf->spi_shader_col_format_blend << (i * 4);
3014 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
3015 surf->spi_shader_col_format_blend_alpha << (i * 4);
3016
3017 if (surf->color_is_int8)
3018 sctx->framebuffer.color_is_int8 |= 1 << i;
3019 if (surf->color_is_int10)
3020 sctx->framebuffer.color_is_int10 |= 1 << i;
3021
3022 if (tex->surface.fmask_offset)
3023 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3024 else
3025 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3026
3027 /* Don't update nr_color_samples for non-AA buffers.
3028 * (e.g. destination of MSAA resolve)
3029 */
3030 if (tex->buffer.b.b.nr_samples >= 2 &&
3031 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3032 sctx->framebuffer.nr_color_samples =
3033 MIN2(sctx->framebuffer.nr_color_samples,
3034 tex->buffer.b.b.nr_storage_samples);
3035 sctx->framebuffer.nr_color_samples =
3036 MAX2(1, sctx->framebuffer.nr_color_samples);
3037 }
3038
3039 if (tex->surface.is_linear)
3040 sctx->framebuffer.any_dst_linear = true;
3041
3042 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3043 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3044
3045 if (sctx->chip_class >= GFX9 &&
3046 !tex->surface.u.gfx9.dcc.pipe_aligned)
3047 sctx->framebuffer.all_DCC_pipe_aligned = false;
3048 }
3049
3050 si_context_add_resource_size(sctx, surf->base.texture);
3051
3052 p_atomic_inc(&tex->framebuffers_bound);
3053
3054 if (tex->dcc_gather_statistics) {
3055 /* Dirty tracking must be enabled for DCC usage analysis. */
3056 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3057 vi_separate_dcc_start_query(sctx, tex);
3058 }
3059
3060 /* Update the minimum but don't keep 0. */
3061 if (!sctx->framebuffer.min_bytes_per_pixel ||
3062 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3063 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3064 }
3065
3066 /* For optimal DCC performance. */
3067 if (sctx->chip_class >= GFX10)
3068 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3069 else
3070 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3071
3072 struct si_texture *zstex = NULL;
3073
3074 if (state->zsbuf) {
3075 surf = (struct si_surface*)state->zsbuf;
3076 zstex = (struct si_texture*)surf->base.texture;
3077
3078 if (!surf->depth_initialized) {
3079 si_init_depth_surface(sctx, surf);
3080 }
3081
3082 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3083 PIPE_MASK_ZS))
3084 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3085
3086 si_context_add_resource_size(sctx, surf->base.texture);
3087
3088 /* Update the minimum but don't keep 0. */
3089 if (!sctx->framebuffer.min_bytes_per_pixel ||
3090 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3091 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
3092 }
3093
3094 si_update_ps_colorbuf0_slot(sctx);
3095 si_update_poly_offset_state(sctx);
3096 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3097 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3098
3099 if (sctx->screen->dpbb_allowed)
3100 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3101
3102 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3103 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3104
3105 if (sctx->screen->has_out_of_order_rast &&
3106 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3107 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3108 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3109 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3110
3111 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3112 struct pipe_constant_buffer constbuf = {0};
3113
3114 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3115 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3116
3117 constbuf.buffer = sctx->sample_pos_buffer;
3118
3119 /* Set sample locations as fragment shader constants. */
3120 switch (sctx->framebuffer.nr_samples) {
3121 case 1:
3122 constbuf.buffer_offset = 0;
3123 break;
3124 case 2:
3125 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3126 (ubyte*)sctx->sample_positions.x1;
3127 break;
3128 case 4:
3129 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3130 (ubyte*)sctx->sample_positions.x1;
3131 break;
3132 case 8:
3133 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3134 (ubyte*)sctx->sample_positions.x1;
3135 break;
3136 case 16:
3137 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3138 (ubyte*)sctx->sample_positions.x1;
3139 break;
3140 default:
3141 PRINT_ERR("Requested an invalid number of samples %i.\n",
3142 sctx->framebuffer.nr_samples);
3143 assert(0);
3144 }
3145 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3146 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3147
3148 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3149 }
3150
3151 sctx->do_update_shaders = true;
3152
3153 if (!sctx->decompression_enabled) {
3154 /* Prevent textures decompression when the framebuffer state
3155 * changes come from the decompression passes themselves.
3156 */
3157 sctx->need_check_render_feedback = true;
3158 }
3159 }
3160
3161 static void si_emit_framebuffer_state(struct si_context *sctx)
3162 {
3163 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3164 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3165 unsigned i, nr_cbufs = state->nr_cbufs;
3166 struct si_texture *tex = NULL;
3167 struct si_surface *cb = NULL;
3168 unsigned cb_color_info = 0;
3169
3170 /* Colorbuffers. */
3171 for (i = 0; i < nr_cbufs; i++) {
3172 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3173 unsigned cb_color_attrib;
3174
3175 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3176 continue;
3177
3178 cb = (struct si_surface*)state->cbufs[i];
3179 if (!cb) {
3180 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3181 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3182 continue;
3183 }
3184
3185 tex = (struct si_texture *)cb->base.texture;
3186 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3187 &tex->buffer, RADEON_USAGE_READWRITE,
3188 tex->buffer.b.b.nr_samples > 1 ?
3189 RADEON_PRIO_COLOR_BUFFER_MSAA :
3190 RADEON_PRIO_COLOR_BUFFER);
3191
3192 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3193 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3194 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3195 RADEON_PRIO_SEPARATE_META);
3196 }
3197
3198 if (tex->dcc_separate_buffer)
3199 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3200 tex->dcc_separate_buffer,
3201 RADEON_USAGE_READWRITE,
3202 RADEON_PRIO_SEPARATE_META);
3203
3204 /* Compute mutable surface parameters. */
3205 cb_color_base = tex->buffer.gpu_address >> 8;
3206 cb_color_fmask = 0;
3207 cb_color_cmask = tex->cmask_base_address_reg;
3208 cb_dcc_base = 0;
3209 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3210 cb_color_attrib = cb->cb_color_attrib;
3211
3212 if (cb->base.u.tex.level > 0)
3213 cb_color_info &= C_028C70_FAST_CLEAR;
3214
3215 if (tex->surface.fmask_offset) {
3216 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3217 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3218 }
3219
3220 /* Set up DCC. */
3221 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3222 bool is_msaa_resolve_dst = state->cbufs[0] &&
3223 state->cbufs[0]->texture->nr_samples > 1 &&
3224 state->cbufs[1] == &cb->base &&
3225 state->cbufs[1]->texture->nr_samples <= 1;
3226
3227 if (!is_msaa_resolve_dst)
3228 cb_color_info |= S_028C70_DCC_ENABLE(1);
3229
3230 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3231 tex->surface.dcc_offset) >> 8;
3232
3233 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3234 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3235 cb_dcc_base |= dcc_tile_swizzle;
3236 }
3237
3238 if (sctx->chip_class >= GFX10) {
3239 unsigned cb_color_attrib3;
3240
3241 /* Set mutable surface parameters. */
3242 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3243 cb_color_base |= tex->surface.tile_swizzle;
3244 if (!tex->surface.fmask_offset)
3245 cb_color_fmask = cb_color_base;
3246 if (cb->base.u.tex.level > 0)
3247 cb_color_cmask = cb_color_base;
3248
3249 cb_color_attrib3 = cb->cb_color_attrib3 |
3250 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3251 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3252 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3253 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3254
3255 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3256 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3257 radeon_emit(cs, 0); /* hole */
3258 radeon_emit(cs, 0); /* hole */
3259 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3260 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3261 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3262 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3263 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3264 radeon_emit(cs, 0); /* hole */
3265 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3266 radeon_emit(cs, 0); /* hole */
3267 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3268 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3269 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3270
3271 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3272 cb_color_base >> 32);
3273 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3274 cb_color_cmask >> 32);
3275 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3276 cb_color_fmask >> 32);
3277 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3278 cb_dcc_base >> 32);
3279 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3280 cb->cb_color_attrib2);
3281 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3282 cb_color_attrib3);
3283 } else if (sctx->chip_class == GFX9) {
3284 struct gfx9_surf_meta_flags meta;
3285
3286 if (tex->surface.dcc_offset)
3287 meta = tex->surface.u.gfx9.dcc;
3288 else
3289 meta = tex->surface.u.gfx9.cmask;
3290
3291 /* Set mutable surface parameters. */
3292 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3293 cb_color_base |= tex->surface.tile_swizzle;
3294 if (!tex->surface.fmask_offset)
3295 cb_color_fmask = cb_color_base;
3296 if (cb->base.u.tex.level > 0)
3297 cb_color_cmask = cb_color_base;
3298 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3299 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3300 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3301 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3302
3303 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3304 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3305 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3306 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3307 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3308 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3309 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3310 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3311 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3312 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3313 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3314 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3315 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3316 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3317 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3318 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3319
3320 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3321 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3322 } else {
3323 /* Compute mutable surface parameters (GFX6-GFX8). */
3324 const struct legacy_surf_level *level_info =
3325 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3326 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3327 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3328
3329 cb_color_base += level_info->offset >> 8;
3330 /* Only macrotiled modes can set tile swizzle. */
3331 if (level_info->mode == RADEON_SURF_MODE_2D)
3332 cb_color_base |= tex->surface.tile_swizzle;
3333
3334 if (!tex->surface.fmask_offset)
3335 cb_color_fmask = cb_color_base;
3336 if (cb->base.u.tex.level > 0)
3337 cb_color_cmask = cb_color_base;
3338 if (cb_dcc_base)
3339 cb_dcc_base += level_info->dcc_offset >> 8;
3340
3341 pitch_tile_max = level_info->nblk_x / 8 - 1;
3342 slice_tile_max = level_info->nblk_x *
3343 level_info->nblk_y / 64 - 1;
3344 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3345
3346 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3347 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3348 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3349
3350 if (tex->surface.fmask_offset) {
3351 if (sctx->chip_class >= GFX7)
3352 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3353 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3354 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3355 } else {
3356 /* This must be set for fast clear to work without FMASK. */
3357 if (sctx->chip_class >= GFX7)
3358 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3359 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3360 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3361 }
3362
3363 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3364 sctx->chip_class >= GFX8 ? 14 : 13);
3365 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3366 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3367 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3368 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3369 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3370 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3371 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3372 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3373 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3374 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3375 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3376 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3377 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3378
3379 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3380 radeon_emit(cs, cb_dcc_base);
3381 }
3382 }
3383 for (; i < 8 ; i++)
3384 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3385 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3386
3387 /* ZS buffer. */
3388 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3389 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3390 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3391
3392 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3393 &tex->buffer, RADEON_USAGE_READWRITE,
3394 zb->base.texture->nr_samples > 1 ?
3395 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3396 RADEON_PRIO_DEPTH_BUFFER);
3397
3398 if (sctx->chip_class >= GFX10) {
3399 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3400 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3401
3402 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3403 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3404 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3405 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3406 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3407 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3408 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3409 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3410 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3411
3412 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3413 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3414 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3415 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3416 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3417 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3418 } else if (sctx->chip_class == GFX9) {
3419 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3420 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3421 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3422 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3423
3424 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3425 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3426 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3427 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3428 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3429 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3430 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3431 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3432 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3433 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3434 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3435 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3436
3437 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3438 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3439 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3440 } else {
3441 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3442
3443 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3444 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3445 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3446 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3447 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3448 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3449 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3450 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3451 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3452 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3453 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3454 }
3455
3456 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3457 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3458 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3459
3460 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3461 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3462 } else if (sctx->framebuffer.dirty_zsbuf) {
3463 if (sctx->chip_class == GFX9)
3464 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3465 else
3466 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3467
3468 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3469 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3470 }
3471
3472 /* Framebuffer dimensions. */
3473 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3474 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3475 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3476
3477 if (sctx->screen->dfsm_allowed) {
3478 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3479 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3480 }
3481
3482 sctx->framebuffer.dirty_cbufs = 0;
3483 sctx->framebuffer.dirty_zsbuf = false;
3484 }
3485
3486 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3487 {
3488 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3489 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3490 unsigned nr_samples = sctx->framebuffer.nr_samples;
3491 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3492
3493 /* Smoothing (only possible with nr_samples == 1) uses the same
3494 * sample locations as the MSAA it simulates.
3495 */
3496 if (nr_samples <= 1 && sctx->smoothing_enabled)
3497 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3498
3499 /* On Polaris, the small primitive filter uses the sample locations
3500 * even when MSAA is off, so we need to make sure they're set to 0.
3501 *
3502 * GFX10 uses sample locations unconditionally, so they always need
3503 * to be set up.
3504 */
3505 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3506 sctx->chip_class >= GFX10) &&
3507 nr_samples != sctx->sample_locs_num_samples) {
3508 sctx->sample_locs_num_samples = nr_samples;
3509 si_emit_sample_locations(cs, nr_samples);
3510 }
3511
3512 if (sctx->family >= CHIP_POLARIS10) {
3513 unsigned small_prim_filter_cntl =
3514 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3515 /* line bug */
3516 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3517
3518 /* The alternative of setting sample locations to 0 would
3519 * require a DB flush to avoid Z errors, see
3520 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3521 */
3522 if (has_msaa_sample_loc_bug &&
3523 sctx->framebuffer.nr_samples > 1 &&
3524 !rs->multisample_enable)
3525 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3526
3527 radeon_opt_set_context_reg(sctx,
3528 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3529 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3530 small_prim_filter_cntl);
3531 }
3532
3533 /* The exclusion bits can be set to improve rasterization efficiency
3534 * if no sample lies on the pixel boundary (-8 sample offset).
3535 */
3536 bool exclusion = sctx->chip_class >= GFX7 &&
3537 (!rs->multisample_enable || nr_samples != 16);
3538 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3539 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3540 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3541 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3542 }
3543
3544 static bool si_out_of_order_rasterization(struct si_context *sctx)
3545 {
3546 struct si_state_blend *blend = sctx->queued.named.blend;
3547 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3548
3549 if (!sctx->screen->has_out_of_order_rast)
3550 return false;
3551
3552 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3553
3554 colormask &= blend->cb_target_enabled_4bit;
3555
3556 /* Conservative: No logic op. */
3557 if (colormask && blend->logicop_enable)
3558 return false;
3559
3560 struct si_dsa_order_invariance dsa_order_invariant = {
3561 .zs = true, .pass_set = true, .pass_last = false
3562 };
3563
3564 if (sctx->framebuffer.state.zsbuf) {
3565 struct si_texture *zstex =
3566 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3567 bool has_stencil = zstex->surface.has_stencil;
3568 dsa_order_invariant = dsa->order_invariance[has_stencil];
3569 if (!dsa_order_invariant.zs)
3570 return false;
3571
3572 /* The set of PS invocations is always order invariant,
3573 * except when early Z/S tests are requested. */
3574 if (sctx->ps_shader.cso &&
3575 sctx->ps_shader.cso->info.writes_memory &&
3576 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3577 !dsa_order_invariant.pass_set)
3578 return false;
3579
3580 if (sctx->num_perfect_occlusion_queries != 0 &&
3581 !dsa_order_invariant.pass_set)
3582 return false;
3583 }
3584
3585 if (!colormask)
3586 return true;
3587
3588 unsigned blendmask = colormask & blend->blend_enable_4bit;
3589
3590 if (blendmask) {
3591 /* Only commutative blending. */
3592 if (blendmask & ~blend->commutative_4bit)
3593 return false;
3594
3595 if (!dsa_order_invariant.pass_set)
3596 return false;
3597 }
3598
3599 if (colormask & ~blendmask) {
3600 if (!dsa_order_invariant.pass_last)
3601 return false;
3602 }
3603
3604 return true;
3605 }
3606
3607 static void si_emit_msaa_config(struct si_context *sctx)
3608 {
3609 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3610 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3611 /* 33% faster rendering to linear color buffers */
3612 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3613 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3614 unsigned sc_mode_cntl_1 =
3615 S_028A4C_WALK_SIZE(dst_is_linear) |
3616 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3617 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3618 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3619 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3620 /* always 1: */
3621 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3622 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3623 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3624 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3625 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3626 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3627 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3628 S_028804_INCOHERENT_EQAA_READS(1) |
3629 S_028804_INTERPOLATE_COMP_Z(1) |
3630 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3631 unsigned coverage_samples, color_samples, z_samples;
3632 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3633
3634 /* S: Coverage samples (up to 16x):
3635 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3636 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3637 *
3638 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3639 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3640 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3641 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3642 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3643 * # Z samples).
3644 *
3645 * F: Color samples (up to 8x, must be <= coverage samples):
3646 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3647 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3648 *
3649 * Can be anything between coverage and color samples:
3650 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3651 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3652 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3653 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3654 * # All are currently set the same as coverage samples.
3655 *
3656 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3657 * flag for undefined color samples. A shader-based resolve must handle unknowns
3658 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3659 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3660 * useful. The CB resolve always drops unknowns.
3661 *
3662 * Sensible AA configurations:
3663 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3664 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3665 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3666 * EQAA 8s 8z 8f = 8x MSAA
3667 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3668 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3669 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3670 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3671 * EQAA 4s 4z 4f = 4x MSAA
3672 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3673 * EQAA 2s 2z 2f = 2x MSAA
3674 */
3675 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3676 coverage_samples = sctx->framebuffer.nr_samples;
3677 color_samples = sctx->framebuffer.nr_color_samples;
3678
3679 if (sctx->framebuffer.state.zsbuf) {
3680 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3681 z_samples = MAX2(1, z_samples);
3682 } else {
3683 z_samples = coverage_samples;
3684 }
3685 } else if (sctx->smoothing_enabled) {
3686 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3687 } else {
3688 coverage_samples = color_samples = z_samples = 1;
3689 }
3690
3691 /* Required by OpenGL line rasterization.
3692 *
3693 * TODO: We should also enable perpendicular endcaps for AA lines,
3694 * but that requires implementing line stippling in the pixel
3695 * shader. SC can only do line stippling with axis-aligned
3696 * endcaps.
3697 */
3698 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3699 unsigned sc_aa_config = 0;
3700
3701 if (coverage_samples > 1) {
3702 /* distance from the pixel center, indexed by log2(nr_samples) */
3703 static unsigned max_dist[] = {
3704 0, /* unused */
3705 4, /* 2x MSAA */
3706 6, /* 4x MSAA */
3707 7, /* 8x MSAA */
3708 8, /* 16x MSAA */
3709 };
3710 unsigned log_samples = util_logbase2(coverage_samples);
3711 unsigned log_z_samples = util_logbase2(z_samples);
3712 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3713 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3714
3715 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3716 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3717 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3718 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3719
3720 if (sctx->framebuffer.nr_samples > 1) {
3721 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3722 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3723 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3724 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3725 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3726 } else if (sctx->smoothing_enabled) {
3727 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3728 }
3729 }
3730
3731 unsigned initial_cdw = cs->current.cdw;
3732
3733 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3734 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3735 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3736 sc_aa_config);
3737 /* R_028804_DB_EQAA */
3738 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3739 db_eqaa);
3740 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3741 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3742 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3743
3744 if (initial_cdw != cs->current.cdw) {
3745 sctx->context_roll = true;
3746
3747 /* GFX9: Flush DFSM when the AA mode changes. */
3748 if (sctx->screen->dfsm_allowed) {
3749 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3750 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3751 }
3752 }
3753 }
3754
3755 void si_update_ps_iter_samples(struct si_context *sctx)
3756 {
3757 if (sctx->framebuffer.nr_samples > 1)
3758 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3759 if (sctx->screen->dpbb_allowed)
3760 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3761 }
3762
3763 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3764 {
3765 struct si_context *sctx = (struct si_context *)ctx;
3766
3767 /* The hardware can only do sample shading with 2^n samples. */
3768 min_samples = util_next_power_of_two(min_samples);
3769
3770 if (sctx->ps_iter_samples == min_samples)
3771 return;
3772
3773 sctx->ps_iter_samples = min_samples;
3774 sctx->do_update_shaders = true;
3775
3776 si_update_ps_iter_samples(sctx);
3777 }
3778
3779 /*
3780 * Samplers
3781 */
3782
3783 /**
3784 * Build the sampler view descriptor for a buffer texture.
3785 * @param state 256-bit descriptor; only the high 128 bits are filled in
3786 */
3787 void
3788 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3789 enum pipe_format format,
3790 unsigned offset, unsigned size,
3791 uint32_t *state)
3792 {
3793 const struct util_format_description *desc;
3794 unsigned stride;
3795 unsigned num_records;
3796
3797 desc = util_format_description(format);
3798 stride = desc->block.bits / 8;
3799
3800 num_records = size / stride;
3801 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3802
3803 /* The NUM_RECORDS field has a different meaning depending on the chip,
3804 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3805 *
3806 * GFX6-7,10:
3807 * - If STRIDE == 0, it's in byte units.
3808 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3809 *
3810 * GFX8:
3811 * - For SMEM and STRIDE == 0, it's in byte units.
3812 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3813 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3814 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3815 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3816 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3817 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3818 * That way the same descriptor can be used by both SMEM and VMEM.
3819 *
3820 * GFX9:
3821 * - For SMEM and STRIDE == 0, it's in byte units.
3822 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3823 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3824 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3825 */
3826 if (screen->info.chip_class == GFX8)
3827 num_records *= stride;
3828
3829 state[4] = 0;
3830 state[5] = S_008F04_STRIDE(stride);
3831 state[6] = num_records;
3832 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3833 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3834 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3835 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3836
3837 if (screen->info.chip_class >= GFX10) {
3838 const struct gfx10_format *fmt = &gfx10_format_table[format];
3839
3840 /* OOB_SELECT chooses the out-of-bounds check:
3841 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3842 * - 1: index >= NUM_RECORDS
3843 * - 2: NUM_RECORDS == 0
3844 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3845 * else: swizzle_address >= NUM_RECORDS
3846 */
3847 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3848 S_008F0C_OOB_SELECT(0) |
3849 S_008F0C_RESOURCE_LEVEL(1);
3850 } else {
3851 int first_non_void;
3852 unsigned num_format, data_format;
3853
3854 first_non_void = util_format_get_first_non_void_channel(format);
3855 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3856 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3857
3858 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3859 S_008F0C_DATA_FORMAT(data_format);
3860 }
3861 }
3862
3863 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3864 {
3865 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3866
3867 if (swizzle[3] == PIPE_SWIZZLE_X) {
3868 /* For the pre-defined border color values (white, opaque
3869 * black, transparent black), the only thing that matters is
3870 * that the alpha channel winds up in the correct place
3871 * (because the RGB channels are all the same) so either of
3872 * these enumerations will work.
3873 */
3874 if (swizzle[2] == PIPE_SWIZZLE_Y)
3875 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3876 else
3877 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3878 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3879 if (swizzle[1] == PIPE_SWIZZLE_Y)
3880 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3881 else
3882 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3883 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3884 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3885 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3886 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3887 }
3888
3889 return bc_swizzle;
3890 }
3891
3892 /**
3893 * Build the sampler view descriptor for a texture.
3894 */
3895 static void
3896 gfx10_make_texture_descriptor(struct si_screen *screen,
3897 struct si_texture *tex,
3898 bool sampler,
3899 enum pipe_texture_target target,
3900 enum pipe_format pipe_format,
3901 const unsigned char state_swizzle[4],
3902 unsigned first_level, unsigned last_level,
3903 unsigned first_layer, unsigned last_layer,
3904 unsigned width, unsigned height, unsigned depth,
3905 uint32_t *state,
3906 uint32_t *fmask_state)
3907 {
3908 struct pipe_resource *res = &tex->buffer.b.b;
3909 const struct util_format_description *desc;
3910 unsigned img_format;
3911 unsigned char swizzle[4];
3912 unsigned type;
3913 uint64_t va;
3914
3915 desc = util_format_description(pipe_format);
3916 img_format = gfx10_format_table[pipe_format].img_format;
3917
3918 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3919 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3920 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3921 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3922 bool is_stencil = false;
3923
3924 switch (pipe_format) {
3925 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3926 case PIPE_FORMAT_X32_S8X24_UINT:
3927 case PIPE_FORMAT_X8Z24_UNORM:
3928 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3929 is_stencil = true;
3930 break;
3931 case PIPE_FORMAT_X24S8_UINT:
3932 /*
3933 * X24S8 is implemented as an 8_8_8_8 data format, to
3934 * fix texture gathers. This affects at least
3935 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3936 */
3937 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3938 is_stencil = true;
3939 break;
3940 default:
3941 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3942 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3943 }
3944
3945 if (tex->upgraded_depth && !is_stencil) {
3946 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3947 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3948 }
3949 } else {
3950 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3951 }
3952
3953 if (!sampler &&
3954 (res->target == PIPE_TEXTURE_CUBE ||
3955 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3956 /* For the purpose of shader images, treat cube maps as 2D
3957 * arrays.
3958 */
3959 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3960 } else {
3961 type = si_tex_dim(screen, tex, target, res->nr_samples);
3962 }
3963
3964 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3965 height = 1;
3966 depth = res->array_size;
3967 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3968 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3969 if (sampler || res->target != PIPE_TEXTURE_3D)
3970 depth = res->array_size;
3971 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3972 depth = res->array_size / 6;
3973
3974 state[0] = 0;
3975 state[1] = S_00A004_FORMAT(img_format) |
3976 S_00A004_WIDTH_LO(width - 1);
3977 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3978 S_00A008_HEIGHT(height - 1) |
3979 S_00A008_RESOURCE_LEVEL(1);
3980 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3981 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3982 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3983 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3984 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3985 0 : first_level) |
3986 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3987 util_logbase2(res->nr_samples) :
3988 last_level) |
3989 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3990 S_00A00C_TYPE(type);
3991 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3992 * to know the total number of layers.
3993 */
3994 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3995 ? depth - 1 : last_layer) |
3996 S_00A010_BASE_ARRAY(first_layer);
3997 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3998 S_00A014_MAX_MIP(res->nr_samples > 1 ?
3999 util_logbase2(res->nr_samples) :
4000 tex->buffer.b.b.last_level) |
4001 S_00A014_PERF_MOD(4);
4002 state[6] = 0;
4003 state[7] = 0;
4004
4005 if (tex->surface.dcc_offset) {
4006 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
4007 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
4008 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4009 }
4010
4011 /* Initialize the sampler view for FMASK. */
4012 if (tex->surface.fmask_offset) {
4013 uint32_t format;
4014
4015 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4016
4017 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4018 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4019 case FMASK(2,1):
4020 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4021 break;
4022 case FMASK(2,2):
4023 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4024 break;
4025 case FMASK(4,1):
4026 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4027 break;
4028 case FMASK(4,2):
4029 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4030 break;
4031 case FMASK(4,4):
4032 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4033 break;
4034 case FMASK(8,1):
4035 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4036 break;
4037 case FMASK(8,2):
4038 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4039 break;
4040 case FMASK(8,4):
4041 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4042 break;
4043 case FMASK(8,8):
4044 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4045 break;
4046 case FMASK(16,1):
4047 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4048 break;
4049 case FMASK(16,2):
4050 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4051 break;
4052 case FMASK(16,4):
4053 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4054 break;
4055 case FMASK(16,8):
4056 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4057 break;
4058 default:
4059 unreachable("invalid nr_samples");
4060 }
4061 #undef FMASK
4062 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4063 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4064 S_00A004_FORMAT(format) |
4065 S_00A004_WIDTH_LO(width - 1);
4066 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4067 S_00A008_HEIGHT(height - 1) |
4068 S_00A008_RESOURCE_LEVEL(1);
4069 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4070 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4071 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4072 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4073 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4074 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4075 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4076 S_00A010_BASE_ARRAY(first_layer);
4077 fmask_state[5] = 0;
4078 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4079 fmask_state[7] = 0;
4080 }
4081 }
4082
4083 /**
4084 * Build the sampler view descriptor for a texture (SI-GFX9).
4085 */
4086 static void
4087 si_make_texture_descriptor(struct si_screen *screen,
4088 struct si_texture *tex,
4089 bool sampler,
4090 enum pipe_texture_target target,
4091 enum pipe_format pipe_format,
4092 const unsigned char state_swizzle[4],
4093 unsigned first_level, unsigned last_level,
4094 unsigned first_layer, unsigned last_layer,
4095 unsigned width, unsigned height, unsigned depth,
4096 uint32_t *state,
4097 uint32_t *fmask_state)
4098 {
4099 struct pipe_resource *res = &tex->buffer.b.b;
4100 const struct util_format_description *desc;
4101 unsigned char swizzle[4];
4102 int first_non_void;
4103 unsigned num_format, data_format, type, num_samples;
4104 uint64_t va;
4105
4106 desc = util_format_description(pipe_format);
4107
4108 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4109 MAX2(1, res->nr_samples) :
4110 MAX2(1, res->nr_storage_samples);
4111
4112 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4113 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4114 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4115 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4116
4117 switch (pipe_format) {
4118 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4119 case PIPE_FORMAT_X32_S8X24_UINT:
4120 case PIPE_FORMAT_X8Z24_UNORM:
4121 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4122 break;
4123 case PIPE_FORMAT_X24S8_UINT:
4124 /*
4125 * X24S8 is implemented as an 8_8_8_8 data format, to
4126 * fix texture gathers. This affects at least
4127 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4128 */
4129 if (screen->info.chip_class <= GFX8)
4130 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4131 else
4132 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4133 break;
4134 default:
4135 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4136 }
4137 } else {
4138 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4139 }
4140
4141 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4142
4143 switch (pipe_format) {
4144 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4145 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4146 break;
4147 default:
4148 if (first_non_void < 0) {
4149 if (util_format_is_compressed(pipe_format)) {
4150 switch (pipe_format) {
4151 case PIPE_FORMAT_DXT1_SRGB:
4152 case PIPE_FORMAT_DXT1_SRGBA:
4153 case PIPE_FORMAT_DXT3_SRGBA:
4154 case PIPE_FORMAT_DXT5_SRGBA:
4155 case PIPE_FORMAT_BPTC_SRGBA:
4156 case PIPE_FORMAT_ETC2_SRGB8:
4157 case PIPE_FORMAT_ETC2_SRGB8A1:
4158 case PIPE_FORMAT_ETC2_SRGBA8:
4159 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4160 break;
4161 case PIPE_FORMAT_RGTC1_SNORM:
4162 case PIPE_FORMAT_LATC1_SNORM:
4163 case PIPE_FORMAT_RGTC2_SNORM:
4164 case PIPE_FORMAT_LATC2_SNORM:
4165 case PIPE_FORMAT_ETC2_R11_SNORM:
4166 case PIPE_FORMAT_ETC2_RG11_SNORM:
4167 /* implies float, so use SNORM/UNORM to determine
4168 whether data is signed or not */
4169 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4170 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4171 break;
4172 default:
4173 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4174 break;
4175 }
4176 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4177 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4178 } else {
4179 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4180 }
4181 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4182 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4183 } else {
4184 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4185
4186 switch (desc->channel[first_non_void].type) {
4187 case UTIL_FORMAT_TYPE_FLOAT:
4188 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4189 break;
4190 case UTIL_FORMAT_TYPE_SIGNED:
4191 if (desc->channel[first_non_void].normalized)
4192 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4193 else if (desc->channel[first_non_void].pure_integer)
4194 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4195 else
4196 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4197 break;
4198 case UTIL_FORMAT_TYPE_UNSIGNED:
4199 if (desc->channel[first_non_void].normalized)
4200 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4201 else if (desc->channel[first_non_void].pure_integer)
4202 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4203 else
4204 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4205 }
4206 }
4207 }
4208
4209 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4210 if (data_format == ~0) {
4211 data_format = 0;
4212 }
4213
4214 /* S8 with Z32 HTILE needs a special format. */
4215 if (screen->info.chip_class == GFX9 &&
4216 pipe_format == PIPE_FORMAT_S8_UINT &&
4217 tex->tc_compatible_htile)
4218 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4219
4220 if (!sampler &&
4221 (res->target == PIPE_TEXTURE_CUBE ||
4222 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4223 (screen->info.chip_class <= GFX8 &&
4224 res->target == PIPE_TEXTURE_3D))) {
4225 /* For the purpose of shader images, treat cube maps and 3D
4226 * textures as 2D arrays. For 3D textures, the address
4227 * calculations for mipmaps are different, so we rely on the
4228 * caller to effectively disable mipmaps.
4229 */
4230 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4231
4232 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4233 } else {
4234 type = si_tex_dim(screen, tex, target, num_samples);
4235 }
4236
4237 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4238 height = 1;
4239 depth = res->array_size;
4240 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4241 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4242 if (sampler || res->target != PIPE_TEXTURE_3D)
4243 depth = res->array_size;
4244 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4245 depth = res->array_size / 6;
4246
4247 state[0] = 0;
4248 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4249 S_008F14_NUM_FORMAT(num_format));
4250 state[2] = (S_008F18_WIDTH(width - 1) |
4251 S_008F18_HEIGHT(height - 1) |
4252 S_008F18_PERF_MOD(4));
4253 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4254 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4255 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4256 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4257 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4258 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4259 util_logbase2(num_samples) :
4260 last_level) |
4261 S_008F1C_TYPE(type));
4262 state[4] = 0;
4263 state[5] = S_008F24_BASE_ARRAY(first_layer);
4264 state[6] = 0;
4265 state[7] = 0;
4266
4267 if (screen->info.chip_class == GFX9) {
4268 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4269
4270 /* Depth is the the last accessible layer on Gfx9.
4271 * The hw doesn't need to know the total number of layers.
4272 */
4273 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4274 state[4] |= S_008F20_DEPTH(depth - 1);
4275 else
4276 state[4] |= S_008F20_DEPTH(last_layer);
4277
4278 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4279 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4280 util_logbase2(num_samples) :
4281 tex->buffer.b.b.last_level);
4282 } else {
4283 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4284 state[4] |= S_008F20_DEPTH(depth - 1);
4285 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4286 }
4287
4288 if (tex->surface.dcc_offset) {
4289 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4290 } else {
4291 /* The last dword is unused by hw. The shader uses it to clear
4292 * bits in the first dword of sampler state.
4293 */
4294 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4295 if (first_level == last_level)
4296 state[7] = C_008F30_MAX_ANISO_RATIO;
4297 else
4298 state[7] = 0xffffffff;
4299 }
4300 }
4301
4302 /* Initialize the sampler view for FMASK. */
4303 if (tex->surface.fmask_offset) {
4304 uint32_t data_format, num_format;
4305
4306 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4307
4308 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4309 if (screen->info.chip_class == GFX9) {
4310 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4311 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4312 case FMASK(2,1):
4313 num_format = V_008F14_IMG_FMASK_8_2_1;
4314 break;
4315 case FMASK(2,2):
4316 num_format = V_008F14_IMG_FMASK_8_2_2;
4317 break;
4318 case FMASK(4,1):
4319 num_format = V_008F14_IMG_FMASK_8_4_1;
4320 break;
4321 case FMASK(4,2):
4322 num_format = V_008F14_IMG_FMASK_8_4_2;
4323 break;
4324 case FMASK(4,4):
4325 num_format = V_008F14_IMG_FMASK_8_4_4;
4326 break;
4327 case FMASK(8,1):
4328 num_format = V_008F14_IMG_FMASK_8_8_1;
4329 break;
4330 case FMASK(8,2):
4331 num_format = V_008F14_IMG_FMASK_16_8_2;
4332 break;
4333 case FMASK(8,4):
4334 num_format = V_008F14_IMG_FMASK_32_8_4;
4335 break;
4336 case FMASK(8,8):
4337 num_format = V_008F14_IMG_FMASK_32_8_8;
4338 break;
4339 case FMASK(16,1):
4340 num_format = V_008F14_IMG_FMASK_16_16_1;
4341 break;
4342 case FMASK(16,2):
4343 num_format = V_008F14_IMG_FMASK_32_16_2;
4344 break;
4345 case FMASK(16,4):
4346 num_format = V_008F14_IMG_FMASK_64_16_4;
4347 break;
4348 case FMASK(16,8):
4349 num_format = V_008F14_IMG_FMASK_64_16_8;
4350 break;
4351 default:
4352 unreachable("invalid nr_samples");
4353 }
4354 } else {
4355 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4356 case FMASK(2,1):
4357 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4358 break;
4359 case FMASK(2,2):
4360 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4361 break;
4362 case FMASK(4,1):
4363 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4364 break;
4365 case FMASK(4,2):
4366 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4367 break;
4368 case FMASK(4,4):
4369 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4370 break;
4371 case FMASK(8,1):
4372 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4373 break;
4374 case FMASK(8,2):
4375 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4376 break;
4377 case FMASK(8,4):
4378 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4379 break;
4380 case FMASK(8,8):
4381 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4382 break;
4383 case FMASK(16,1):
4384 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4385 break;
4386 case FMASK(16,2):
4387 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4388 break;
4389 case FMASK(16,4):
4390 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4391 break;
4392 case FMASK(16,8):
4393 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4394 break;
4395 default:
4396 unreachable("invalid nr_samples");
4397 }
4398 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4399 }
4400 #undef FMASK
4401
4402 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4403 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4404 S_008F14_DATA_FORMAT(data_format) |
4405 S_008F14_NUM_FORMAT(num_format);
4406 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4407 S_008F18_HEIGHT(height - 1);
4408 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4409 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4410 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4411 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4412 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4413 fmask_state[4] = 0;
4414 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4415 fmask_state[6] = 0;
4416 fmask_state[7] = 0;
4417
4418 if (screen->info.chip_class == GFX9) {
4419 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4420 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4421 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4422 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4423 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4424 } else {
4425 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4426 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4427 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4428 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4429 }
4430 }
4431 }
4432
4433 /**
4434 * Create a sampler view.
4435 *
4436 * @param ctx context
4437 * @param texture texture
4438 * @param state sampler view template
4439 * @param width0 width0 override (for compressed textures as int)
4440 * @param height0 height0 override (for compressed textures as int)
4441 * @param force_level set the base address to the level (for compressed textures)
4442 */
4443 struct pipe_sampler_view *
4444 si_create_sampler_view_custom(struct pipe_context *ctx,
4445 struct pipe_resource *texture,
4446 const struct pipe_sampler_view *state,
4447 unsigned width0, unsigned height0,
4448 unsigned force_level)
4449 {
4450 struct si_context *sctx = (struct si_context*)ctx;
4451 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4452 struct si_texture *tex = (struct si_texture*)texture;
4453 unsigned base_level, first_level, last_level;
4454 unsigned char state_swizzle[4];
4455 unsigned height, depth, width;
4456 unsigned last_layer = state->u.tex.last_layer;
4457 enum pipe_format pipe_format;
4458 const struct legacy_surf_level *surflevel;
4459
4460 if (!view)
4461 return NULL;
4462
4463 /* initialize base object */
4464 view->base = *state;
4465 view->base.texture = NULL;
4466 view->base.reference.count = 1;
4467 view->base.context = ctx;
4468
4469 assert(texture);
4470 pipe_resource_reference(&view->base.texture, texture);
4471
4472 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4473 state->format == PIPE_FORMAT_S8X24_UINT ||
4474 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4475 state->format == PIPE_FORMAT_S8_UINT)
4476 view->is_stencil_sampler = true;
4477
4478 /* Buffer resource. */
4479 if (texture->target == PIPE_BUFFER) {
4480 si_make_buffer_descriptor(sctx->screen,
4481 si_resource(texture),
4482 state->format,
4483 state->u.buf.offset,
4484 state->u.buf.size,
4485 view->state);
4486 return &view->base;
4487 }
4488
4489 state_swizzle[0] = state->swizzle_r;
4490 state_swizzle[1] = state->swizzle_g;
4491 state_swizzle[2] = state->swizzle_b;
4492 state_swizzle[3] = state->swizzle_a;
4493
4494 base_level = 0;
4495 first_level = state->u.tex.first_level;
4496 last_level = state->u.tex.last_level;
4497 width = width0;
4498 height = height0;
4499 depth = texture->depth0;
4500
4501 if (sctx->chip_class <= GFX8 && force_level) {
4502 assert(force_level == first_level &&
4503 force_level == last_level);
4504 base_level = force_level;
4505 first_level = 0;
4506 last_level = 0;
4507 width = u_minify(width, force_level);
4508 height = u_minify(height, force_level);
4509 depth = u_minify(depth, force_level);
4510 }
4511
4512 /* This is not needed if state trackers set last_layer correctly. */
4513 if (state->target == PIPE_TEXTURE_1D ||
4514 state->target == PIPE_TEXTURE_2D ||
4515 state->target == PIPE_TEXTURE_RECT ||
4516 state->target == PIPE_TEXTURE_CUBE)
4517 last_layer = state->u.tex.first_layer;
4518
4519 /* Texturing with separate depth and stencil. */
4520 pipe_format = state->format;
4521
4522 /* Depth/stencil texturing sometimes needs separate texture. */
4523 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4524 if (!tex->flushed_depth_texture &&
4525 !si_init_flushed_depth_texture(ctx, texture)) {
4526 pipe_resource_reference(&view->base.texture, NULL);
4527 FREE(view);
4528 return NULL;
4529 }
4530
4531 assert(tex->flushed_depth_texture);
4532
4533 /* Override format for the case where the flushed texture
4534 * contains only Z or only S.
4535 */
4536 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4537 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4538
4539 tex = tex->flushed_depth_texture;
4540 }
4541
4542 surflevel = tex->surface.u.legacy.level;
4543
4544 if (tex->db_compatible) {
4545 if (!view->is_stencil_sampler)
4546 pipe_format = tex->db_render_format;
4547
4548 switch (pipe_format) {
4549 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4550 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4551 break;
4552 case PIPE_FORMAT_X8Z24_UNORM:
4553 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4554 /* Z24 is always stored like this for DB
4555 * compatibility.
4556 */
4557 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4558 break;
4559 case PIPE_FORMAT_X24S8_UINT:
4560 case PIPE_FORMAT_S8X24_UINT:
4561 case PIPE_FORMAT_X32_S8X24_UINT:
4562 pipe_format = PIPE_FORMAT_S8_UINT;
4563 surflevel = tex->surface.u.legacy.stencil_level;
4564 break;
4565 default:;
4566 }
4567 }
4568
4569 view->dcc_incompatible =
4570 vi_dcc_formats_are_incompatible(texture,
4571 state->u.tex.first_level,
4572 state->format);
4573
4574 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4575 state->target, pipe_format, state_swizzle,
4576 first_level, last_level,
4577 state->u.tex.first_layer, last_layer,
4578 width, height, depth,
4579 view->state, view->fmask_state);
4580
4581 const struct util_format_description *desc = util_format_description(pipe_format);
4582 view->is_integer = false;
4583
4584 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4585 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4586 continue;
4587
4588 /* Whether the number format is {U,S}{SCALED,INT} */
4589 view->is_integer =
4590 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4591 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4592 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4593 break;
4594 }
4595
4596 view->base_level_info = &surflevel[base_level];
4597 view->base_level = base_level;
4598 view->block_width = util_format_get_blockwidth(pipe_format);
4599 return &view->base;
4600 }
4601
4602 static struct pipe_sampler_view *
4603 si_create_sampler_view(struct pipe_context *ctx,
4604 struct pipe_resource *texture,
4605 const struct pipe_sampler_view *state)
4606 {
4607 return si_create_sampler_view_custom(ctx, texture, state,
4608 texture ? texture->width0 : 0,
4609 texture ? texture->height0 : 0, 0);
4610 }
4611
4612 static void si_sampler_view_destroy(struct pipe_context *ctx,
4613 struct pipe_sampler_view *state)
4614 {
4615 struct si_sampler_view *view = (struct si_sampler_view *)state;
4616
4617 pipe_resource_reference(&state->texture, NULL);
4618 FREE(view);
4619 }
4620
4621 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4622 {
4623 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4624 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4625 (linear_filter &&
4626 (wrap == PIPE_TEX_WRAP_CLAMP ||
4627 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4628 }
4629
4630 static uint32_t si_translate_border_color(struct si_context *sctx,
4631 const struct pipe_sampler_state *state,
4632 const union pipe_color_union *color,
4633 bool is_integer)
4634 {
4635 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4636 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4637
4638 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4639 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4640 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4641 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4642
4643 #define simple_border_types(elt) \
4644 do { \
4645 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4646 color->elt[2] == 0 && color->elt[3] == 0) \
4647 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4648 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4649 color->elt[2] == 0 && color->elt[3] == 1) \
4650 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4651 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4652 color->elt[2] == 1 && color->elt[3] == 1) \
4653 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4654 } while (false)
4655
4656 if (is_integer)
4657 simple_border_types(ui);
4658 else
4659 simple_border_types(f);
4660
4661 #undef simple_border_types
4662
4663 int i;
4664
4665 /* Check if the border has been uploaded already. */
4666 for (i = 0; i < sctx->border_color_count; i++)
4667 if (memcmp(&sctx->border_color_table[i], color,
4668 sizeof(*color)) == 0)
4669 break;
4670
4671 if (i >= SI_MAX_BORDER_COLORS) {
4672 /* Getting 4096 unique border colors is very unlikely. */
4673 fprintf(stderr, "radeonsi: The border color table is full. "
4674 "Any new border colors will be just black. "
4675 "Please file a bug.\n");
4676 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4677 }
4678
4679 if (i == sctx->border_color_count) {
4680 /* Upload a new border color. */
4681 memcpy(&sctx->border_color_table[i], color,
4682 sizeof(*color));
4683 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4684 color, sizeof(*color));
4685 sctx->border_color_count++;
4686 }
4687
4688 return S_008F3C_BORDER_COLOR_PTR(i) |
4689 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4690 }
4691
4692 static inline int S_FIXED(float value, unsigned frac_bits)
4693 {
4694 return value * (1 << frac_bits);
4695 }
4696
4697 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4698 {
4699 if (filter == PIPE_TEX_FILTER_LINEAR)
4700 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4701 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4702 else
4703 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4704 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4705 }
4706
4707 static inline unsigned si_tex_aniso_filter(unsigned filter)
4708 {
4709 if (filter < 2)
4710 return 0;
4711 if (filter < 4)
4712 return 1;
4713 if (filter < 8)
4714 return 2;
4715 if (filter < 16)
4716 return 3;
4717 return 4;
4718 }
4719
4720 static void *si_create_sampler_state(struct pipe_context *ctx,
4721 const struct pipe_sampler_state *state)
4722 {
4723 struct si_context *sctx = (struct si_context *)ctx;
4724 struct si_screen *sscreen = sctx->screen;
4725 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4726 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4727 : state->max_anisotropy;
4728 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4729 union pipe_color_union clamped_border_color;
4730
4731 if (!rstate) {
4732 return NULL;
4733 }
4734
4735 #ifndef NDEBUG
4736 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4737 #endif
4738 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4739 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4740 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4741 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4742 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4743 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4744 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4745 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4746 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4747 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4748 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4749 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4750 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4751 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4752 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4753 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4754 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4755 S_008F38_MIP_POINT_PRECLAMP(0));
4756 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4757
4758 if (sscreen->info.chip_class >= GFX10) {
4759 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4760 } else {
4761 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4762 S_008F38_FILTER_PREC_FIX(1) |
4763 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4764 }
4765
4766 /* Create sampler resource for integer textures. */
4767 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4768 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4769
4770 /* Create sampler resource for upgraded depth textures. */
4771 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4772
4773 for (unsigned i = 0; i < 4; ++i) {
4774 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4775 * when the border color is 1.0. */
4776 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4777 }
4778
4779 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4780 if (sscreen->info.chip_class <= GFX9)
4781 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4782 } else {
4783 rstate->upgraded_depth_val[3] =
4784 si_translate_border_color(sctx, state, &clamped_border_color, false);
4785 }
4786
4787 return rstate;
4788 }
4789
4790 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4791 {
4792 struct si_context *sctx = (struct si_context *)ctx;
4793
4794 if (sctx->sample_mask == (uint16_t)sample_mask)
4795 return;
4796
4797 sctx->sample_mask = sample_mask;
4798 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4799 }
4800
4801 static void si_emit_sample_mask(struct si_context *sctx)
4802 {
4803 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4804 unsigned mask = sctx->sample_mask;
4805
4806 /* Needed for line and polygon smoothing as well as for the Polaris
4807 * small primitive filter. We expect the state tracker to take care of
4808 * this for us.
4809 */
4810 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4811 (mask & 1 && sctx->blitter->running));
4812
4813 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4814 radeon_emit(cs, mask | (mask << 16));
4815 radeon_emit(cs, mask | (mask << 16));
4816 }
4817
4818 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4819 {
4820 #ifndef NDEBUG
4821 struct si_sampler_state *s = state;
4822
4823 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4824 s->magic = 0;
4825 #endif
4826 free(state);
4827 }
4828
4829 /*
4830 * Vertex elements & buffers
4831 */
4832
4833 struct si_fast_udiv_info32
4834 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4835 {
4836 struct util_fast_udiv_info info =
4837 util_compute_fast_udiv_info(D, num_bits, 32);
4838
4839 struct si_fast_udiv_info32 result = {
4840 info.multiplier,
4841 info.pre_shift,
4842 info.post_shift,
4843 info.increment,
4844 };
4845 return result;
4846 }
4847
4848 static void *si_create_vertex_elements(struct pipe_context *ctx,
4849 unsigned count,
4850 const struct pipe_vertex_element *elements)
4851 {
4852 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4853 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4854 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4855 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4856 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4857 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4858 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4859 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4860 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4861 int i;
4862
4863 assert(count <= SI_MAX_ATTRIBS);
4864 if (!v)
4865 return NULL;
4866
4867 v->count = count;
4868 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4869
4870 for (i = 0; i < count; ++i) {
4871 const struct util_format_description *desc;
4872 const struct util_format_channel_description *channel;
4873 int first_non_void;
4874 unsigned vbo_index = elements[i].vertex_buffer_index;
4875
4876 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4877 FREE(v);
4878 return NULL;
4879 }
4880
4881 unsigned instance_divisor = elements[i].instance_divisor;
4882 if (instance_divisor) {
4883 v->uses_instance_divisors = true;
4884
4885 if (instance_divisor == 1) {
4886 v->instance_divisor_is_one |= 1u << i;
4887 } else {
4888 v->instance_divisor_is_fetched |= 1u << i;
4889 divisor_factors[i] =
4890 si_compute_fast_udiv_info32(instance_divisor, 32);
4891 }
4892 }
4893
4894 if (!used[vbo_index]) {
4895 v->first_vb_use_mask |= 1 << i;
4896 used[vbo_index] = true;
4897 }
4898
4899 desc = util_format_description(elements[i].src_format);
4900 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4901 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4902
4903 v->format_size[i] = desc->block.bits / 8;
4904 v->src_offset[i] = elements[i].src_offset;
4905 v->vertex_buffer_index[i] = vbo_index;
4906
4907 bool always_fix = false;
4908 union si_vs_fix_fetch fix_fetch;
4909 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4910
4911 fix_fetch.bits = 0;
4912 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4913
4914 if (channel) {
4915 switch (channel->type) {
4916 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4917 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4918 case UTIL_FORMAT_TYPE_SIGNED: {
4919 if (channel->pure_integer)
4920 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4921 else if (channel->normalized)
4922 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4923 else
4924 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4925 break;
4926 }
4927 case UTIL_FORMAT_TYPE_UNSIGNED: {
4928 if (channel->pure_integer)
4929 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4930 else if (channel->normalized)
4931 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4932 else
4933 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4934 break;
4935 }
4936 default: unreachable("bad format type");
4937 }
4938 } else {
4939 switch (elements[i].src_format) {
4940 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4941 default: unreachable("bad other format");
4942 }
4943 }
4944
4945 if (desc->channel[0].size == 10) {
4946 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4947 log_hw_load_size = 2;
4948
4949 /* The hardware always treats the 2-bit alpha channel as
4950 * unsigned, so a shader workaround is needed. The affected
4951 * chips are GFX8 and older except Stoney (GFX8.1).
4952 */
4953 always_fix = sscreen->info.chip_class <= GFX8 &&
4954 sscreen->info.family != CHIP_STONEY &&
4955 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4956 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4957 fix_fetch.u.log_size = 3; /* special encoding */
4958 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4959 log_hw_load_size = 2;
4960 } else {
4961 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4962 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4963
4964 /* Always fix up:
4965 * - doubles (multiple loads + truncate to float)
4966 * - 32-bit requiring a conversion
4967 */
4968 always_fix =
4969 (fix_fetch.u.log_size == 3) ||
4970 (fix_fetch.u.log_size == 2 &&
4971 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4972 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4973 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4974
4975 /* Also fixup 8_8_8 and 16_16_16. */
4976 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4977 always_fix = true;
4978 log_hw_load_size = fix_fetch.u.log_size;
4979 }
4980 }
4981
4982 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4983 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4984 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4985 fix_fetch.u.reverse = 1;
4986 }
4987
4988 /* Force the workaround for unaligned access here already if the
4989 * offset relative to the vertex buffer base is unaligned.
4990 *
4991 * There is a theoretical case in which this is too conservative:
4992 * if the vertex buffer's offset is also unaligned in just the
4993 * right way, we end up with an aligned address after all.
4994 * However, this case should be extremely rare in practice (it
4995 * won't happen in well-behaved applications), and taking it
4996 * into account would complicate the fast path (where everything
4997 * is nicely aligned).
4998 */
4999 bool check_alignment =
5000 log_hw_load_size >= 1 &&
5001 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
5002 bool opencode = sscreen->options.vs_fetch_always_opencode;
5003
5004 if (check_alignment &&
5005 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
5006 opencode = true;
5007
5008 if (always_fix || check_alignment || opencode)
5009 v->fix_fetch[i] = fix_fetch.bits;
5010
5011 if (opencode)
5012 v->fix_fetch_opencode |= 1 << i;
5013 if (opencode || always_fix)
5014 v->fix_fetch_always |= 1 << i;
5015
5016 if (check_alignment && !opencode) {
5017 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5018
5019 v->fix_fetch_unaligned |= 1 << i;
5020 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5021 v->vb_alignment_check_mask |= 1 << vbo_index;
5022 }
5023
5024 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5025 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5026 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5027 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5028
5029 if (sscreen->info.chip_class >= GFX10) {
5030 const struct gfx10_format *fmt =
5031 &gfx10_format_table[elements[i].src_format];
5032 assert(fmt->img_format != 0 && fmt->img_format < 128);
5033 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5034 S_008F0C_RESOURCE_LEVEL(1);
5035 } else {
5036 unsigned data_format, num_format;
5037 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5038 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5039 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5040 S_008F0C_DATA_FORMAT(data_format);
5041 }
5042 }
5043
5044 if (v->instance_divisor_is_fetched) {
5045 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5046
5047 v->instance_divisor_factor_buffer =
5048 (struct si_resource*)
5049 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5050 num_divisors * sizeof(divisor_factors[0]));
5051 if (!v->instance_divisor_factor_buffer) {
5052 FREE(v);
5053 return NULL;
5054 }
5055 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5056 NULL, PIPE_TRANSFER_WRITE);
5057 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5058 }
5059 return v;
5060 }
5061
5062 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5063 {
5064 struct si_context *sctx = (struct si_context *)ctx;
5065 struct si_vertex_elements *old = sctx->vertex_elements;
5066 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5067
5068 sctx->vertex_elements = v;
5069 sctx->vertex_buffers_dirty = true;
5070
5071 if (v &&
5072 (!old ||
5073 old->count != v->count ||
5074 old->uses_instance_divisors != v->uses_instance_divisors ||
5075 /* we don't check which divisors changed */
5076 v->uses_instance_divisors ||
5077 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5078 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5079 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5080 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5081 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5082 * functions of fix_fetch and the src_offset alignment.
5083 * If they change and fix_fetch doesn't, it must be due to different
5084 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5085 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5086 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5087 sctx->do_update_shaders = true;
5088
5089 if (v && v->instance_divisor_is_fetched) {
5090 struct pipe_constant_buffer cb;
5091
5092 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5093 cb.user_buffer = NULL;
5094 cb.buffer_offset = 0;
5095 cb.buffer_size = 0xffffffff;
5096 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5097 }
5098 }
5099
5100 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5101 {
5102 struct si_context *sctx = (struct si_context *)ctx;
5103 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5104
5105 if (sctx->vertex_elements == state)
5106 sctx->vertex_elements = NULL;
5107 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5108 FREE(state);
5109 }
5110
5111 static void si_set_vertex_buffers(struct pipe_context *ctx,
5112 unsigned start_slot, unsigned count,
5113 const struct pipe_vertex_buffer *buffers)
5114 {
5115 struct si_context *sctx = (struct si_context *)ctx;
5116 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5117 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5118 uint32_t unaligned = orig_unaligned;
5119 int i;
5120
5121 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5122
5123 if (buffers) {
5124 for (i = 0; i < count; i++) {
5125 const struct pipe_vertex_buffer *src = buffers + i;
5126 struct pipe_vertex_buffer *dsti = dst + i;
5127 struct pipe_resource *buf = src->buffer.resource;
5128
5129 pipe_resource_reference(&dsti->buffer.resource, buf);
5130 dsti->buffer_offset = src->buffer_offset;
5131 dsti->stride = src->stride;
5132 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5133 unaligned |= 1 << (start_slot + i);
5134 else
5135 unaligned &= ~(1 << (start_slot + i));
5136
5137 si_context_add_resource_size(sctx, buf);
5138 if (buf)
5139 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5140 }
5141 } else {
5142 for (i = 0; i < count; i++) {
5143 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5144 }
5145 unaligned &= ~u_bit_consecutive(start_slot, count);
5146 }
5147 sctx->vertex_buffers_dirty = true;
5148 sctx->vertex_buffer_unaligned = unaligned;
5149
5150 /* Check whether alignment may have changed in a way that requires
5151 * shader changes. This check is conservative: a vertex buffer can only
5152 * trigger a shader change if the misalignment amount changes (e.g.
5153 * from byte-aligned to short-aligned), but we only keep track of
5154 * whether buffers are at least dword-aligned, since that should always
5155 * be the case in well-behaved applications anyway.
5156 */
5157 if (sctx->vertex_elements &&
5158 (sctx->vertex_elements->vb_alignment_check_mask &
5159 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5160 sctx->do_update_shaders = true;
5161 }
5162
5163 /*
5164 * Misc
5165 */
5166
5167 static void si_set_tess_state(struct pipe_context *ctx,
5168 const float default_outer_level[4],
5169 const float default_inner_level[2])
5170 {
5171 struct si_context *sctx = (struct si_context *)ctx;
5172 struct pipe_constant_buffer cb;
5173 float array[8];
5174
5175 memcpy(array, default_outer_level, sizeof(float) * 4);
5176 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5177
5178 cb.buffer = NULL;
5179 cb.user_buffer = NULL;
5180 cb.buffer_size = sizeof(array);
5181
5182 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5183 (void*)array, sizeof(array),
5184 &cb.buffer_offset);
5185
5186 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5187 pipe_resource_reference(&cb.buffer, NULL);
5188 }
5189
5190 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5191 {
5192 struct si_context *sctx = (struct si_context *)ctx;
5193
5194 si_update_fb_dirtiness_after_rendering(sctx);
5195
5196 /* Multisample surfaces are flushed in si_decompress_textures. */
5197 if (sctx->framebuffer.uncompressed_cb_mask) {
5198 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5199 sctx->framebuffer.CB_has_shader_readable_metadata,
5200 sctx->framebuffer.all_DCC_pipe_aligned);
5201 }
5202 }
5203
5204 /* This only ensures coherency for shader image/buffer stores. */
5205 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5206 {
5207 struct si_context *sctx = (struct si_context *)ctx;
5208
5209 if (!(flags & ~PIPE_BARRIER_UPDATE))
5210 return;
5211
5212 /* Subsequent commands must wait for all shader invocations to
5213 * complete. */
5214 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5215 SI_CONTEXT_CS_PARTIAL_FLUSH;
5216
5217 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5218 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5219 SI_CONTEXT_INV_VCACHE;
5220
5221 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5222 PIPE_BARRIER_SHADER_BUFFER |
5223 PIPE_BARRIER_TEXTURE |
5224 PIPE_BARRIER_IMAGE |
5225 PIPE_BARRIER_STREAMOUT_BUFFER |
5226 PIPE_BARRIER_GLOBAL_BUFFER)) {
5227 /* As far as I can tell, L1 contents are written back to L2
5228 * automatically at end of shader, but the contents of other
5229 * L1 caches might still be stale. */
5230 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5231 }
5232
5233 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5234 /* Indices are read through TC L2 since GFX8.
5235 * L1 isn't used.
5236 */
5237 if (sctx->screen->info.chip_class <= GFX7)
5238 sctx->flags |= SI_CONTEXT_WB_L2;
5239 }
5240
5241 /* MSAA color, any depth and any stencil are flushed in
5242 * si_decompress_textures when needed.
5243 */
5244 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5245 sctx->framebuffer.uncompressed_cb_mask) {
5246 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5247
5248 if (sctx->chip_class <= GFX8)
5249 sctx->flags |= SI_CONTEXT_WB_L2;
5250 }
5251
5252 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5253 if (sctx->screen->info.chip_class <= GFX8 &&
5254 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5255 sctx->flags |= SI_CONTEXT_WB_L2;
5256 }
5257
5258 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5259 {
5260 struct pipe_blend_state blend;
5261
5262 memset(&blend, 0, sizeof(blend));
5263 blend.independent_blend_enable = true;
5264 blend.rt[0].colormask = 0xf;
5265 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5266 }
5267
5268 static void si_init_config(struct si_context *sctx);
5269
5270 void si_init_state_compute_functions(struct si_context *sctx)
5271 {
5272 sctx->b.create_sampler_state = si_create_sampler_state;
5273 sctx->b.delete_sampler_state = si_delete_sampler_state;
5274 sctx->b.create_sampler_view = si_create_sampler_view;
5275 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5276 sctx->b.memory_barrier = si_memory_barrier;
5277 }
5278
5279 void si_init_state_functions(struct si_context *sctx)
5280 {
5281 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5282 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5283 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5284 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5285 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5286 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5287 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5288 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5289 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5290 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5291 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5292
5293 sctx->b.create_blend_state = si_create_blend_state;
5294 sctx->b.bind_blend_state = si_bind_blend_state;
5295 sctx->b.delete_blend_state = si_delete_blend_state;
5296 sctx->b.set_blend_color = si_set_blend_color;
5297
5298 sctx->b.create_rasterizer_state = si_create_rs_state;
5299 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5300 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5301
5302 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5303 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5304 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5305
5306 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5307 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5308 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5309 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5310 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5311
5312 sctx->b.set_clip_state = si_set_clip_state;
5313 sctx->b.set_stencil_ref = si_set_stencil_ref;
5314
5315 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5316
5317 sctx->b.set_sample_mask = si_set_sample_mask;
5318
5319 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5320 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5321 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5322 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5323
5324 sctx->b.texture_barrier = si_texture_barrier;
5325 sctx->b.set_min_samples = si_set_min_samples;
5326 sctx->b.set_tess_state = si_set_tess_state;
5327
5328 sctx->b.set_active_query_state = si_set_active_query_state;
5329
5330 si_init_config(sctx);
5331 }
5332
5333 void si_init_screen_state_functions(struct si_screen *sscreen)
5334 {
5335 sscreen->b.is_format_supported = si_is_format_supported;
5336
5337 if (sscreen->info.chip_class >= GFX10) {
5338 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5339 } else {
5340 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5341 }
5342 }
5343
5344 static void si_set_grbm_gfx_index(struct si_context *sctx,
5345 struct si_pm4_state *pm4, unsigned value)
5346 {
5347 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5348 R_00802C_GRBM_GFX_INDEX;
5349 si_pm4_set_reg(pm4, reg, value);
5350 }
5351
5352 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5353 struct si_pm4_state *pm4, unsigned se)
5354 {
5355 assert(se == ~0 || se < sctx->screen->info.max_se);
5356 si_set_grbm_gfx_index(sctx, pm4,
5357 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5358 S_030800_SE_INDEX(se)) |
5359 S_030800_SH_BROADCAST_WRITES(1) |
5360 S_030800_INSTANCE_BROADCAST_WRITES(1));
5361 }
5362
5363 static void
5364 si_write_harvested_raster_configs(struct si_context *sctx,
5365 struct si_pm4_state *pm4,
5366 unsigned raster_config,
5367 unsigned raster_config_1)
5368 {
5369 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5370 unsigned raster_config_se[4];
5371 unsigned se;
5372
5373 ac_get_harvested_configs(&sctx->screen->info,
5374 raster_config,
5375 &raster_config_1,
5376 raster_config_se);
5377
5378 for (se = 0; se < num_se; se++) {
5379 si_set_grbm_gfx_index_se(sctx, pm4, se);
5380 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5381 }
5382 si_set_grbm_gfx_index(sctx, pm4, ~0);
5383
5384 if (sctx->chip_class >= GFX7) {
5385 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5386 }
5387 }
5388
5389 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5390 {
5391 struct si_screen *sscreen = sctx->screen;
5392 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5393 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5394 unsigned raster_config = sscreen->pa_sc_raster_config;
5395 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5396
5397 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5398 /* Always use the default config when all backends are enabled
5399 * (or when we failed to determine the enabled backends).
5400 */
5401 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5402 raster_config);
5403 if (sctx->chip_class >= GFX7)
5404 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5405 raster_config_1);
5406 } else {
5407 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5408 }
5409 }
5410
5411 static void si_init_config(struct si_context *sctx)
5412 {
5413 struct si_screen *sscreen = sctx->screen;
5414 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5415 bool has_clear_state = sscreen->info.has_clear_state;
5416 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5417
5418 if (!pm4)
5419 return;
5420
5421 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5422 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5423 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5424 si_pm4_cmd_end(pm4, false);
5425
5426 if (has_clear_state) {
5427 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5428 si_pm4_cmd_add(pm4, 0);
5429 si_pm4_cmd_end(pm4, false);
5430 }
5431
5432 if (sctx->chip_class <= GFX8)
5433 si_set_raster_config(sctx, pm4);
5434
5435 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5436 if (!has_clear_state)
5437 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5438
5439 /* FIXME calculate these values somehow ??? */
5440 if (sctx->chip_class <= GFX8) {
5441 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5442 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5443 }
5444
5445 if (!has_clear_state) {
5446 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5447 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5448 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5449 }
5450
5451 if (sscreen->info.chip_class <= GFX9)
5452 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5453 if (!has_clear_state)
5454 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5455 if (sctx->chip_class < GFX7)
5456 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5457 S_008A14_CLIP_VTX_REORDER_ENA(1));
5458
5459 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5460 * I don't know why. Deduced by trial and error.
5461 */
5462 if (sctx->chip_class <= GFX7 || !has_clear_state) {
5463 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5464 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5465 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5466 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5467 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5468 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5469 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5470 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5471 }
5472
5473 if (!has_clear_state) {
5474 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5475 S_028230_ER_TRI(0xA) |
5476 S_028230_ER_POINT(0xA) |
5477 S_028230_ER_RECT(0xA) |
5478 /* Required by DX10_DIAMOND_TEST_ENA: */
5479 S_028230_ER_LINE_LR(0x1A) |
5480 S_028230_ER_LINE_RL(0x26) |
5481 S_028230_ER_LINE_TB(0xA) |
5482 S_028230_ER_LINE_BT(0xA));
5483 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5484 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5485 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5486 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5487 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5488 }
5489
5490 if (sctx->chip_class >= GFX10) {
5491 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5492 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5493 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5494 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5495 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5496 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5497 } else if (sctx->chip_class == GFX9) {
5498 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5499 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5500 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5501 } else {
5502 /* These registers, when written, also overwrite the CLEAR_STATE
5503 * context, so we can't rely on CLEAR_STATE setting them.
5504 * It would be an issue if there was another UMD changing them.
5505 */
5506 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5507 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5508 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5509 }
5510
5511 if (sctx->chip_class >= GFX7) {
5512 if (sctx->chip_class >= GFX10) {
5513 /* Logical CUs 16 - 31 */
5514 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5515 S_00B404_CU_EN(0xffff));
5516 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5517 S_00B104_CU_EN(0xffff));
5518 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5519 S_00B004_CU_EN(0xffff));
5520 }
5521
5522 if (sctx->chip_class >= GFX9) {
5523 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5524 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5525 } else {
5526 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5527 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5528 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5529 S_00B41C_WAVE_LIMIT(0x3F));
5530 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5531 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5532
5533 /* If this is 0, Bonaire can hang even if GS isn't being used.
5534 * Other chips are unaffected. These are suboptimal values,
5535 * but we don't use on-chip GS.
5536 */
5537 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5538 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5539 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5540 }
5541
5542 /* Compute LATE_ALLOC_VS.LIMIT. */
5543 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5544 unsigned late_alloc_limit; /* The limit is per SH. */
5545
5546 if (sctx->family == CHIP_KABINI) {
5547 late_alloc_limit = 0; /* Potential hang on Kabini. */
5548 } else if (num_cu_per_sh <= 4) {
5549 /* Too few available compute units per SH. Disallowing
5550 * VS to run on one CU could hurt us more than late VS
5551 * allocation would help.
5552 *
5553 * 2 is the highest safe number that allows us to keep
5554 * all CUs enabled.
5555 */
5556 late_alloc_limit = 2;
5557 } else {
5558 /* This is a good initial value, allowing 1 late_alloc
5559 * wave per SIMD on num_cu - 2.
5560 */
5561 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5562 }
5563
5564 unsigned late_alloc_limit_gs = late_alloc_limit;
5565 unsigned cu_mask_vs = 0xffff;
5566 unsigned cu_mask_gs = 0xffff;
5567
5568 if (late_alloc_limit > 2) {
5569 if (sctx->chip_class >= GFX10) {
5570 /* CU2 & CU3 disabled because of the dual CU design */
5571 cu_mask_vs = 0xfff3;
5572 cu_mask_gs = 0xfff3; /* NGG only */
5573 } else {
5574 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5575 }
5576 }
5577
5578 /* Don't use late alloc for NGG on Navi14 due to a hw bug.
5579 * If NGG is never used, enable all CUs.
5580 */
5581 if (!sscreen->use_ngg || sctx->family == CHIP_NAVI14) {
5582 late_alloc_limit_gs = 0;
5583 cu_mask_gs = 0xffff;
5584 }
5585
5586 /* VS can't execute on one CU if the limit is > 2. */
5587 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5588 S_00B118_CU_EN(cu_mask_vs) |
5589 S_00B118_WAVE_LIMIT(0x3F));
5590 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5591 S_00B11C_LIMIT(late_alloc_limit));
5592
5593 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5594 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5595
5596 if (sctx->chip_class >= GFX10) {
5597 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5598 S_00B204_CU_EN(0xffff) |
5599 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
5600 }
5601
5602 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5603 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5604 }
5605
5606 if (sctx->chip_class >= GFX10) {
5607 /* Break up a pixel wave if it contains deallocs for more than
5608 * half the parameter cache.
5609 *
5610 * To avoid a deadlock where pixel waves aren't launched
5611 * because they're waiting for more pixels while the frontend
5612 * is stuck waiting for PC space, the maximum allowed value is
5613 * the size of the PC minus the largest possible allocation for
5614 * a single primitive shader subgroup.
5615 */
5616 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5617 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5618 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5619
5620 if (!has_clear_state) {
5621 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5622 sscreen->info.pa_sc_tile_steering_override);
5623 }
5624
5625 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5626 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5627 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5628 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5629 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5630 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5631 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5632 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
5633
5634 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5635 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5636 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5637 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5638 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5639 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5640 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5641 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
5642 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5643 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5644
5645 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5646 S_00B0C0_SOFT_GROUPING_EN(1) |
5647 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5648 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5649
5650 if (sctx->family == CHIP_NAVI10 ||
5651 sctx->family == CHIP_NAVI12 ||
5652 sctx->family == CHIP_NAVI14) {
5653 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
5654 si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
5655 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
5656 si_pm4_cmd_end(pm4, false);
5657 }
5658 /* TODO: For culling, replace 128 with 256. */
5659 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
5660 S_030980_OVERSUB_EN(1) |
5661 S_030980_NUM_PC_LINES(128 * sscreen->info.max_se - 1));
5662 }
5663
5664 if (sctx->chip_class >= GFX8) {
5665 unsigned vgt_tess_distribution;
5666
5667 vgt_tess_distribution =
5668 S_028B50_ACCUM_ISOLINE(32) |
5669 S_028B50_ACCUM_TRI(11) |
5670 S_028B50_ACCUM_QUAD(11) |
5671 S_028B50_DONUT_SPLIT(16);
5672
5673 /* Testing with Unigine Heaven extreme tesselation yielded best results
5674 * with TRAP_SPLIT = 3.
5675 */
5676 if (sctx->family == CHIP_FIJI ||
5677 sctx->family >= CHIP_POLARIS10)
5678 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5679
5680 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5681 } else if (!has_clear_state) {
5682 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5683 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5684 }
5685
5686 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5687 if (sctx->chip_class >= GFX7) {
5688 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5689 S_028084_ADDRESS(border_color_va >> 40));
5690 }
5691 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5692 RADEON_PRIO_BORDER_COLORS);
5693
5694 if (sctx->chip_class >= GFX9) {
5695 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5696 S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
5697 S_028C48_MAX_PRIM_PER_BATCH(1023));
5698 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5699 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5700 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5701 }
5702
5703 si_pm4_upload_indirect_buffer(sctx, pm4);
5704 sctx->init_config = pm4;
5705 }