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radeonsi: move some inline functions from si_pipe.h to si_state.c
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "si_pipe.h"
38 #include "si_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split)
44 {
45 if (sscreen->b.info.cik_macrotile_mode_array_valid) {
46 unsigned index, tileb;
47
48 tileb = 8 * 8 * bpe;
49 tileb = MIN2(tile_split, tileb);
50
51 for (index = 0; tileb > 64; index++) {
52 tileb >>= 1;
53 }
54
55 assert(index < 16);
56
57 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
58 }
59
60 /* The old way. */
61 switch (sscreen->b.tiling_info.num_banks) {
62 case 2:
63 return V_02803C_ADDR_SURF_2_BANK;
64 case 4:
65 return V_02803C_ADDR_SURF_4_BANK;
66 case 8:
67 default:
68 return V_02803C_ADDR_SURF_8_BANK;
69 case 16:
70 return V_02803C_ADDR_SURF_16_BANK;
71 }
72 }
73
74 static unsigned cik_tile_split(unsigned tile_split)
75 {
76 switch (tile_split) {
77 case 64:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
79 break;
80 case 128:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
82 break;
83 case 256:
84 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
85 break;
86 case 512:
87 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
88 break;
89 default:
90 case 1024:
91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
92 break;
93 case 2048:
94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
95 break;
96 case 4096:
97 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
98 break;
99 }
100 return tile_split;
101 }
102
103 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
104 {
105 switch (macro_tile_aspect) {
106 default:
107 case 1:
108 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
109 break;
110 case 2:
111 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
112 break;
113 case 4:
114 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
115 break;
116 case 8:
117 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
118 break;
119 }
120 return macro_tile_aspect;
121 }
122
123 static unsigned cik_bank_wh(unsigned bankwh)
124 {
125 switch (bankwh) {
126 default:
127 case 1:
128 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
129 break;
130 case 2:
131 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
132 break;
133 case 4:
134 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
135 break;
136 case 8:
137 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
138 break;
139 }
140 return bankwh;
141 }
142
143 static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
144 {
145 if (sscreen->b.info.si_tile_mode_array_valid) {
146 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
147
148 return G_009910_PIPE_CONFIG(gb_tile_mode);
149 }
150
151 /* This is probably broken for a lot of chips, but it's only used
152 * if the kernel cannot return the tile mode array for CIK. */
153 switch (sscreen->b.info.r600_num_tile_pipes) {
154 case 16:
155 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
156 case 8:
157 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
158 case 4:
159 default:
160 if (sscreen->b.info.r600_num_backends == 4)
161 return V_02803C_X_ADDR_SURF_P4_16X16;
162 else
163 return V_02803C_X_ADDR_SURF_P4_8X16;
164 case 2:
165 return V_02803C_ADDR_SURF_P2;
166 }
167 }
168
169 static unsigned si_map_swizzle(unsigned swizzle)
170 {
171 switch (swizzle) {
172 case UTIL_FORMAT_SWIZZLE_Y:
173 return V_008F0C_SQ_SEL_Y;
174 case UTIL_FORMAT_SWIZZLE_Z:
175 return V_008F0C_SQ_SEL_Z;
176 case UTIL_FORMAT_SWIZZLE_W:
177 return V_008F0C_SQ_SEL_W;
178 case UTIL_FORMAT_SWIZZLE_0:
179 return V_008F0C_SQ_SEL_0;
180 case UTIL_FORMAT_SWIZZLE_1:
181 return V_008F0C_SQ_SEL_1;
182 default: /* UTIL_FORMAT_SWIZZLE_X */
183 return V_008F0C_SQ_SEL_X;
184 }
185 }
186
187 static uint32_t S_FIXED(float value, uint32_t frac_bits)
188 {
189 return value * (1 << frac_bits);
190 }
191
192 /* 12.4 fixed-point */
193 static unsigned si_pack_float_12p4(float x)
194 {
195 return x <= 0 ? 0 :
196 x >= 4096 ? 0xffff : x * 16;
197 }
198
199 /*
200 * inferred framebuffer and blender state
201 */
202 static void si_update_fb_blend_state(struct si_context *sctx)
203 {
204 struct si_pm4_state *pm4;
205 struct si_state_blend *blend = sctx->queued.named.blend;
206 uint32_t mask;
207
208 if (blend == NULL)
209 return;
210
211 pm4 = si_pm4_alloc_state(sctx);
212 if (pm4 == NULL)
213 return;
214
215 mask = (1ULL << ((unsigned)sctx->framebuffer.nr_cbufs * 4)) - 1;
216 mask &= blend->cb_target_mask;
217 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
218
219 si_pm4_set_state(sctx, fb_blend, pm4);
220 }
221
222 /*
223 * Blender functions
224 */
225
226 static uint32_t si_translate_blend_function(int blend_func)
227 {
228 switch (blend_func) {
229 case PIPE_BLEND_ADD:
230 return V_028780_COMB_DST_PLUS_SRC;
231 case PIPE_BLEND_SUBTRACT:
232 return V_028780_COMB_SRC_MINUS_DST;
233 case PIPE_BLEND_REVERSE_SUBTRACT:
234 return V_028780_COMB_DST_MINUS_SRC;
235 case PIPE_BLEND_MIN:
236 return V_028780_COMB_MIN_DST_SRC;
237 case PIPE_BLEND_MAX:
238 return V_028780_COMB_MAX_DST_SRC;
239 default:
240 R600_ERR("Unknown blend function %d\n", blend_func);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static uint32_t si_translate_blend_factor(int blend_fact)
248 {
249 switch (blend_fact) {
250 case PIPE_BLENDFACTOR_ONE:
251 return V_028780_BLEND_ONE;
252 case PIPE_BLENDFACTOR_SRC_COLOR:
253 return V_028780_BLEND_SRC_COLOR;
254 case PIPE_BLENDFACTOR_SRC_ALPHA:
255 return V_028780_BLEND_SRC_ALPHA;
256 case PIPE_BLENDFACTOR_DST_ALPHA:
257 return V_028780_BLEND_DST_ALPHA;
258 case PIPE_BLENDFACTOR_DST_COLOR:
259 return V_028780_BLEND_DST_COLOR;
260 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
261 return V_028780_BLEND_SRC_ALPHA_SATURATE;
262 case PIPE_BLENDFACTOR_CONST_COLOR:
263 return V_028780_BLEND_CONSTANT_COLOR;
264 case PIPE_BLENDFACTOR_CONST_ALPHA:
265 return V_028780_BLEND_CONSTANT_ALPHA;
266 case PIPE_BLENDFACTOR_ZERO:
267 return V_028780_BLEND_ZERO;
268 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
269 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
270 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
271 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
272 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
273 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
274 case PIPE_BLENDFACTOR_INV_DST_COLOR:
275 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
276 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
277 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
278 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
279 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
280 case PIPE_BLENDFACTOR_SRC1_COLOR:
281 return V_028780_BLEND_SRC1_COLOR;
282 case PIPE_BLENDFACTOR_SRC1_ALPHA:
283 return V_028780_BLEND_SRC1_ALPHA;
284 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
285 return V_028780_BLEND_INV_SRC1_COLOR;
286 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
287 return V_028780_BLEND_INV_SRC1_ALPHA;
288 default:
289 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
290 assert(0);
291 break;
292 }
293 return 0;
294 }
295
296 static void *si_create_blend_state_mode(struct pipe_context *ctx,
297 const struct pipe_blend_state *state,
298 unsigned mode)
299 {
300 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
301 struct si_pm4_state *pm4 = &blend->pm4;
302
303 uint32_t color_control = 0;
304
305 if (blend == NULL)
306 return NULL;
307
308 blend->alpha_to_one = state->alpha_to_one;
309
310 if (state->logicop_enable) {
311 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
312 } else {
313 color_control |= S_028808_ROP3(0xcc);
314 }
315
316 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
317 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
318 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
319 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
320 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
321 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
322
323 blend->cb_target_mask = 0;
324 for (int i = 0; i < 8; i++) {
325 /* state->rt entries > 0 only written if independent blending */
326 const int j = state->independent_blend_enable ? i : 0;
327
328 unsigned eqRGB = state->rt[j].rgb_func;
329 unsigned srcRGB = state->rt[j].rgb_src_factor;
330 unsigned dstRGB = state->rt[j].rgb_dst_factor;
331 unsigned eqA = state->rt[j].alpha_func;
332 unsigned srcA = state->rt[j].alpha_src_factor;
333 unsigned dstA = state->rt[j].alpha_dst_factor;
334
335 unsigned blend_cntl = 0;
336
337 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
338 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
339
340 if (!state->rt[j].blend_enable) {
341 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
342 continue;
343 }
344
345 blend_cntl |= S_028780_ENABLE(1);
346 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
347 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
348 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
349
350 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
351 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
352 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
353 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
354 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
355 }
356 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
357 }
358
359 if (blend->cb_target_mask) {
360 color_control |= S_028808_MODE(mode);
361 } else {
362 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
363 }
364 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
365
366 return blend;
367 }
368
369 static void *si_create_blend_state(struct pipe_context *ctx,
370 const struct pipe_blend_state *state)
371 {
372 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
373 }
374
375 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
376 {
377 struct si_context *sctx = (struct si_context *)ctx;
378 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
379 si_update_fb_blend_state(sctx);
380 }
381
382 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
383 {
384 struct si_context *sctx = (struct si_context *)ctx;
385 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
386 }
387
388 static void si_set_blend_color(struct pipe_context *ctx,
389 const struct pipe_blend_color *state)
390 {
391 struct si_context *sctx = (struct si_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
393
394 if (pm4 == NULL)
395 return;
396
397 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
398 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
399 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
400 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
401
402 si_pm4_set_state(sctx, blend_color, pm4);
403 }
404
405 /*
406 * Clipping, scissors and viewport
407 */
408
409 static void si_set_clip_state(struct pipe_context *ctx,
410 const struct pipe_clip_state *state)
411 {
412 struct si_context *sctx = (struct si_context *)ctx;
413 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
414 struct pipe_constant_buffer cb;
415
416 if (pm4 == NULL)
417 return;
418
419 for (int i = 0; i < 6; i++) {
420 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
421 fui(state->ucp[i][0]));
422 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
423 fui(state->ucp[i][1]));
424 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
425 fui(state->ucp[i][2]));
426 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
427 fui(state->ucp[i][3]));
428 }
429
430 cb.buffer = NULL;
431 cb.user_buffer = state->ucp;
432 cb.buffer_offset = 0;
433 cb.buffer_size = 4*4*8;
434 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
435 pipe_resource_reference(&cb.buffer, NULL);
436
437 si_pm4_set_state(sctx, clip, pm4);
438 }
439
440 static void si_set_scissor_states(struct pipe_context *ctx,
441 unsigned start_slot,
442 unsigned num_scissors,
443 const struct pipe_scissor_state *state)
444 {
445 struct si_context *sctx = (struct si_context *)ctx;
446 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
447
448 if (pm4 == NULL)
449 return;
450
451 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
452 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
453 S_028250_WINDOW_OFFSET_DISABLE(1));
454 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
455 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
456
457 si_pm4_set_state(sctx, scissor, pm4);
458 }
459
460 static void si_set_viewport_states(struct pipe_context *ctx,
461 unsigned start_slot,
462 unsigned num_viewports,
463 const struct pipe_viewport_state *state)
464 {
465 struct si_context *sctx = (struct si_context *)ctx;
466 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
467 struct si_pm4_state *pm4 = &viewport->pm4;
468
469 if (viewport == NULL)
470 return;
471
472 viewport->viewport = *state;
473 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
474 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
475 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
476 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
477 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
478 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
479
480 si_pm4_set_state(sctx, viewport, viewport);
481 }
482
483 /*
484 * inferred state between framebuffer and rasterizer
485 */
486 static void si_update_fb_rs_state(struct si_context *sctx)
487 {
488 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
489 struct si_pm4_state *pm4;
490 unsigned offset_db_fmt_cntl = 0, depth;
491 float offset_units;
492
493 if (!rs || !sctx->framebuffer.zsbuf)
494 return;
495
496 offset_units = sctx->queued.named.rasterizer->offset_units;
497 switch (sctx->framebuffer.zsbuf->texture->format) {
498 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
499 case PIPE_FORMAT_X8Z24_UNORM:
500 case PIPE_FORMAT_Z24X8_UNORM:
501 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
502 depth = -24;
503 offset_units *= 2.0f;
504 break;
505 case PIPE_FORMAT_Z32_FLOAT:
506 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
507 depth = -23;
508 offset_units *= 1.0f;
509 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
510 break;
511 case PIPE_FORMAT_Z16_UNORM:
512 depth = -16;
513 offset_units *= 4.0f;
514 break;
515 default:
516 return;
517 }
518
519 pm4 = si_pm4_alloc_state(sctx);
520
521 if (pm4 == NULL)
522 return;
523
524 /* FIXME some of those reg can be computed with cso */
525 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
526 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
527 fui(sctx->queued.named.rasterizer->offset_scale));
528 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
529 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
530 fui(sctx->queued.named.rasterizer->offset_scale));
531 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
532 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
533
534 si_pm4_set_state(sctx, fb_rs, pm4);
535 }
536
537 /*
538 * Rasterizer
539 */
540
541 static uint32_t si_translate_fill(uint32_t func)
542 {
543 switch(func) {
544 case PIPE_POLYGON_MODE_FILL:
545 return V_028814_X_DRAW_TRIANGLES;
546 case PIPE_POLYGON_MODE_LINE:
547 return V_028814_X_DRAW_LINES;
548 case PIPE_POLYGON_MODE_POINT:
549 return V_028814_X_DRAW_POINTS;
550 default:
551 assert(0);
552 return V_028814_X_DRAW_POINTS;
553 }
554 }
555
556 static void *si_create_rs_state(struct pipe_context *ctx,
557 const struct pipe_rasterizer_state *state)
558 {
559 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
560 struct si_pm4_state *pm4 = &rs->pm4;
561 unsigned tmp;
562 unsigned prov_vtx = 1, polygon_dual_mode;
563 float psize_min, psize_max;
564
565 if (rs == NULL) {
566 return NULL;
567 }
568
569 rs->two_side = state->light_twoside;
570 rs->multisample_enable = state->multisample;
571 rs->clip_plane_enable = state->clip_plane_enable;
572 rs->line_stipple_enable = state->line_stipple_enable;
573
574 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
575 state->fill_back != PIPE_POLYGON_MODE_FILL);
576
577 if (state->flatshade_first)
578 prov_vtx = 0;
579
580 rs->flatshade = state->flatshade;
581 rs->sprite_coord_enable = state->sprite_coord_enable;
582 rs->pa_sc_line_stipple = state->line_stipple_enable ?
583 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
584 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
585 rs->pa_su_sc_mode_cntl =
586 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
587 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
588 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
589 S_028814_FACE(!state->front_ccw) |
590 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
591 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
592 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
593 S_028814_POLY_MODE(polygon_dual_mode) |
594 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
595 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
596 rs->pa_cl_clip_cntl =
597 S_028810_PS_UCP_MODE(3) |
598 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
599 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
600 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
601 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
602
603 /* offset */
604 rs->offset_units = state->offset_units;
605 rs->offset_scale = state->offset_scale * 12.0f;
606
607 tmp = S_0286D4_FLAT_SHADE_ENA(1);
608 if (state->sprite_coord_enable) {
609 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
610 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
611 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
612 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
613 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
614 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
615 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
616 }
617 }
618 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
619
620 /* point size 12.4 fixed point */
621 tmp = (unsigned)(state->point_size * 8.0);
622 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
623
624 if (state->point_size_per_vertex) {
625 psize_min = util_get_min_point_size(state);
626 psize_max = 8192;
627 } else {
628 /* Force the point size to be as if the vertex output was disabled. */
629 psize_min = state->point_size;
630 psize_max = state->point_size;
631 }
632 /* Divide by two, because 0.5 = 1 pixel. */
633 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
634 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
635 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
636
637 tmp = (unsigned)state->line_width * 8;
638 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
639 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
640 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
641 S_028A48_MSAA_ENABLE(state->multisample) |
642 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
643
644 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
645 S_028BE4_PIX_CENTER(state->half_pixel_center) |
646 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
647
648 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
649
650 return rs;
651 }
652
653 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
654 {
655 struct si_context *sctx = (struct si_context *)ctx;
656 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
657
658 if (state == NULL)
659 return;
660
661 // TODO
662 sctx->sprite_coord_enable = rs->sprite_coord_enable;
663 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
664 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
665
666 si_pm4_bind_state(sctx, rasterizer, rs);
667 si_update_fb_rs_state(sctx);
668 }
669
670 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
671 {
672 struct si_context *sctx = (struct si_context *)ctx;
673 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
674 }
675
676 /*
677 * infeered state between dsa and stencil ref
678 */
679 static void si_update_dsa_stencil_ref(struct si_context *sctx)
680 {
681 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
682 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
683 struct si_state_dsa *dsa = sctx->queued.named.dsa;
684
685 if (pm4 == NULL)
686 return;
687
688 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
689 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
690 S_028430_STENCILMASK(dsa->valuemask[0]) |
691 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
692 S_028430_STENCILOPVAL(1));
693 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
694 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
695 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
696 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
697 S_028434_STENCILOPVAL_BF(1));
698
699 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
700 }
701
702 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
703 const struct pipe_stencil_ref *state)
704 {
705 struct si_context *sctx = (struct si_context *)ctx;
706 sctx->stencil_ref = *state;
707 si_update_dsa_stencil_ref(sctx);
708 }
709
710
711 /*
712 * DSA
713 */
714
715 static uint32_t si_translate_stencil_op(int s_op)
716 {
717 switch (s_op) {
718 case PIPE_STENCIL_OP_KEEP:
719 return V_02842C_STENCIL_KEEP;
720 case PIPE_STENCIL_OP_ZERO:
721 return V_02842C_STENCIL_ZERO;
722 case PIPE_STENCIL_OP_REPLACE:
723 return V_02842C_STENCIL_REPLACE_TEST;
724 case PIPE_STENCIL_OP_INCR:
725 return V_02842C_STENCIL_ADD_CLAMP;
726 case PIPE_STENCIL_OP_DECR:
727 return V_02842C_STENCIL_SUB_CLAMP;
728 case PIPE_STENCIL_OP_INCR_WRAP:
729 return V_02842C_STENCIL_ADD_WRAP;
730 case PIPE_STENCIL_OP_DECR_WRAP:
731 return V_02842C_STENCIL_SUB_WRAP;
732 case PIPE_STENCIL_OP_INVERT:
733 return V_02842C_STENCIL_INVERT;
734 default:
735 R600_ERR("Unknown stencil op %d", s_op);
736 assert(0);
737 break;
738 }
739 return 0;
740 }
741
742 static void *si_create_dsa_state(struct pipe_context *ctx,
743 const struct pipe_depth_stencil_alpha_state *state)
744 {
745 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
746 struct si_pm4_state *pm4 = &dsa->pm4;
747 unsigned db_depth_control;
748 unsigned db_render_control;
749 uint32_t db_stencil_control = 0;
750
751 if (dsa == NULL) {
752 return NULL;
753 }
754
755 dsa->valuemask[0] = state->stencil[0].valuemask;
756 dsa->valuemask[1] = state->stencil[1].valuemask;
757 dsa->writemask[0] = state->stencil[0].writemask;
758 dsa->writemask[1] = state->stencil[1].writemask;
759
760 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
761 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
762 S_028800_ZFUNC(state->depth.func);
763
764 /* stencil */
765 if (state->stencil[0].enabled) {
766 db_depth_control |= S_028800_STENCIL_ENABLE(1);
767 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
768 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
769 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
770 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
771
772 if (state->stencil[1].enabled) {
773 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
774 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
775 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
776 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
777 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
778 }
779 }
780
781 /* alpha */
782 if (state->alpha.enabled) {
783 dsa->alpha_func = state->alpha.func;
784 dsa->alpha_ref = state->alpha.ref_value;
785
786 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
787 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
788 } else {
789 dsa->alpha_func = PIPE_FUNC_ALWAYS;
790 }
791
792 /* misc */
793 db_render_control = 0;
794 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
795 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
796 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
797
798 return dsa;
799 }
800
801 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
802 {
803 struct si_context *sctx = (struct si_context *)ctx;
804 struct si_state_dsa *dsa = state;
805
806 if (state == NULL)
807 return;
808
809 si_pm4_bind_state(sctx, dsa, dsa);
810 si_update_dsa_stencil_ref(sctx);
811 }
812
813 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
817 }
818
819 static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
820 bool copy_stencil, int sample)
821 {
822 struct pipe_depth_stencil_alpha_state dsa;
823 struct si_state_dsa *state;
824
825 memset(&dsa, 0, sizeof(dsa));
826
827 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
828 if (copy_depth || copy_stencil) {
829 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
830 S_028000_DEPTH_COPY(copy_depth) |
831 S_028000_STENCIL_COPY(copy_stencil) |
832 S_028000_COPY_CENTROID(1) |
833 S_028000_COPY_SAMPLE(sample));
834 } else {
835 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
836 S_028000_DEPTH_COMPRESS_DISABLE(1) |
837 S_028000_STENCIL_COMPRESS_DISABLE(1));
838 }
839
840 return state;
841 }
842
843 /*
844 * format translation
845 */
846 static uint32_t si_translate_colorformat(enum pipe_format format)
847 {
848 const struct util_format_description *desc = util_format_description(format);
849
850 #define HAS_SIZE(x,y,z,w) \
851 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
852 desc->channel[2].size == (z) && desc->channel[3].size == (w))
853
854 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
855 return V_028C70_COLOR_10_11_11;
856
857 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
858 return V_028C70_COLOR_INVALID;
859
860 switch (desc->nr_channels) {
861 case 1:
862 switch (desc->channel[0].size) {
863 case 8:
864 return V_028C70_COLOR_8;
865 case 16:
866 return V_028C70_COLOR_16;
867 case 32:
868 return V_028C70_COLOR_32;
869 }
870 break;
871 case 2:
872 if (desc->channel[0].size == desc->channel[1].size) {
873 switch (desc->channel[0].size) {
874 case 8:
875 return V_028C70_COLOR_8_8;
876 case 16:
877 return V_028C70_COLOR_16_16;
878 case 32:
879 return V_028C70_COLOR_32_32;
880 }
881 } else if (HAS_SIZE(8,24,0,0)) {
882 return V_028C70_COLOR_24_8;
883 } else if (HAS_SIZE(24,8,0,0)) {
884 return V_028C70_COLOR_8_24;
885 }
886 break;
887 case 3:
888 if (HAS_SIZE(5,6,5,0)) {
889 return V_028C70_COLOR_5_6_5;
890 } else if (HAS_SIZE(32,8,24,0)) {
891 return V_028C70_COLOR_X24_8_32_FLOAT;
892 }
893 break;
894 case 4:
895 if (desc->channel[0].size == desc->channel[1].size &&
896 desc->channel[0].size == desc->channel[2].size &&
897 desc->channel[0].size == desc->channel[3].size) {
898 switch (desc->channel[0].size) {
899 case 4:
900 return V_028C70_COLOR_4_4_4_4;
901 case 8:
902 return V_028C70_COLOR_8_8_8_8;
903 case 16:
904 return V_028C70_COLOR_16_16_16_16;
905 case 32:
906 return V_028C70_COLOR_32_32_32_32;
907 }
908 } else if (HAS_SIZE(5,5,5,1)) {
909 return V_028C70_COLOR_1_5_5_5;
910 } else if (HAS_SIZE(10,10,10,2)) {
911 return V_028C70_COLOR_2_10_10_10;
912 }
913 break;
914 }
915 return V_028C70_COLOR_INVALID;
916 }
917
918 static uint32_t si_translate_colorswap(enum pipe_format format)
919 {
920 const struct util_format_description *desc = util_format_description(format);
921
922 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
923
924 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
925 return V_028C70_SWAP_STD;
926
927 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
928 return ~0;
929
930 switch (desc->nr_channels) {
931 case 1:
932 if (HAS_SWIZZLE(0,X))
933 return V_028C70_SWAP_STD; /* X___ */
934 else if (HAS_SWIZZLE(3,X))
935 return V_028C70_SWAP_ALT_REV; /* ___X */
936 break;
937 case 2:
938 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
939 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
940 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
941 return V_028C70_SWAP_STD; /* XY__ */
942 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
943 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
944 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
945 return V_028C70_SWAP_STD_REV; /* YX__ */
946 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
947 return V_028C70_SWAP_ALT; /* X__Y */
948 break;
949 case 3:
950 if (HAS_SWIZZLE(0,X))
951 return V_028C70_SWAP_STD; /* XYZ */
952 else if (HAS_SWIZZLE(0,Z))
953 return V_028C70_SWAP_STD_REV; /* ZYX */
954 break;
955 case 4:
956 /* check the middle channels, the 1st and 4th channel can be NONE */
957 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
958 return V_028C70_SWAP_STD; /* XYZW */
959 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
960 return V_028C70_SWAP_STD_REV; /* WZYX */
961 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
962 return V_028C70_SWAP_ALT; /* ZYXW */
963 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
964 return V_028C70_SWAP_ALT_REV; /* WXYZ */
965 break;
966 }
967 return ~0U;
968 }
969
970 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
971 {
972 if (SI_BIG_ENDIAN) {
973 switch(colorformat) {
974 /* 8-bit buffers. */
975 case V_028C70_COLOR_8:
976 return V_028C70_ENDIAN_NONE;
977
978 /* 16-bit buffers. */
979 case V_028C70_COLOR_5_6_5:
980 case V_028C70_COLOR_1_5_5_5:
981 case V_028C70_COLOR_4_4_4_4:
982 case V_028C70_COLOR_16:
983 case V_028C70_COLOR_8_8:
984 return V_028C70_ENDIAN_8IN16;
985
986 /* 32-bit buffers. */
987 case V_028C70_COLOR_8_8_8_8:
988 case V_028C70_COLOR_2_10_10_10:
989 case V_028C70_COLOR_8_24:
990 case V_028C70_COLOR_24_8:
991 case V_028C70_COLOR_16_16:
992 return V_028C70_ENDIAN_8IN32;
993
994 /* 64-bit buffers. */
995 case V_028C70_COLOR_16_16_16_16:
996 return V_028C70_ENDIAN_8IN16;
997
998 case V_028C70_COLOR_32_32:
999 return V_028C70_ENDIAN_8IN32;
1000
1001 /* 128-bit buffers. */
1002 case V_028C70_COLOR_32_32_32_32:
1003 return V_028C70_ENDIAN_8IN32;
1004 default:
1005 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1006 }
1007 } else {
1008 return V_028C70_ENDIAN_NONE;
1009 }
1010 }
1011
1012 /* Returns the size in bits of the widest component of a CB format */
1013 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1014 {
1015 switch(colorformat) {
1016 case V_028C70_COLOR_4_4_4_4:
1017 return 4;
1018
1019 case V_028C70_COLOR_1_5_5_5:
1020 case V_028C70_COLOR_5_5_5_1:
1021 return 5;
1022
1023 case V_028C70_COLOR_5_6_5:
1024 return 6;
1025
1026 case V_028C70_COLOR_8:
1027 case V_028C70_COLOR_8_8:
1028 case V_028C70_COLOR_8_8_8_8:
1029 return 8;
1030
1031 case V_028C70_COLOR_10_10_10_2:
1032 case V_028C70_COLOR_2_10_10_10:
1033 return 10;
1034
1035 case V_028C70_COLOR_10_11_11:
1036 case V_028C70_COLOR_11_11_10:
1037 return 11;
1038
1039 case V_028C70_COLOR_16:
1040 case V_028C70_COLOR_16_16:
1041 case V_028C70_COLOR_16_16_16_16:
1042 return 16;
1043
1044 case V_028C70_COLOR_8_24:
1045 case V_028C70_COLOR_24_8:
1046 return 24;
1047
1048 case V_028C70_COLOR_32:
1049 case V_028C70_COLOR_32_32:
1050 case V_028C70_COLOR_32_32_32_32:
1051 case V_028C70_COLOR_X24_8_32_FLOAT:
1052 return 32;
1053 }
1054
1055 assert(!"Unknown maximum component size");
1056 return 0;
1057 }
1058
1059 static uint32_t si_translate_dbformat(enum pipe_format format)
1060 {
1061 switch (format) {
1062 case PIPE_FORMAT_Z16_UNORM:
1063 return V_028040_Z_16;
1064 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1065 case PIPE_FORMAT_X8Z24_UNORM:
1066 case PIPE_FORMAT_Z24X8_UNORM:
1067 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1068 return V_028040_Z_24; /* deprecated on SI */
1069 case PIPE_FORMAT_Z32_FLOAT:
1070 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1071 return V_028040_Z_32_FLOAT;
1072 default:
1073 return V_028040_Z_INVALID;
1074 }
1075 }
1076
1077 /*
1078 * Texture translation
1079 */
1080
1081 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1082 enum pipe_format format,
1083 const struct util_format_description *desc,
1084 int first_non_void)
1085 {
1086 struct si_screen *sscreen = (struct si_screen*)screen;
1087 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1088 boolean uniform = TRUE;
1089 int i;
1090
1091 /* Colorspace (return non-RGB formats directly). */
1092 switch (desc->colorspace) {
1093 /* Depth stencil formats */
1094 case UTIL_FORMAT_COLORSPACE_ZS:
1095 switch (format) {
1096 case PIPE_FORMAT_Z16_UNORM:
1097 return V_008F14_IMG_DATA_FORMAT_16;
1098 case PIPE_FORMAT_X24S8_UINT:
1099 case PIPE_FORMAT_Z24X8_UNORM:
1100 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1101 return V_008F14_IMG_DATA_FORMAT_8_24;
1102 case PIPE_FORMAT_X8Z24_UNORM:
1103 case PIPE_FORMAT_S8X24_UINT:
1104 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1105 return V_008F14_IMG_DATA_FORMAT_24_8;
1106 case PIPE_FORMAT_S8_UINT:
1107 return V_008F14_IMG_DATA_FORMAT_8;
1108 case PIPE_FORMAT_Z32_FLOAT:
1109 return V_008F14_IMG_DATA_FORMAT_32;
1110 case PIPE_FORMAT_X32_S8X24_UINT:
1111 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1112 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1113 default:
1114 goto out_unknown;
1115 }
1116
1117 case UTIL_FORMAT_COLORSPACE_YUV:
1118 goto out_unknown; /* TODO */
1119
1120 case UTIL_FORMAT_COLORSPACE_SRGB:
1121 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1122 goto out_unknown;
1123 break;
1124
1125 default:
1126 break;
1127 }
1128
1129 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1130 if (!enable_s3tc)
1131 goto out_unknown;
1132
1133 switch (format) {
1134 case PIPE_FORMAT_RGTC1_SNORM:
1135 case PIPE_FORMAT_LATC1_SNORM:
1136 case PIPE_FORMAT_RGTC1_UNORM:
1137 case PIPE_FORMAT_LATC1_UNORM:
1138 return V_008F14_IMG_DATA_FORMAT_BC4;
1139 case PIPE_FORMAT_RGTC2_SNORM:
1140 case PIPE_FORMAT_LATC2_SNORM:
1141 case PIPE_FORMAT_RGTC2_UNORM:
1142 case PIPE_FORMAT_LATC2_UNORM:
1143 return V_008F14_IMG_DATA_FORMAT_BC5;
1144 default:
1145 goto out_unknown;
1146 }
1147 }
1148
1149 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1150
1151 if (!enable_s3tc)
1152 goto out_unknown;
1153
1154 if (!util_format_s3tc_enabled) {
1155 goto out_unknown;
1156 }
1157
1158 switch (format) {
1159 case PIPE_FORMAT_DXT1_RGB:
1160 case PIPE_FORMAT_DXT1_RGBA:
1161 case PIPE_FORMAT_DXT1_SRGB:
1162 case PIPE_FORMAT_DXT1_SRGBA:
1163 return V_008F14_IMG_DATA_FORMAT_BC1;
1164 case PIPE_FORMAT_DXT3_RGBA:
1165 case PIPE_FORMAT_DXT3_SRGBA:
1166 return V_008F14_IMG_DATA_FORMAT_BC2;
1167 case PIPE_FORMAT_DXT5_RGBA:
1168 case PIPE_FORMAT_DXT5_SRGBA:
1169 return V_008F14_IMG_DATA_FORMAT_BC3;
1170 default:
1171 goto out_unknown;
1172 }
1173 }
1174
1175 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1176 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1177 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1178 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1179 }
1180
1181 /* R8G8Bx_SNORM - TODO CxV8U8 */
1182
1183 /* See whether the components are of the same size. */
1184 for (i = 1; i < desc->nr_channels; i++) {
1185 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1186 }
1187
1188 /* Non-uniform formats. */
1189 if (!uniform) {
1190 switch(desc->nr_channels) {
1191 case 3:
1192 if (desc->channel[0].size == 5 &&
1193 desc->channel[1].size == 6 &&
1194 desc->channel[2].size == 5) {
1195 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1196 }
1197 goto out_unknown;
1198 case 4:
1199 if (desc->channel[0].size == 5 &&
1200 desc->channel[1].size == 5 &&
1201 desc->channel[2].size == 5 &&
1202 desc->channel[3].size == 1) {
1203 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1204 }
1205 if (desc->channel[0].size == 10 &&
1206 desc->channel[1].size == 10 &&
1207 desc->channel[2].size == 10 &&
1208 desc->channel[3].size == 2) {
1209 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1210 }
1211 goto out_unknown;
1212 }
1213 goto out_unknown;
1214 }
1215
1216 if (first_non_void < 0 || first_non_void > 3)
1217 goto out_unknown;
1218
1219 /* uniform formats */
1220 switch (desc->channel[first_non_void].size) {
1221 case 4:
1222 switch (desc->nr_channels) {
1223 #if 0 /* Not supported for render targets */
1224 case 2:
1225 return V_008F14_IMG_DATA_FORMAT_4_4;
1226 #endif
1227 case 4:
1228 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1229 }
1230 break;
1231 case 8:
1232 switch (desc->nr_channels) {
1233 case 1:
1234 return V_008F14_IMG_DATA_FORMAT_8;
1235 case 2:
1236 return V_008F14_IMG_DATA_FORMAT_8_8;
1237 case 4:
1238 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1239 }
1240 break;
1241 case 16:
1242 switch (desc->nr_channels) {
1243 case 1:
1244 return V_008F14_IMG_DATA_FORMAT_16;
1245 case 2:
1246 return V_008F14_IMG_DATA_FORMAT_16_16;
1247 case 4:
1248 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1249 }
1250 break;
1251 case 32:
1252 switch (desc->nr_channels) {
1253 case 1:
1254 return V_008F14_IMG_DATA_FORMAT_32;
1255 case 2:
1256 return V_008F14_IMG_DATA_FORMAT_32_32;
1257 #if 0 /* Not supported for render targets */
1258 case 3:
1259 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1260 #endif
1261 case 4:
1262 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1263 }
1264 }
1265
1266 out_unknown:
1267 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1268 return ~0;
1269 }
1270
1271 static unsigned si_tex_wrap(unsigned wrap)
1272 {
1273 switch (wrap) {
1274 default:
1275 case PIPE_TEX_WRAP_REPEAT:
1276 return V_008F30_SQ_TEX_WRAP;
1277 case PIPE_TEX_WRAP_CLAMP:
1278 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1279 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1280 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1281 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1282 return V_008F30_SQ_TEX_CLAMP_BORDER;
1283 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1284 return V_008F30_SQ_TEX_MIRROR;
1285 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1286 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1287 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1288 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1289 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1290 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1291 }
1292 }
1293
1294 static unsigned si_tex_filter(unsigned filter)
1295 {
1296 switch (filter) {
1297 default:
1298 case PIPE_TEX_FILTER_NEAREST:
1299 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1300 case PIPE_TEX_FILTER_LINEAR:
1301 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1302 }
1303 }
1304
1305 static unsigned si_tex_mipfilter(unsigned filter)
1306 {
1307 switch (filter) {
1308 case PIPE_TEX_MIPFILTER_NEAREST:
1309 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1310 case PIPE_TEX_MIPFILTER_LINEAR:
1311 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1312 default:
1313 case PIPE_TEX_MIPFILTER_NONE:
1314 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1315 }
1316 }
1317
1318 static unsigned si_tex_compare(unsigned compare)
1319 {
1320 switch (compare) {
1321 default:
1322 case PIPE_FUNC_NEVER:
1323 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1324 case PIPE_FUNC_LESS:
1325 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1326 case PIPE_FUNC_EQUAL:
1327 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1328 case PIPE_FUNC_LEQUAL:
1329 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1330 case PIPE_FUNC_GREATER:
1331 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1332 case PIPE_FUNC_NOTEQUAL:
1333 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1334 case PIPE_FUNC_GEQUAL:
1335 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1336 case PIPE_FUNC_ALWAYS:
1337 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1338 }
1339 }
1340
1341 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1342 {
1343 switch (dim) {
1344 default:
1345 case PIPE_TEXTURE_1D:
1346 return V_008F1C_SQ_RSRC_IMG_1D;
1347 case PIPE_TEXTURE_1D_ARRAY:
1348 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1349 case PIPE_TEXTURE_2D:
1350 case PIPE_TEXTURE_RECT:
1351 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1352 V_008F1C_SQ_RSRC_IMG_2D;
1353 case PIPE_TEXTURE_2D_ARRAY:
1354 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1355 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1356 case PIPE_TEXTURE_3D:
1357 return V_008F1C_SQ_RSRC_IMG_3D;
1358 case PIPE_TEXTURE_CUBE:
1359 return V_008F1C_SQ_RSRC_IMG_CUBE;
1360 }
1361 }
1362
1363 /*
1364 * Format support testing
1365 */
1366
1367 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1368 {
1369 return si_translate_texformat(screen, format, util_format_description(format),
1370 util_format_get_first_non_void_channel(format)) != ~0U;
1371 }
1372
1373 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1374 const struct util_format_description *desc,
1375 int first_non_void)
1376 {
1377 unsigned type = desc->channel[first_non_void].type;
1378 int i;
1379
1380 if (type == UTIL_FORMAT_TYPE_FIXED)
1381 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1382
1383 if (desc->nr_channels == 4 &&
1384 desc->channel[0].size == 10 &&
1385 desc->channel[1].size == 10 &&
1386 desc->channel[2].size == 10 &&
1387 desc->channel[3].size == 2)
1388 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1389
1390 /* See whether the components are of the same size. */
1391 for (i = 0; i < desc->nr_channels; i++) {
1392 if (desc->channel[first_non_void].size != desc->channel[i].size)
1393 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1394 }
1395
1396 switch (desc->channel[first_non_void].size) {
1397 case 8:
1398 switch (desc->nr_channels) {
1399 case 1:
1400 return V_008F0C_BUF_DATA_FORMAT_8;
1401 case 2:
1402 return V_008F0C_BUF_DATA_FORMAT_8_8;
1403 case 3:
1404 case 4:
1405 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1406 }
1407 break;
1408 case 16:
1409 switch (desc->nr_channels) {
1410 case 1:
1411 return V_008F0C_BUF_DATA_FORMAT_16;
1412 case 2:
1413 return V_008F0C_BUF_DATA_FORMAT_16_16;
1414 case 3:
1415 case 4:
1416 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1417 }
1418 break;
1419 case 32:
1420 /* From the Southern Islands ISA documentation about MTBUF:
1421 * 'Memory reads of data in memory that is 32 or 64 bits do not
1422 * undergo any format conversion.'
1423 */
1424 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1425 !desc->channel[first_non_void].pure_integer)
1426 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1427
1428 switch (desc->nr_channels) {
1429 case 1:
1430 return V_008F0C_BUF_DATA_FORMAT_32;
1431 case 2:
1432 return V_008F0C_BUF_DATA_FORMAT_32_32;
1433 case 3:
1434 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1435 case 4:
1436 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1437 }
1438 break;
1439 }
1440
1441 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1442 }
1443
1444 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1445 const struct util_format_description *desc,
1446 int first_non_void)
1447 {
1448 switch (desc->channel[first_non_void].type) {
1449 case UTIL_FORMAT_TYPE_SIGNED:
1450 if (desc->channel[first_non_void].normalized)
1451 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1452 else if (desc->channel[first_non_void].pure_integer)
1453 return V_008F0C_BUF_NUM_FORMAT_SINT;
1454 else
1455 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1456 break;
1457 case UTIL_FORMAT_TYPE_UNSIGNED:
1458 if (desc->channel[first_non_void].normalized)
1459 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1460 else if (desc->channel[first_non_void].pure_integer)
1461 return V_008F0C_BUF_NUM_FORMAT_UINT;
1462 else
1463 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1464 break;
1465 case UTIL_FORMAT_TYPE_FLOAT:
1466 default:
1467 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1468 }
1469 }
1470
1471 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1472 {
1473 const struct util_format_description *desc;
1474 int first_non_void;
1475 unsigned data_format;
1476
1477 desc = util_format_description(format);
1478 first_non_void = util_format_get_first_non_void_channel(format);
1479 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1480 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1481 }
1482
1483 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1484 {
1485 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1486 si_translate_colorswap(format) != ~0U;
1487 }
1488
1489 static bool si_is_zs_format_supported(enum pipe_format format)
1490 {
1491 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1492 }
1493
1494 boolean si_is_format_supported(struct pipe_screen *screen,
1495 enum pipe_format format,
1496 enum pipe_texture_target target,
1497 unsigned sample_count,
1498 unsigned usage)
1499 {
1500 struct si_screen *sscreen = (struct si_screen *)screen;
1501 unsigned retval = 0;
1502
1503 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1504 R600_ERR("r600: unsupported texture type %d\n", target);
1505 return FALSE;
1506 }
1507
1508 if (!util_format_is_supported(format, usage))
1509 return FALSE;
1510
1511 if (sample_count > 1) {
1512 if (HAVE_LLVM < 0x0304)
1513 return FALSE;
1514
1515 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1516 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1517 return FALSE;
1518
1519 switch (sample_count) {
1520 case 2:
1521 case 4:
1522 case 8:
1523 break;
1524 default:
1525 return FALSE;
1526 }
1527 }
1528
1529 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1530 if (target == PIPE_BUFFER) {
1531 if (si_is_vertex_format_supported(screen, format))
1532 retval |= PIPE_BIND_SAMPLER_VIEW;
1533 } else {
1534 if (si_is_sampler_format_supported(screen, format))
1535 retval |= PIPE_BIND_SAMPLER_VIEW;
1536 }
1537 }
1538
1539 if ((usage & (PIPE_BIND_RENDER_TARGET |
1540 PIPE_BIND_DISPLAY_TARGET |
1541 PIPE_BIND_SCANOUT |
1542 PIPE_BIND_SHARED)) &&
1543 si_is_colorbuffer_format_supported(format)) {
1544 retval |= usage &
1545 (PIPE_BIND_RENDER_TARGET |
1546 PIPE_BIND_DISPLAY_TARGET |
1547 PIPE_BIND_SCANOUT |
1548 PIPE_BIND_SHARED);
1549 }
1550
1551 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1552 si_is_zs_format_supported(format)) {
1553 retval |= PIPE_BIND_DEPTH_STENCIL;
1554 }
1555
1556 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1557 si_is_vertex_format_supported(screen, format)) {
1558 retval |= PIPE_BIND_VERTEX_BUFFER;
1559 }
1560
1561 if (usage & PIPE_BIND_TRANSFER_READ)
1562 retval |= PIPE_BIND_TRANSFER_READ;
1563 if (usage & PIPE_BIND_TRANSFER_WRITE)
1564 retval |= PIPE_BIND_TRANSFER_WRITE;
1565
1566 return retval == usage;
1567 }
1568
1569 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1570 {
1571 unsigned tile_mode_index = 0;
1572
1573 if (stencil) {
1574 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1575 } else {
1576 tile_mode_index = rtex->surface.tiling_index[level];
1577 }
1578 return tile_mode_index;
1579 }
1580
1581 /*
1582 * framebuffer handling
1583 */
1584
1585 static void si_cb(struct si_context *sctx, struct si_pm4_state *pm4,
1586 const struct pipe_framebuffer_state *state, int cb)
1587 {
1588 struct r600_texture *rtex;
1589 struct si_surface *surf;
1590 unsigned level = state->cbufs[cb]->u.tex.level;
1591 unsigned pitch, slice;
1592 unsigned color_info, color_attrib, color_pitch, color_view;
1593 unsigned tile_mode_index;
1594 unsigned format, swap, ntype, endian;
1595 uint64_t offset;
1596 const struct util_format_description *desc;
1597 int i;
1598 unsigned blend_clamp = 0, blend_bypass = 0;
1599 unsigned max_comp_size;
1600
1601 surf = (struct si_surface *)state->cbufs[cb];
1602 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1603
1604 offset = rtex->surface.level[level].offset;
1605
1606 /* Layered rendering doesn't work with LINEAR_GENERAL.
1607 * (LINEAR_ALIGNED and others work) */
1608 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1609 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1610 offset += rtex->surface.level[level].slice_size *
1611 state->cbufs[cb]->u.tex.first_layer;
1612 color_view = 0;
1613 } else {
1614 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1615 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1616 }
1617
1618 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1619 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1620 if (slice) {
1621 slice = slice - 1;
1622 }
1623
1624 tile_mode_index = si_tile_mode_index(rtex, level, false);
1625
1626 desc = util_format_description(surf->base.format);
1627 for (i = 0; i < 4; i++) {
1628 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1629 break;
1630 }
1631 }
1632 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1633 ntype = V_028C70_NUMBER_FLOAT;
1634 } else {
1635 ntype = V_028C70_NUMBER_UNORM;
1636 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1637 ntype = V_028C70_NUMBER_SRGB;
1638 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1639 if (desc->channel[i].pure_integer) {
1640 ntype = V_028C70_NUMBER_SINT;
1641 } else {
1642 assert(desc->channel[i].normalized);
1643 ntype = V_028C70_NUMBER_SNORM;
1644 }
1645 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1646 if (desc->channel[i].pure_integer) {
1647 ntype = V_028C70_NUMBER_UINT;
1648 } else {
1649 assert(desc->channel[i].normalized);
1650 ntype = V_028C70_NUMBER_UNORM;
1651 }
1652 }
1653 }
1654
1655 format = si_translate_colorformat(surf->base.format);
1656 if (format == V_028C70_COLOR_INVALID) {
1657 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1658 }
1659 assert(format != V_028C70_COLOR_INVALID);
1660 swap = si_translate_colorswap(surf->base.format);
1661 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1662 endian = V_028C70_ENDIAN_NONE;
1663 } else {
1664 endian = si_colorformat_endian_swap(format);
1665 }
1666
1667 /* blend clamp should be set for all NORM/SRGB types */
1668 if (ntype == V_028C70_NUMBER_UNORM ||
1669 ntype == V_028C70_NUMBER_SNORM ||
1670 ntype == V_028C70_NUMBER_SRGB)
1671 blend_clamp = 1;
1672
1673 /* set blend bypass according to docs if SINT/UINT or
1674 8/24 COLOR variants */
1675 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1676 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1677 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1678 blend_clamp = 0;
1679 blend_bypass = 1;
1680 }
1681
1682 color_info = S_028C70_FORMAT(format) |
1683 S_028C70_COMP_SWAP(swap) |
1684 S_028C70_BLEND_CLAMP(blend_clamp) |
1685 S_028C70_BLEND_BYPASS(blend_bypass) |
1686 S_028C70_NUMBER_TYPE(ntype) |
1687 S_028C70_ENDIAN(endian);
1688
1689 color_pitch = S_028C64_TILE_MAX(pitch);
1690
1691 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1692 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1693
1694 if (rtex->resource.b.b.nr_samples > 1) {
1695 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1696
1697 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1698 S_028C74_NUM_FRAGMENTS(log_samples);
1699
1700 if (rtex->fmask.size) {
1701 color_info |= S_028C70_COMPRESSION(1);
1702 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1703
1704 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1705
1706 if (sctx->b.chip_class == SI) {
1707 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1708 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1709 }
1710 if (sctx->b.chip_class >= CIK) {
1711 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1712 }
1713 }
1714 }
1715
1716 if (rtex->cmask.size) {
1717 color_info |= S_028C70_FAST_CLEAR(1);
1718 }
1719
1720 offset += r600_resource_va(sctx->b.b.screen, state->cbufs[cb]->texture);
1721 offset >>= 8;
1722
1723 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1724 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1725 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1726 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1727 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1728 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1729 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1730
1731 if (rtex->cmask.size) {
1732 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1733 offset + (rtex->cmask.offset >> 8));
1734 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1735 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1736 }
1737 if (rtex->fmask.size) {
1738 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1739 offset + (rtex->fmask.offset >> 8));
1740 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1741 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1742 }
1743
1744 /* set CB_COLOR1_INFO for possible dual-src blending */
1745 if (state->nr_cbufs == 1) {
1746 assert(cb == 0);
1747 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1748 }
1749
1750 /* Determine pixel shader export format */
1751 max_comp_size = si_colorformat_max_comp_size(format);
1752 if (ntype == V_028C70_NUMBER_SRGB ||
1753 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1754 max_comp_size <= 10) ||
1755 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1756 sctx->export_16bpc |= 1 << cb;
1757 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1758 if (state->nr_cbufs == 1)
1759 sctx->export_16bpc |= 1 << 1;
1760 }
1761 }
1762
1763 static void si_db(struct si_context *sctx, struct si_pm4_state *pm4,
1764 const struct pipe_framebuffer_state *state)
1765 {
1766 struct si_screen *sscreen = sctx->screen;
1767 struct r600_texture *rtex;
1768 struct si_surface *surf;
1769 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1770 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1771 uint32_t z_info, s_info, db_depth_info;
1772 uint64_t z_offs, s_offs;
1773 uint32_t db_htile_data_base, db_htile_surface;
1774
1775 if (state->zsbuf == NULL) {
1776 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1777 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1778 return;
1779 }
1780
1781 surf = (struct si_surface *)state->zsbuf;
1782 level = surf->base.u.tex.level;
1783 rtex = (struct r600_texture*)surf->base.texture;
1784
1785 format = si_translate_dbformat(rtex->resource.b.b.format);
1786
1787 if (format == V_028040_Z_INVALID) {
1788 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1789 }
1790 assert(format != V_028040_Z_INVALID);
1791
1792 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture);
1793 z_offs += rtex->surface.level[level].offset;
1794 s_offs += rtex->surface.stencil_level[level].offset;
1795
1796 z_offs >>= 8;
1797 s_offs >>= 8;
1798
1799 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1800 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1801 if (slice) {
1802 slice = slice - 1;
1803 }
1804
1805 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1806
1807 z_info = S_028040_FORMAT(format);
1808 if (rtex->resource.b.b.nr_samples > 1) {
1809 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1810 }
1811
1812 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1813 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1814 else
1815 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1816
1817 if (sctx->b.chip_class >= CIK) {
1818 switch (rtex->surface.level[level].mode) {
1819 case RADEON_SURF_MODE_2D:
1820 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1821 break;
1822 case RADEON_SURF_MODE_1D:
1823 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1824 case RADEON_SURF_MODE_LINEAR:
1825 default:
1826 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1827 break;
1828 }
1829 tile_split = rtex->surface.tile_split;
1830 stile_split = rtex->surface.stencil_tile_split;
1831 macro_aspect = rtex->surface.mtilea;
1832 bankw = rtex->surface.bankw;
1833 bankh = rtex->surface.bankh;
1834 tile_split = cik_tile_split(tile_split);
1835 stile_split = cik_tile_split(stile_split);
1836 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1837 bankw = cik_bank_wh(bankw);
1838 bankh = cik_bank_wh(bankh);
1839 nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split);
1840 tile_mode_index = si_tile_mode_index(rtex, level, false);
1841 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1842
1843 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1844 S_02803C_PIPE_CONFIG(pipe_config) |
1845 S_02803C_BANK_WIDTH(bankw) |
1846 S_02803C_BANK_HEIGHT(bankh) |
1847 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1848 S_02803C_NUM_BANKS(nbanks);
1849 z_info |= S_028040_TILE_SPLIT(tile_split);
1850 s_info |= S_028044_TILE_SPLIT(stile_split);
1851 } else {
1852 tile_mode_index = si_tile_mode_index(rtex, level, false);
1853 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1854 tile_mode_index = si_tile_mode_index(rtex, level, true);
1855 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1856 }
1857
1858 /* HiZ aka depth buffer htile */
1859 /* use htile only for first level */
1860 if (rtex->htile_buffer && !level) {
1861 const struct util_format_description *fmt_desc;
1862
1863 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1864
1865 /* This is optimal for the clear value of 1.0 and using
1866 * the LESS and LEQUAL test functions. Set this to 0
1867 * for the opposite case. This can only be changed when
1868 * clearing. */
1869 z_info |= S_028040_ZRANGE_PRECISION(1);
1870
1871 fmt_desc = util_format_description(rtex->resource.b.b.format);
1872 if (!util_format_has_stencil(fmt_desc)) {
1873 /* Use all of the htile_buffer for depth */
1874 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1875 }
1876
1877 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b);
1878 db_htile_data_base = va >> 8;
1879 db_htile_surface = S_028ABC_FULL_CACHE(1);
1880
1881 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
1882 } else {
1883 db_htile_data_base = 0;
1884 db_htile_surface = 0;
1885 }
1886
1887 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1888 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1889 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1890 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1891
1892 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1893 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1894 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1895
1896 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1897 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1898 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1899 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1900 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1901
1902 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1903 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1904
1905 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1906 }
1907
1908 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1909 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1910 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1911 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1912 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1913
1914 /* 2xMSAA
1915 * There are two locations (-4, 4), (4, -4). */
1916 static uint32_t sample_locs_2x[] = {
1917 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1918 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1919 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1920 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1921 };
1922 static unsigned max_dist_2x = 4;
1923 /* 4xMSAA
1924 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1925 static uint32_t sample_locs_4x[] = {
1926 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1927 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1928 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1929 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1930 };
1931 static unsigned max_dist_4x = 6;
1932 /* Cayman/SI 8xMSAA */
1933 static uint32_t cm_sample_locs_8x[] = {
1934 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1935 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1936 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1937 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1938 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1939 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1940 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1941 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1942 };
1943 static unsigned cm_max_dist_8x = 8;
1944 /* Cayman/SI 16xMSAA */
1945 static uint32_t cm_sample_locs_16x[] = {
1946 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1947 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1948 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1949 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1950 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1951 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1952 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1953 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1954 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1955 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1956 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1957 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1958 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1959 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1960 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1961 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1962 };
1963 static unsigned cm_max_dist_16x = 8;
1964
1965 static void si_get_sample_position(struct pipe_context *ctx,
1966 unsigned sample_count,
1967 unsigned sample_index,
1968 float *out_value)
1969 {
1970 int offset, index;
1971 struct {
1972 int idx:4;
1973 } val;
1974 switch (sample_count) {
1975 case 1:
1976 default:
1977 out_value[0] = out_value[1] = 0.5;
1978 break;
1979 case 2:
1980 offset = 4 * (sample_index * 2);
1981 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1982 out_value[0] = (float)(val.idx + 8) / 16.0f;
1983 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1984 out_value[1] = (float)(val.idx + 8) / 16.0f;
1985 break;
1986 case 4:
1987 offset = 4 * (sample_index * 2);
1988 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1989 out_value[0] = (float)(val.idx + 8) / 16.0f;
1990 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1991 out_value[1] = (float)(val.idx + 8) / 16.0f;
1992 break;
1993 case 8:
1994 offset = 4 * (sample_index % 4 * 2);
1995 index = (sample_index / 4) * 4;
1996 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1997 out_value[0] = (float)(val.idx + 8) / 16.0f;
1998 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1999 out_value[1] = (float)(val.idx + 8) / 16.0f;
2000 break;
2001 case 16:
2002 offset = 4 * (sample_index % 4 * 2);
2003 index = (sample_index / 4) * 4;
2004 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2005 out_value[0] = (float)(val.idx + 8) / 16.0f;
2006 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2007 out_value[1] = (float)(val.idx + 8) / 16.0f;
2008 break;
2009 }
2010 }
2011
2012 static void si_set_msaa_state(struct si_context *sctx, struct si_pm4_state *pm4, int nr_samples)
2013 {
2014 unsigned max_dist = 0;
2015
2016 switch (nr_samples) {
2017 default:
2018 nr_samples = 0;
2019 break;
2020 case 2:
2021 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2022 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2023 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2024 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2025 max_dist = max_dist_2x;
2026 break;
2027 case 4:
2028 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2029 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2030 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2031 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2032 max_dist = max_dist_4x;
2033 break;
2034 case 8:
2035 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2036 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2037 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2038 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2039 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2040 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2041 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2042 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2043 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2044 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2045 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2046 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2047 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2048 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2049 max_dist = cm_max_dist_8x;
2050 break;
2051 case 16:
2052 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2053 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2054 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2055 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2056 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2057 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2058 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2059 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2060 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2061 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2062 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2063 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2064 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2065 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2066 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2067 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2068 max_dist = cm_max_dist_16x;
2069 break;
2070 }
2071
2072 if (nr_samples > 1) {
2073 unsigned log_samples = util_logbase2(nr_samples);
2074
2075 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2076 S_028BDC_LAST_PIXEL(1) |
2077 S_028BDC_EXPAND_LINE_WIDTH(1));
2078 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2079 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2080 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2081 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2082
2083 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2084 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2085 S_028804_PS_ITER_SAMPLES(log_samples) |
2086 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2087 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2088 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2089 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2090 } else {
2091 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2092 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2093
2094 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2095 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2096 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2097 }
2098 }
2099
2100 static void si_set_framebuffer_state(struct pipe_context *ctx,
2101 const struct pipe_framebuffer_state *state)
2102 {
2103 struct si_context *sctx = (struct si_context *)ctx;
2104 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2105 int nr_samples, i;
2106
2107 if (pm4 == NULL)
2108 return;
2109
2110 if (sctx->framebuffer.nr_cbufs) {
2111 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2112 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2113 }
2114 if (sctx->framebuffer.zsbuf) {
2115 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
2116 R600_CONTEXT_FLUSH_AND_INV_DB_META;
2117 }
2118
2119 util_copy_framebuffer_state(&sctx->framebuffer, state);
2120
2121 /* build states */
2122 sctx->export_16bpc = 0;
2123 sctx->fb_compressed_cb_mask = 0;
2124 for (i = 0; i < state->nr_cbufs; i++) {
2125 struct r600_texture *rtex;
2126
2127 if (!state->cbufs[i]) {
2128 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2129 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2130 continue;
2131 }
2132
2133 rtex = (struct r600_texture*)state->cbufs[i]->texture;
2134
2135 si_cb(sctx, pm4, state, i);
2136
2137 if (rtex->fmask.size || rtex->cmask.size) {
2138 sctx->fb_compressed_cb_mask |= 1 << i;
2139 }
2140 }
2141 for (; i < 8; i++) {
2142 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2143 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2144 }
2145
2146 assert(!(sctx->export_16bpc & ~0xff));
2147 si_db(sctx, pm4, state);
2148
2149 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2150 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2151 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2152
2153 nr_samples = util_framebuffer_get_num_samples(state);
2154
2155 si_set_msaa_state(sctx, pm4, nr_samples);
2156 sctx->fb_log_samples = util_logbase2(nr_samples);
2157 sctx->fb_cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2158 util_format_is_pure_integer(state->cbufs[0]->format);
2159
2160 si_pm4_set_state(sctx, framebuffer, pm4);
2161 si_update_fb_rs_state(sctx);
2162 si_update_fb_blend_state(sctx);
2163 }
2164
2165 /*
2166 * shaders
2167 */
2168
2169 /* Compute the key for the hw shader variant */
2170 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2171 struct si_pipe_shader_selector *sel,
2172 union si_shader_key *key)
2173 {
2174 struct si_context *sctx = (struct si_context *)ctx;
2175 memset(key, 0, sizeof(*key));
2176
2177 if (sel->type == PIPE_SHADER_VERTEX) {
2178 unsigned i;
2179 if (!sctx->vertex_elements)
2180 return;
2181
2182 for (i = 0; i < sctx->vertex_elements->count; ++i)
2183 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2184
2185 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2186 key->vs.ucps_enabled |= 0x2;
2187 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2188 key->vs.ucps_enabled |= 0x1;
2189 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2190 if (sel->fs_write_all)
2191 key->ps.nr_cbufs = sctx->framebuffer.nr_cbufs;
2192 key->ps.export_16bpc = sctx->export_16bpc;
2193
2194 if (sctx->queued.named.rasterizer) {
2195 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2196 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2197
2198 if (sctx->queued.named.blend) {
2199 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2200 sctx->queued.named.rasterizer->multisample_enable &&
2201 !sctx->fb_cb0_is_integer;
2202 }
2203 }
2204 if (sctx->queued.named.dsa) {
2205 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2206
2207 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2208 if (sctx->framebuffer.nr_cbufs &&
2209 sctx->framebuffer.cbufs[0] &&
2210 util_format_is_pure_integer(sctx->framebuffer.cbufs[0]->texture->format))
2211 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2212 } else {
2213 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2214 }
2215 }
2216 }
2217
2218 /* Select the hw shader variant depending on the current state.
2219 * (*dirty) is set to 1 if current variant was changed */
2220 int si_shader_select(struct pipe_context *ctx,
2221 struct si_pipe_shader_selector *sel,
2222 unsigned *dirty)
2223 {
2224 union si_shader_key key;
2225 struct si_pipe_shader * shader = NULL;
2226 int r;
2227
2228 si_shader_selector_key(ctx, sel, &key);
2229
2230 /* Check if we don't need to change anything.
2231 * This path is also used for most shaders that don't need multiple
2232 * variants, it will cost just a computation of the key and this
2233 * test. */
2234 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2235 return 0;
2236 }
2237
2238 /* lookup if we have other variants in the list */
2239 if (sel->num_shaders > 1) {
2240 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2241
2242 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2243 p = c;
2244 c = c->next_variant;
2245 }
2246
2247 if (c) {
2248 p->next_variant = c->next_variant;
2249 shader = c;
2250 }
2251 }
2252
2253 if (unlikely(!shader)) {
2254 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2255 shader->selector = sel;
2256 shader->key = key;
2257
2258 r = si_pipe_shader_create(ctx, shader);
2259 if (unlikely(r)) {
2260 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2261 sel->type, r);
2262 sel->current = NULL;
2263 FREE(shader);
2264 return r;
2265 }
2266 sel->num_shaders++;
2267 }
2268
2269 if (dirty)
2270 *dirty = 1;
2271
2272 shader->next_variant = sel->current;
2273 sel->current = shader;
2274
2275 return 0;
2276 }
2277
2278 static void *si_create_shader_state(struct pipe_context *ctx,
2279 const struct pipe_shader_state *state,
2280 unsigned pipe_shader_type)
2281 {
2282 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2283 int r;
2284
2285 sel->type = pipe_shader_type;
2286 sel->tokens = tgsi_dup_tokens(state->tokens);
2287 sel->so = state->stream_output;
2288
2289 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2290 struct tgsi_shader_info info;
2291
2292 tgsi_scan_shader(state->tokens, &info);
2293 sel->fs_write_all = info.color0_writes_all_cbufs;
2294 }
2295
2296 r = si_shader_select(ctx, sel, NULL);
2297 if (r) {
2298 free(sel);
2299 return NULL;
2300 }
2301
2302 return sel;
2303 }
2304
2305 static void *si_create_fs_state(struct pipe_context *ctx,
2306 const struct pipe_shader_state *state)
2307 {
2308 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2309 }
2310
2311 static void *si_create_vs_state(struct pipe_context *ctx,
2312 const struct pipe_shader_state *state)
2313 {
2314 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2315 }
2316
2317 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2318 {
2319 struct si_context *sctx = (struct si_context *)ctx;
2320 struct si_pipe_shader_selector *sel = state;
2321
2322 if (sctx->vs_shader == sel)
2323 return;
2324
2325 if (!sel || !sel->current)
2326 return;
2327
2328 sctx->vs_shader = sel;
2329 si_pm4_bind_state(sctx, vs, sel->current->pm4);
2330 sctx->b.streamout.stride_in_dw = sel->so.stride;
2331 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2332 }
2333
2334 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2335 {
2336 struct si_context *sctx = (struct si_context *)ctx;
2337 struct si_pipe_shader_selector *sel = state;
2338
2339 if (sctx->ps_shader == sel)
2340 return;
2341
2342 if (!sel || !sel->current)
2343 sel = sctx->dummy_pixel_shader;
2344
2345 sctx->ps_shader = sel;
2346 si_pm4_bind_state(sctx, ps, sel->current->pm4);
2347 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2348 }
2349
2350 static void si_delete_shader_selector(struct pipe_context *ctx,
2351 struct si_pipe_shader_selector *sel)
2352 {
2353 struct si_context *sctx = (struct si_context *)ctx;
2354 struct si_pipe_shader *p = sel->current, *c;
2355
2356 while (p) {
2357 c = p->next_variant;
2358 si_pm4_delete_state(sctx, vs, p->pm4);
2359 si_pipe_shader_destroy(ctx, p);
2360 free(p);
2361 p = c;
2362 }
2363
2364 free(sel->tokens);
2365 free(sel);
2366 }
2367
2368 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2369 {
2370 struct si_context *sctx = (struct si_context *)ctx;
2371 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2372
2373 if (sctx->vs_shader == sel) {
2374 sctx->vs_shader = NULL;
2375 }
2376
2377 si_delete_shader_selector(ctx, sel);
2378 }
2379
2380 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2381 {
2382 struct si_context *sctx = (struct si_context *)ctx;
2383 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2384
2385 if (sctx->ps_shader == sel) {
2386 sctx->ps_shader = NULL;
2387 }
2388
2389 si_delete_shader_selector(ctx, sel);
2390 }
2391
2392 /*
2393 * Samplers
2394 */
2395
2396 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2397 struct pipe_resource *texture,
2398 const struct pipe_sampler_view *state)
2399 {
2400 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2401 struct r600_texture *tmp = (struct r600_texture*)texture;
2402 const struct util_format_description *desc;
2403 unsigned format, num_format;
2404 uint32_t pitch = 0;
2405 unsigned char state_swizzle[4], swizzle[4];
2406 unsigned height, depth, width;
2407 enum pipe_format pipe_format = state->format;
2408 struct radeon_surface_level *surflevel;
2409 int first_non_void;
2410 uint64_t va;
2411
2412 if (view == NULL)
2413 return NULL;
2414
2415 /* initialize base object */
2416 view->base = *state;
2417 view->base.texture = NULL;
2418 pipe_resource_reference(&view->base.texture, texture);
2419 view->base.reference.count = 1;
2420 view->base.context = ctx;
2421 view->resource = &tmp->resource;
2422
2423 /* Buffer resource. */
2424 if (texture->target == PIPE_BUFFER) {
2425 unsigned stride;
2426
2427 desc = util_format_description(state->format);
2428 first_non_void = util_format_get_first_non_void_channel(state->format);
2429 stride = desc->block.bits / 8;
2430 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2431 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2432 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2433
2434 view->state[0] = va;
2435 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2436 S_008F04_STRIDE(stride);
2437 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2438 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2439 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2440 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2441 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2442 S_008F0C_NUM_FORMAT(num_format) |
2443 S_008F0C_DATA_FORMAT(format);
2444 return &view->base;
2445 }
2446
2447 state_swizzle[0] = state->swizzle_r;
2448 state_swizzle[1] = state->swizzle_g;
2449 state_swizzle[2] = state->swizzle_b;
2450 state_swizzle[3] = state->swizzle_a;
2451
2452 surflevel = tmp->surface.level;
2453
2454 /* Texturing with separate depth and stencil. */
2455 if (tmp->is_depth && !tmp->is_flushing_texture) {
2456 switch (pipe_format) {
2457 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2458 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2459 break;
2460 case PIPE_FORMAT_X8Z24_UNORM:
2461 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2462 /* Z24 is always stored like this. */
2463 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2464 break;
2465 case PIPE_FORMAT_X24S8_UINT:
2466 case PIPE_FORMAT_S8X24_UINT:
2467 case PIPE_FORMAT_X32_S8X24_UINT:
2468 pipe_format = PIPE_FORMAT_S8_UINT;
2469 surflevel = tmp->surface.stencil_level;
2470 break;
2471 default:;
2472 }
2473 }
2474
2475 desc = util_format_description(pipe_format);
2476
2477 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2478 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2479 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2480
2481 switch (pipe_format) {
2482 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2483 case PIPE_FORMAT_X24S8_UINT:
2484 case PIPE_FORMAT_X32_S8X24_UINT:
2485 case PIPE_FORMAT_X8Z24_UNORM:
2486 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2487 break;
2488 default:
2489 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2490 }
2491 } else {
2492 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2493 }
2494
2495 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2496
2497 switch (pipe_format) {
2498 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2499 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2500 break;
2501 default:
2502 if (first_non_void < 0) {
2503 if (util_format_is_compressed(pipe_format)) {
2504 switch (pipe_format) {
2505 case PIPE_FORMAT_DXT1_SRGB:
2506 case PIPE_FORMAT_DXT1_SRGBA:
2507 case PIPE_FORMAT_DXT3_SRGBA:
2508 case PIPE_FORMAT_DXT5_SRGBA:
2509 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2510 break;
2511 case PIPE_FORMAT_RGTC1_SNORM:
2512 case PIPE_FORMAT_LATC1_SNORM:
2513 case PIPE_FORMAT_RGTC2_SNORM:
2514 case PIPE_FORMAT_LATC2_SNORM:
2515 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2516 break;
2517 default:
2518 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2519 break;
2520 }
2521 } else {
2522 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2523 }
2524 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2525 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2526 } else {
2527 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2528
2529 switch (desc->channel[first_non_void].type) {
2530 case UTIL_FORMAT_TYPE_FLOAT:
2531 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2532 break;
2533 case UTIL_FORMAT_TYPE_SIGNED:
2534 if (desc->channel[first_non_void].normalized)
2535 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2536 else if (desc->channel[first_non_void].pure_integer)
2537 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2538 else
2539 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2540 break;
2541 case UTIL_FORMAT_TYPE_UNSIGNED:
2542 if (desc->channel[first_non_void].normalized)
2543 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2544 else if (desc->channel[first_non_void].pure_integer)
2545 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2546 else
2547 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2548 }
2549 }
2550 }
2551
2552 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2553 if (format == ~0) {
2554 format = 0;
2555 }
2556
2557 /* not supported any more */
2558 //endian = si_colorformat_endian_swap(format);
2559
2560 width = surflevel[0].npix_x;
2561 height = surflevel[0].npix_y;
2562 depth = surflevel[0].npix_z;
2563 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2564
2565 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2566 height = 1;
2567 depth = texture->array_size;
2568 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2569 depth = texture->array_size;
2570 }
2571
2572 va = r600_resource_va(ctx->screen, texture);
2573 va += surflevel[0].offset;
2574 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2575 view->state[0] = va >> 8;
2576 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2577 S_008F14_DATA_FORMAT(format) |
2578 S_008F14_NUM_FORMAT(num_format));
2579 view->state[2] = (S_008F18_WIDTH(width - 1) |
2580 S_008F18_HEIGHT(height - 1));
2581 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2582 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2583 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2584 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2585 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2586 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2587 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2588 util_logbase2(texture->nr_samples) :
2589 state->u.tex.last_level - tmp->mipmap_shift) |
2590 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2591 S_008F1C_POW2_PAD(texture->last_level > 0) |
2592 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2593 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2594 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2595 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2596 view->state[6] = 0;
2597 view->state[7] = 0;
2598
2599 /* Initialize the sampler view for FMASK. */
2600 if (tmp->fmask.size) {
2601 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2602 uint32_t fmask_format;
2603
2604 switch (texture->nr_samples) {
2605 case 2:
2606 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2607 break;
2608 case 4:
2609 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2610 break;
2611 case 8:
2612 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2613 break;
2614 default:
2615 assert(0);
2616 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2617 }
2618
2619 view->fmask_state[0] = va >> 8;
2620 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2621 S_008F14_DATA_FORMAT(fmask_format) |
2622 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2623 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2624 S_008F18_HEIGHT(height - 1);
2625 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2626 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2627 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2628 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2629 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2630 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2631 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2632 S_008F20_PITCH(tmp->fmask.pitch - 1);
2633 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2634 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2635 view->fmask_state[6] = 0;
2636 view->fmask_state[7] = 0;
2637 }
2638
2639 return &view->base;
2640 }
2641
2642 static void si_sampler_view_destroy(struct pipe_context *ctx,
2643 struct pipe_sampler_view *state)
2644 {
2645 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2646
2647 pipe_resource_reference(&state->texture, NULL);
2648 FREE(resource);
2649 }
2650
2651 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2652 {
2653 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2654 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2655 (linear_filter &&
2656 (wrap == PIPE_TEX_WRAP_CLAMP ||
2657 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2658 }
2659
2660 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2661 {
2662 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2663 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2664
2665 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2666 state->border_color.ui[2] || state->border_color.ui[3]) &&
2667 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2668 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2669 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2670 }
2671
2672 static void *si_create_sampler_state(struct pipe_context *ctx,
2673 const struct pipe_sampler_state *state)
2674 {
2675 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2676 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2677 unsigned border_color_type;
2678
2679 if (rstate == NULL) {
2680 return NULL;
2681 }
2682
2683 if (sampler_state_needs_border_color(state))
2684 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2685 else
2686 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2687
2688 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2689 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2690 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2691 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2692 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2693 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2694 aniso_flag_offset << 16 | /* XXX */
2695 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2696 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2697 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2698 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2699 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2700 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2701 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2702 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2703
2704 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2705 memcpy(rstate->border_color, state->border_color.ui,
2706 sizeof(rstate->border_color));
2707 }
2708
2709 return rstate;
2710 }
2711
2712 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2713 * the si_set_sampler_view calls. LTO might help too. */
2714 static void si_set_sampler_views(struct pipe_context *ctx,
2715 unsigned shader, unsigned start,
2716 unsigned count,
2717 struct pipe_sampler_view **views)
2718 {
2719 struct si_context *sctx = (struct si_context *)ctx;
2720 struct si_textures_info *samplers = &sctx->samplers[shader];
2721 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2722 int i;
2723
2724 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2725 return;
2726
2727 assert(start == 0);
2728
2729 for (i = 0; i < count; i++) {
2730 if (!views[i]) {
2731 samplers->depth_texture_mask &= ~(1 << i);
2732 samplers->compressed_colortex_mask &= ~(1 << i);
2733 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2734 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2735 NULL, NULL);
2736 continue;
2737 }
2738
2739 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state);
2740
2741 if (views[i]->texture->target != PIPE_BUFFER) {
2742 struct r600_texture *rtex =
2743 (struct r600_texture*)views[i]->texture;
2744
2745 if (rtex->is_depth && !rtex->is_flushing_texture) {
2746 samplers->depth_texture_mask |= 1 << i;
2747 } else {
2748 samplers->depth_texture_mask &= ~(1 << i);
2749 }
2750 if (rtex->cmask.size || rtex->fmask.size) {
2751 samplers->compressed_colortex_mask |= 1 << i;
2752 } else {
2753 samplers->compressed_colortex_mask &= ~(1 << i);
2754 }
2755
2756 if (rtex->fmask.size) {
2757 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2758 views[i], rviews[i]->fmask_state);
2759 } else {
2760 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2761 NULL, NULL);
2762 }
2763 }
2764 }
2765 for (; i < samplers->n_views; i++) {
2766 samplers->depth_texture_mask &= ~(1 << i);
2767 samplers->compressed_colortex_mask &= ~(1 << i);
2768 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2769 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2770 NULL, NULL);
2771 }
2772
2773 samplers->n_views = count;
2774 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2775 }
2776
2777 static struct si_pm4_state *si_set_sampler_states(struct si_context *sctx, unsigned count,
2778 void **states,
2779 struct si_textures_info *samplers,
2780 unsigned user_data_reg)
2781 {
2782 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2783 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2784 uint32_t *border_color_table = NULL;
2785 int i, j;
2786
2787 if (!count)
2788 goto out;
2789
2790 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2791
2792 si_pm4_sh_data_begin(pm4);
2793 for (i = 0; i < count; i++) {
2794 if (rstates[i] &&
2795 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2796 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2797 if (!sctx->border_color_table ||
2798 ((sctx->border_color_offset + count - i) &
2799 C_008F3C_BORDER_COLOR_PTR)) {
2800 r600_resource_reference(&sctx->border_color_table, NULL);
2801 sctx->border_color_offset = 0;
2802
2803 sctx->border_color_table =
2804 si_resource_create_custom(&sctx->screen->b.b,
2805 PIPE_USAGE_STAGING,
2806 4096 * 4 * 4);
2807 }
2808
2809 if (!border_color_table) {
2810 border_color_table =
2811 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2812 sctx->b.rings.gfx.cs,
2813 PIPE_TRANSFER_WRITE |
2814 PIPE_TRANSFER_UNSYNCHRONIZED);
2815 }
2816
2817 for (j = 0; j < 4; j++) {
2818 border_color_table[4 * sctx->border_color_offset + j] =
2819 util_le32_to_cpu(rstates[i]->border_color[j]);
2820 }
2821
2822 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2823 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2824 }
2825
2826 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2827 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2828 }
2829 }
2830 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2831
2832 if (border_color_table) {
2833 uint64_t va_offset =
2834 r600_resource_va(&sctx->screen->b.b,
2835 (void*)sctx->border_color_table);
2836
2837 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2838 if (sctx->b.chip_class >= CIK)
2839 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2840 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
2841 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ);
2842 }
2843
2844 memcpy(samplers->samplers, states, sizeof(void*) * count);
2845
2846 out:
2847 samplers->n_samplers = count;
2848 return pm4;
2849 }
2850
2851 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2852 {
2853 struct si_context *sctx = (struct si_context *)ctx;
2854 struct si_pm4_state *pm4;
2855
2856 pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_VERTEX],
2857 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2858 si_pm4_set_state(sctx, vs_sampler, pm4);
2859 }
2860
2861 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2862 {
2863 struct si_context *sctx = (struct si_context *)ctx;
2864 struct si_pm4_state *pm4;
2865
2866 pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_FRAGMENT],
2867 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2868 si_pm4_set_state(sctx, ps_sampler, pm4);
2869 }
2870
2871
2872 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2873 unsigned start, unsigned count,
2874 void **states)
2875 {
2876 assert(start == 0);
2877
2878 switch (shader) {
2879 case PIPE_SHADER_VERTEX:
2880 si_bind_vs_sampler_states(ctx, count, states);
2881 break;
2882 case PIPE_SHADER_FRAGMENT:
2883 si_bind_ps_sampler_states(ctx, count, states);
2884 break;
2885 default:
2886 ;
2887 }
2888 }
2889
2890
2891
2892 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2893 {
2894 struct si_context *sctx = (struct si_context *)ctx;
2895 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2896 uint16_t mask = sample_mask;
2897
2898 if (pm4 == NULL)
2899 return;
2900
2901 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2902 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2903
2904 si_pm4_set_state(sctx, sample_mask, pm4);
2905 }
2906
2907 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2908 {
2909 free(state);
2910 }
2911
2912 /*
2913 * Vertex elements & buffers
2914 */
2915
2916 static void *si_create_vertex_elements(struct pipe_context *ctx,
2917 unsigned count,
2918 const struct pipe_vertex_element *elements)
2919 {
2920 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2921 int i;
2922
2923 assert(count < PIPE_MAX_ATTRIBS);
2924 if (!v)
2925 return NULL;
2926
2927 v->count = count;
2928 for (i = 0; i < count; ++i) {
2929 const struct util_format_description *desc;
2930 unsigned data_format, num_format;
2931 int first_non_void;
2932
2933 desc = util_format_description(elements[i].src_format);
2934 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2935 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2936 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2937
2938 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2939 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2940 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2941 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2942 S_008F0C_NUM_FORMAT(num_format) |
2943 S_008F0C_DATA_FORMAT(data_format);
2944 }
2945 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2946
2947 return v;
2948 }
2949
2950 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2951 {
2952 struct si_context *sctx = (struct si_context *)ctx;
2953 struct si_vertex_element *v = (struct si_vertex_element*)state;
2954
2955 sctx->vertex_elements = v;
2956 }
2957
2958 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2959 {
2960 struct si_context *sctx = (struct si_context *)ctx;
2961
2962 if (sctx->vertex_elements == state)
2963 sctx->vertex_elements = NULL;
2964 FREE(state);
2965 }
2966
2967 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2968 const struct pipe_vertex_buffer *buffers)
2969 {
2970 struct si_context *sctx = (struct si_context *)ctx;
2971
2972 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count);
2973 }
2974
2975 static void si_set_index_buffer(struct pipe_context *ctx,
2976 const struct pipe_index_buffer *ib)
2977 {
2978 struct si_context *sctx = (struct si_context *)ctx;
2979
2980 if (ib) {
2981 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2982 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2983 } else {
2984 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2985 }
2986 }
2987
2988 /*
2989 * Misc
2990 */
2991 static void si_set_polygon_stipple(struct pipe_context *ctx,
2992 const struct pipe_poly_stipple *state)
2993 {
2994 }
2995
2996 static void si_texture_barrier(struct pipe_context *ctx)
2997 {
2998 struct si_context *sctx = (struct si_context *)ctx;
2999
3000 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
3001 R600_CONTEXT_FLUSH_AND_INV_CB;
3002 }
3003
3004 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3005 {
3006 struct pipe_blend_state blend;
3007
3008 memset(&blend, 0, sizeof(blend));
3009 blend.independent_blend_enable = true;
3010 blend.rt[0].colormask = 0xf;
3011 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3012 }
3013
3014 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
3015 struct pipe_resource *texture,
3016 const struct pipe_surface *surf_tmpl)
3017 {
3018 struct r600_texture *rtex = (struct r600_texture*)texture;
3019 struct si_surface *surface = CALLOC_STRUCT(si_surface);
3020 unsigned level = surf_tmpl->u.tex.level;
3021
3022 if (surface == NULL)
3023 return NULL;
3024
3025 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3026 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3027
3028 pipe_reference_init(&surface->base.reference, 1);
3029 pipe_resource_reference(&surface->base.texture, texture);
3030 surface->base.context = pipe;
3031 surface->base.format = surf_tmpl->format;
3032 surface->base.width = rtex->surface.level[level].npix_x;
3033 surface->base.height = rtex->surface.level[level].npix_y;
3034 surface->base.texture = texture;
3035 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3036 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3037 surface->base.u.tex.level = level;
3038
3039 return &surface->base;
3040 }
3041
3042 static void r600_surface_destroy(struct pipe_context *pipe,
3043 struct pipe_surface *surface)
3044 {
3045 pipe_resource_reference(&surface->texture, NULL);
3046 FREE(surface);
3047 }
3048
3049 static boolean si_dma_copy(struct pipe_context *ctx,
3050 struct pipe_resource *dst,
3051 unsigned dst_level,
3052 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3053 struct pipe_resource *src,
3054 unsigned src_level,
3055 const struct pipe_box *src_box)
3056 {
3057 /* XXX implement this or share evergreen_dma_blit with r600g */
3058 return FALSE;
3059 }
3060
3061 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
3062 {
3063 /* XXX Turn this into a proper state. Right now the queries are
3064 * enabled in draw_vbo, which snoops r600_common_context to see
3065 * if any occlusion queries are active. */
3066 }
3067
3068 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3069 bool include_draw_vbo)
3070 {
3071 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3072 }
3073
3074 void si_init_state_functions(struct si_context *sctx)
3075 {
3076 int i;
3077
3078 sctx->b.b.create_blend_state = si_create_blend_state;
3079 sctx->b.b.bind_blend_state = si_bind_blend_state;
3080 sctx->b.b.delete_blend_state = si_delete_blend_state;
3081 sctx->b.b.set_blend_color = si_set_blend_color;
3082
3083 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3084 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3085 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3086
3087 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3088 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3089 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3090
3091 for (i = 0; i < 8; i++) {
3092 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
3093 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
3094 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
3095 }
3096 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
3097 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3098 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3099
3100 sctx->b.b.set_clip_state = si_set_clip_state;
3101 sctx->b.b.set_scissor_states = si_set_scissor_states;
3102 sctx->b.b.set_viewport_states = si_set_viewport_states;
3103 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3104
3105 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3106 sctx->b.b.get_sample_position = si_get_sample_position;
3107
3108 sctx->b.b.create_vs_state = si_create_vs_state;
3109 sctx->b.b.create_fs_state = si_create_fs_state;
3110 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3111 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3112 sctx->b.b.delete_vs_state = si_delete_vs_shader;
3113 sctx->b.b.delete_fs_state = si_delete_ps_shader;
3114
3115 sctx->b.b.create_sampler_state = si_create_sampler_state;
3116 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3117 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3118
3119 sctx->b.b.create_sampler_view = si_create_sampler_view;
3120 sctx->b.b.set_sampler_views = si_set_sampler_views;
3121 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3122
3123 sctx->b.b.set_sample_mask = si_set_sample_mask;
3124
3125 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3126 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3127 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3128 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3129 sctx->b.b.set_index_buffer = si_set_index_buffer;
3130
3131 sctx->b.b.texture_barrier = si_texture_barrier;
3132 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3133 sctx->b.b.create_surface = r600_create_surface;
3134 sctx->b.b.surface_destroy = r600_surface_destroy;
3135 sctx->b.dma_copy = si_dma_copy;
3136 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3137 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3138
3139 sctx->b.b.draw_vbo = si_draw_vbo;
3140 }
3141
3142 void si_init_config(struct si_context *sctx)
3143 {
3144 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3145
3146 if (pm4 == NULL)
3147 return;
3148
3149 si_cmd_context_control(pm4);
3150
3151 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3152
3153 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3154 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3155 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3156 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3157 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3158 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3159 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3160 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3161 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3162 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3163 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3164 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3165 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3166 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3167 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3168 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3169 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3170 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3171 if (sctx->b.chip_class == SI) {
3172 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3173 S_028AA8_SWITCH_ON_EOP(1) |
3174 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3175 S_028AA8_PRIMGROUP_SIZE(63));
3176 }
3177 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3178 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3179 if (sctx->b.chip_class < CIK)
3180 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3181 S_008A14_CLIP_VTX_REORDER_ENA(1));
3182
3183 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3184 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3185 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3186
3187 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3188
3189 if (sctx->b.chip_class >= CIK) {
3190 switch (sctx->screen->b.family) {
3191 case CHIP_BONAIRE:
3192 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3193 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3194 break;
3195 case CHIP_HAWAII:
3196 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3197 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3198 break;
3199 case CHIP_KAVERI:
3200 /* XXX todo */
3201 case CHIP_KABINI:
3202 /* XXX todo */
3203 default:
3204 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3205 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3206 break;
3207 }
3208 } else {
3209 switch (sctx->screen->b.family) {
3210 case CHIP_TAHITI:
3211 case CHIP_PITCAIRN:
3212 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3213 break;
3214 case CHIP_VERDE:
3215 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3216 break;
3217 case CHIP_OLAND:
3218 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3219 break;
3220 case CHIP_HAINAN:
3221 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3222 break;
3223 default:
3224 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3225 break;
3226 }
3227 }
3228
3229 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3230 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3231 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3232 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3233 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3234 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3235 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3236
3237 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3238 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3239 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3240 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3241 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3242 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3243 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3244 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3245 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3246 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3247 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3248 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3249 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3250 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3251 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3252 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3253 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3254 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3255 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3256 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3257 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3258 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3259
3260 if (sctx->b.chip_class >= CIK) {
3261 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3262 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3263 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3264 }
3265
3266 si_pm4_set_state(sctx, init, pm4);
3267 }