2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 unsigned img_format
:9;
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
46 #include "gfx10_format_table.h"
48 static unsigned si_map_swizzle(unsigned swizzle
)
52 return V_008F0C_SQ_SEL_Y
;
54 return V_008F0C_SQ_SEL_Z
;
56 return V_008F0C_SQ_SEL_W
;
58 return V_008F0C_SQ_SEL_0
;
60 return V_008F0C_SQ_SEL_1
;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X
;
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x
)
70 x
>= 4096 ? 0xffff : x
* 16;
74 * Inferred framebuffer and blender state.
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
79 static void si_emit_cb_render_state(struct si_context
*sctx
)
81 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
82 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
89 cb_target_mask
&= blend
->cb_target_mask
;
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
97 if (blend
&& blend
->dual_src_blend
&&
98 sctx
->ps_shader
.cso
&&
99 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
105 if (sctx
->screen
->dpbb_allowed
&&
106 sctx
->last_cb_target_mask
!= cb_target_mask
) {
107 sctx
->last_cb_target_mask
= cb_target_mask
;
109 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
110 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
113 unsigned initial_cdw
= cs
->current
.cdw
;
114 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
115 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
117 if (sctx
->chip_class
>= GFX8
) {
118 /* DCC MSAA workaround.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
122 bool oc_disable
= blend
&&
123 blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&&
124 sctx
->framebuffer
.nr_samples
>= 2;
125 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
127 radeon_opt_set_context_reg(
128 sctx
, R_028424_CB_DCC_CONTROL
,
129 SI_TRACKED_CB_DCC_CONTROL
,
130 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
131 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
132 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
133 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->has_dcc_constant_encode
));
136 /* RB+ register settings. */
137 if (sctx
->screen
->rbplus_allowed
) {
138 unsigned spi_shader_col_format
=
139 sctx
->ps_shader
.cso
?
140 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
141 unsigned sx_ps_downconvert
= 0;
142 unsigned sx_blend_opt_epsilon
= 0;
143 unsigned sx_blend_opt_control
= 0;
145 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
146 struct si_surface
*surf
=
147 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
148 unsigned format
, swap
, spi_format
, colormask
;
149 bool has_alpha
, has_rgb
;
152 /* If the color buffer is not set, the driver sets 32_R
153 * as the SPI color format, because the hw doesn't allow
154 * holes between color outputs, so also set this to
157 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
161 format
= G_028C70_FORMAT(surf
->cb_color_info
);
162 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
163 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
164 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
166 /* Set if RGB and A are present. */
167 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
169 if (format
== V_028C70_COLOR_8
||
170 format
== V_028C70_COLOR_16
||
171 format
== V_028C70_COLOR_32
)
172 has_rgb
= !has_alpha
;
176 /* Check the colormask and export format. */
177 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
179 if (!(colormask
& PIPE_MASK_A
))
182 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
187 /* Disable value checking for disabled channels. */
189 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
191 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
193 /* Enable down-conversion for 32bpp and smaller formats. */
195 case V_028C70_COLOR_8
:
196 case V_028C70_COLOR_8_8
:
197 case V_028C70_COLOR_8_8_8_8
:
198 /* For 1 and 2-channel formats, use the superset thereof. */
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
200 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
201 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
202 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
203 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
207 case V_028C70_COLOR_5_6_5
:
208 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
209 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
210 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
214 case V_028C70_COLOR_1_5_5_5
:
215 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
216 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
217 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
221 case V_028C70_COLOR_4_4_4_4
:
222 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
224 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
228 case V_028C70_COLOR_32
:
229 if (swap
== V_028C70_SWAP_STD
&&
230 spi_format
== V_028714_SPI_SHADER_32_R
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
232 else if (swap
== V_028C70_SWAP_ALT_REV
&&
233 spi_format
== V_028714_SPI_SHADER_32_AR
)
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
237 case V_028C70_COLOR_16
:
238 case V_028C70_COLOR_16_16
:
239 /* For 1-channel formats, use the superset thereof. */
240 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
241 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
242 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
243 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
244 if (swap
== V_028C70_SWAP_STD
||
245 swap
== V_028C70_SWAP_STD_REV
)
246 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
248 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
252 case V_028C70_COLOR_10_11_11
:
253 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
254 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
257 case V_028C70_COLOR_2_10_10_10
:
258 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
259 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
260 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
266 /* If there are no color outputs, the first color export is
267 * always enabled as 32_R, so also set this to enable RB+.
269 if (!sx_ps_downconvert
)
270 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
272 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
273 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
274 SI_TRACKED_SX_PS_DOWNCONVERT
,
275 sx_ps_downconvert
, sx_blend_opt_epsilon
,
276 sx_blend_opt_control
);
278 if (initial_cdw
!= cs
->current
.cdw
)
279 sctx
->context_roll
= true;
286 static uint32_t si_translate_blend_function(int blend_func
)
288 switch (blend_func
) {
290 return V_028780_COMB_DST_PLUS_SRC
;
291 case PIPE_BLEND_SUBTRACT
:
292 return V_028780_COMB_SRC_MINUS_DST
;
293 case PIPE_BLEND_REVERSE_SUBTRACT
:
294 return V_028780_COMB_DST_MINUS_SRC
;
296 return V_028780_COMB_MIN_DST_SRC
;
298 return V_028780_COMB_MAX_DST_SRC
;
300 PRINT_ERR("Unknown blend function %d\n", blend_func
);
307 static uint32_t si_translate_blend_factor(int blend_fact
)
309 switch (blend_fact
) {
310 case PIPE_BLENDFACTOR_ONE
:
311 return V_028780_BLEND_ONE
;
312 case PIPE_BLENDFACTOR_SRC_COLOR
:
313 return V_028780_BLEND_SRC_COLOR
;
314 case PIPE_BLENDFACTOR_SRC_ALPHA
:
315 return V_028780_BLEND_SRC_ALPHA
;
316 case PIPE_BLENDFACTOR_DST_ALPHA
:
317 return V_028780_BLEND_DST_ALPHA
;
318 case PIPE_BLENDFACTOR_DST_COLOR
:
319 return V_028780_BLEND_DST_COLOR
;
320 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
321 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
322 case PIPE_BLENDFACTOR_CONST_COLOR
:
323 return V_028780_BLEND_CONSTANT_COLOR
;
324 case PIPE_BLENDFACTOR_CONST_ALPHA
:
325 return V_028780_BLEND_CONSTANT_ALPHA
;
326 case PIPE_BLENDFACTOR_ZERO
:
327 return V_028780_BLEND_ZERO
;
328 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
330 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
331 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
332 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
333 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
334 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
335 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
336 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
337 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
338 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
340 case PIPE_BLENDFACTOR_SRC1_COLOR
:
341 return V_028780_BLEND_SRC1_COLOR
;
342 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
343 return V_028780_BLEND_SRC1_ALPHA
;
344 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
345 return V_028780_BLEND_INV_SRC1_COLOR
;
346 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
347 return V_028780_BLEND_INV_SRC1_ALPHA
;
349 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
356 static uint32_t si_translate_blend_opt_function(int blend_func
)
358 switch (blend_func
) {
360 return V_028760_OPT_COMB_ADD
;
361 case PIPE_BLEND_SUBTRACT
:
362 return V_028760_OPT_COMB_SUBTRACT
;
363 case PIPE_BLEND_REVERSE_SUBTRACT
:
364 return V_028760_OPT_COMB_REVSUBTRACT
;
366 return V_028760_OPT_COMB_MIN
;
368 return V_028760_OPT_COMB_MAX
;
370 return V_028760_OPT_COMB_BLEND_DISABLED
;
374 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
376 switch (blend_fact
) {
377 case PIPE_BLENDFACTOR_ZERO
:
378 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
379 case PIPE_BLENDFACTOR_ONE
:
380 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
381 case PIPE_BLENDFACTOR_SRC_COLOR
:
382 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
383 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
384 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
385 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
386 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
387 case PIPE_BLENDFACTOR_SRC_ALPHA
:
388 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
389 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
390 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
391 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
392 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
393 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
395 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
399 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
400 struct si_state_blend
*blend
,
401 enum pipe_blend_func func
,
402 enum pipe_blendfactor src
,
403 enum pipe_blendfactor dst
,
406 /* Src factor is allowed when it does not depend on Dst */
407 static const uint32_t src_allowed
=
408 (1u << PIPE_BLENDFACTOR_ONE
) |
409 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
412 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
413 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
414 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_ZERO
) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
419 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
420 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
421 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
422 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
424 if (dst
== PIPE_BLENDFACTOR_ONE
&&
425 (src_allowed
& (1u << src
))) {
426 /* Addition is commutative, but floating point addition isn't
427 * associative: subtle changes can be introduced via different
430 * Out-of-order is also non-deterministic, which means that
431 * this breaks OpenGL invariance requirements. So only enable
432 * out-of-order additive blending if explicitly allowed by a
435 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
436 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
437 blend
->commutative_4bit
|= chanmask
;
442 * Get rid of DST in the blend factors by commuting the operands:
443 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
445 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
446 unsigned *dst_factor
, unsigned expected_dst
,
447 unsigned replacement_src
)
449 if (*src_factor
== expected_dst
&&
450 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
451 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
452 *dst_factor
= replacement_src
;
454 /* Commuting the operands requires reversing subtractions. */
455 if (*func
== PIPE_BLEND_SUBTRACT
)
456 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
457 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
458 *func
= PIPE_BLEND_SUBTRACT
;
462 static bool si_blend_factor_uses_dst(unsigned factor
)
464 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
465 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
466 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
467 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
468 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
471 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
472 const struct pipe_blend_state
*state
,
475 struct si_context
*sctx
= (struct si_context
*)ctx
;
476 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
477 struct si_pm4_state
*pm4
= &blend
->pm4
;
478 uint32_t sx_mrt_blend_opt
[8] = {0};
479 uint32_t color_control
= 0;
480 bool logicop_enable
= state
->logicop_enable
&&
481 state
->logicop_func
!= PIPE_LOGICOP_COPY
;
486 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
487 blend
->alpha_to_one
= state
->alpha_to_one
;
488 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
489 blend
->logicop_enable
= logicop_enable
;
491 if (logicop_enable
) {
492 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
494 color_control
|= S_028808_ROP3(0xcc);
497 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
498 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
499 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
500 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
501 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
502 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
503 S_028B70_OFFSET_ROUND(1));
505 if (state
->alpha_to_coverage
)
506 blend
->need_src_alpha_4bit
|= 0xf;
508 blend
->cb_target_mask
= 0;
509 blend
->cb_target_enabled_4bit
= 0;
511 for (int i
= 0; i
< 8; i
++) {
512 /* state->rt entries > 0 only written if independent blending */
513 const int j
= state
->independent_blend_enable
? i
: 0;
515 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
516 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
517 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
518 unsigned eqA
= state
->rt
[j
].alpha_func
;
519 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
520 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
522 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
523 unsigned blend_cntl
= 0;
525 sx_mrt_blend_opt
[i
] =
526 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
527 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
529 /* Only set dual source blending for MRT0 to avoid a hang. */
530 if (i
>= 1 && blend
->dual_src_blend
) {
531 /* Vulkan does this for dual source blending. */
533 blend_cntl
|= S_028780_ENABLE(1);
535 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
539 /* Only addition and subtraction equations are supported with
540 * dual source blending.
542 if (blend
->dual_src_blend
&&
543 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
544 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
545 assert(!"Unsupported equation for dual source blending");
546 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
550 /* cb_render_state will disable unused ones */
551 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
552 if (state
->rt
[j
].colormask
)
553 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
555 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
556 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
560 si_blend_check_commutativity(sctx
->screen
, blend
,
561 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
562 si_blend_check_commutativity(sctx
->screen
, blend
,
563 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
565 /* Blending optimizations for RB+.
566 * These transformations don't change the behavior.
568 * First, get rid of DST in the blend factors:
569 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
571 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
572 PIPE_BLENDFACTOR_DST_COLOR
,
573 PIPE_BLENDFACTOR_SRC_COLOR
);
574 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
575 PIPE_BLENDFACTOR_DST_COLOR
,
576 PIPE_BLENDFACTOR_SRC_COLOR
);
577 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
578 PIPE_BLENDFACTOR_DST_ALPHA
,
579 PIPE_BLENDFACTOR_SRC_ALPHA
);
581 /* Look up the ideal settings from tables. */
582 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
583 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
584 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
585 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
587 /* Handle interdependencies. */
588 if (si_blend_factor_uses_dst(srcRGB
))
589 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
590 if (si_blend_factor_uses_dst(srcA
))
591 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
593 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
594 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
595 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
596 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
597 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
599 /* Set the final value. */
600 sx_mrt_blend_opt
[i
] =
601 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
602 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
603 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
604 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
605 S_028760_ALPHA_DST_OPT(dstA_opt
) |
606 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
608 /* Set blend state. */
609 blend_cntl
|= S_028780_ENABLE(1);
610 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
611 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
612 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
614 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
615 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
616 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
617 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
618 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
620 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
622 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
624 if (sctx
->family
<= CHIP_NAVI14
)
625 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
627 /* This is only important for formats without alpha. */
628 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
629 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
630 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
631 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
632 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
633 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
634 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
637 if (sctx
->family
<= CHIP_NAVI14
&& logicop_enable
)
638 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
640 if (blend
->cb_target_mask
) {
641 color_control
|= S_028808_MODE(mode
);
643 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
646 if (sctx
->screen
->rbplus_allowed
) {
647 /* Disable RB+ blend optimizations for dual source blending.
650 if (blend
->dual_src_blend
) {
651 for (int i
= 0; i
< 8; i
++) {
652 sx_mrt_blend_opt
[i
] =
653 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
654 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
658 for (int i
= 0; i
< 8; i
++)
659 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
660 sx_mrt_blend_opt
[i
]);
662 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
663 if (blend
->dual_src_blend
|| logicop_enable
||
664 mode
== V_028808_CB_RESOLVE
)
665 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
668 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
672 static void *si_create_blend_state(struct pipe_context
*ctx
,
673 const struct pipe_blend_state
*state
)
675 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
678 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
680 struct si_context
*sctx
= (struct si_context
*)ctx
;
681 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
682 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
687 si_pm4_bind_state(sctx
, blend
, state
);
690 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
691 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
692 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
693 sctx
->framebuffer
.nr_samples
>= 2 &&
694 sctx
->screen
->dcc_msaa_allowed
))
695 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
698 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
699 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
700 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
701 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
702 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
703 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
704 sctx
->do_update_shaders
= true;
706 if (sctx
->screen
->dpbb_allowed
&&
708 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
709 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
710 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
711 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
713 if (sctx
->screen
->has_out_of_order_rast
&&
715 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
716 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
717 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
718 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
719 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
722 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
724 struct si_context
*sctx
= (struct si_context
*)ctx
;
725 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
728 static void si_set_blend_color(struct pipe_context
*ctx
,
729 const struct pipe_blend_color
*state
)
731 struct si_context
*sctx
= (struct si_context
*)ctx
;
732 static const struct pipe_blend_color zeros
;
734 sctx
->blend_color
.state
= *state
;
735 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
736 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
739 static void si_emit_blend_color(struct si_context
*sctx
)
741 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
743 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
744 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
751 static void si_set_clip_state(struct pipe_context
*ctx
,
752 const struct pipe_clip_state
*state
)
754 struct si_context
*sctx
= (struct si_context
*)ctx
;
755 struct pipe_constant_buffer cb
;
756 static const struct pipe_clip_state zeros
;
758 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
761 sctx
->clip_state
.state
= *state
;
762 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
763 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
766 cb
.user_buffer
= state
->ucp
;
767 cb
.buffer_offset
= 0;
768 cb
.buffer_size
= 4*4*8;
769 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
770 pipe_resource_reference(&cb
.buffer
, NULL
);
773 static void si_emit_clip_state(struct si_context
*sctx
)
775 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
777 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
778 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
781 static void si_emit_clip_regs(struct si_context
*sctx
)
783 struct si_shader
*vs
= si_get_vs_state(sctx
);
784 struct si_shader_selector
*vs_sel
= vs
->selector
;
785 struct tgsi_shader_info
*info
= &vs_sel
->info
;
786 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
787 unsigned window_space
=
788 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
789 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
790 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
791 unsigned culldist_mask
= vs_sel
->culldist_mask
;
794 if (vs
->key
.opt
.clip_disable
) {
795 assert(!info
->culldist_writemask
);
799 total_mask
= clipdist_mask
| culldist_mask
;
801 /* Clip distances on points have no effect, so need to be implemented
802 * as cull distances. This applies for the clipvertex case as well.
804 * Setting this for primitives other than points should have no adverse
807 clipdist_mask
&= rs
->clip_plane_enable
;
808 culldist_mask
|= clipdist_mask
;
810 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
811 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
812 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
813 vs_sel
->pa_cl_vs_out_cntl
|
814 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
815 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
816 clipdist_mask
| (culldist_mask
<< 8));
817 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
818 SI_TRACKED_PA_CL_CLIP_CNTL
,
819 rs
->pa_cl_clip_cntl
|
821 S_028810_CLIP_DISABLE(window_space
));
823 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
824 sctx
->context_roll
= true;
828 * inferred state between framebuffer and rasterizer
830 static void si_update_poly_offset_state(struct si_context
*sctx
)
832 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
834 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
835 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
839 /* Use the user format, not db_render_format, so that the polygon
840 * offset behaves as expected by applications.
842 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
843 case PIPE_FORMAT_Z16_UNORM
:
844 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
846 default: /* 24-bit */
847 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
849 case PIPE_FORMAT_Z32_FLOAT
:
850 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
851 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
860 static uint32_t si_translate_fill(uint32_t func
)
863 case PIPE_POLYGON_MODE_FILL
:
864 return V_028814_X_DRAW_TRIANGLES
;
865 case PIPE_POLYGON_MODE_LINE
:
866 return V_028814_X_DRAW_LINES
;
867 case PIPE_POLYGON_MODE_POINT
:
868 return V_028814_X_DRAW_POINTS
;
871 return V_028814_X_DRAW_POINTS
;
875 static void *si_create_rs_state(struct pipe_context
*ctx
,
876 const struct pipe_rasterizer_state
*state
)
878 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
879 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
880 struct si_pm4_state
*pm4
= &rs
->pm4
;
882 float psize_min
, psize_max
;
888 if (!state
->front_ccw
) {
889 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
890 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
892 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
893 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
895 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
896 rs
->provoking_vertex_first
= state
->flatshade_first
;
897 rs
->scissor_enable
= state
->scissor
;
898 rs
->clip_halfz
= state
->clip_halfz
;
899 rs
->two_side
= state
->light_twoside
;
900 rs
->multisample_enable
= state
->multisample
;
901 rs
->force_persample_interp
= state
->force_persample_interp
;
902 rs
->clip_plane_enable
= state
->clip_plane_enable
;
903 rs
->half_pixel_center
= state
->half_pixel_center
;
904 rs
->line_stipple_enable
= state
->line_stipple_enable
;
905 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
906 rs
->line_smooth
= state
->line_smooth
;
907 rs
->line_width
= state
->line_width
;
908 rs
->poly_smooth
= state
->poly_smooth
;
909 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
911 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
912 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
913 rs
->flatshade
= state
->flatshade
;
914 rs
->flatshade_first
= state
->flatshade_first
;
915 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
916 rs
->rasterizer_discard
= state
->rasterizer_discard
;
917 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
918 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
919 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
920 rs
->pa_cl_clip_cntl
=
921 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
922 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
923 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
924 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
925 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
927 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
928 S_0286D4_FLAT_SHADE_ENA(1) |
929 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
930 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
931 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
932 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
933 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
934 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
936 /* point size 12.4 fixed point */
937 tmp
= (unsigned)(state
->point_size
* 8.0);
938 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
940 if (state
->point_size_per_vertex
) {
941 psize_min
= util_get_min_point_size(state
);
942 psize_max
= SI_MAX_POINT_SIZE
;
944 /* Force the point size to be as if the vertex output was disabled. */
945 psize_min
= state
->point_size
;
946 psize_max
= state
->point_size
;
948 rs
->max_point_size
= psize_max
;
950 /* Divide by two, because 0.5 = 1 pixel. */
951 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
952 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
953 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
955 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
956 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
957 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
958 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
959 S_028A48_MSAA_ENABLE(state
->multisample
||
960 state
->poly_smooth
||
961 state
->line_smooth
) |
962 S_028A48_VPORT_SCISSOR_ENABLE(1) |
963 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
965 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
966 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
967 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
968 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
969 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
970 S_028814_FACE(!state
->front_ccw
) |
971 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
972 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
973 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
974 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
975 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
976 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
977 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
979 if (!rs
->uses_poly_offset
)
982 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
983 if (!rs
->pm4_poly_offset
) {
988 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
989 for (i
= 0; i
< 3; i
++) {
990 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
991 float offset_units
= state
->offset_units
;
992 float offset_scale
= state
->offset_scale
* 16.0f
;
993 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
995 if (!state
->offset_units_unscaled
) {
997 case 0: /* 16-bit zbuffer */
998 offset_units
*= 4.0f
;
999 pa_su_poly_offset_db_fmt_cntl
=
1000 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1002 case 1: /* 24-bit zbuffer */
1003 offset_units
*= 2.0f
;
1004 pa_su_poly_offset_db_fmt_cntl
=
1005 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1007 case 2: /* 32-bit zbuffer */
1008 offset_units
*= 1.0f
;
1009 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1010 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1015 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1017 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1019 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1021 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1023 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1024 pa_su_poly_offset_db_fmt_cntl
);
1030 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1032 struct si_context
*sctx
= (struct si_context
*)ctx
;
1033 struct si_state_rasterizer
*old_rs
=
1034 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1035 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1040 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1041 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1043 /* Update the small primitive filter workaround if necessary. */
1044 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1045 sctx
->framebuffer
.nr_samples
> 1)
1046 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1049 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1050 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1052 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1053 si_update_poly_offset_state(sctx
);
1056 old_rs
->scissor_enable
!= rs
->scissor_enable
)
1057 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1060 old_rs
->line_width
!= rs
->line_width
||
1061 old_rs
->max_point_size
!= rs
->max_point_size
||
1062 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1063 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1066 old_rs
->clip_halfz
!= rs
->clip_halfz
)
1067 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1070 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1071 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1072 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1074 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1075 rs
->line_stipple_enable
;
1078 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1079 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1080 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1081 old_rs
->flatshade
!= rs
->flatshade
||
1082 old_rs
->two_side
!= rs
->two_side
||
1083 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1084 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1085 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1086 old_rs
->line_smooth
!= rs
->line_smooth
||
1087 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1088 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1089 sctx
->do_update_shaders
= true;
1092 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1094 struct si_context
*sctx
= (struct si_context
*)ctx
;
1095 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1097 if (sctx
->queued
.named
.rasterizer
== state
)
1098 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1100 FREE(rs
->pm4_poly_offset
);
1101 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1105 * infeered state between dsa and stencil ref
1107 static void si_emit_stencil_ref(struct si_context
*sctx
)
1109 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1110 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1111 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1113 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1114 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1115 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1116 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1117 S_028430_STENCILOPVAL(1));
1118 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1119 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1120 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1121 S_028434_STENCILOPVAL_BF(1));
1124 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1125 const struct pipe_stencil_ref
*state
)
1127 struct si_context
*sctx
= (struct si_context
*)ctx
;
1129 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1132 sctx
->stencil_ref
.state
= *state
;
1133 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1141 static uint32_t si_translate_stencil_op(int s_op
)
1144 case PIPE_STENCIL_OP_KEEP
:
1145 return V_02842C_STENCIL_KEEP
;
1146 case PIPE_STENCIL_OP_ZERO
:
1147 return V_02842C_STENCIL_ZERO
;
1148 case PIPE_STENCIL_OP_REPLACE
:
1149 return V_02842C_STENCIL_REPLACE_TEST
;
1150 case PIPE_STENCIL_OP_INCR
:
1151 return V_02842C_STENCIL_ADD_CLAMP
;
1152 case PIPE_STENCIL_OP_DECR
:
1153 return V_02842C_STENCIL_SUB_CLAMP
;
1154 case PIPE_STENCIL_OP_INCR_WRAP
:
1155 return V_02842C_STENCIL_ADD_WRAP
;
1156 case PIPE_STENCIL_OP_DECR_WRAP
:
1157 return V_02842C_STENCIL_SUB_WRAP
;
1158 case PIPE_STENCIL_OP_INVERT
:
1159 return V_02842C_STENCIL_INVERT
;
1161 PRINT_ERR("Unknown stencil op %d", s_op
);
1168 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1170 return s
->enabled
&& s
->writemask
&&
1171 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1172 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1173 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1176 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1178 /* REPLACE is normally order invariant, except when the stencil
1179 * reference value is written by the fragment shader. Tracking this
1180 * interaction does not seem worth the effort, so be conservative. */
1181 return op
!= PIPE_STENCIL_OP_INCR
&&
1182 op
!= PIPE_STENCIL_OP_DECR
&&
1183 op
!= PIPE_STENCIL_OP_REPLACE
;
1186 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1187 * invariant in the sense that the set of passing fragments as well as the
1188 * final stencil buffer result does not depend on the order of fragments. */
1189 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1191 return !state
->enabled
|| !state
->writemask
||
1192 /* The following assumes that Z writes are disabled. */
1193 (state
->func
== PIPE_FUNC_ALWAYS
&&
1194 si_order_invariant_stencil_op(state
->zpass_op
) &&
1195 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1196 (state
->func
== PIPE_FUNC_NEVER
&&
1197 si_order_invariant_stencil_op(state
->fail_op
));
1200 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1201 const struct pipe_depth_stencil_alpha_state
*state
)
1203 struct si_context
*sctx
= (struct si_context
*)ctx
;
1204 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1205 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1206 unsigned db_depth_control
;
1207 uint32_t db_stencil_control
= 0;
1213 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1214 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1215 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1216 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1218 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1219 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1220 S_028800_ZFUNC(state
->depth
.func
) |
1221 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1224 if (state
->stencil
[0].enabled
) {
1225 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1226 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1227 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1228 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1229 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1231 if (state
->stencil
[1].enabled
) {
1232 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1233 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1234 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1235 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1236 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1241 if (state
->alpha
.enabled
) {
1242 dsa
->alpha_func
= state
->alpha
.func
;
1244 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1245 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1247 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1250 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1251 if (state
->stencil
[0].enabled
)
1252 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1253 if (state
->depth
.bounds_test
) {
1254 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1255 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1258 dsa
->depth_enabled
= state
->depth
.enabled
;
1259 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1260 state
->depth
.writemask
;
1261 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1262 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1263 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1264 si_dsa_writes_stencil(&state
->stencil
[1]));
1265 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1266 dsa
->stencil_write_enabled
;
1268 bool zfunc_is_ordered
=
1269 state
->depth
.func
== PIPE_FUNC_NEVER
||
1270 state
->depth
.func
== PIPE_FUNC_LESS
||
1271 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1272 state
->depth
.func
== PIPE_FUNC_GREATER
||
1273 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1275 bool nozwrite_and_order_invariant_stencil
=
1276 !dsa
->db_can_write
||
1277 (!dsa
->depth_write_enabled
&&
1278 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1279 si_order_invariant_stencil_state(&state
->stencil
[1]));
1281 dsa
->order_invariance
[1].zs
=
1282 nozwrite_and_order_invariant_stencil
||
1283 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1284 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1286 dsa
->order_invariance
[1].pass_set
=
1287 nozwrite_and_order_invariant_stencil
||
1288 (!dsa
->stencil_write_enabled
&&
1289 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1290 state
->depth
.func
== PIPE_FUNC_NEVER
));
1291 dsa
->order_invariance
[0].pass_set
=
1292 !dsa
->depth_write_enabled
||
1293 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1294 state
->depth
.func
== PIPE_FUNC_NEVER
);
1296 dsa
->order_invariance
[1].pass_last
=
1297 sctx
->screen
->assume_no_z_fights
&&
1298 !dsa
->stencil_write_enabled
&&
1299 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1300 dsa
->order_invariance
[0].pass_last
=
1301 sctx
->screen
->assume_no_z_fights
&&
1302 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1307 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1309 struct si_context
*sctx
= (struct si_context
*)ctx
;
1310 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1311 struct si_state_dsa
*dsa
= state
;
1316 si_pm4_bind_state(sctx
, dsa
, dsa
);
1318 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1319 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1320 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1321 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1324 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1325 sctx
->do_update_shaders
= true;
1327 if (sctx
->screen
->dpbb_allowed
&&
1329 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1330 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1331 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1332 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1334 if (sctx
->screen
->has_out_of_order_rast
&&
1336 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1337 sizeof(old_dsa
->order_invariance
))))
1338 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1341 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1343 struct si_context
*sctx
= (struct si_context
*)ctx
;
1344 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1347 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1349 struct pipe_depth_stencil_alpha_state dsa
= {};
1351 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1354 /* DB RENDER STATE */
1356 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1358 struct si_context
*sctx
= (struct si_context
*)ctx
;
1360 /* Pipeline stat & streamout queries. */
1362 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1363 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1365 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1366 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1369 /* Occlusion queries. */
1370 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1371 sctx
->occlusion_queries_disabled
= !enable
;
1372 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1376 void si_set_occlusion_query_state(struct si_context
*sctx
,
1377 bool old_perfect_enable
)
1379 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1381 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1383 if (perfect_enable
!= old_perfect_enable
)
1384 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1387 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1389 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1391 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1392 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1394 st
->saved_ssbo_writable_mask
= 0;
1396 for (unsigned i
= 0; i
< 3; i
++) {
1397 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1398 (1u << si_get_shaderbuf_slot(i
)))
1399 st
->saved_ssbo_writable_mask
|= 1 << i
;
1403 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1405 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1407 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1408 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1410 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1411 st
->saved_ssbo_writable_mask
);
1412 for (unsigned i
= 0; i
< 3; ++i
)
1413 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1416 static void si_emit_db_render_state(struct si_context
*sctx
)
1418 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1419 unsigned db_shader_control
, db_render_control
, db_count_control
;
1420 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1422 /* DB_RENDER_CONTROL */
1423 if (sctx
->dbcb_depth_copy_enabled
||
1424 sctx
->dbcb_stencil_copy_enabled
) {
1426 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1427 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1428 S_028000_COPY_CENTROID(1) |
1429 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1430 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1432 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1433 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1436 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1437 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1440 /* DB_COUNT_CONTROL (occlusion queries) */
1441 if (sctx
->num_occlusion_queries
> 0 &&
1442 !sctx
->occlusion_queries_disabled
) {
1443 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1444 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1446 if (sctx
->chip_class
>= GFX7
) {
1447 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1449 /* Stoney doesn't increment occlusion query counters
1450 * if the sample rate is 16x. Use 8x sample rate instead.
1452 if (sctx
->family
== CHIP_STONEY
)
1453 log_sample_rate
= MIN2(log_sample_rate
, 3);
1456 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1457 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1458 S_028004_SAMPLE_RATE(log_sample_rate
) |
1459 S_028004_ZPASS_ENABLE(1) |
1460 S_028004_SLICE_EVEN_ENABLE(1) |
1461 S_028004_SLICE_ODD_ENABLE(1);
1464 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1465 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1468 /* Disable occlusion queries. */
1469 if (sctx
->chip_class
>= GFX7
) {
1470 db_count_control
= 0;
1472 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1476 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1477 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1480 /* DB_RENDER_OVERRIDE2 */
1481 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1482 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1483 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1484 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1485 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1487 db_shader_control
= sctx
->ps_db_shader_control
;
1489 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1490 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1491 db_shader_control
&= C_02880C_Z_ORDER
;
1492 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1495 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1496 if (!rs
->multisample_enable
)
1497 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1499 if (sctx
->screen
->has_rbplus
&&
1500 !sctx
->screen
->rbplus_allowed
)
1501 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1503 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1504 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1506 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1507 sctx
->context_roll
= true;
1511 * format translation
1513 static uint32_t si_translate_colorformat(enum pipe_format format
)
1515 const struct util_format_description
*desc
= util_format_description(format
);
1517 return V_028C70_COLOR_INVALID
;
1519 #define HAS_SIZE(x,y,z,w) \
1520 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1521 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1523 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1524 return V_028C70_COLOR_10_11_11
;
1526 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1527 return V_028C70_COLOR_INVALID
;
1529 /* hw cannot support mixed formats (except depth/stencil, since
1530 * stencil is not written to). */
1531 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1532 return V_028C70_COLOR_INVALID
;
1534 switch (desc
->nr_channels
) {
1536 switch (desc
->channel
[0].size
) {
1538 return V_028C70_COLOR_8
;
1540 return V_028C70_COLOR_16
;
1542 return V_028C70_COLOR_32
;
1546 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1547 switch (desc
->channel
[0].size
) {
1549 return V_028C70_COLOR_8_8
;
1551 return V_028C70_COLOR_16_16
;
1553 return V_028C70_COLOR_32_32
;
1555 } else if (HAS_SIZE(8,24,0,0)) {
1556 return V_028C70_COLOR_24_8
;
1557 } else if (HAS_SIZE(24,8,0,0)) {
1558 return V_028C70_COLOR_8_24
;
1562 if (HAS_SIZE(5,6,5,0)) {
1563 return V_028C70_COLOR_5_6_5
;
1564 } else if (HAS_SIZE(32,8,24,0)) {
1565 return V_028C70_COLOR_X24_8_32_FLOAT
;
1569 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1570 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1571 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1572 switch (desc
->channel
[0].size
) {
1574 return V_028C70_COLOR_4_4_4_4
;
1576 return V_028C70_COLOR_8_8_8_8
;
1578 return V_028C70_COLOR_16_16_16_16
;
1580 return V_028C70_COLOR_32_32_32_32
;
1582 } else if (HAS_SIZE(5,5,5,1)) {
1583 return V_028C70_COLOR_1_5_5_5
;
1584 } else if (HAS_SIZE(1,5,5,5)) {
1585 return V_028C70_COLOR_5_5_5_1
;
1586 } else if (HAS_SIZE(10,10,10,2)) {
1587 return V_028C70_COLOR_2_10_10_10
;
1591 return V_028C70_COLOR_INVALID
;
1594 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1596 if (SI_BIG_ENDIAN
) {
1597 switch(colorformat
) {
1598 /* 8-bit buffers. */
1599 case V_028C70_COLOR_8
:
1600 return V_028C70_ENDIAN_NONE
;
1602 /* 16-bit buffers. */
1603 case V_028C70_COLOR_5_6_5
:
1604 case V_028C70_COLOR_1_5_5_5
:
1605 case V_028C70_COLOR_4_4_4_4
:
1606 case V_028C70_COLOR_16
:
1607 case V_028C70_COLOR_8_8
:
1608 return V_028C70_ENDIAN_8IN16
;
1610 /* 32-bit buffers. */
1611 case V_028C70_COLOR_8_8_8_8
:
1612 case V_028C70_COLOR_2_10_10_10
:
1613 case V_028C70_COLOR_8_24
:
1614 case V_028C70_COLOR_24_8
:
1615 case V_028C70_COLOR_16_16
:
1616 return V_028C70_ENDIAN_8IN32
;
1618 /* 64-bit buffers. */
1619 case V_028C70_COLOR_16_16_16_16
:
1620 return V_028C70_ENDIAN_8IN16
;
1622 case V_028C70_COLOR_32_32
:
1623 return V_028C70_ENDIAN_8IN32
;
1625 /* 128-bit buffers. */
1626 case V_028C70_COLOR_32_32_32_32
:
1627 return V_028C70_ENDIAN_8IN32
;
1629 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1632 return V_028C70_ENDIAN_NONE
;
1636 static uint32_t si_translate_dbformat(enum pipe_format format
)
1639 case PIPE_FORMAT_Z16_UNORM
:
1640 return V_028040_Z_16
;
1641 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1642 case PIPE_FORMAT_X8Z24_UNORM
:
1643 case PIPE_FORMAT_Z24X8_UNORM
:
1644 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1645 return V_028040_Z_24
; /* deprecated on AMD GCN */
1646 case PIPE_FORMAT_Z32_FLOAT
:
1647 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1648 return V_028040_Z_32_FLOAT
;
1650 return V_028040_Z_INVALID
;
1655 * Texture translation
1658 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1659 enum pipe_format format
,
1660 const struct util_format_description
*desc
,
1663 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1664 bool uniform
= true;
1667 assert(sscreen
->info
.chip_class
<= GFX9
);
1669 /* Colorspace (return non-RGB formats directly). */
1670 switch (desc
->colorspace
) {
1671 /* Depth stencil formats */
1672 case UTIL_FORMAT_COLORSPACE_ZS
:
1674 case PIPE_FORMAT_Z16_UNORM
:
1675 return V_008F14_IMG_DATA_FORMAT_16
;
1676 case PIPE_FORMAT_X24S8_UINT
:
1677 case PIPE_FORMAT_S8X24_UINT
:
1679 * Implemented as an 8_8_8_8 data format to fix texture
1680 * gathers in stencil sampling. This affects at least
1681 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1683 if (sscreen
->info
.chip_class
<= GFX8
)
1684 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1686 if (format
== PIPE_FORMAT_X24S8_UINT
)
1687 return V_008F14_IMG_DATA_FORMAT_8_24
;
1689 return V_008F14_IMG_DATA_FORMAT_24_8
;
1690 case PIPE_FORMAT_Z24X8_UNORM
:
1691 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1692 return V_008F14_IMG_DATA_FORMAT_8_24
;
1693 case PIPE_FORMAT_X8Z24_UNORM
:
1694 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1695 return V_008F14_IMG_DATA_FORMAT_24_8
;
1696 case PIPE_FORMAT_S8_UINT
:
1697 return V_008F14_IMG_DATA_FORMAT_8
;
1698 case PIPE_FORMAT_Z32_FLOAT
:
1699 return V_008F14_IMG_DATA_FORMAT_32
;
1700 case PIPE_FORMAT_X32_S8X24_UINT
:
1701 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1702 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1707 case UTIL_FORMAT_COLORSPACE_YUV
:
1708 goto out_unknown
; /* TODO */
1710 case UTIL_FORMAT_COLORSPACE_SRGB
:
1711 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1719 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1720 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1724 case PIPE_FORMAT_RGTC1_SNORM
:
1725 case PIPE_FORMAT_LATC1_SNORM
:
1726 case PIPE_FORMAT_RGTC1_UNORM
:
1727 case PIPE_FORMAT_LATC1_UNORM
:
1728 return V_008F14_IMG_DATA_FORMAT_BC4
;
1729 case PIPE_FORMAT_RGTC2_SNORM
:
1730 case PIPE_FORMAT_LATC2_SNORM
:
1731 case PIPE_FORMAT_RGTC2_UNORM
:
1732 case PIPE_FORMAT_LATC2_UNORM
:
1733 return V_008F14_IMG_DATA_FORMAT_BC5
;
1739 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1740 (sscreen
->info
.family
== CHIP_STONEY
||
1741 sscreen
->info
.family
== CHIP_VEGA10
||
1742 sscreen
->info
.family
== CHIP_RAVEN
)) {
1744 case PIPE_FORMAT_ETC1_RGB8
:
1745 case PIPE_FORMAT_ETC2_RGB8
:
1746 case PIPE_FORMAT_ETC2_SRGB8
:
1747 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1748 case PIPE_FORMAT_ETC2_RGB8A1
:
1749 case PIPE_FORMAT_ETC2_SRGB8A1
:
1750 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1751 case PIPE_FORMAT_ETC2_RGBA8
:
1752 case PIPE_FORMAT_ETC2_SRGBA8
:
1753 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1754 case PIPE_FORMAT_ETC2_R11_UNORM
:
1755 case PIPE_FORMAT_ETC2_R11_SNORM
:
1756 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1757 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1758 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1759 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1765 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1766 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1770 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1771 case PIPE_FORMAT_BPTC_SRGBA
:
1772 return V_008F14_IMG_DATA_FORMAT_BC7
;
1773 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1774 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1775 return V_008F14_IMG_DATA_FORMAT_BC6
;
1781 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1783 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1784 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1785 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1786 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1787 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1788 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1794 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1795 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1799 case PIPE_FORMAT_DXT1_RGB
:
1800 case PIPE_FORMAT_DXT1_RGBA
:
1801 case PIPE_FORMAT_DXT1_SRGB
:
1802 case PIPE_FORMAT_DXT1_SRGBA
:
1803 return V_008F14_IMG_DATA_FORMAT_BC1
;
1804 case PIPE_FORMAT_DXT3_RGBA
:
1805 case PIPE_FORMAT_DXT3_SRGBA
:
1806 return V_008F14_IMG_DATA_FORMAT_BC2
;
1807 case PIPE_FORMAT_DXT5_RGBA
:
1808 case PIPE_FORMAT_DXT5_SRGBA
:
1809 return V_008F14_IMG_DATA_FORMAT_BC3
;
1815 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1816 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1817 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1818 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1821 /* R8G8Bx_SNORM - TODO CxV8U8 */
1823 /* hw cannot support mixed formats (except depth/stencil, since only
1825 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1828 /* See whether the components are of the same size. */
1829 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1830 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1833 /* Non-uniform formats. */
1835 switch(desc
->nr_channels
) {
1837 if (desc
->channel
[0].size
== 5 &&
1838 desc
->channel
[1].size
== 6 &&
1839 desc
->channel
[2].size
== 5) {
1840 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1844 if (desc
->channel
[0].size
== 5 &&
1845 desc
->channel
[1].size
== 5 &&
1846 desc
->channel
[2].size
== 5 &&
1847 desc
->channel
[3].size
== 1) {
1848 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1850 if (desc
->channel
[0].size
== 1 &&
1851 desc
->channel
[1].size
== 5 &&
1852 desc
->channel
[2].size
== 5 &&
1853 desc
->channel
[3].size
== 5) {
1854 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1856 if (desc
->channel
[0].size
== 10 &&
1857 desc
->channel
[1].size
== 10 &&
1858 desc
->channel
[2].size
== 10 &&
1859 desc
->channel
[3].size
== 2) {
1860 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1867 if (first_non_void
< 0 || first_non_void
> 3)
1870 /* uniform formats */
1871 switch (desc
->channel
[first_non_void
].size
) {
1873 switch (desc
->nr_channels
) {
1874 #if 0 /* Not supported for render targets */
1876 return V_008F14_IMG_DATA_FORMAT_4_4
;
1879 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1883 switch (desc
->nr_channels
) {
1885 return V_008F14_IMG_DATA_FORMAT_8
;
1887 return V_008F14_IMG_DATA_FORMAT_8_8
;
1889 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1893 switch (desc
->nr_channels
) {
1895 return V_008F14_IMG_DATA_FORMAT_16
;
1897 return V_008F14_IMG_DATA_FORMAT_16_16
;
1899 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1903 switch (desc
->nr_channels
) {
1905 return V_008F14_IMG_DATA_FORMAT_32
;
1907 return V_008F14_IMG_DATA_FORMAT_32_32
;
1908 #if 0 /* Not supported for render targets */
1910 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1913 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1921 static unsigned si_tex_wrap(unsigned wrap
)
1925 case PIPE_TEX_WRAP_REPEAT
:
1926 return V_008F30_SQ_TEX_WRAP
;
1927 case PIPE_TEX_WRAP_CLAMP
:
1928 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1929 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1930 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1931 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1932 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1933 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1934 return V_008F30_SQ_TEX_MIRROR
;
1935 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1936 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1937 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1938 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1939 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1940 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1944 static unsigned si_tex_mipfilter(unsigned filter
)
1947 case PIPE_TEX_MIPFILTER_NEAREST
:
1948 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1949 case PIPE_TEX_MIPFILTER_LINEAR
:
1950 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1952 case PIPE_TEX_MIPFILTER_NONE
:
1953 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1957 static unsigned si_tex_compare(unsigned compare
)
1961 case PIPE_FUNC_NEVER
:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1963 case PIPE_FUNC_LESS
:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1965 case PIPE_FUNC_EQUAL
:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1967 case PIPE_FUNC_LEQUAL
:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1969 case PIPE_FUNC_GREATER
:
1970 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1971 case PIPE_FUNC_NOTEQUAL
:
1972 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1973 case PIPE_FUNC_GEQUAL
:
1974 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1975 case PIPE_FUNC_ALWAYS
:
1976 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1980 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1981 unsigned view_target
, unsigned nr_samples
)
1983 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1985 if (view_target
== PIPE_TEXTURE_CUBE
||
1986 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1987 res_target
= view_target
;
1988 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1989 else if (res_target
== PIPE_TEXTURE_CUBE
||
1990 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1991 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1993 /* GFX9 allocates 1D textures as 2D. */
1994 if ((res_target
== PIPE_TEXTURE_1D
||
1995 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1996 sscreen
->info
.chip_class
== GFX9
&&
1997 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1998 if (res_target
== PIPE_TEXTURE_1D
)
1999 res_target
= PIPE_TEXTURE_2D
;
2001 res_target
= PIPE_TEXTURE_2D_ARRAY
;
2004 switch (res_target
) {
2006 case PIPE_TEXTURE_1D
:
2007 return V_008F1C_SQ_RSRC_IMG_1D
;
2008 case PIPE_TEXTURE_1D_ARRAY
:
2009 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
2010 case PIPE_TEXTURE_2D
:
2011 case PIPE_TEXTURE_RECT
:
2012 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
2013 V_008F1C_SQ_RSRC_IMG_2D
;
2014 case PIPE_TEXTURE_2D_ARRAY
:
2015 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
2016 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2017 case PIPE_TEXTURE_3D
:
2018 return V_008F1C_SQ_RSRC_IMG_3D
;
2019 case PIPE_TEXTURE_CUBE
:
2020 case PIPE_TEXTURE_CUBE_ARRAY
:
2021 return V_008F1C_SQ_RSRC_IMG_CUBE
;
2026 * Format support testing
2029 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
2031 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2033 if (sscreen
->info
.chip_class
>= GFX10
) {
2034 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2035 if (!fmt
->img_format
|| fmt
->buffers_only
)
2040 const struct util_format_description
*desc
= util_format_description(format
);
2044 return si_translate_texformat(screen
, format
, desc
,
2045 util_format_get_first_non_void_channel(format
)) != ~0U;
2048 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
2049 const struct util_format_description
*desc
,
2054 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2056 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2057 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
2059 assert(first_non_void
>= 0);
2061 if (desc
->nr_channels
== 4 &&
2062 desc
->channel
[0].size
== 10 &&
2063 desc
->channel
[1].size
== 10 &&
2064 desc
->channel
[2].size
== 10 &&
2065 desc
->channel
[3].size
== 2)
2066 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
2068 /* See whether the components are of the same size. */
2069 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2070 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2071 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2074 switch (desc
->channel
[first_non_void
].size
) {
2076 switch (desc
->nr_channels
) {
2078 case 3: /* 3 loads */
2079 return V_008F0C_BUF_DATA_FORMAT_8
;
2081 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2083 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2087 switch (desc
->nr_channels
) {
2089 case 3: /* 3 loads */
2090 return V_008F0C_BUF_DATA_FORMAT_16
;
2092 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2094 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2098 switch (desc
->nr_channels
) {
2100 return V_008F0C_BUF_DATA_FORMAT_32
;
2102 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2104 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2106 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2110 /* Legacy double formats. */
2111 switch (desc
->nr_channels
) {
2112 case 1: /* 1 load */
2113 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2114 case 2: /* 1 load */
2115 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2116 case 3: /* 3 loads */
2117 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2118 case 4: /* 2 loads */
2119 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2124 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2127 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2128 const struct util_format_description
*desc
,
2131 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2133 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2134 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2136 assert(first_non_void
>= 0);
2138 switch (desc
->channel
[first_non_void
].type
) {
2139 case UTIL_FORMAT_TYPE_SIGNED
:
2140 case UTIL_FORMAT_TYPE_FIXED
:
2141 if (desc
->channel
[first_non_void
].size
>= 32 ||
2142 desc
->channel
[first_non_void
].pure_integer
)
2143 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2144 else if (desc
->channel
[first_non_void
].normalized
)
2145 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2147 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2149 case UTIL_FORMAT_TYPE_UNSIGNED
:
2150 if (desc
->channel
[first_non_void
].size
>= 32 ||
2151 desc
->channel
[first_non_void
].pure_integer
)
2152 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2153 else if (desc
->channel
[first_non_void
].normalized
)
2154 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2156 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2158 case UTIL_FORMAT_TYPE_FLOAT
:
2160 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2164 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2165 enum pipe_format format
,
2168 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2169 const struct util_format_description
*desc
;
2171 unsigned data_format
;
2173 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2174 PIPE_BIND_SAMPLER_VIEW
|
2175 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2177 desc
= util_format_description(format
);
2181 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2182 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2183 * for read-only access (with caveats surrounding bounds checks), but
2184 * obviously fails for write access which we have to implement for
2185 * shader images. Luckily, OpenGL doesn't expect this to be supported
2186 * anyway, and so the only impact is on PBO uploads / downloads, which
2187 * shouldn't be expected to be fast for GL_RGB anyway.
2189 if (desc
->block
.bits
== 3 * 8 ||
2190 desc
->block
.bits
== 3 * 16) {
2191 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2192 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2198 if (sscreen
->info
.chip_class
>= GFX10
) {
2199 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2200 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2205 first_non_void
= util_format_get_first_non_void_channel(format
);
2206 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2207 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2213 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2215 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2216 si_translate_colorswap(format
, false) != ~0U;
2219 static bool si_is_zs_format_supported(enum pipe_format format
)
2221 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2224 static bool si_is_format_supported(struct pipe_screen
*screen
,
2225 enum pipe_format format
,
2226 enum pipe_texture_target target
,
2227 unsigned sample_count
,
2228 unsigned storage_sample_count
,
2231 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2232 unsigned retval
= 0;
2234 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2235 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2239 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2242 if (sample_count
> 1) {
2243 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2246 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2249 /* Only power-of-two sample counts are supported. */
2250 if (!util_is_power_of_two_or_zero(sample_count
) ||
2251 !util_is_power_of_two_or_zero(storage_sample_count
))
2254 /* MSAA support without framebuffer attachments. */
2255 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2258 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2259 util_format_is_depth_or_stencil(format
)) {
2260 /* Color without EQAA or depth/stencil. */
2261 if (sample_count
> 8 ||
2262 sample_count
!= storage_sample_count
)
2265 /* Color with EQAA. */
2266 if (sample_count
> 16 ||
2267 storage_sample_count
> 8)
2272 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2273 PIPE_BIND_SHADER_IMAGE
)) {
2274 if (target
== PIPE_BUFFER
) {
2275 retval
|= si_is_vertex_format_supported(
2276 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2277 PIPE_BIND_SHADER_IMAGE
));
2279 if (si_is_sampler_format_supported(screen
, format
))
2280 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2281 PIPE_BIND_SHADER_IMAGE
);
2285 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2286 PIPE_BIND_DISPLAY_TARGET
|
2289 PIPE_BIND_BLENDABLE
)) &&
2290 si_is_colorbuffer_format_supported(format
)) {
2292 (PIPE_BIND_RENDER_TARGET
|
2293 PIPE_BIND_DISPLAY_TARGET
|
2296 if (!util_format_is_pure_integer(format
) &&
2297 !util_format_is_depth_or_stencil(format
))
2298 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2301 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2302 si_is_zs_format_supported(format
)) {
2303 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2306 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2307 retval
|= si_is_vertex_format_supported(screen
, format
,
2308 PIPE_BIND_VERTEX_BUFFER
);
2311 if ((usage
& PIPE_BIND_LINEAR
) &&
2312 !util_format_is_compressed(format
) &&
2313 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2314 retval
|= PIPE_BIND_LINEAR
;
2316 return retval
== usage
;
2320 * framebuffer handling
2323 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2324 unsigned format
, unsigned swap
,
2325 unsigned ntype
, bool is_depth
)
2327 /* Alpha is needed for alpha-to-coverage.
2328 * Blending may be with or without alpha.
2330 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2331 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2332 unsigned blend
= 0; /* supports blending, but may not export alpha */
2333 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2335 /* Choose the SPI color formats. These are required values for RB+.
2336 * Other chips have multiple choices, though they are not necessarily better.
2339 case V_028C70_COLOR_5_6_5
:
2340 case V_028C70_COLOR_1_5_5_5
:
2341 case V_028C70_COLOR_5_5_5_1
:
2342 case V_028C70_COLOR_4_4_4_4
:
2343 case V_028C70_COLOR_10_11_11
:
2344 case V_028C70_COLOR_11_11_10
:
2345 case V_028C70_COLOR_8
:
2346 case V_028C70_COLOR_8_8
:
2347 case V_028C70_COLOR_8_8_8_8
:
2348 case V_028C70_COLOR_10_10_10_2
:
2349 case V_028C70_COLOR_2_10_10_10
:
2350 if (ntype
== V_028C70_NUMBER_UINT
)
2351 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2352 else if (ntype
== V_028C70_NUMBER_SINT
)
2353 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2355 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2358 case V_028C70_COLOR_16
:
2359 case V_028C70_COLOR_16_16
:
2360 case V_028C70_COLOR_16_16_16_16
:
2361 if (ntype
== V_028C70_NUMBER_UNORM
||
2362 ntype
== V_028C70_NUMBER_SNORM
) {
2363 /* UNORM16 and SNORM16 don't support blending */
2364 if (ntype
== V_028C70_NUMBER_UNORM
)
2365 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2367 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2369 /* Use 32 bits per channel for blending. */
2370 if (format
== V_028C70_COLOR_16
) {
2371 if (swap
== V_028C70_SWAP_STD
) { /* R */
2372 blend
= V_028714_SPI_SHADER_32_R
;
2373 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2374 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2375 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2378 } else if (format
== V_028C70_COLOR_16_16
) {
2379 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2380 blend
= V_028714_SPI_SHADER_32_GR
;
2381 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2382 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2383 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2386 } else /* 16_16_16_16 */
2387 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2388 } else if (ntype
== V_028C70_NUMBER_UINT
)
2389 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2390 else if (ntype
== V_028C70_NUMBER_SINT
)
2391 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2392 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2393 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2398 case V_028C70_COLOR_32
:
2399 if (swap
== V_028C70_SWAP_STD
) { /* R */
2400 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2401 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2402 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2403 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2408 case V_028C70_COLOR_32_32
:
2409 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2410 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2411 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2412 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2413 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2418 case V_028C70_COLOR_32_32_32_32
:
2419 case V_028C70_COLOR_8_24
:
2420 case V_028C70_COLOR_24_8
:
2421 case V_028C70_COLOR_X24_8_32_FLOAT
:
2422 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2430 /* The DB->CB copy needs 32_ABGR. */
2432 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2434 surf
->spi_shader_col_format
= normal
;
2435 surf
->spi_shader_col_format_alpha
= alpha
;
2436 surf
->spi_shader_col_format_blend
= blend
;
2437 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2440 static void si_initialize_color_surface(struct si_context
*sctx
,
2441 struct si_surface
*surf
)
2443 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2444 unsigned color_info
, color_attrib
;
2445 unsigned format
, swap
, ntype
, endian
;
2446 const struct util_format_description
*desc
;
2448 unsigned blend_clamp
= 0, blend_bypass
= 0;
2450 desc
= util_format_description(surf
->base
.format
);
2451 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2452 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2456 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2457 ntype
= V_028C70_NUMBER_FLOAT
;
2459 ntype
= V_028C70_NUMBER_UNORM
;
2460 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2461 ntype
= V_028C70_NUMBER_SRGB
;
2462 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2463 if (desc
->channel
[firstchan
].pure_integer
) {
2464 ntype
= V_028C70_NUMBER_SINT
;
2466 assert(desc
->channel
[firstchan
].normalized
);
2467 ntype
= V_028C70_NUMBER_SNORM
;
2469 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2470 if (desc
->channel
[firstchan
].pure_integer
) {
2471 ntype
= V_028C70_NUMBER_UINT
;
2473 assert(desc
->channel
[firstchan
].normalized
);
2474 ntype
= V_028C70_NUMBER_UNORM
;
2479 format
= si_translate_colorformat(surf
->base
.format
);
2480 if (format
== V_028C70_COLOR_INVALID
) {
2481 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2483 assert(format
!= V_028C70_COLOR_INVALID
);
2484 swap
= si_translate_colorswap(surf
->base
.format
, false);
2485 endian
= si_colorformat_endian_swap(format
);
2487 /* blend clamp should be set for all NORM/SRGB types */
2488 if (ntype
== V_028C70_NUMBER_UNORM
||
2489 ntype
== V_028C70_NUMBER_SNORM
||
2490 ntype
== V_028C70_NUMBER_SRGB
)
2493 /* set blend bypass according to docs if SINT/UINT or
2494 8/24 COLOR variants */
2495 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2496 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2497 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2502 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2503 if (format
== V_028C70_COLOR_8
||
2504 format
== V_028C70_COLOR_8_8
||
2505 format
== V_028C70_COLOR_8_8_8_8
)
2506 surf
->color_is_int8
= true;
2507 else if (format
== V_028C70_COLOR_10_10_10_2
||
2508 format
== V_028C70_COLOR_2_10_10_10
)
2509 surf
->color_is_int10
= true;
2512 color_info
= S_028C70_FORMAT(format
) |
2513 S_028C70_COMP_SWAP(swap
) |
2514 S_028C70_BLEND_CLAMP(blend_clamp
) |
2515 S_028C70_BLEND_BYPASS(blend_bypass
) |
2516 S_028C70_SIMPLE_FLOAT(1) |
2517 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2518 ntype
!= V_028C70_NUMBER_SNORM
&&
2519 ntype
!= V_028C70_NUMBER_SRGB
&&
2520 format
!= V_028C70_COLOR_8_24
&&
2521 format
!= V_028C70_COLOR_24_8
) |
2522 S_028C70_NUMBER_TYPE(ntype
) |
2523 S_028C70_ENDIAN(endian
);
2525 /* Intensity is implemented as Red, so treat it that way. */
2526 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2527 util_format_is_intensity(surf
->base
.format
));
2529 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2530 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2531 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2533 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2534 S_028C74_NUM_FRAGMENTS(log_fragments
);
2536 if (tex
->fmask_offset
) {
2537 color_info
|= S_028C70_COMPRESSION(1);
2538 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2540 if (sctx
->chip_class
== GFX6
) {
2541 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2542 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2547 if (sctx
->chip_class
>= GFX10
) {
2548 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2550 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2551 64 for APU because all of our APUs to date use DIMMs which have
2552 a request granularity size of 64B while all other chips have a
2554 if (!sctx
->screen
->info
.has_dedicated_vram
)
2555 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2557 surf
->cb_dcc_control
=
2558 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2559 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2560 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2561 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2562 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2563 } else if (sctx
->chip_class
>= GFX8
) {
2564 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2565 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2567 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2568 64 for APU because all of our APUs to date use DIMMs which have
2569 a request granularity size of 64B while all other chips have a
2571 if (!sctx
->screen
->info
.has_dedicated_vram
)
2572 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2574 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2575 if (tex
->surface
.bpe
== 1)
2576 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2577 else if (tex
->surface
.bpe
== 2)
2578 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2581 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2582 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2583 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2586 /* This must be set for fast clear to work without FMASK. */
2587 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2588 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2589 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2592 /* GFX10 field has the same base shift as the GFX6 field */
2593 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2594 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2595 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2597 if (sctx
->chip_class
>= GFX10
) {
2598 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2600 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2601 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2602 S_028EE0_RESOURCE_LEVEL(1);
2603 } else if (sctx
->chip_class
== GFX9
) {
2604 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2605 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2606 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2609 if (sctx
->chip_class
>= GFX9
) {
2610 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2611 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2612 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2615 surf
->cb_color_view
= color_view
;
2616 surf
->cb_color_info
= color_info
;
2617 surf
->cb_color_attrib
= color_attrib
;
2619 /* Determine pixel shader export format */
2620 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2622 surf
->color_initialized
= true;
2625 static void si_init_depth_surface(struct si_context
*sctx
,
2626 struct si_surface
*surf
)
2628 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2629 unsigned level
= surf
->base
.u
.tex
.level
;
2630 unsigned format
, stencil_format
;
2631 uint32_t z_info
, s_info
;
2633 format
= si_translate_dbformat(tex
->db_render_format
);
2634 stencil_format
= tex
->surface
.has_stencil
?
2635 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2637 assert(format
!= V_028040_Z_INVALID
);
2638 if (format
== V_028040_Z_INVALID
)
2639 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2641 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2642 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2643 surf
->db_htile_data_base
= 0;
2644 surf
->db_htile_surface
= 0;
2646 if (sctx
->chip_class
>= GFX10
) {
2647 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2648 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2651 if (sctx
->chip_class
>= GFX9
) {
2652 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2653 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2654 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2655 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2656 z_info
= S_028038_FORMAT(format
) |
2657 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2658 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2659 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2660 s_info
= S_02803C_FORMAT(stencil_format
) |
2661 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2663 if (sctx
->chip_class
== GFX9
) {
2664 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2665 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2667 surf
->db_depth_view
|= S_028008_MIPID(level
);
2668 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2669 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2671 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2672 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2673 S_028038_ALLOW_EXPCLEAR(1);
2675 if (tex
->tc_compatible_htile
) {
2676 unsigned max_zplanes
= 4;
2678 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2679 tex
->buffer
.b
.b
.nr_samples
> 1)
2682 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2684 if (sctx
->chip_class
>= GFX10
) {
2685 z_info
|= S_028040_ITERATE_FLUSH(1);
2686 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2688 z_info
|= S_028038_ITERATE_FLUSH(1);
2689 s_info
|= S_02803C_ITERATE_FLUSH(1);
2693 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2694 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2695 * See that for explanation.
2697 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2699 /* Use all HTILE for depth if there's no stencil. */
2700 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2703 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2704 tex
->htile_offset
) >> 8;
2705 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2706 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2707 if (sctx
->chip_class
== GFX9
) {
2708 surf
->db_htile_surface
|=
2709 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2714 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2716 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2718 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2719 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2720 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2721 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2723 z_info
= S_028040_FORMAT(format
) |
2724 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2725 s_info
= S_028044_FORMAT(stencil_format
);
2726 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2728 if (sctx
->chip_class
>= GFX7
) {
2729 struct radeon_info
*info
= &sctx
->screen
->info
;
2730 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2731 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2732 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2733 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2734 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2735 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2737 surf
->db_depth_info
|=
2738 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2739 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2740 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2741 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2742 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2743 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2744 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2745 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2747 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2748 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2749 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2750 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2753 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2754 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2755 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2756 levelinfo
->nblk_y
) / 64 - 1);
2758 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2759 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2760 S_028040_ALLOW_EXPCLEAR(1);
2762 if (tex
->surface
.has_stencil
) {
2763 /* Workaround: For a not yet understood reason, the
2764 * combination of MSAA, fast stencil clear and stencil
2765 * decompress messes with subsequent stencil buffer
2766 * uses. Problem was reproduced on Verde, Bonaire,
2767 * Tonga, and Carrizo.
2769 * Disabling EXPCLEAR works around the problem.
2771 * Check piglit's arb_texture_multisample-stencil-clear
2772 * test if you want to try changing this.
2774 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2775 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2776 } else if (!tex
->tc_compatible_htile
) {
2777 /* Use all of the htile_buffer for depth if there's no stencil.
2778 * This must not be set when TC-compatible HTILE is enabled
2781 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2784 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2785 tex
->htile_offset
) >> 8;
2786 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2788 if (tex
->tc_compatible_htile
) {
2789 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2791 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2792 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2793 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2794 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2795 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2797 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2802 surf
->db_z_info
= z_info
;
2803 surf
->db_stencil_info
= s_info
;
2805 surf
->depth_initialized
= true;
2808 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2810 if (sctx
->decompression_enabled
)
2813 if (sctx
->framebuffer
.state
.zsbuf
) {
2814 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2815 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2817 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2819 if (tex
->surface
.has_stencil
)
2820 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2823 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2824 while (compressed_cb_mask
) {
2825 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2826 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2827 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2829 if (tex
->fmask_offset
)
2830 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2831 if (tex
->dcc_gather_statistics
)
2832 tex
->separate_dcc_dirty
= true;
2836 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2838 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2839 struct si_surface
*surf
= NULL
;
2840 struct si_texture
*tex
;
2842 if (!state
->cbufs
[i
])
2844 surf
= (struct si_surface
*)state
->cbufs
[i
];
2845 tex
= (struct si_texture
*)surf
->base
.texture
;
2847 p_atomic_dec(&tex
->framebuffers_bound
);
2851 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2852 const struct pipe_framebuffer_state
*state
)
2854 struct si_context
*sctx
= (struct si_context
*)ctx
;
2855 struct si_surface
*surf
= NULL
;
2856 struct si_texture
*tex
;
2857 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2858 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2859 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2860 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2861 bool old_has_stencil
=
2863 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2864 bool unbound
= false;
2867 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2868 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2869 * We could implement the full workaround here, but it's a useless case.
2871 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2872 unreachable("the framebuffer shouldn't have zero area");
2876 si_update_fb_dirtiness_after_rendering(sctx
);
2878 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2879 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2882 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2883 if (tex
->dcc_gather_statistics
)
2884 vi_separate_dcc_stop_query(sctx
, tex
);
2887 /* Disable DCC if the formats are incompatible. */
2888 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2889 if (!state
->cbufs
[i
])
2892 surf
= (struct si_surface
*)state
->cbufs
[i
];
2893 tex
= (struct si_texture
*)surf
->base
.texture
;
2895 if (!surf
->dcc_incompatible
)
2898 /* Since the DCC decompression calls back into set_framebuffer-
2899 * _state, we need to unbind the framebuffer, so that
2900 * vi_separate_dcc_stop_query isn't called twice with the same
2904 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2908 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2909 if (!si_texture_disable_dcc(sctx
, tex
))
2910 si_decompress_dcc(sctx
, tex
);
2912 surf
->dcc_incompatible
= false;
2915 /* Only flush TC when changing the framebuffer state, because
2916 * the only client not using TC that can change textures is
2919 * Wait for compute shaders because of possible transitions:
2920 * - FB write -> shader read
2921 * - shader write -> FB read
2923 * DB caches are flushed on demand (using si_decompress_textures).
2925 * When MSAA is enabled, CB and TC caches are flushed on demand
2926 * (after FMASK decompression). Shader write -> FB read transitions
2927 * cannot happen for MSAA textures, because MSAA shader images are
2930 * Only flush and wait for CB if there is actually a bound color buffer.
2932 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2933 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2934 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2935 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2938 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2940 /* u_blitter doesn't invoke depth decompression when it does multiple
2941 * blits in a row, but the only case when it matters for DB is when
2942 * doing generate_mipmap. So here we flush DB manually between
2943 * individual generate_mipmap blits.
2944 * Note that lower mipmap levels aren't compressed.
2946 if (sctx
->generate_mipmap_for_depth
) {
2947 si_make_DB_shader_coherent(sctx
, 1, false,
2948 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2949 } else if (sctx
->chip_class
== GFX9
) {
2950 /* It appears that DB metadata "leaks" in a sequence of:
2952 * - DCC decompress for shader image writes (with DB disabled)
2953 * - render with DEPTH_BEFORE_SHADER=1
2954 * Flushing DB metadata works around the problem.
2956 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2959 /* Take the maximum of the old and new count. If the new count is lower,
2960 * dirtying is needed to disable the unbound colorbuffers.
2962 sctx
->framebuffer
.dirty_cbufs
|=
2963 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2964 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2966 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2967 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2969 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2970 sctx
->framebuffer
.spi_shader_col_format
= 0;
2971 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2972 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2973 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2974 sctx
->framebuffer
.color_is_int8
= 0;
2975 sctx
->framebuffer
.color_is_int10
= 0;
2977 sctx
->framebuffer
.compressed_cb_mask
= 0;
2978 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2979 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2980 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2981 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2982 sctx
->framebuffer
.any_dst_linear
= false;
2983 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2984 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2985 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2986 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2988 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2989 if (!state
->cbufs
[i
])
2992 surf
= (struct si_surface
*)state
->cbufs
[i
];
2993 tex
= (struct si_texture
*)surf
->base
.texture
;
2995 if (!surf
->color_initialized
) {
2996 si_initialize_color_surface(sctx
, surf
);
2999 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
3000 sctx
->framebuffer
.spi_shader_col_format
|=
3001 surf
->spi_shader_col_format
<< (i
* 4);
3002 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
3003 surf
->spi_shader_col_format_alpha
<< (i
* 4);
3004 sctx
->framebuffer
.spi_shader_col_format_blend
|=
3005 surf
->spi_shader_col_format_blend
<< (i
* 4);
3006 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
3007 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
3009 if (surf
->color_is_int8
)
3010 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
3011 if (surf
->color_is_int10
)
3012 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
3014 if (tex
->fmask_offset
)
3015 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3017 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
3019 /* Don't update nr_color_samples for non-AA buffers.
3020 * (e.g. destination of MSAA resolve)
3022 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
3023 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
3024 sctx
->framebuffer
.nr_color_samples
=
3025 MIN2(sctx
->framebuffer
.nr_color_samples
,
3026 tex
->buffer
.b
.b
.nr_storage_samples
);
3027 sctx
->framebuffer
.nr_color_samples
=
3028 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
3031 if (tex
->surface
.is_linear
)
3032 sctx
->framebuffer
.any_dst_linear
= true;
3034 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
3035 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
3037 if (sctx
->chip_class
>= GFX9
&&
3038 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
3039 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
3042 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3044 p_atomic_inc(&tex
->framebuffers_bound
);
3046 if (tex
->dcc_gather_statistics
) {
3047 /* Dirty tracking must be enabled for DCC usage analysis. */
3048 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3049 vi_separate_dcc_start_query(sctx
, tex
);
3052 /* Update the minimum but don't keep 0. */
3053 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3054 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3055 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
3058 /* For optimal DCC performance. */
3059 if (sctx
->chip_class
>= GFX10
)
3060 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
3062 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
3064 struct si_texture
*zstex
= NULL
;
3067 surf
= (struct si_surface
*)state
->zsbuf
;
3068 zstex
= (struct si_texture
*)surf
->base
.texture
;
3070 if (!surf
->depth_initialized
) {
3071 si_init_depth_surface(sctx
, surf
);
3074 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
,
3076 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
3078 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3080 /* Update the minimum but don't keep 0. */
3081 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3082 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3083 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
3086 si_update_ps_colorbuf0_slot(sctx
);
3087 si_update_poly_offset_state(sctx
);
3088 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3089 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
3091 if (sctx
->screen
->dpbb_allowed
)
3092 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3094 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
3095 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3097 if (sctx
->screen
->has_out_of_order_rast
&&
3098 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
3099 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
3100 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
3101 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3103 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
3104 struct pipe_constant_buffer constbuf
= {0};
3106 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3107 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3109 constbuf
.buffer
= sctx
->sample_pos_buffer
;
3111 /* Set sample locations as fragment shader constants. */
3112 switch (sctx
->framebuffer
.nr_samples
) {
3114 constbuf
.buffer_offset
= 0;
3117 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
3118 (ubyte
*)sctx
->sample_positions
.x1
;
3121 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
3122 (ubyte
*)sctx
->sample_positions
.x1
;
3125 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
3126 (ubyte
*)sctx
->sample_positions
.x1
;
3129 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3130 (ubyte
*)sctx
->sample_positions
.x1
;
3133 PRINT_ERR("Requested an invalid number of samples %i.\n",
3134 sctx
->framebuffer
.nr_samples
);
3137 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3138 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3140 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3143 sctx
->do_update_shaders
= true;
3145 if (!sctx
->decompression_enabled
) {
3146 /* Prevent textures decompression when the framebuffer state
3147 * changes come from the decompression passes themselves.
3149 sctx
->need_check_render_feedback
= true;
3153 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3155 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3156 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3157 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3158 struct si_texture
*tex
= NULL
;
3159 struct si_surface
*cb
= NULL
;
3160 unsigned cb_color_info
= 0;
3163 for (i
= 0; i
< nr_cbufs
; i
++) {
3164 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3165 unsigned cb_color_attrib
;
3167 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3170 cb
= (struct si_surface
*)state
->cbufs
[i
];
3172 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3173 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3177 tex
= (struct si_texture
*)cb
->base
.texture
;
3178 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3179 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3180 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3181 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3182 RADEON_PRIO_COLOR_BUFFER
);
3184 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3185 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3186 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3187 RADEON_PRIO_SEPARATE_META
);
3190 if (tex
->dcc_separate_buffer
)
3191 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3192 tex
->dcc_separate_buffer
,
3193 RADEON_USAGE_READWRITE
,
3194 RADEON_PRIO_SEPARATE_META
);
3196 /* Compute mutable surface parameters. */
3197 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3199 cb_color_cmask
= tex
->cmask_base_address_reg
;
3201 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3202 cb_color_attrib
= cb
->cb_color_attrib
;
3204 if (cb
->base
.u
.tex
.level
> 0)
3205 cb_color_info
&= C_028C70_FAST_CLEAR
;
3207 if (tex
->fmask_offset
) {
3208 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3209 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3213 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3214 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3215 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3216 state
->cbufs
[1] == &cb
->base
&&
3217 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3219 if (!is_msaa_resolve_dst
)
3220 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3222 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3223 tex
->dcc_offset
) >> 8;
3225 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3226 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3227 cb_dcc_base
|= dcc_tile_swizzle
;
3230 if (sctx
->chip_class
>= GFX10
) {
3231 unsigned cb_color_attrib3
;
3233 /* Set mutable surface parameters. */
3234 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3235 cb_color_base
|= tex
->surface
.tile_swizzle
;
3236 if (!tex
->fmask_offset
)
3237 cb_color_fmask
= cb_color_base
;
3238 if (cb
->base
.u
.tex
.level
> 0)
3239 cb_color_cmask
= cb_color_base
;
3241 cb_color_attrib3
= cb
->cb_color_attrib3
|
3242 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3243 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3244 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3245 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3247 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3248 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3249 radeon_emit(cs
, 0); /* hole */
3250 radeon_emit(cs
, 0); /* hole */
3251 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3252 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3253 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3254 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3255 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3256 radeon_emit(cs
, 0); /* hole */
3257 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3258 radeon_emit(cs
, 0); /* hole */
3259 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3260 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3261 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3263 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4,
3264 cb_color_base
>> 32);
3265 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3266 cb_color_cmask
>> 32);
3267 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3268 cb_color_fmask
>> 32);
3269 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4,
3271 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4,
3272 cb
->cb_color_attrib2
);
3273 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4,
3275 } else if (sctx
->chip_class
== GFX9
) {
3276 struct gfx9_surf_meta_flags meta
;
3278 if (tex
->dcc_offset
)
3279 meta
= tex
->surface
.u
.gfx9
.dcc
;
3281 meta
= tex
->surface
.u
.gfx9
.cmask
;
3283 /* Set mutable surface parameters. */
3284 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3285 cb_color_base
|= tex
->surface
.tile_swizzle
;
3286 if (!tex
->fmask_offset
)
3287 cb_color_fmask
= cb_color_base
;
3288 if (cb
->base
.u
.tex
.level
> 0)
3289 cb_color_cmask
= cb_color_base
;
3290 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3291 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3292 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3293 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3295 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3296 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3297 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3298 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3299 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3300 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3301 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3302 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3303 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3304 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3305 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3306 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3307 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3308 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3309 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3310 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3312 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3313 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3315 /* Compute mutable surface parameters (GFX6-GFX8). */
3316 const struct legacy_surf_level
*level_info
=
3317 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3318 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3319 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3321 cb_color_base
+= level_info
->offset
>> 8;
3322 /* Only macrotiled modes can set tile swizzle. */
3323 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3324 cb_color_base
|= tex
->surface
.tile_swizzle
;
3326 if (!tex
->fmask_offset
)
3327 cb_color_fmask
= cb_color_base
;
3328 if (cb
->base
.u
.tex
.level
> 0)
3329 cb_color_cmask
= cb_color_base
;
3331 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3333 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3334 slice_tile_max
= level_info
->nblk_x
*
3335 level_info
->nblk_y
/ 64 - 1;
3336 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3338 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3339 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3340 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3342 if (tex
->fmask_offset
) {
3343 if (sctx
->chip_class
>= GFX7
)
3344 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3345 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3346 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3348 /* This must be set for fast clear to work without FMASK. */
3349 if (sctx
->chip_class
>= GFX7
)
3350 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3351 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3352 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3355 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3356 sctx
->chip_class
>= GFX8
? 14 : 13);
3357 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3358 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3359 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3360 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3361 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3362 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3363 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3364 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3365 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3366 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3367 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3368 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3369 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3371 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3372 radeon_emit(cs
, cb_dcc_base
);
3376 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3377 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3380 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3381 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3382 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3384 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3385 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3386 zb
->base
.texture
->nr_samples
> 1 ?
3387 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3388 RADEON_PRIO_DEPTH_BUFFER
);
3390 if (sctx
->chip_class
>= GFX10
) {
3391 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3392 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3394 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3395 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3396 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3397 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3398 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3399 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3400 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3401 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3402 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3404 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3405 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3406 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3407 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3408 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3409 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3410 } else if (sctx
->chip_class
== GFX9
) {
3411 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3412 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3413 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3414 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3416 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3417 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3418 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3419 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3420 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3421 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3422 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3423 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3424 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3425 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3426 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3427 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3429 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3430 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3431 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3433 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3435 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3436 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3437 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3438 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3439 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3440 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3441 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3442 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3443 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3444 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3445 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3448 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3449 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3450 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3452 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3453 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3454 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3455 if (sctx
->chip_class
== GFX9
)
3456 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3458 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3460 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3461 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3464 /* Framebuffer dimensions. */
3465 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3466 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3467 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3469 if (sctx
->screen
->dfsm_allowed
) {
3470 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3471 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3474 sctx
->framebuffer
.dirty_cbufs
= 0;
3475 sctx
->framebuffer
.dirty_zsbuf
= false;
3478 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3480 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3481 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3482 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3483 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3485 /* Smoothing (only possible with nr_samples == 1) uses the same
3486 * sample locations as the MSAA it simulates.
3488 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3489 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3491 /* On Polaris, the small primitive filter uses the sample locations
3492 * even when MSAA is off, so we need to make sure they're set to 0.
3494 * GFX10 uses sample locations unconditionally, so they always need
3497 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
||
3498 sctx
->chip_class
>= GFX10
) &&
3499 nr_samples
!= sctx
->sample_locs_num_samples
) {
3500 sctx
->sample_locs_num_samples
= nr_samples
;
3501 si_emit_sample_locations(cs
, nr_samples
);
3504 if (sctx
->family
>= CHIP_POLARIS10
) {
3505 unsigned small_prim_filter_cntl
=
3506 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3508 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3510 /* The alternative of setting sample locations to 0 would
3511 * require a DB flush to avoid Z errors, see
3512 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3514 if (has_msaa_sample_loc_bug
&&
3515 sctx
->framebuffer
.nr_samples
> 1 &&
3516 !rs
->multisample_enable
)
3517 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3519 radeon_opt_set_context_reg(sctx
,
3520 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3521 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3522 small_prim_filter_cntl
);
3525 /* The exclusion bits can be set to improve rasterization efficiency
3526 * if no sample lies on the pixel boundary (-8 sample offset).
3528 bool exclusion
= sctx
->chip_class
>= GFX7
&&
3529 (!rs
->multisample_enable
|| nr_samples
!= 16);
3530 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3531 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3532 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3533 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3536 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3538 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3539 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3541 if (!sctx
->screen
->has_out_of_order_rast
)
3544 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3547 colormask
&= blend
->cb_target_enabled_4bit
;
3552 /* Conservative: No logic op. */
3553 if (colormask
&& blend
->logicop_enable
)
3556 struct si_dsa_order_invariance dsa_order_invariant
= {
3557 .zs
= true, .pass_set
= true, .pass_last
= false
3560 if (sctx
->framebuffer
.state
.zsbuf
) {
3561 struct si_texture
*zstex
=
3562 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3563 bool has_stencil
= zstex
->surface
.has_stencil
;
3564 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3565 if (!dsa_order_invariant
.zs
)
3568 /* The set of PS invocations is always order invariant,
3569 * except when early Z/S tests are requested. */
3570 if (sctx
->ps_shader
.cso
&&
3571 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3572 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3573 !dsa_order_invariant
.pass_set
)
3576 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3577 !dsa_order_invariant
.pass_set
)
3584 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3587 /* Only commutative blending. */
3588 if (blendmask
& ~blend
->commutative_4bit
)
3591 if (!dsa_order_invariant
.pass_set
)
3595 if (colormask
& ~blendmask
) {
3596 if (!dsa_order_invariant
.pass_last
)
3603 static void si_emit_msaa_config(struct si_context
*sctx
)
3605 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3606 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3607 /* 33% faster rendering to linear color buffers */
3608 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3609 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3610 unsigned sc_mode_cntl_1
=
3611 S_028A4C_WALK_SIZE(dst_is_linear
) |
3612 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3613 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3614 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3615 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3617 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3618 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3619 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3620 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3621 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3622 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3623 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3624 S_028804_INCOHERENT_EQAA_READS(1) |
3625 S_028804_INTERPOLATE_COMP_Z(1) |
3626 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3627 unsigned coverage_samples
, color_samples
, z_samples
;
3628 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3630 /* S: Coverage samples (up to 16x):
3631 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3632 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3634 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3635 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3636 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3637 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3638 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3641 * F: Color samples (up to 8x, must be <= coverage samples):
3642 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3643 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3645 * Can be anything between coverage and color samples:
3646 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3647 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3648 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3649 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3650 * # All are currently set the same as coverage samples.
3652 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3653 * flag for undefined color samples. A shader-based resolve must handle unknowns
3654 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3655 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3656 * useful. The CB resolve always drops unknowns.
3658 * Sensible AA configurations:
3659 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3660 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3661 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3662 * EQAA 8s 8z 8f = 8x MSAA
3663 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3664 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3665 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3666 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3667 * EQAA 4s 4z 4f = 4x MSAA
3668 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3669 * EQAA 2s 2z 2f = 2x MSAA
3671 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3672 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3673 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3675 if (sctx
->framebuffer
.state
.zsbuf
) {
3676 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3677 z_samples
= MAX2(1, z_samples
);
3679 z_samples
= coverage_samples
;
3681 } else if (sctx
->smoothing_enabled
) {
3682 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3684 coverage_samples
= color_samples
= z_samples
= 1;
3687 /* Required by OpenGL line rasterization.
3689 * TODO: We should also enable perpendicular endcaps for AA lines,
3690 * but that requires implementing line stippling in the pixel
3691 * shader. SC can only do line stippling with axis-aligned
3694 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3695 unsigned sc_aa_config
= 0;
3697 if (coverage_samples
> 1) {
3698 /* distance from the pixel center, indexed by log2(nr_samples) */
3699 static unsigned max_dist
[] = {
3706 unsigned log_samples
= util_logbase2(coverage_samples
);
3707 unsigned log_z_samples
= util_logbase2(z_samples
);
3708 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3709 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3711 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3712 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3713 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3714 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3716 if (sctx
->framebuffer
.nr_samples
> 1) {
3717 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3718 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3719 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3720 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3721 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3722 } else if (sctx
->smoothing_enabled
) {
3723 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3727 unsigned initial_cdw
= cs
->current
.cdw
;
3729 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3730 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3731 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3733 /* R_028804_DB_EQAA */
3734 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3736 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3737 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3738 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3740 if (initial_cdw
!= cs
->current
.cdw
) {
3741 sctx
->context_roll
= true;
3743 /* GFX9: Flush DFSM when the AA mode changes. */
3744 if (sctx
->screen
->dfsm_allowed
) {
3745 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3746 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3751 void si_update_ps_iter_samples(struct si_context
*sctx
)
3753 if (sctx
->framebuffer
.nr_samples
> 1)
3754 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3755 if (sctx
->screen
->dpbb_allowed
)
3756 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3759 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3761 struct si_context
*sctx
= (struct si_context
*)ctx
;
3763 /* The hardware can only do sample shading with 2^n samples. */
3764 min_samples
= util_next_power_of_two(min_samples
);
3766 if (sctx
->ps_iter_samples
== min_samples
)
3769 sctx
->ps_iter_samples
= min_samples
;
3770 sctx
->do_update_shaders
= true;
3772 si_update_ps_iter_samples(sctx
);
3780 * Build the sampler view descriptor for a buffer texture.
3781 * @param state 256-bit descriptor; only the high 128 bits are filled in
3784 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3785 enum pipe_format format
,
3786 unsigned offset
, unsigned size
,
3789 const struct util_format_description
*desc
;
3791 unsigned num_records
;
3793 desc
= util_format_description(format
);
3794 stride
= desc
->block
.bits
/ 8;
3796 num_records
= size
/ stride
;
3797 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3799 /* The NUM_RECORDS field has a different meaning depending on the chip,
3800 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3803 * - If STRIDE == 0, it's in byte units.
3804 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3807 * - For SMEM and STRIDE == 0, it's in byte units.
3808 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3809 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3810 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3811 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3812 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3813 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3814 * That way the same descriptor can be used by both SMEM and VMEM.
3817 * - For SMEM and STRIDE == 0, it's in byte units.
3818 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3819 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3820 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3822 if (screen
->info
.chip_class
== GFX9
&& HAVE_LLVM
< 0x0800)
3823 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3824 * from STRIDE to bytes. This works around it by setting
3825 * NUM_RECORDS to at least the size of one element, so that
3826 * the first element is readable when IDXEN == 0.
3828 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3829 else if (screen
->info
.chip_class
== GFX8
)
3830 num_records
*= stride
;
3833 state
[5] = S_008F04_STRIDE(stride
);
3834 state
[6] = num_records
;
3835 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3836 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3837 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3838 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3840 if (screen
->info
.chip_class
>= GFX10
) {
3841 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3843 /* OOB_SELECT chooses the out-of-bounds check:
3844 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3845 * - 1: index >= NUM_RECORDS
3846 * - 2: NUM_RECORDS == 0
3847 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3848 * else: swizzle_address >= NUM_RECORDS
3850 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3851 S_008F0C_OOB_SELECT(0) |
3852 S_008F0C_RESOURCE_LEVEL(1);
3855 unsigned num_format
, data_format
;
3857 first_non_void
= util_format_get_first_non_void_channel(format
);
3858 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3859 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3861 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) |
3862 S_008F0C_DATA_FORMAT(data_format
);
3866 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3868 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3870 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3871 /* For the pre-defined border color values (white, opaque
3872 * black, transparent black), the only thing that matters is
3873 * that the alpha channel winds up in the correct place
3874 * (because the RGB channels are all the same) so either of
3875 * these enumerations will work.
3877 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3878 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3880 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3881 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3882 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3883 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3885 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3886 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3887 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3888 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3889 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3896 * Build the sampler view descriptor for a texture.
3899 gfx10_make_texture_descriptor(struct si_screen
*screen
,
3900 struct si_texture
*tex
,
3902 enum pipe_texture_target target
,
3903 enum pipe_format pipe_format
,
3904 const unsigned char state_swizzle
[4],
3905 unsigned first_level
, unsigned last_level
,
3906 unsigned first_layer
, unsigned last_layer
,
3907 unsigned width
, unsigned height
, unsigned depth
,
3909 uint32_t *fmask_state
)
3911 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3912 const struct util_format_description
*desc
;
3913 unsigned img_format
;
3914 unsigned char swizzle
[4];
3918 desc
= util_format_description(pipe_format
);
3919 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3921 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3922 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3923 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3924 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3925 bool is_stencil
= false;
3927 switch (pipe_format
) {
3928 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3929 case PIPE_FORMAT_X32_S8X24_UINT
:
3930 case PIPE_FORMAT_X8Z24_UNORM
:
3931 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3934 case PIPE_FORMAT_X24S8_UINT
:
3936 * X24S8 is implemented as an 8_8_8_8 data format, to
3937 * fix texture gathers. This affects at least
3938 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3940 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3944 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3945 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3948 if (tex
->upgraded_depth
&& !is_stencil
) {
3949 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3950 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3953 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3957 (res
->target
== PIPE_TEXTURE_CUBE
||
3958 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3959 /* For the purpose of shader images, treat cube maps as 2D
3962 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3964 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3967 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3969 depth
= res
->array_size
;
3970 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3971 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3972 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3973 depth
= res
->array_size
;
3974 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3975 depth
= res
->array_size
/ 6;
3978 state
[1] = S_00A004_FORMAT(img_format
) |
3979 S_00A004_WIDTH_LO(width
- 1);
3980 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
3981 S_00A008_HEIGHT(height
- 1) |
3982 S_00A008_RESOURCE_LEVEL(1);
3983 state
[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3984 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3985 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3986 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3987 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ?
3989 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ?
3990 util_logbase2(res
->nr_samples
) :
3992 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) |
3993 S_00A00C_TYPE(type
);
3994 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3995 * to know the total number of layers.
3997 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
)
3998 ? depth
- 1 : last_layer
) |
3999 S_00A010_BASE_ARRAY(first_layer
);
4000 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
4001 S_00A014_MAX_MIP(res
->nr_samples
> 1 ?
4002 util_logbase2(res
->nr_samples
) :
4003 tex
->buffer
.b
.b
.last_level
) |
4004 S_00A014_PERF_MOD(4);
4008 if (tex
->dcc_offset
) {
4009 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
4010 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
4011 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4014 /* Initialize the sampler view for FMASK. */
4015 if (tex
->fmask_offset
) {
4018 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4020 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4021 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4023 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
4026 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
4029 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
4032 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
4035 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
4038 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
4041 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
4044 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
4047 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
4050 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
4053 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
4056 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
4059 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
4062 unreachable("invalid nr_samples");
4065 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4066 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
4067 S_00A004_FORMAT(format
) |
4068 S_00A004_WIDTH_LO(width
- 1);
4069 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
4070 S_00A008_HEIGHT(height
- 1) |
4071 S_00A008_RESOURCE_LEVEL(1);
4072 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4073 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4074 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4075 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4076 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4077 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4078 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
4079 S_00A010_BASE_ARRAY(first_layer
);
4081 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
4087 * Build the sampler view descriptor for a texture (SI-GFX9).
4090 si_make_texture_descriptor(struct si_screen
*screen
,
4091 struct si_texture
*tex
,
4093 enum pipe_texture_target target
,
4094 enum pipe_format pipe_format
,
4095 const unsigned char state_swizzle
[4],
4096 unsigned first_level
, unsigned last_level
,
4097 unsigned first_layer
, unsigned last_layer
,
4098 unsigned width
, unsigned height
, unsigned depth
,
4100 uint32_t *fmask_state
)
4102 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
4103 const struct util_format_description
*desc
;
4104 unsigned char swizzle
[4];
4106 unsigned num_format
, data_format
, type
, num_samples
;
4109 desc
= util_format_description(pipe_format
);
4111 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
4112 MAX2(1, res
->nr_samples
) :
4113 MAX2(1, res
->nr_storage_samples
);
4115 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
4116 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
4117 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
4118 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
4120 switch (pipe_format
) {
4121 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4122 case PIPE_FORMAT_X32_S8X24_UINT
:
4123 case PIPE_FORMAT_X8Z24_UNORM
:
4124 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4126 case PIPE_FORMAT_X24S8_UINT
:
4128 * X24S8 is implemented as an 8_8_8_8 data format, to
4129 * fix texture gathers. This affects at least
4130 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4132 if (screen
->info
.chip_class
<= GFX8
)
4133 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
4135 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4138 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
4141 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
4144 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
4146 switch (pipe_format
) {
4147 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4148 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4151 if (first_non_void
< 0) {
4152 if (util_format_is_compressed(pipe_format
)) {
4153 switch (pipe_format
) {
4154 case PIPE_FORMAT_DXT1_SRGB
:
4155 case PIPE_FORMAT_DXT1_SRGBA
:
4156 case PIPE_FORMAT_DXT3_SRGBA
:
4157 case PIPE_FORMAT_DXT5_SRGBA
:
4158 case PIPE_FORMAT_BPTC_SRGBA
:
4159 case PIPE_FORMAT_ETC2_SRGB8
:
4160 case PIPE_FORMAT_ETC2_SRGB8A1
:
4161 case PIPE_FORMAT_ETC2_SRGBA8
:
4162 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4164 case PIPE_FORMAT_RGTC1_SNORM
:
4165 case PIPE_FORMAT_LATC1_SNORM
:
4166 case PIPE_FORMAT_RGTC2_SNORM
:
4167 case PIPE_FORMAT_LATC2_SNORM
:
4168 case PIPE_FORMAT_ETC2_R11_SNORM
:
4169 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4170 /* implies float, so use SNORM/UNORM to determine
4171 whether data is signed or not */
4172 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4173 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4176 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4179 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4180 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4182 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4184 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4185 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4187 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4189 switch (desc
->channel
[first_non_void
].type
) {
4190 case UTIL_FORMAT_TYPE_FLOAT
:
4191 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4193 case UTIL_FORMAT_TYPE_SIGNED
:
4194 if (desc
->channel
[first_non_void
].normalized
)
4195 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4196 else if (desc
->channel
[first_non_void
].pure_integer
)
4197 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4199 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4201 case UTIL_FORMAT_TYPE_UNSIGNED
:
4202 if (desc
->channel
[first_non_void
].normalized
)
4203 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4204 else if (desc
->channel
[first_non_void
].pure_integer
)
4205 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4207 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4212 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4213 if (data_format
== ~0) {
4217 /* S8 with Z32 HTILE needs a special format. */
4218 if (screen
->info
.chip_class
== GFX9
&&
4219 pipe_format
== PIPE_FORMAT_S8_UINT
&&
4220 tex
->tc_compatible_htile
)
4221 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4224 (res
->target
== PIPE_TEXTURE_CUBE
||
4225 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4226 (screen
->info
.chip_class
<= GFX8
&&
4227 res
->target
== PIPE_TEXTURE_3D
))) {
4228 /* For the purpose of shader images, treat cube maps and 3D
4229 * textures as 2D arrays. For 3D textures, the address
4230 * calculations for mipmaps are different, so we rely on the
4231 * caller to effectively disable mipmaps.
4233 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4235 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4237 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4240 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4242 depth
= res
->array_size
;
4243 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
4244 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4245 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4246 depth
= res
->array_size
;
4247 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4248 depth
= res
->array_size
/ 6;
4251 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
4252 S_008F14_NUM_FORMAT(num_format
));
4253 state
[2] = (S_008F18_WIDTH(width
- 1) |
4254 S_008F18_HEIGHT(height
- 1) |
4255 S_008F18_PERF_MOD(4));
4256 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4257 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4258 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4259 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4260 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4261 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
4262 util_logbase2(num_samples
) :
4264 S_008F1C_TYPE(type
));
4266 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4270 if (screen
->info
.chip_class
== GFX9
) {
4271 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4273 /* Depth is the the last accessible layer on Gfx9.
4274 * The hw doesn't need to know the total number of layers.
4276 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4277 state
[4] |= S_008F20_DEPTH(depth
- 1);
4279 state
[4] |= S_008F20_DEPTH(last_layer
);
4281 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4282 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
4283 util_logbase2(num_samples
) :
4284 tex
->buffer
.b
.b
.last_level
);
4286 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4287 state
[4] |= S_008F20_DEPTH(depth
- 1);
4288 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4291 if (tex
->dcc_offset
) {
4292 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4294 /* The last dword is unused by hw. The shader uses it to clear
4295 * bits in the first dword of sampler state.
4297 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4298 if (first_level
== last_level
)
4299 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4301 state
[7] = 0xffffffff;
4305 /* Initialize the sampler view for FMASK. */
4306 if (tex
->fmask_offset
) {
4307 uint32_t data_format
, num_format
;
4309 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4311 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4312 if (screen
->info
.chip_class
== GFX9
) {
4313 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4314 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4316 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4319 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4322 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4325 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4328 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4331 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4334 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4337 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4340 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4343 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4346 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4349 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4352 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4355 unreachable("invalid nr_samples");
4358 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4360 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4363 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4366 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4369 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4372 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4375 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4378 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4381 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4384 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4387 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4390 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4393 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4396 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4399 unreachable("invalid nr_samples");
4401 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4405 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4406 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
4407 S_008F14_DATA_FORMAT(data_format
) |
4408 S_008F14_NUM_FORMAT(num_format
);
4409 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
4410 S_008F18_HEIGHT(height
- 1);
4411 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4412 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4413 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4414 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4415 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4417 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4421 if (screen
->info
.chip_class
== GFX9
) {
4422 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4423 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4424 S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4425 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4426 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4428 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4429 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4430 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4431 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4437 * Create a sampler view.
4439 * @param ctx context
4440 * @param texture texture
4441 * @param state sampler view template
4442 * @param width0 width0 override (for compressed textures as int)
4443 * @param height0 height0 override (for compressed textures as int)
4444 * @param force_level set the base address to the level (for compressed textures)
4446 struct pipe_sampler_view
*
4447 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4448 struct pipe_resource
*texture
,
4449 const struct pipe_sampler_view
*state
,
4450 unsigned width0
, unsigned height0
,
4451 unsigned force_level
)
4453 struct si_context
*sctx
= (struct si_context
*)ctx
;
4454 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4455 struct si_texture
*tex
= (struct si_texture
*)texture
;
4456 unsigned base_level
, first_level
, last_level
;
4457 unsigned char state_swizzle
[4];
4458 unsigned height
, depth
, width
;
4459 unsigned last_layer
= state
->u
.tex
.last_layer
;
4460 enum pipe_format pipe_format
;
4461 const struct legacy_surf_level
*surflevel
;
4466 /* initialize base object */
4467 view
->base
= *state
;
4468 view
->base
.texture
= NULL
;
4469 view
->base
.reference
.count
= 1;
4470 view
->base
.context
= ctx
;
4473 pipe_resource_reference(&view
->base
.texture
, texture
);
4475 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4476 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4477 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4478 state
->format
== PIPE_FORMAT_S8_UINT
)
4479 view
->is_stencil_sampler
= true;
4481 /* Buffer resource. */
4482 if (texture
->target
== PIPE_BUFFER
) {
4483 si_make_buffer_descriptor(sctx
->screen
,
4484 si_resource(texture
),
4486 state
->u
.buf
.offset
,
4492 state_swizzle
[0] = state
->swizzle_r
;
4493 state_swizzle
[1] = state
->swizzle_g
;
4494 state_swizzle
[2] = state
->swizzle_b
;
4495 state_swizzle
[3] = state
->swizzle_a
;
4498 first_level
= state
->u
.tex
.first_level
;
4499 last_level
= state
->u
.tex
.last_level
;
4502 depth
= texture
->depth0
;
4504 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4505 assert(force_level
== first_level
&&
4506 force_level
== last_level
);
4507 base_level
= force_level
;
4510 width
= u_minify(width
, force_level
);
4511 height
= u_minify(height
, force_level
);
4512 depth
= u_minify(depth
, force_level
);
4515 /* This is not needed if state trackers set last_layer correctly. */
4516 if (state
->target
== PIPE_TEXTURE_1D
||
4517 state
->target
== PIPE_TEXTURE_2D
||
4518 state
->target
== PIPE_TEXTURE_RECT
||
4519 state
->target
== PIPE_TEXTURE_CUBE
)
4520 last_layer
= state
->u
.tex
.first_layer
;
4522 /* Texturing with separate depth and stencil. */
4523 pipe_format
= state
->format
;
4525 /* Depth/stencil texturing sometimes needs separate texture. */
4526 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4527 if (!tex
->flushed_depth_texture
&&
4528 !si_init_flushed_depth_texture(ctx
, texture
)) {
4529 pipe_resource_reference(&view
->base
.texture
, NULL
);
4534 assert(tex
->flushed_depth_texture
);
4536 /* Override format for the case where the flushed texture
4537 * contains only Z or only S.
4539 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4540 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4542 tex
= tex
->flushed_depth_texture
;
4545 surflevel
= tex
->surface
.u
.legacy
.level
;
4547 if (tex
->db_compatible
) {
4548 if (!view
->is_stencil_sampler
)
4549 pipe_format
= tex
->db_render_format
;
4551 switch (pipe_format
) {
4552 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4553 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4555 case PIPE_FORMAT_X8Z24_UNORM
:
4556 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4557 /* Z24 is always stored like this for DB
4560 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4562 case PIPE_FORMAT_X24S8_UINT
:
4563 case PIPE_FORMAT_S8X24_UINT
:
4564 case PIPE_FORMAT_X32_S8X24_UINT
:
4565 pipe_format
= PIPE_FORMAT_S8_UINT
;
4566 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4572 view
->dcc_incompatible
=
4573 vi_dcc_formats_are_incompatible(texture
,
4574 state
->u
.tex
.first_level
,
4577 sctx
->screen
->make_texture_descriptor(sctx
->screen
, tex
, true,
4578 state
->target
, pipe_format
, state_swizzle
,
4579 first_level
, last_level
,
4580 state
->u
.tex
.first_layer
, last_layer
,
4581 width
, height
, depth
,
4582 view
->state
, view
->fmask_state
);
4584 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4585 view
->is_integer
= false;
4587 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4588 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4591 /* Whether the number format is {U,S}{SCALED,INT} */
4593 (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4594 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4595 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4599 view
->base_level_info
= &surflevel
[base_level
];
4600 view
->base_level
= base_level
;
4601 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4605 static struct pipe_sampler_view
*
4606 si_create_sampler_view(struct pipe_context
*ctx
,
4607 struct pipe_resource
*texture
,
4608 const struct pipe_sampler_view
*state
)
4610 return si_create_sampler_view_custom(ctx
, texture
, state
,
4611 texture
? texture
->width0
: 0,
4612 texture
? texture
->height0
: 0, 0);
4615 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4616 struct pipe_sampler_view
*state
)
4618 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4620 pipe_resource_reference(&state
->texture
, NULL
);
4624 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4626 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4627 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4629 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4630 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4633 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4634 const struct pipe_sampler_state
*state
,
4635 const union pipe_color_union
*color
,
4638 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4639 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4641 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4642 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4643 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4644 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4646 #define simple_border_types(elt) \
4648 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4649 color->elt[2] == 0 && color->elt[3] == 0) \
4650 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4651 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4652 color->elt[2] == 0 && color->elt[3] == 1) \
4653 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4654 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4655 color->elt[2] == 1 && color->elt[3] == 1) \
4656 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4660 simple_border_types(ui
);
4662 simple_border_types(f
);
4664 #undef simple_border_types
4668 /* Check if the border has been uploaded already. */
4669 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4670 if (memcmp(&sctx
->border_color_table
[i
], color
,
4671 sizeof(*color
)) == 0)
4674 if (i
>= SI_MAX_BORDER_COLORS
) {
4675 /* Getting 4096 unique border colors is very unlikely. */
4676 fprintf(stderr
, "radeonsi: The border color table is full. "
4677 "Any new border colors will be just black. "
4678 "Please file a bug.\n");
4679 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4682 if (i
== sctx
->border_color_count
) {
4683 /* Upload a new border color. */
4684 memcpy(&sctx
->border_color_table
[i
], color
,
4686 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4687 color
, sizeof(*color
));
4688 sctx
->border_color_count
++;
4691 return S_008F3C_BORDER_COLOR_PTR(i
) |
4692 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4695 static inline int S_FIXED(float value
, unsigned frac_bits
)
4697 return value
* (1 << frac_bits
);
4700 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4702 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4703 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4704 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4706 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4707 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4710 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4723 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4724 const struct pipe_sampler_state
*state
)
4726 struct si_context
*sctx
= (struct si_context
*)ctx
;
4727 struct si_screen
*sscreen
= sctx
->screen
;
4728 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4729 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4730 : state
->max_anisotropy
;
4731 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4732 union pipe_color_union clamped_border_color
;
4739 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4741 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4742 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4743 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4744 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4745 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4746 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4747 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4748 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4749 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4750 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4751 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4752 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4753 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4754 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4755 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4756 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4757 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4758 S_008F38_MIP_POINT_PRECLAMP(0));
4759 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4761 if (sscreen
->info
.chip_class
>= GFX10
) {
4762 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4764 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4765 S_008F38_FILTER_PREC_FIX(1) |
4766 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4769 /* Create sampler resource for integer textures. */
4770 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4771 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4773 /* Create sampler resource for upgraded depth textures. */
4774 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4776 for (unsigned i
= 0; i
< 4; ++i
) {
4777 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4778 * when the border color is 1.0. */
4779 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4782 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4783 if (sscreen
->info
.chip_class
<= GFX9
)
4784 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4786 rstate
->upgraded_depth_val
[3] =
4787 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4793 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4795 struct si_context
*sctx
= (struct si_context
*)ctx
;
4797 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4800 sctx
->sample_mask
= sample_mask
;
4801 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4804 static void si_emit_sample_mask(struct si_context
*sctx
)
4806 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4807 unsigned mask
= sctx
->sample_mask
;
4809 /* Needed for line and polygon smoothing as well as for the Polaris
4810 * small primitive filter. We expect the state tracker to take care of
4813 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4814 (mask
& 1 && sctx
->blitter
->running
));
4816 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4817 radeon_emit(cs
, mask
| (mask
<< 16));
4818 radeon_emit(cs
, mask
| (mask
<< 16));
4821 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4824 struct si_sampler_state
*s
= state
;
4826 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4833 * Vertex elements & buffers
4836 struct si_fast_udiv_info32
4837 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4839 struct util_fast_udiv_info info
=
4840 util_compute_fast_udiv_info(D
, num_bits
, 32);
4842 struct si_fast_udiv_info32 result
= {
4851 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4853 const struct pipe_vertex_element
*elements
)
4855 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4856 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4857 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4858 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4859 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4860 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4861 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4862 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4863 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4866 assert(count
<= SI_MAX_ATTRIBS
);
4871 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4873 for (i
= 0; i
< count
; ++i
) {
4874 const struct util_format_description
*desc
;
4875 const struct util_format_channel_description
*channel
;
4877 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4879 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4884 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4885 if (instance_divisor
) {
4886 v
->uses_instance_divisors
= true;
4888 if (instance_divisor
== 1) {
4889 v
->instance_divisor_is_one
|= 1u << i
;
4891 v
->instance_divisor_is_fetched
|= 1u << i
;
4892 divisor_factors
[i
] =
4893 si_compute_fast_udiv_info32(instance_divisor
, 32);
4897 if (!used
[vbo_index
]) {
4898 v
->first_vb_use_mask
|= 1 << i
;
4899 used
[vbo_index
] = true;
4902 desc
= util_format_description(elements
[i
].src_format
);
4903 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4904 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4906 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4907 v
->src_offset
[i
] = elements
[i
].src_offset
;
4908 v
->vertex_buffer_index
[i
] = vbo_index
;
4910 bool always_fix
= false;
4911 union si_vs_fix_fetch fix_fetch
;
4912 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4915 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4918 switch (channel
->type
) {
4919 case UTIL_FORMAT_TYPE_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4920 case UTIL_FORMAT_TYPE_FIXED
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
; break;
4921 case UTIL_FORMAT_TYPE_SIGNED
: {
4922 if (channel
->pure_integer
)
4923 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4924 else if (channel
->normalized
)
4925 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4927 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4930 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4931 if (channel
->pure_integer
)
4932 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4933 else if (channel
->normalized
)
4934 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4936 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4939 default: unreachable("bad format type");
4942 switch (elements
[i
].src_format
) {
4943 case PIPE_FORMAT_R11G11B10_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4944 default: unreachable("bad other format");
4948 if (desc
->channel
[0].size
== 10) {
4949 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4950 log_hw_load_size
= 2;
4952 /* The hardware always treats the 2-bit alpha channel as
4953 * unsigned, so a shader workaround is needed. The affected
4954 * chips are GFX8 and older except Stoney (GFX8.1).
4956 always_fix
= sscreen
->info
.chip_class
<= GFX8
&&
4957 sscreen
->info
.family
!= CHIP_STONEY
&&
4958 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4959 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4960 fix_fetch
.u
.log_size
= 3; /* special encoding */
4961 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4962 log_hw_load_size
= 2;
4964 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4965 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4968 * - doubles (multiple loads + truncate to float)
4969 * - 32-bit requiring a conversion
4972 (fix_fetch
.u
.log_size
== 3) ||
4973 (fix_fetch
.u
.log_size
== 2 &&
4974 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4975 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4976 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4978 /* Also fixup 8_8_8 and 16_16_16. */
4979 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4981 log_hw_load_size
= fix_fetch
.u
.log_size
;
4985 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4986 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4987 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4988 fix_fetch
.u
.reverse
= 1;
4991 /* Force the workaround for unaligned access here already if the
4992 * offset relative to the vertex buffer base is unaligned.
4994 * There is a theoretical case in which this is too conservative:
4995 * if the vertex buffer's offset is also unaligned in just the
4996 * right way, we end up with an aligned address after all.
4997 * However, this case should be extremely rare in practice (it
4998 * won't happen in well-behaved applications), and taking it
4999 * into account would complicate the fast path (where everything
5000 * is nicely aligned).
5002 bool check_alignment
=
5003 log_hw_load_size
>= 1 &&
5004 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
== GFX10
);
5005 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
5007 if (check_alignment
&&
5008 (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
5011 if (always_fix
|| check_alignment
|| opencode
)
5012 v
->fix_fetch
[i
] = fix_fetch
.bits
;
5015 v
->fix_fetch_opencode
|= 1 << i
;
5016 if (opencode
|| always_fix
)
5017 v
->fix_fetch_always
|= 1 << i
;
5019 if (check_alignment
&& !opencode
) {
5020 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
5022 v
->fix_fetch_unaligned
|= 1 << i
;
5023 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
5024 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
5027 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
5028 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
5029 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
5030 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
5032 if (sscreen
->info
.chip_class
>= GFX10
) {
5033 const struct gfx10_format
*fmt
=
5034 &gfx10_format_table
[elements
[i
].src_format
];
5035 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
5036 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) |
5037 S_008F0C_RESOURCE_LEVEL(1);
5039 unsigned data_format
, num_format
;
5040 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
5041 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
5042 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) |
5043 S_008F0C_DATA_FORMAT(data_format
);
5047 if (v
->instance_divisor_is_fetched
) {
5048 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
5050 v
->instance_divisor_factor_buffer
=
5051 (struct si_resource
*)
5052 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
5053 num_divisors
* sizeof(divisor_factors
[0]));
5054 if (!v
->instance_divisor_factor_buffer
) {
5058 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
5059 NULL
, PIPE_TRANSFER_WRITE
);
5060 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
5065 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
5067 struct si_context
*sctx
= (struct si_context
*)ctx
;
5068 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
5069 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5071 sctx
->vertex_elements
= v
;
5072 sctx
->vertex_buffers_dirty
= true;
5076 old
->count
!= v
->count
||
5077 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
5078 /* we don't check which divisors changed */
5079 v
->uses_instance_divisors
||
5080 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) & sctx
->vertex_buffer_unaligned
||
5081 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
5082 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
5083 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
5084 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5085 * functions of fix_fetch and the src_offset alignment.
5086 * If they change and fix_fetch doesn't, it must be due to different
5087 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5088 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
5089 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
5090 sctx
->do_update_shaders
= true;
5092 if (v
&& v
->instance_divisor_is_fetched
) {
5093 struct pipe_constant_buffer cb
;
5095 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
5096 cb
.user_buffer
= NULL
;
5097 cb
.buffer_offset
= 0;
5098 cb
.buffer_size
= 0xffffffff;
5099 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
5103 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
5105 struct si_context
*sctx
= (struct si_context
*)ctx
;
5106 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5108 if (sctx
->vertex_elements
== state
)
5109 sctx
->vertex_elements
= NULL
;
5110 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
5114 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
5115 unsigned start_slot
, unsigned count
,
5116 const struct pipe_vertex_buffer
*buffers
)
5118 struct si_context
*sctx
= (struct si_context
*)ctx
;
5119 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
5120 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
5121 uint32_t unaligned
= orig_unaligned
;
5124 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
5127 for (i
= 0; i
< count
; i
++) {
5128 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
5129 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
5130 struct pipe_resource
*buf
= src
->buffer
.resource
;
5132 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
5133 dsti
->buffer_offset
= src
->buffer_offset
;
5134 dsti
->stride
= src
->stride
;
5135 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
5136 unaligned
|= 1 << (start_slot
+ i
);
5138 unaligned
&= ~(1 << (start_slot
+ i
));
5140 si_context_add_resource_size(sctx
, buf
);
5142 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
5145 for (i
= 0; i
< count
; i
++) {
5146 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
5148 unaligned
&= ~u_bit_consecutive(start_slot
, count
);
5150 sctx
->vertex_buffers_dirty
= true;
5151 sctx
->vertex_buffer_unaligned
= unaligned
;
5153 /* Check whether alignment may have changed in a way that requires
5154 * shader changes. This check is conservative: a vertex buffer can only
5155 * trigger a shader change if the misalignment amount changes (e.g.
5156 * from byte-aligned to short-aligned), but we only keep track of
5157 * whether buffers are at least dword-aligned, since that should always
5158 * be the case in well-behaved applications anyway.
5160 if (sctx
->vertex_elements
&&
5161 (sctx
->vertex_elements
->vb_alignment_check_mask
&
5162 (unaligned
| orig_unaligned
) & u_bit_consecutive(start_slot
, count
)))
5163 sctx
->do_update_shaders
= true;
5170 static void si_set_tess_state(struct pipe_context
*ctx
,
5171 const float default_outer_level
[4],
5172 const float default_inner_level
[2])
5174 struct si_context
*sctx
= (struct si_context
*)ctx
;
5175 struct pipe_constant_buffer cb
;
5178 memcpy(array
, default_outer_level
, sizeof(float) * 4);
5179 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
5182 cb
.user_buffer
= NULL
;
5183 cb
.buffer_size
= sizeof(array
);
5185 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
5186 (void*)array
, sizeof(array
),
5189 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
5190 pipe_resource_reference(&cb
.buffer
, NULL
);
5193 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5195 struct si_context
*sctx
= (struct si_context
*)ctx
;
5197 si_update_fb_dirtiness_after_rendering(sctx
);
5199 /* Multisample surfaces are flushed in si_decompress_textures. */
5200 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5201 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5202 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5203 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5207 /* This only ensures coherency for shader image/buffer stores. */
5208 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5210 struct si_context
*sctx
= (struct si_context
*)ctx
;
5212 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5215 /* Subsequent commands must wait for all shader invocations to
5217 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
5218 SI_CONTEXT_CS_PARTIAL_FLUSH
;
5220 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5221 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
|
5222 SI_CONTEXT_INV_VCACHE
;
5224 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
5225 PIPE_BARRIER_SHADER_BUFFER
|
5226 PIPE_BARRIER_TEXTURE
|
5227 PIPE_BARRIER_IMAGE
|
5228 PIPE_BARRIER_STREAMOUT_BUFFER
|
5229 PIPE_BARRIER_GLOBAL_BUFFER
)) {
5230 /* As far as I can tell, L1 contents are written back to L2
5231 * automatically at end of shader, but the contents of other
5232 * L1 caches might still be stale. */
5233 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5236 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5237 /* Indices are read through TC L2 since GFX8.
5240 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5241 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5244 /* MSAA color, any depth and any stencil are flushed in
5245 * si_decompress_textures when needed.
5247 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
5248 sctx
->framebuffer
.uncompressed_cb_mask
) {
5249 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5251 if (sctx
->chip_class
<= GFX8
)
5252 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5255 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5256 if (sctx
->screen
->info
.chip_class
<= GFX8
&&
5257 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5258 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5261 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5263 struct pipe_blend_state blend
;
5265 memset(&blend
, 0, sizeof(blend
));
5266 blend
.independent_blend_enable
= true;
5267 blend
.rt
[0].colormask
= 0xf;
5268 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5271 static void si_init_config(struct si_context
*sctx
);
5273 void si_init_state_compute_functions(struct si_context
*sctx
)
5275 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5276 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5277 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5278 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5279 sctx
->b
.memory_barrier
= si_memory_barrier
;
5282 void si_init_state_functions(struct si_context
*sctx
)
5284 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5285 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5286 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5287 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5288 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5289 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5290 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5291 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5292 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5293 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5294 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5296 sctx
->b
.create_blend_state
= si_create_blend_state
;
5297 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5298 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5299 sctx
->b
.set_blend_color
= si_set_blend_color
;
5301 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5302 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5303 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5305 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5306 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5307 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5309 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5310 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5311 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5312 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5313 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5315 sctx
->b
.set_clip_state
= si_set_clip_state
;
5316 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5318 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5320 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5322 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5323 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5324 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5325 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5327 sctx
->b
.texture_barrier
= si_texture_barrier
;
5328 sctx
->b
.set_min_samples
= si_set_min_samples
;
5329 sctx
->b
.set_tess_state
= si_set_tess_state
;
5331 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5333 si_init_config(sctx
);
5336 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5338 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5340 if (sscreen
->info
.chip_class
>= GFX10
) {
5341 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5343 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5347 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
5348 struct si_pm4_state
*pm4
, unsigned value
)
5350 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
:
5351 R_00802C_GRBM_GFX_INDEX
;
5352 si_pm4_set_reg(pm4
, reg
, value
);
5355 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
5356 struct si_pm4_state
*pm4
, unsigned se
)
5358 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5359 si_set_grbm_gfx_index(sctx
, pm4
,
5360 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5361 S_030800_SE_INDEX(se
)) |
5362 S_030800_SH_BROADCAST_WRITES(1) |
5363 S_030800_INSTANCE_BROADCAST_WRITES(1));
5367 si_write_harvested_raster_configs(struct si_context
*sctx
,
5368 struct si_pm4_state
*pm4
,
5369 unsigned raster_config
,
5370 unsigned raster_config_1
)
5372 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5373 unsigned raster_config_se
[4];
5376 ac_get_harvested_configs(&sctx
->screen
->info
,
5381 for (se
= 0; se
< num_se
; se
++) {
5382 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5383 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5385 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5387 if (sctx
->chip_class
>= GFX7
) {
5388 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5392 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5394 struct si_screen
*sscreen
= sctx
->screen
;
5395 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5396 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5397 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5398 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5400 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5401 /* Always use the default config when all backends are enabled
5402 * (or when we failed to determine the enabled backends).
5404 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
5406 if (sctx
->chip_class
>= GFX7
)
5407 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
5410 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5414 static void si_init_config(struct si_context
*sctx
)
5416 struct si_screen
*sscreen
= sctx
->screen
;
5417 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5418 bool has_clear_state
= sscreen
->has_clear_state
;
5419 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5424 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5425 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5426 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5427 si_pm4_cmd_end(pm4
, false);
5429 if (has_clear_state
) {
5430 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5431 si_pm4_cmd_add(pm4
, 0);
5432 si_pm4_cmd_end(pm4
, false);
5435 if (sctx
->chip_class
<= GFX8
)
5436 si_set_raster_config(sctx
, pm4
);
5438 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5439 if (!has_clear_state
)
5440 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5442 /* FIXME calculate these values somehow ??? */
5443 if (sctx
->chip_class
<= GFX8
) {
5444 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5445 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5448 if (!has_clear_state
) {
5449 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5450 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5451 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5454 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5455 if (!has_clear_state
)
5456 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5457 if (sctx
->chip_class
< GFX7
)
5458 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
5459 S_008A14_CLIP_VTX_REORDER_ENA(1));
5461 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5462 * I don't know why. Deduced by trial and error.
5464 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5465 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5466 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5467 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5468 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5469 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5470 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5471 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5472 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5475 if (!has_clear_state
) {
5476 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5477 S_028230_ER_TRI(0xA) |
5478 S_028230_ER_POINT(0xA) |
5479 S_028230_ER_RECT(0xA) |
5480 /* Required by DX10_DIAMOND_TEST_ENA: */
5481 S_028230_ER_LINE_LR(0x1A) |
5482 S_028230_ER_LINE_RL(0x26) |
5483 S_028230_ER_LINE_TB(0xA) |
5484 S_028230_ER_LINE_BT(0xA));
5485 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5486 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5487 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5488 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5489 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5492 if (sctx
->chip_class
>= GFX10
) {
5493 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5494 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5495 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5496 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5497 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5498 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5499 } else if (sctx
->chip_class
== GFX9
) {
5500 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5501 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5502 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5504 /* These registers, when written, also overwrite the CLEAR_STATE
5505 * context, so we can't rely on CLEAR_STATE setting them.
5506 * It would be an issue if there was another UMD changing them.
5508 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5509 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5510 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5513 if (sctx
->chip_class
>= GFX7
) {
5514 if (sctx
->chip_class
>= GFX10
) {
5515 /* Logical CUs 16 - 31 */
5516 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
5517 S_00B404_CU_EN(0xffff));
5518 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
5519 S_00B104_CU_EN(0xffff));
5520 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
5521 S_00B004_CU_EN(0xffff));
5524 if (sctx
->chip_class
>= GFX9
) {
5525 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5526 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5528 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5529 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5530 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5531 S_00B41C_WAVE_LIMIT(0x3F));
5532 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5533 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5535 /* If this is 0, Bonaire can hang even if GS isn't being used.
5536 * Other chips are unaffected. These are suboptimal values,
5537 * but we don't use on-chip GS.
5539 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5540 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5541 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5544 /* Compute LATE_ALLOC_VS.LIMIT. */
5545 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5546 unsigned late_alloc_limit
; /* The limit is per SH. */
5548 if (sctx
->family
== CHIP_KABINI
) {
5549 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5550 } else if (num_cu_per_sh
<= 4) {
5551 /* Too few available compute units per SH. Disallowing
5552 * VS to run on one CU could hurt us more than late VS
5553 * allocation would help.
5555 * 2 is the highest safe number that allows us to keep
5558 late_alloc_limit
= 2;
5560 /* This is a good initial value, allowing 1 late_alloc
5561 * wave per SIMD on num_cu - 2.
5563 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5566 unsigned cu_mask_vs
= 0xffff;
5567 unsigned cu_mask_gs
= 0xffff;
5569 if (late_alloc_limit
> 2) {
5570 if (sctx
->chip_class
>= GFX10
) {
5571 /* CU2 & CU3 disabled because of the dual CU design */
5572 cu_mask_vs
= 0xfff3;
5573 cu_mask_gs
= 0xfff3; /* NGG only */
5575 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5579 /* VS can't execute on one CU if the limit is > 2. */
5580 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5581 S_00B118_CU_EN(cu_mask_vs
) |
5582 S_00B118_WAVE_LIMIT(0x3F));
5583 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5584 S_00B11C_LIMIT(late_alloc_limit
));
5586 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5587 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5589 if (sctx
->chip_class
>= GFX10
) {
5590 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
5591 S_00B204_CU_EN(0xffff) |
5592 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit
));
5595 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5596 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5599 if (sctx
->chip_class
>= GFX10
) {
5600 /* Break up a pixel wave if it contains deallocs for more than
5601 * half the parameter cache.
5603 * To avoid a deadlock where pixel waves aren't launched
5604 * because they're waiting for more pixels while the frontend
5605 * is stuck waiting for PC space, the maximum allowed value is
5606 * the size of the PC minus the largest possible allocation for
5607 * a single primitive shader subgroup.
5609 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
,
5610 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5611 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5612 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5613 sscreen
->info
.pa_sc_tile_steering_override
);
5615 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5616 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5617 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5618 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5619 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5620 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5621 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5622 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD
));
5624 si_pm4_set_reg(pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5625 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5626 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5627 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5628 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5629 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5630 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5631 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5632 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5633 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5635 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5636 S_00B0C0_SOFT_GROUPING_EN(1) |
5637 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5638 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5642 if (sctx
->chip_class
>= GFX8
) {
5643 unsigned vgt_tess_distribution
;
5645 vgt_tess_distribution
=
5646 S_028B50_ACCUM_ISOLINE(32) |
5647 S_028B50_ACCUM_TRI(11) |
5648 S_028B50_ACCUM_QUAD(11) |
5649 S_028B50_DONUT_SPLIT(16);
5651 /* Testing with Unigine Heaven extreme tesselation yielded best results
5652 * with TRAP_SPLIT = 3.
5654 if (sctx
->family
== CHIP_FIJI
||
5655 sctx
->family
>= CHIP_POLARIS10
)
5656 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5658 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5659 } else if (!has_clear_state
) {
5660 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5661 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5664 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5665 if (sctx
->chip_class
>= GFX7
) {
5666 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5667 S_028084_ADDRESS(border_color_va
>> 40));
5669 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5670 RADEON_PRIO_BORDER_COLORS
);
5672 if (sctx
->chip_class
>= GFX9
) {
5673 unsigned num_se
= sscreen
->info
.max_se
;
5674 unsigned pc_lines
= 0;
5675 unsigned max_alloc_count
= 0;
5677 switch (sctx
->family
) {
5696 if (sctx
->chip_class
>= GFX10
) {
5697 max_alloc_count
= pc_lines
/ 3;
5699 max_alloc_count
= MIN2(128, pc_lines
/ (4 * num_se
));
5702 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5703 S_028C48_MAX_ALLOC_COUNT(max_alloc_count
) |
5704 S_028C48_MAX_PRIM_PER_BATCH(1023));
5705 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5706 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5707 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5710 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5711 sctx
->init_config
= pm4
;