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radeonsi: make sure that DSA state != NULL and remove all NULL checking
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit &
86 blend->cb_target_mask;
87 unsigned i;
88
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
92 *
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
94 */
95 if (blend->dual_src_blend &&
96 sctx->ps_shader.cso &&
97 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
98 cb_target_mask = 0;
99
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
102 */
103 if (sctx->screen->dpbb_allowed &&
104 sctx->last_cb_target_mask != cb_target_mask) {
105 sctx->last_cb_target_mask = cb_target_mask;
106
107 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
108 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
109 }
110
111 unsigned initial_cdw = cs->current.cdw;
112 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
113 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
114
115 if (sctx->chip_class >= GFX8) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
119 */
120 bool oc_disable = blend->dcc_msaa_corruption_4bit & cb_target_mask &&
121 sctx->framebuffer.nr_samples >= 2;
122 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
123
124 radeon_opt_set_context_reg(
125 sctx, R_028424_CB_DCC_CONTROL,
126 SI_TRACKED_CB_DCC_CONTROL,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
131 }
132
133 /* RB+ register settings. */
134 if (sctx->screen->rbplus_allowed) {
135 unsigned spi_shader_col_format =
136 sctx->ps_shader.cso ?
137 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
138 unsigned sx_ps_downconvert = 0;
139 unsigned sx_blend_opt_epsilon = 0;
140 unsigned sx_blend_opt_control = 0;
141
142 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
143 struct si_surface *surf =
144 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
145 unsigned format, swap, spi_format, colormask;
146 bool has_alpha, has_rgb;
147
148 if (!surf) {
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
152 * enable RB+.
153 */
154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
155 continue;
156 }
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 break;
253
254 case V_028C70_COLOR_2_10_10_10:
255 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
256 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
257 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
258 }
259 break;
260 }
261 }
262
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
265 */
266 if (!sx_ps_downconvert)
267 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
268
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
271 SI_TRACKED_SX_PS_DOWNCONVERT,
272 sx_ps_downconvert, sx_blend_opt_epsilon,
273 sx_blend_opt_control);
274 }
275 if (initial_cdw != cs->current.cdw)
276 sctx->context_roll = true;
277 }
278
279 /*
280 * Blender functions
281 */
282
283 static uint32_t si_translate_blend_function(int blend_func)
284 {
285 switch (blend_func) {
286 case PIPE_BLEND_ADD:
287 return V_028780_COMB_DST_PLUS_SRC;
288 case PIPE_BLEND_SUBTRACT:
289 return V_028780_COMB_SRC_MINUS_DST;
290 case PIPE_BLEND_REVERSE_SUBTRACT:
291 return V_028780_COMB_DST_MINUS_SRC;
292 case PIPE_BLEND_MIN:
293 return V_028780_COMB_MIN_DST_SRC;
294 case PIPE_BLEND_MAX:
295 return V_028780_COMB_MAX_DST_SRC;
296 default:
297 PRINT_ERR("Unknown blend function %d\n", blend_func);
298 assert(0);
299 break;
300 }
301 return 0;
302 }
303
304 static uint32_t si_translate_blend_factor(int blend_fact)
305 {
306 switch (blend_fact) {
307 case PIPE_BLENDFACTOR_ONE:
308 return V_028780_BLEND_ONE;
309 case PIPE_BLENDFACTOR_SRC_COLOR:
310 return V_028780_BLEND_SRC_COLOR;
311 case PIPE_BLENDFACTOR_SRC_ALPHA:
312 return V_028780_BLEND_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_DST_ALPHA:
314 return V_028780_BLEND_DST_ALPHA;
315 case PIPE_BLENDFACTOR_DST_COLOR:
316 return V_028780_BLEND_DST_COLOR;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE;
319 case PIPE_BLENDFACTOR_CONST_COLOR:
320 return V_028780_BLEND_CONSTANT_COLOR;
321 case PIPE_BLENDFACTOR_CONST_ALPHA:
322 return V_028780_BLEND_CONSTANT_ALPHA;
323 case PIPE_BLENDFACTOR_ZERO:
324 return V_028780_BLEND_ZERO;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
337 case PIPE_BLENDFACTOR_SRC1_COLOR:
338 return V_028780_BLEND_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA:
340 return V_028780_BLEND_SRC1_ALPHA;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
342 return V_028780_BLEND_INV_SRC1_COLOR;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
344 return V_028780_BLEND_INV_SRC1_ALPHA;
345 default:
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
347 assert(0);
348 break;
349 }
350 return 0;
351 }
352
353 static uint32_t si_translate_blend_opt_function(int blend_func)
354 {
355 switch (blend_func) {
356 case PIPE_BLEND_ADD:
357 return V_028760_OPT_COMB_ADD;
358 case PIPE_BLEND_SUBTRACT:
359 return V_028760_OPT_COMB_SUBTRACT;
360 case PIPE_BLEND_REVERSE_SUBTRACT:
361 return V_028760_OPT_COMB_REVSUBTRACT;
362 case PIPE_BLEND_MIN:
363 return V_028760_OPT_COMB_MIN;
364 case PIPE_BLEND_MAX:
365 return V_028760_OPT_COMB_MAX;
366 default:
367 return V_028760_OPT_COMB_BLEND_DISABLED;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
372 {
373 switch (blend_fact) {
374 case PIPE_BLENDFACTOR_ZERO:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
376 case PIPE_BLENDFACTOR_ONE:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
378 case PIPE_BLENDFACTOR_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
382 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
384 case PIPE_BLENDFACTOR_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
389 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
391 default:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
393 }
394 }
395
396 static void si_blend_check_commutativity(struct si_screen *sscreen,
397 struct si_state_blend *blend,
398 enum pipe_blend_func func,
399 enum pipe_blendfactor src,
400 enum pipe_blendfactor dst,
401 unsigned chanmask)
402 {
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed =
405 (1u << PIPE_BLENDFACTOR_ONE) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_ZERO) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
420
421 if (dst == PIPE_BLENDFACTOR_ONE &&
422 (src_allowed & (1u << src))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
425 * rounding.
426 *
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
430 * setting.
431 */
432 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
433 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
434 blend->commutative_4bit |= chanmask;
435 }
436 }
437
438 /**
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
441 */
442 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
443 unsigned *dst_factor, unsigned expected_dst,
444 unsigned replacement_src)
445 {
446 if (*src_factor == expected_dst &&
447 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
448 *src_factor = PIPE_BLENDFACTOR_ZERO;
449 *dst_factor = replacement_src;
450
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func == PIPE_BLEND_SUBTRACT)
453 *func = PIPE_BLEND_REVERSE_SUBTRACT;
454 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
455 *func = PIPE_BLEND_SUBTRACT;
456 }
457 }
458
459 static bool si_blend_factor_uses_dst(unsigned factor)
460 {
461 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
462 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
464 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
465 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
466 }
467
468 static void *si_create_blend_state_mode(struct pipe_context *ctx,
469 const struct pipe_blend_state *state,
470 unsigned mode)
471 {
472 struct si_context *sctx = (struct si_context*)ctx;
473 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
474 struct si_pm4_state *pm4 = &blend->pm4;
475 uint32_t sx_mrt_blend_opt[8] = {0};
476 uint32_t color_control = 0;
477 bool logicop_enable = state->logicop_enable &&
478 state->logicop_func != PIPE_LOGICOP_COPY;
479
480 if (!blend)
481 return NULL;
482
483 blend->alpha_to_coverage = state->alpha_to_coverage;
484 blend->alpha_to_one = state->alpha_to_one;
485 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
486 blend->logicop_enable = logicop_enable;
487
488 if (logicop_enable) {
489 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
490 } else {
491 color_control |= S_028808_ROP3(0xcc);
492 }
493
494 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
501
502 if (state->alpha_to_coverage)
503 blend->need_src_alpha_4bit |= 0xf;
504
505 blend->cb_target_mask = 0;
506 blend->cb_target_enabled_4bit = 0;
507
508 for (int i = 0; i < 8; i++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j = state->independent_blend_enable ? i : 0;
511
512 unsigned eqRGB = state->rt[j].rgb_func;
513 unsigned srcRGB = state->rt[j].rgb_src_factor;
514 unsigned dstRGB = state->rt[j].rgb_dst_factor;
515 unsigned eqA = state->rt[j].alpha_func;
516 unsigned srcA = state->rt[j].alpha_src_factor;
517 unsigned dstA = state->rt[j].alpha_dst_factor;
518
519 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
520 unsigned blend_cntl = 0;
521
522 sx_mrt_blend_opt[i] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
525
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i >= 1 && blend->dual_src_blend) {
528 /* Vulkan does this for dual source blending. */
529 if (i == 1)
530 blend_cntl |= S_028780_ENABLE(1);
531
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
538 */
539 if (blend->dual_src_blend &&
540 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
541 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544 continue;
545 }
546
547 /* cb_render_state will disable unused ones */
548 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
549 if (state->rt[j].colormask)
550 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
551
552 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
553 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
554 continue;
555 }
556
557 si_blend_check_commutativity(sctx->screen, blend,
558 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
559 si_blend_check_commutativity(sctx->screen, blend,
560 eqA, srcA, dstA, 0x8 << (4 * i));
561
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
564 *
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
567 */
568 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
569 PIPE_BLENDFACTOR_DST_COLOR,
570 PIPE_BLENDFACTOR_SRC_COLOR);
571 si_blend_remove_dst(&eqA, &srcA, &dstA,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_ALPHA,
576 PIPE_BLENDFACTOR_SRC_ALPHA);
577
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
580 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
581 srcA_opt = si_translate_blend_opt_factor(srcA, true);
582 dstA_opt = si_translate_blend_opt_factor(dstA, true);
583
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB))
586 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
587 if (si_blend_factor_uses_dst(srcA))
588 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
589
590 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
591 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
592 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
594 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
595
596 /* Set the final value. */
597 sx_mrt_blend_opt[i] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt) |
602 S_028760_ALPHA_DST_OPT(dstA_opt) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
604
605 /* Set blend state. */
606 blend_cntl |= S_028780_ENABLE(1);
607 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
608 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
609 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
610
611 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
612 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
614 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
615 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
616 }
617 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
618
619 blend->blend_enable_4bit |= 0xfu << (i * 4);
620
621 if (sctx->family <= CHIP_NAVI14)
622 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (sctx->family <= CHIP_NAVI14 && logicop_enable)
635 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
636
637 if (blend->cb_target_mask) {
638 color_control |= S_028808_MODE(mode);
639 } else {
640 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
641 }
642
643 if (sctx->screen->rbplus_allowed) {
644 /* Disable RB+ blend optimizations for dual source blending.
645 * Vulkan does this.
646 */
647 if (blend->dual_src_blend) {
648 for (int i = 0; i < 8; i++) {
649 sx_mrt_blend_opt[i] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
652 }
653 }
654
655 for (int i = 0; i < 8; i++)
656 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
657 sx_mrt_blend_opt[i]);
658
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend->dual_src_blend || logicop_enable ||
661 mode == V_028808_CB_RESOLVE)
662 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
663 }
664
665 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
666 return blend;
667 }
668
669 static void *si_create_blend_state(struct pipe_context *ctx,
670 const struct pipe_blend_state *state)
671 {
672 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
673 }
674
675 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
676 {
677 struct si_context *sctx = (struct si_context *)ctx;
678 struct si_state_blend *old_blend = sctx->queued.named.blend;
679 struct si_state_blend *blend = (struct si_state_blend *)state;
680
681 if (!blend)
682 blend = (struct si_state_blend *)sctx->noop_blend;
683
684 si_pm4_bind_state(sctx, blend, blend);
685
686 if (old_blend->cb_target_mask != blend->cb_target_mask ||
687 old_blend->dual_src_blend != blend->dual_src_blend ||
688 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
689 sctx->framebuffer.nr_samples >= 2 &&
690 sctx->screen->dcc_msaa_allowed))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
692
693 if (old_blend->cb_target_mask != blend->cb_target_mask ||
694 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
695 old_blend->alpha_to_one != blend->alpha_to_one ||
696 old_blend->dual_src_blend != blend->dual_src_blend ||
697 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
698 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
699 sctx->do_update_shaders = true;
700
701 if (sctx->screen->dpbb_allowed &&
702 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
709 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
710 old_blend->commutative_4bit != blend->commutative_4bit ||
711 old_blend->logicop_enable != blend->logicop_enable)))
712 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
713 }
714
715 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
719 }
720
721 static void si_set_blend_color(struct pipe_context *ctx,
722 const struct pipe_blend_color *state)
723 {
724 struct si_context *sctx = (struct si_context *)ctx;
725 static const struct pipe_blend_color zeros;
726
727 sctx->blend_color.state = *state;
728 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
729 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
730 }
731
732 static void si_emit_blend_color(struct si_context *sctx)
733 {
734 struct radeon_cmdbuf *cs = sctx->gfx_cs;
735
736 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
737 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
738 }
739
740 /*
741 * Clipping
742 */
743
744 static void si_set_clip_state(struct pipe_context *ctx,
745 const struct pipe_clip_state *state)
746 {
747 struct si_context *sctx = (struct si_context *)ctx;
748 struct pipe_constant_buffer cb;
749 static const struct pipe_clip_state zeros;
750
751 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
752 return;
753
754 sctx->clip_state.state = *state;
755 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
756 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
757
758 cb.buffer = NULL;
759 cb.user_buffer = state->ucp;
760 cb.buffer_offset = 0;
761 cb.buffer_size = 4*4*8;
762 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
763 pipe_resource_reference(&cb.buffer, NULL);
764 }
765
766 static void si_emit_clip_state(struct si_context *sctx)
767 {
768 struct radeon_cmdbuf *cs = sctx->gfx_cs;
769
770 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
771 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
772 }
773
774 static void si_emit_clip_regs(struct si_context *sctx)
775 {
776 struct si_shader *vs = si_get_vs_state(sctx);
777 struct si_shader_selector *vs_sel = vs->selector;
778 struct tgsi_shader_info *info = &vs_sel->info;
779 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
780 unsigned window_space =
781 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
782 unsigned clipdist_mask = vs_sel->clipdist_mask;
783 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
784 unsigned culldist_mask = vs_sel->culldist_mask;
785 unsigned total_mask;
786
787 if (vs->key.opt.clip_disable) {
788 assert(!info->culldist_writemask);
789 clipdist_mask = 0;
790 culldist_mask = 0;
791 }
792 total_mask = clipdist_mask | culldist_mask;
793
794 /* Clip distances on points have no effect, so need to be implemented
795 * as cull distances. This applies for the clipvertex case as well.
796 *
797 * Setting this for primitives other than points should have no adverse
798 * effects.
799 */
800 clipdist_mask &= rs->clip_plane_enable;
801 culldist_mask |= clipdist_mask;
802
803 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
804 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
805 SI_TRACKED_PA_CL_VS_OUT_CNTL,
806 vs_sel->pa_cl_vs_out_cntl |
807 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
808 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
809 clipdist_mask | (culldist_mask << 8));
810 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
811 SI_TRACKED_PA_CL_CLIP_CNTL,
812 rs->pa_cl_clip_cntl |
813 ucp_mask |
814 S_028810_CLIP_DISABLE(window_space));
815
816 if (initial_cdw != sctx->gfx_cs->current.cdw)
817 sctx->context_roll = true;
818 }
819
820 /*
821 * inferred state between framebuffer and rasterizer
822 */
823 static void si_update_poly_offset_state(struct si_context *sctx)
824 {
825 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
826
827 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
828 si_pm4_bind_state(sctx, poly_offset, NULL);
829 return;
830 }
831
832 /* Use the user format, not db_render_format, so that the polygon
833 * offset behaves as expected by applications.
834 */
835 switch (sctx->framebuffer.state.zsbuf->texture->format) {
836 case PIPE_FORMAT_Z16_UNORM:
837 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
838 break;
839 default: /* 24-bit */
840 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
841 break;
842 case PIPE_FORMAT_Z32_FLOAT:
843 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
844 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
845 break;
846 }
847 }
848
849 /*
850 * Rasterizer
851 */
852
853 static uint32_t si_translate_fill(uint32_t func)
854 {
855 switch(func) {
856 case PIPE_POLYGON_MODE_FILL:
857 return V_028814_X_DRAW_TRIANGLES;
858 case PIPE_POLYGON_MODE_LINE:
859 return V_028814_X_DRAW_LINES;
860 case PIPE_POLYGON_MODE_POINT:
861 return V_028814_X_DRAW_POINTS;
862 default:
863 assert(0);
864 return V_028814_X_DRAW_POINTS;
865 }
866 }
867
868 static void *si_create_rs_state(struct pipe_context *ctx,
869 const struct pipe_rasterizer_state *state)
870 {
871 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
872 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
873 struct si_pm4_state *pm4 = &rs->pm4;
874 unsigned tmp, i;
875 float psize_min, psize_max;
876
877 if (!rs) {
878 return NULL;
879 }
880
881 if (!state->front_ccw) {
882 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
883 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
884 } else {
885 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
886 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
887 }
888 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
889 rs->provoking_vertex_first = state->flatshade_first;
890 rs->scissor_enable = state->scissor;
891 rs->clip_halfz = state->clip_halfz;
892 rs->two_side = state->light_twoside;
893 rs->multisample_enable = state->multisample;
894 rs->force_persample_interp = state->force_persample_interp;
895 rs->clip_plane_enable = state->clip_plane_enable;
896 rs->half_pixel_center = state->half_pixel_center;
897 rs->line_stipple_enable = state->line_stipple_enable;
898 rs->poly_stipple_enable = state->poly_stipple_enable;
899 rs->line_smooth = state->line_smooth;
900 rs->line_width = state->line_width;
901 rs->poly_smooth = state->poly_smooth;
902 rs->uses_poly_offset = state->offset_point || state->offset_line ||
903 state->offset_tri;
904 rs->clamp_fragment_color = state->clamp_fragment_color;
905 rs->clamp_vertex_color = state->clamp_vertex_color;
906 rs->flatshade = state->flatshade;
907 rs->flatshade_first = state->flatshade_first;
908 rs->sprite_coord_enable = state->sprite_coord_enable;
909 rs->rasterizer_discard = state->rasterizer_discard;
910 rs->pa_sc_line_stipple = state->line_stipple_enable ?
911 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
912 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
913 rs->pa_cl_clip_cntl =
914 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
915 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
916 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
917 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
918 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
919
920 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
921 S_0286D4_FLAT_SHADE_ENA(1) |
922 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
923 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
924 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
925 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
926 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
927 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
928
929 /* point size 12.4 fixed point */
930 tmp = (unsigned)(state->point_size * 8.0);
931 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
932
933 if (state->point_size_per_vertex) {
934 psize_min = util_get_min_point_size(state);
935 psize_max = SI_MAX_POINT_SIZE;
936 } else {
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min = state->point_size;
939 psize_max = state->point_size;
940 }
941 rs->max_point_size = psize_max;
942
943 /* Divide by two, because 0.5 = 1 pixel. */
944 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
945 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
946 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
947
948 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
949 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
950 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
951 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
952 S_028A48_MSAA_ENABLE(state->multisample ||
953 state->poly_smooth ||
954 state->line_smooth) |
955 S_028A48_VPORT_SCISSOR_ENABLE(1) |
956 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
957
958 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
959 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
960 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
961 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
962 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
963 S_028814_FACE(!state->front_ccw) |
964 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
965 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
966 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
967 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
968 state->fill_back != PIPE_POLYGON_MODE_FILL) |
969 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
970 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
971
972 if (!rs->uses_poly_offset)
973 return rs;
974
975 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
976 if (!rs->pm4_poly_offset) {
977 FREE(rs);
978 return NULL;
979 }
980
981 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
982 for (i = 0; i < 3; i++) {
983 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
984 float offset_units = state->offset_units;
985 float offset_scale = state->offset_scale * 16.0f;
986 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
987
988 if (!state->offset_units_unscaled) {
989 switch (i) {
990 case 0: /* 16-bit zbuffer */
991 offset_units *= 4.0f;
992 pa_su_poly_offset_db_fmt_cntl =
993 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
994 break;
995 case 1: /* 24-bit zbuffer */
996 offset_units *= 2.0f;
997 pa_su_poly_offset_db_fmt_cntl =
998 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
999 break;
1000 case 2: /* 32-bit zbuffer */
1001 offset_units *= 1.0f;
1002 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1003 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1004 break;
1005 }
1006 }
1007
1008 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1009 fui(offset_scale));
1010 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1011 fui(offset_units));
1012 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1013 fui(offset_scale));
1014 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1015 fui(offset_units));
1016 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1017 pa_su_poly_offset_db_fmt_cntl);
1018 }
1019
1020 return rs;
1021 }
1022
1023 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1024 {
1025 struct si_context *sctx = (struct si_context *)ctx;
1026 struct si_state_rasterizer *old_rs =
1027 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1028 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1029
1030 if (!state)
1031 return;
1032
1033 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1034 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1035
1036 /* Update the small primitive filter workaround if necessary. */
1037 if (sctx->screen->has_msaa_sample_loc_bug &&
1038 sctx->framebuffer.nr_samples > 1)
1039 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1040 }
1041
1042 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1043 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1044
1045 si_pm4_bind_state(sctx, rasterizer, rs);
1046 si_update_poly_offset_state(sctx);
1047
1048 if (!old_rs ||
1049 old_rs->scissor_enable != rs->scissor_enable)
1050 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1051
1052 if (!old_rs ||
1053 old_rs->line_width != rs->line_width ||
1054 old_rs->max_point_size != rs->max_point_size ||
1055 old_rs->half_pixel_center != rs->half_pixel_center)
1056 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1057
1058 if (!old_rs ||
1059 old_rs->clip_halfz != rs->clip_halfz)
1060 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1061
1062 if (!old_rs ||
1063 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1064 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1065 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1066
1067 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1068 rs->line_stipple_enable;
1069
1070 if (!old_rs ||
1071 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1072 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1073 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1074 old_rs->flatshade != rs->flatshade ||
1075 old_rs->two_side != rs->two_side ||
1076 old_rs->multisample_enable != rs->multisample_enable ||
1077 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1078 old_rs->poly_smooth != rs->poly_smooth ||
1079 old_rs->line_smooth != rs->line_smooth ||
1080 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1081 old_rs->force_persample_interp != rs->force_persample_interp)
1082 sctx->do_update_shaders = true;
1083 }
1084
1085 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1086 {
1087 struct si_context *sctx = (struct si_context *)ctx;
1088 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1089
1090 if (sctx->queued.named.rasterizer == state)
1091 si_pm4_bind_state(sctx, poly_offset, NULL);
1092
1093 FREE(rs->pm4_poly_offset);
1094 si_pm4_delete_state(sctx, rasterizer, rs);
1095 }
1096
1097 /*
1098 * infeered state between dsa and stencil ref
1099 */
1100 static void si_emit_stencil_ref(struct si_context *sctx)
1101 {
1102 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1103 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1104 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1105
1106 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1107 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1108 S_028430_STENCILMASK(dsa->valuemask[0]) |
1109 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1110 S_028430_STENCILOPVAL(1));
1111 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1112 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1113 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1114 S_028434_STENCILOPVAL_BF(1));
1115 }
1116
1117 static void si_set_stencil_ref(struct pipe_context *ctx,
1118 const struct pipe_stencil_ref *state)
1119 {
1120 struct si_context *sctx = (struct si_context *)ctx;
1121
1122 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1123 return;
1124
1125 sctx->stencil_ref.state = *state;
1126 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1127 }
1128
1129
1130 /*
1131 * DSA
1132 */
1133
1134 static uint32_t si_translate_stencil_op(int s_op)
1135 {
1136 switch (s_op) {
1137 case PIPE_STENCIL_OP_KEEP:
1138 return V_02842C_STENCIL_KEEP;
1139 case PIPE_STENCIL_OP_ZERO:
1140 return V_02842C_STENCIL_ZERO;
1141 case PIPE_STENCIL_OP_REPLACE:
1142 return V_02842C_STENCIL_REPLACE_TEST;
1143 case PIPE_STENCIL_OP_INCR:
1144 return V_02842C_STENCIL_ADD_CLAMP;
1145 case PIPE_STENCIL_OP_DECR:
1146 return V_02842C_STENCIL_SUB_CLAMP;
1147 case PIPE_STENCIL_OP_INCR_WRAP:
1148 return V_02842C_STENCIL_ADD_WRAP;
1149 case PIPE_STENCIL_OP_DECR_WRAP:
1150 return V_02842C_STENCIL_SUB_WRAP;
1151 case PIPE_STENCIL_OP_INVERT:
1152 return V_02842C_STENCIL_INVERT;
1153 default:
1154 PRINT_ERR("Unknown stencil op %d", s_op);
1155 assert(0);
1156 break;
1157 }
1158 return 0;
1159 }
1160
1161 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1162 {
1163 return s->enabled && s->writemask &&
1164 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1165 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1166 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1167 }
1168
1169 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1170 {
1171 /* REPLACE is normally order invariant, except when the stencil
1172 * reference value is written by the fragment shader. Tracking this
1173 * interaction does not seem worth the effort, so be conservative. */
1174 return op != PIPE_STENCIL_OP_INCR &&
1175 op != PIPE_STENCIL_OP_DECR &&
1176 op != PIPE_STENCIL_OP_REPLACE;
1177 }
1178
1179 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1180 * invariant in the sense that the set of passing fragments as well as the
1181 * final stencil buffer result does not depend on the order of fragments. */
1182 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1183 {
1184 return !state->enabled || !state->writemask ||
1185 /* The following assumes that Z writes are disabled. */
1186 (state->func == PIPE_FUNC_ALWAYS &&
1187 si_order_invariant_stencil_op(state->zpass_op) &&
1188 si_order_invariant_stencil_op(state->zfail_op)) ||
1189 (state->func == PIPE_FUNC_NEVER &&
1190 si_order_invariant_stencil_op(state->fail_op));
1191 }
1192
1193 static void *si_create_dsa_state(struct pipe_context *ctx,
1194 const struct pipe_depth_stencil_alpha_state *state)
1195 {
1196 struct si_context *sctx = (struct si_context *)ctx;
1197 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1198 struct si_pm4_state *pm4 = &dsa->pm4;
1199 unsigned db_depth_control;
1200 uint32_t db_stencil_control = 0;
1201
1202 if (!dsa) {
1203 return NULL;
1204 }
1205
1206 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1207 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1208 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1209 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1210
1211 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1212 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1213 S_028800_ZFUNC(state->depth.func) |
1214 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1215
1216 /* stencil */
1217 if (state->stencil[0].enabled) {
1218 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1219 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1220 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1221 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1222 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1223
1224 if (state->stencil[1].enabled) {
1225 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1226 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1227 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1228 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1229 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1230 }
1231 }
1232
1233 /* alpha */
1234 if (state->alpha.enabled) {
1235 dsa->alpha_func = state->alpha.func;
1236
1237 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1238 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1239 } else {
1240 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1241 }
1242
1243 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1244 if (state->stencil[0].enabled)
1245 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1246 if (state->depth.bounds_test) {
1247 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1248 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1249 }
1250
1251 dsa->depth_enabled = state->depth.enabled;
1252 dsa->depth_write_enabled = state->depth.enabled &&
1253 state->depth.writemask;
1254 dsa->stencil_enabled = state->stencil[0].enabled;
1255 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1256 (si_dsa_writes_stencil(&state->stencil[0]) ||
1257 si_dsa_writes_stencil(&state->stencil[1]));
1258 dsa->db_can_write = dsa->depth_write_enabled ||
1259 dsa->stencil_write_enabled;
1260
1261 bool zfunc_is_ordered =
1262 state->depth.func == PIPE_FUNC_NEVER ||
1263 state->depth.func == PIPE_FUNC_LESS ||
1264 state->depth.func == PIPE_FUNC_LEQUAL ||
1265 state->depth.func == PIPE_FUNC_GREATER ||
1266 state->depth.func == PIPE_FUNC_GEQUAL;
1267
1268 bool nozwrite_and_order_invariant_stencil =
1269 !dsa->db_can_write ||
1270 (!dsa->depth_write_enabled &&
1271 si_order_invariant_stencil_state(&state->stencil[0]) &&
1272 si_order_invariant_stencil_state(&state->stencil[1]));
1273
1274 dsa->order_invariance[1].zs =
1275 nozwrite_and_order_invariant_stencil ||
1276 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1277 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1278
1279 dsa->order_invariance[1].pass_set =
1280 nozwrite_and_order_invariant_stencil ||
1281 (!dsa->stencil_write_enabled &&
1282 (state->depth.func == PIPE_FUNC_ALWAYS ||
1283 state->depth.func == PIPE_FUNC_NEVER));
1284 dsa->order_invariance[0].pass_set =
1285 !dsa->depth_write_enabled ||
1286 (state->depth.func == PIPE_FUNC_ALWAYS ||
1287 state->depth.func == PIPE_FUNC_NEVER);
1288
1289 dsa->order_invariance[1].pass_last =
1290 sctx->screen->assume_no_z_fights &&
1291 !dsa->stencil_write_enabled &&
1292 dsa->depth_write_enabled && zfunc_is_ordered;
1293 dsa->order_invariance[0].pass_last =
1294 sctx->screen->assume_no_z_fights &&
1295 dsa->depth_write_enabled && zfunc_is_ordered;
1296
1297 return dsa;
1298 }
1299
1300 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1301 {
1302 struct si_context *sctx = (struct si_context *)ctx;
1303 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1304 struct si_state_dsa *dsa = state;
1305
1306 if (!dsa)
1307 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1308
1309 si_pm4_bind_state(sctx, dsa, dsa);
1310
1311 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1312 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1313 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1314 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1315 }
1316
1317 if (old_dsa->alpha_func != dsa->alpha_func)
1318 sctx->do_update_shaders = true;
1319
1320 if (sctx->screen->dpbb_allowed &&
1321 ((old_dsa->depth_enabled != dsa->depth_enabled ||
1322 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1323 old_dsa->db_can_write != dsa->db_can_write)))
1324 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1325
1326 if (sctx->screen->has_out_of_order_rast &&
1327 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1328 sizeof(old_dsa->order_invariance))))
1329 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1330 }
1331
1332 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1333 {
1334 struct si_context *sctx = (struct si_context *)ctx;
1335 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1336 }
1337
1338 static void *si_create_db_flush_dsa(struct si_context *sctx)
1339 {
1340 struct pipe_depth_stencil_alpha_state dsa = {};
1341
1342 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1343 }
1344
1345 /* DB RENDER STATE */
1346
1347 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1348 {
1349 struct si_context *sctx = (struct si_context*)ctx;
1350
1351 /* Pipeline stat & streamout queries. */
1352 if (enable) {
1353 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1354 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1355 } else {
1356 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1357 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1358 }
1359
1360 /* Occlusion queries. */
1361 if (sctx->occlusion_queries_disabled != !enable) {
1362 sctx->occlusion_queries_disabled = !enable;
1363 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1364 }
1365 }
1366
1367 void si_set_occlusion_query_state(struct si_context *sctx,
1368 bool old_perfect_enable)
1369 {
1370 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1371
1372 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1373
1374 if (perfect_enable != old_perfect_enable)
1375 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1376 }
1377
1378 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1379 {
1380 st->saved_compute = sctx->cs_shader_state.program;
1381
1382 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1383 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1384
1385 st->saved_ssbo_writable_mask = 0;
1386
1387 for (unsigned i = 0; i < 3; i++) {
1388 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1389 (1u << si_get_shaderbuf_slot(i)))
1390 st->saved_ssbo_writable_mask |= 1 << i;
1391 }
1392 }
1393
1394 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1395 {
1396 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1397
1398 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1399 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1400
1401 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1402 st->saved_ssbo_writable_mask);
1403 for (unsigned i = 0; i < 3; ++i)
1404 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1405 }
1406
1407 static void si_emit_db_render_state(struct si_context *sctx)
1408 {
1409 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1410 unsigned db_shader_control, db_render_control, db_count_control;
1411 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1412
1413 /* DB_RENDER_CONTROL */
1414 if (sctx->dbcb_depth_copy_enabled ||
1415 sctx->dbcb_stencil_copy_enabled) {
1416 db_render_control =
1417 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1418 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1419 S_028000_COPY_CENTROID(1) |
1420 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1421 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1422 db_render_control =
1423 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1424 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1425 } else {
1426 db_render_control =
1427 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1428 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1429 }
1430
1431 /* DB_COUNT_CONTROL (occlusion queries) */
1432 if (sctx->num_occlusion_queries > 0 &&
1433 !sctx->occlusion_queries_disabled) {
1434 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1435 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1436
1437 if (sctx->chip_class >= GFX7) {
1438 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1439
1440 /* Stoney doesn't increment occlusion query counters
1441 * if the sample rate is 16x. Use 8x sample rate instead.
1442 */
1443 if (sctx->family == CHIP_STONEY)
1444 log_sample_rate = MIN2(log_sample_rate, 3);
1445
1446 db_count_control =
1447 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1448 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1449 S_028004_SAMPLE_RATE(log_sample_rate) |
1450 S_028004_ZPASS_ENABLE(1) |
1451 S_028004_SLICE_EVEN_ENABLE(1) |
1452 S_028004_SLICE_ODD_ENABLE(1);
1453 } else {
1454 db_count_control =
1455 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1456 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1457 }
1458 } else {
1459 /* Disable occlusion queries. */
1460 if (sctx->chip_class >= GFX7) {
1461 db_count_control = 0;
1462 } else {
1463 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1464 }
1465 }
1466
1467 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1468 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1469 db_count_control);
1470
1471 /* DB_RENDER_OVERRIDE2 */
1472 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1473 SI_TRACKED_DB_RENDER_OVERRIDE2,
1474 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1475 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1476 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1477
1478 db_shader_control = sctx->ps_db_shader_control;
1479
1480 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1481 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1482 db_shader_control &= C_02880C_Z_ORDER;
1483 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1484 }
1485
1486 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1487 if (!rs->multisample_enable)
1488 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1489
1490 if (sctx->screen->has_rbplus &&
1491 !sctx->screen->rbplus_allowed)
1492 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1493
1494 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1495 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1496
1497 if (initial_cdw != sctx->gfx_cs->current.cdw)
1498 sctx->context_roll = true;
1499 }
1500
1501 /*
1502 * format translation
1503 */
1504 static uint32_t si_translate_colorformat(enum pipe_format format)
1505 {
1506 const struct util_format_description *desc = util_format_description(format);
1507 if (!desc)
1508 return V_028C70_COLOR_INVALID;
1509
1510 #define HAS_SIZE(x,y,z,w) \
1511 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1512 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1513
1514 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1515 return V_028C70_COLOR_10_11_11;
1516
1517 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1518 return V_028C70_COLOR_INVALID;
1519
1520 /* hw cannot support mixed formats (except depth/stencil, since
1521 * stencil is not written to). */
1522 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1523 return V_028C70_COLOR_INVALID;
1524
1525 switch (desc->nr_channels) {
1526 case 1:
1527 switch (desc->channel[0].size) {
1528 case 8:
1529 return V_028C70_COLOR_8;
1530 case 16:
1531 return V_028C70_COLOR_16;
1532 case 32:
1533 return V_028C70_COLOR_32;
1534 }
1535 break;
1536 case 2:
1537 if (desc->channel[0].size == desc->channel[1].size) {
1538 switch (desc->channel[0].size) {
1539 case 8:
1540 return V_028C70_COLOR_8_8;
1541 case 16:
1542 return V_028C70_COLOR_16_16;
1543 case 32:
1544 return V_028C70_COLOR_32_32;
1545 }
1546 } else if (HAS_SIZE(8,24,0,0)) {
1547 return V_028C70_COLOR_24_8;
1548 } else if (HAS_SIZE(24,8,0,0)) {
1549 return V_028C70_COLOR_8_24;
1550 }
1551 break;
1552 case 3:
1553 if (HAS_SIZE(5,6,5,0)) {
1554 return V_028C70_COLOR_5_6_5;
1555 } else if (HAS_SIZE(32,8,24,0)) {
1556 return V_028C70_COLOR_X24_8_32_FLOAT;
1557 }
1558 break;
1559 case 4:
1560 if (desc->channel[0].size == desc->channel[1].size &&
1561 desc->channel[0].size == desc->channel[2].size &&
1562 desc->channel[0].size == desc->channel[3].size) {
1563 switch (desc->channel[0].size) {
1564 case 4:
1565 return V_028C70_COLOR_4_4_4_4;
1566 case 8:
1567 return V_028C70_COLOR_8_8_8_8;
1568 case 16:
1569 return V_028C70_COLOR_16_16_16_16;
1570 case 32:
1571 return V_028C70_COLOR_32_32_32_32;
1572 }
1573 } else if (HAS_SIZE(5,5,5,1)) {
1574 return V_028C70_COLOR_1_5_5_5;
1575 } else if (HAS_SIZE(1,5,5,5)) {
1576 return V_028C70_COLOR_5_5_5_1;
1577 } else if (HAS_SIZE(10,10,10,2)) {
1578 return V_028C70_COLOR_2_10_10_10;
1579 }
1580 break;
1581 }
1582 return V_028C70_COLOR_INVALID;
1583 }
1584
1585 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1586 {
1587 if (SI_BIG_ENDIAN) {
1588 switch(colorformat) {
1589 /* 8-bit buffers. */
1590 case V_028C70_COLOR_8:
1591 return V_028C70_ENDIAN_NONE;
1592
1593 /* 16-bit buffers. */
1594 case V_028C70_COLOR_5_6_5:
1595 case V_028C70_COLOR_1_5_5_5:
1596 case V_028C70_COLOR_4_4_4_4:
1597 case V_028C70_COLOR_16:
1598 case V_028C70_COLOR_8_8:
1599 return V_028C70_ENDIAN_8IN16;
1600
1601 /* 32-bit buffers. */
1602 case V_028C70_COLOR_8_8_8_8:
1603 case V_028C70_COLOR_2_10_10_10:
1604 case V_028C70_COLOR_8_24:
1605 case V_028C70_COLOR_24_8:
1606 case V_028C70_COLOR_16_16:
1607 return V_028C70_ENDIAN_8IN32;
1608
1609 /* 64-bit buffers. */
1610 case V_028C70_COLOR_16_16_16_16:
1611 return V_028C70_ENDIAN_8IN16;
1612
1613 case V_028C70_COLOR_32_32:
1614 return V_028C70_ENDIAN_8IN32;
1615
1616 /* 128-bit buffers. */
1617 case V_028C70_COLOR_32_32_32_32:
1618 return V_028C70_ENDIAN_8IN32;
1619 default:
1620 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1621 }
1622 } else {
1623 return V_028C70_ENDIAN_NONE;
1624 }
1625 }
1626
1627 static uint32_t si_translate_dbformat(enum pipe_format format)
1628 {
1629 switch (format) {
1630 case PIPE_FORMAT_Z16_UNORM:
1631 return V_028040_Z_16;
1632 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1633 case PIPE_FORMAT_X8Z24_UNORM:
1634 case PIPE_FORMAT_Z24X8_UNORM:
1635 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1636 return V_028040_Z_24; /* deprecated on AMD GCN */
1637 case PIPE_FORMAT_Z32_FLOAT:
1638 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1639 return V_028040_Z_32_FLOAT;
1640 default:
1641 return V_028040_Z_INVALID;
1642 }
1643 }
1644
1645 /*
1646 * Texture translation
1647 */
1648
1649 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1650 enum pipe_format format,
1651 const struct util_format_description *desc,
1652 int first_non_void)
1653 {
1654 struct si_screen *sscreen = (struct si_screen*)screen;
1655 bool uniform = true;
1656 int i;
1657
1658 assert(sscreen->info.chip_class <= GFX9);
1659
1660 /* Colorspace (return non-RGB formats directly). */
1661 switch (desc->colorspace) {
1662 /* Depth stencil formats */
1663 case UTIL_FORMAT_COLORSPACE_ZS:
1664 switch (format) {
1665 case PIPE_FORMAT_Z16_UNORM:
1666 return V_008F14_IMG_DATA_FORMAT_16;
1667 case PIPE_FORMAT_X24S8_UINT:
1668 case PIPE_FORMAT_S8X24_UINT:
1669 /*
1670 * Implemented as an 8_8_8_8 data format to fix texture
1671 * gathers in stencil sampling. This affects at least
1672 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1673 */
1674 if (sscreen->info.chip_class <= GFX8)
1675 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1676
1677 if (format == PIPE_FORMAT_X24S8_UINT)
1678 return V_008F14_IMG_DATA_FORMAT_8_24;
1679 else
1680 return V_008F14_IMG_DATA_FORMAT_24_8;
1681 case PIPE_FORMAT_Z24X8_UNORM:
1682 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1683 return V_008F14_IMG_DATA_FORMAT_8_24;
1684 case PIPE_FORMAT_X8Z24_UNORM:
1685 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1686 return V_008F14_IMG_DATA_FORMAT_24_8;
1687 case PIPE_FORMAT_S8_UINT:
1688 return V_008F14_IMG_DATA_FORMAT_8;
1689 case PIPE_FORMAT_Z32_FLOAT:
1690 return V_008F14_IMG_DATA_FORMAT_32;
1691 case PIPE_FORMAT_X32_S8X24_UINT:
1692 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1693 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1694 default:
1695 goto out_unknown;
1696 }
1697
1698 case UTIL_FORMAT_COLORSPACE_YUV:
1699 goto out_unknown; /* TODO */
1700
1701 case UTIL_FORMAT_COLORSPACE_SRGB:
1702 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1703 goto out_unknown;
1704 break;
1705
1706 default:
1707 break;
1708 }
1709
1710 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1711 if (!sscreen->info.has_format_bc1_through_bc7)
1712 goto out_unknown;
1713
1714 switch (format) {
1715 case PIPE_FORMAT_RGTC1_SNORM:
1716 case PIPE_FORMAT_LATC1_SNORM:
1717 case PIPE_FORMAT_RGTC1_UNORM:
1718 case PIPE_FORMAT_LATC1_UNORM:
1719 return V_008F14_IMG_DATA_FORMAT_BC4;
1720 case PIPE_FORMAT_RGTC2_SNORM:
1721 case PIPE_FORMAT_LATC2_SNORM:
1722 case PIPE_FORMAT_RGTC2_UNORM:
1723 case PIPE_FORMAT_LATC2_UNORM:
1724 return V_008F14_IMG_DATA_FORMAT_BC5;
1725 default:
1726 goto out_unknown;
1727 }
1728 }
1729
1730 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1731 (sscreen->info.family == CHIP_STONEY ||
1732 sscreen->info.family == CHIP_VEGA10 ||
1733 sscreen->info.family == CHIP_RAVEN)) {
1734 switch (format) {
1735 case PIPE_FORMAT_ETC1_RGB8:
1736 case PIPE_FORMAT_ETC2_RGB8:
1737 case PIPE_FORMAT_ETC2_SRGB8:
1738 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1739 case PIPE_FORMAT_ETC2_RGB8A1:
1740 case PIPE_FORMAT_ETC2_SRGB8A1:
1741 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1742 case PIPE_FORMAT_ETC2_RGBA8:
1743 case PIPE_FORMAT_ETC2_SRGBA8:
1744 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1745 case PIPE_FORMAT_ETC2_R11_UNORM:
1746 case PIPE_FORMAT_ETC2_R11_SNORM:
1747 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1748 case PIPE_FORMAT_ETC2_RG11_UNORM:
1749 case PIPE_FORMAT_ETC2_RG11_SNORM:
1750 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1751 default:
1752 goto out_unknown;
1753 }
1754 }
1755
1756 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1757 if (!sscreen->info.has_format_bc1_through_bc7)
1758 goto out_unknown;
1759
1760 switch (format) {
1761 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1762 case PIPE_FORMAT_BPTC_SRGBA:
1763 return V_008F14_IMG_DATA_FORMAT_BC7;
1764 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1765 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1766 return V_008F14_IMG_DATA_FORMAT_BC6;
1767 default:
1768 goto out_unknown;
1769 }
1770 }
1771
1772 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1773 switch (format) {
1774 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1775 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1776 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1777 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1778 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1779 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1780 default:
1781 goto out_unknown;
1782 }
1783 }
1784
1785 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1786 if (!sscreen->info.has_format_bc1_through_bc7)
1787 goto out_unknown;
1788
1789 switch (format) {
1790 case PIPE_FORMAT_DXT1_RGB:
1791 case PIPE_FORMAT_DXT1_RGBA:
1792 case PIPE_FORMAT_DXT1_SRGB:
1793 case PIPE_FORMAT_DXT1_SRGBA:
1794 return V_008F14_IMG_DATA_FORMAT_BC1;
1795 case PIPE_FORMAT_DXT3_RGBA:
1796 case PIPE_FORMAT_DXT3_SRGBA:
1797 return V_008F14_IMG_DATA_FORMAT_BC2;
1798 case PIPE_FORMAT_DXT5_RGBA:
1799 case PIPE_FORMAT_DXT5_SRGBA:
1800 return V_008F14_IMG_DATA_FORMAT_BC3;
1801 default:
1802 goto out_unknown;
1803 }
1804 }
1805
1806 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1807 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1808 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1809 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1810 }
1811
1812 /* R8G8Bx_SNORM - TODO CxV8U8 */
1813
1814 /* hw cannot support mixed formats (except depth/stencil, since only
1815 * depth is read).*/
1816 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1817 goto out_unknown;
1818
1819 /* See whether the components are of the same size. */
1820 for (i = 1; i < desc->nr_channels; i++) {
1821 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1822 }
1823
1824 /* Non-uniform formats. */
1825 if (!uniform) {
1826 switch(desc->nr_channels) {
1827 case 3:
1828 if (desc->channel[0].size == 5 &&
1829 desc->channel[1].size == 6 &&
1830 desc->channel[2].size == 5) {
1831 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1832 }
1833 goto out_unknown;
1834 case 4:
1835 if (desc->channel[0].size == 5 &&
1836 desc->channel[1].size == 5 &&
1837 desc->channel[2].size == 5 &&
1838 desc->channel[3].size == 1) {
1839 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1840 }
1841 if (desc->channel[0].size == 1 &&
1842 desc->channel[1].size == 5 &&
1843 desc->channel[2].size == 5 &&
1844 desc->channel[3].size == 5) {
1845 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1846 }
1847 if (desc->channel[0].size == 10 &&
1848 desc->channel[1].size == 10 &&
1849 desc->channel[2].size == 10 &&
1850 desc->channel[3].size == 2) {
1851 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1852 }
1853 goto out_unknown;
1854 }
1855 goto out_unknown;
1856 }
1857
1858 if (first_non_void < 0 || first_non_void > 3)
1859 goto out_unknown;
1860
1861 /* uniform formats */
1862 switch (desc->channel[first_non_void].size) {
1863 case 4:
1864 switch (desc->nr_channels) {
1865 #if 0 /* Not supported for render targets */
1866 case 2:
1867 return V_008F14_IMG_DATA_FORMAT_4_4;
1868 #endif
1869 case 4:
1870 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1871 }
1872 break;
1873 case 8:
1874 switch (desc->nr_channels) {
1875 case 1:
1876 return V_008F14_IMG_DATA_FORMAT_8;
1877 case 2:
1878 return V_008F14_IMG_DATA_FORMAT_8_8;
1879 case 4:
1880 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1881 }
1882 break;
1883 case 16:
1884 switch (desc->nr_channels) {
1885 case 1:
1886 return V_008F14_IMG_DATA_FORMAT_16;
1887 case 2:
1888 return V_008F14_IMG_DATA_FORMAT_16_16;
1889 case 4:
1890 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1891 }
1892 break;
1893 case 32:
1894 switch (desc->nr_channels) {
1895 case 1:
1896 return V_008F14_IMG_DATA_FORMAT_32;
1897 case 2:
1898 return V_008F14_IMG_DATA_FORMAT_32_32;
1899 #if 0 /* Not supported for render targets */
1900 case 3:
1901 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1902 #endif
1903 case 4:
1904 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1905 }
1906 }
1907
1908 out_unknown:
1909 return ~0;
1910 }
1911
1912 static unsigned si_tex_wrap(unsigned wrap)
1913 {
1914 switch (wrap) {
1915 default:
1916 case PIPE_TEX_WRAP_REPEAT:
1917 return V_008F30_SQ_TEX_WRAP;
1918 case PIPE_TEX_WRAP_CLAMP:
1919 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1920 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1921 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1922 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1923 return V_008F30_SQ_TEX_CLAMP_BORDER;
1924 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1925 return V_008F30_SQ_TEX_MIRROR;
1926 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1927 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1928 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1929 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1930 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1931 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1932 }
1933 }
1934
1935 static unsigned si_tex_mipfilter(unsigned filter)
1936 {
1937 switch (filter) {
1938 case PIPE_TEX_MIPFILTER_NEAREST:
1939 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1940 case PIPE_TEX_MIPFILTER_LINEAR:
1941 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1942 default:
1943 case PIPE_TEX_MIPFILTER_NONE:
1944 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1945 }
1946 }
1947
1948 static unsigned si_tex_compare(unsigned compare)
1949 {
1950 switch (compare) {
1951 default:
1952 case PIPE_FUNC_NEVER:
1953 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1954 case PIPE_FUNC_LESS:
1955 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1956 case PIPE_FUNC_EQUAL:
1957 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1958 case PIPE_FUNC_LEQUAL:
1959 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1960 case PIPE_FUNC_GREATER:
1961 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1962 case PIPE_FUNC_NOTEQUAL:
1963 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1964 case PIPE_FUNC_GEQUAL:
1965 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1966 case PIPE_FUNC_ALWAYS:
1967 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1968 }
1969 }
1970
1971 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1972 unsigned view_target, unsigned nr_samples)
1973 {
1974 unsigned res_target = tex->buffer.b.b.target;
1975
1976 if (view_target == PIPE_TEXTURE_CUBE ||
1977 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1978 res_target = view_target;
1979 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1980 else if (res_target == PIPE_TEXTURE_CUBE ||
1981 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1982 res_target = PIPE_TEXTURE_2D_ARRAY;
1983
1984 /* GFX9 allocates 1D textures as 2D. */
1985 if ((res_target == PIPE_TEXTURE_1D ||
1986 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1987 sscreen->info.chip_class == GFX9 &&
1988 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1989 if (res_target == PIPE_TEXTURE_1D)
1990 res_target = PIPE_TEXTURE_2D;
1991 else
1992 res_target = PIPE_TEXTURE_2D_ARRAY;
1993 }
1994
1995 switch (res_target) {
1996 default:
1997 case PIPE_TEXTURE_1D:
1998 return V_008F1C_SQ_RSRC_IMG_1D;
1999 case PIPE_TEXTURE_1D_ARRAY:
2000 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2001 case PIPE_TEXTURE_2D:
2002 case PIPE_TEXTURE_RECT:
2003 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2004 V_008F1C_SQ_RSRC_IMG_2D;
2005 case PIPE_TEXTURE_2D_ARRAY:
2006 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2007 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2008 case PIPE_TEXTURE_3D:
2009 return V_008F1C_SQ_RSRC_IMG_3D;
2010 case PIPE_TEXTURE_CUBE:
2011 case PIPE_TEXTURE_CUBE_ARRAY:
2012 return V_008F1C_SQ_RSRC_IMG_CUBE;
2013 }
2014 }
2015
2016 /*
2017 * Format support testing
2018 */
2019
2020 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2021 {
2022 struct si_screen *sscreen = (struct si_screen *)screen;
2023
2024 if (sscreen->info.chip_class >= GFX10) {
2025 const struct gfx10_format *fmt = &gfx10_format_table[format];
2026 if (!fmt->img_format || fmt->buffers_only)
2027 return false;
2028 return true;
2029 }
2030
2031 const struct util_format_description *desc = util_format_description(format);
2032 if (!desc)
2033 return false;
2034
2035 return si_translate_texformat(screen, format, desc,
2036 util_format_get_first_non_void_channel(format)) != ~0U;
2037 }
2038
2039 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2040 const struct util_format_description *desc,
2041 int first_non_void)
2042 {
2043 int i;
2044
2045 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2046
2047 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2048 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2049
2050 assert(first_non_void >= 0);
2051
2052 if (desc->nr_channels == 4 &&
2053 desc->channel[0].size == 10 &&
2054 desc->channel[1].size == 10 &&
2055 desc->channel[2].size == 10 &&
2056 desc->channel[3].size == 2)
2057 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2058
2059 /* See whether the components are of the same size. */
2060 for (i = 0; i < desc->nr_channels; i++) {
2061 if (desc->channel[first_non_void].size != desc->channel[i].size)
2062 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2063 }
2064
2065 switch (desc->channel[first_non_void].size) {
2066 case 8:
2067 switch (desc->nr_channels) {
2068 case 1:
2069 case 3: /* 3 loads */
2070 return V_008F0C_BUF_DATA_FORMAT_8;
2071 case 2:
2072 return V_008F0C_BUF_DATA_FORMAT_8_8;
2073 case 4:
2074 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2075 }
2076 break;
2077 case 16:
2078 switch (desc->nr_channels) {
2079 case 1:
2080 case 3: /* 3 loads */
2081 return V_008F0C_BUF_DATA_FORMAT_16;
2082 case 2:
2083 return V_008F0C_BUF_DATA_FORMAT_16_16;
2084 case 4:
2085 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2086 }
2087 break;
2088 case 32:
2089 switch (desc->nr_channels) {
2090 case 1:
2091 return V_008F0C_BUF_DATA_FORMAT_32;
2092 case 2:
2093 return V_008F0C_BUF_DATA_FORMAT_32_32;
2094 case 3:
2095 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2096 case 4:
2097 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2098 }
2099 break;
2100 case 64:
2101 /* Legacy double formats. */
2102 switch (desc->nr_channels) {
2103 case 1: /* 1 load */
2104 return V_008F0C_BUF_DATA_FORMAT_32_32;
2105 case 2: /* 1 load */
2106 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2107 case 3: /* 3 loads */
2108 return V_008F0C_BUF_DATA_FORMAT_32_32;
2109 case 4: /* 2 loads */
2110 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2111 }
2112 break;
2113 }
2114
2115 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2116 }
2117
2118 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2119 const struct util_format_description *desc,
2120 int first_non_void)
2121 {
2122 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2123
2124 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2125 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2126
2127 assert(first_non_void >= 0);
2128
2129 switch (desc->channel[first_non_void].type) {
2130 case UTIL_FORMAT_TYPE_SIGNED:
2131 case UTIL_FORMAT_TYPE_FIXED:
2132 if (desc->channel[first_non_void].size >= 32 ||
2133 desc->channel[first_non_void].pure_integer)
2134 return V_008F0C_BUF_NUM_FORMAT_SINT;
2135 else if (desc->channel[first_non_void].normalized)
2136 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2137 else
2138 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2139 break;
2140 case UTIL_FORMAT_TYPE_UNSIGNED:
2141 if (desc->channel[first_non_void].size >= 32 ||
2142 desc->channel[first_non_void].pure_integer)
2143 return V_008F0C_BUF_NUM_FORMAT_UINT;
2144 else if (desc->channel[first_non_void].normalized)
2145 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2146 else
2147 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2148 break;
2149 case UTIL_FORMAT_TYPE_FLOAT:
2150 default:
2151 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2152 }
2153 }
2154
2155 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2156 enum pipe_format format,
2157 unsigned usage)
2158 {
2159 struct si_screen *sscreen = (struct si_screen *)screen;
2160 const struct util_format_description *desc;
2161 int first_non_void;
2162 unsigned data_format;
2163
2164 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2165 PIPE_BIND_SAMPLER_VIEW |
2166 PIPE_BIND_VERTEX_BUFFER)) == 0);
2167
2168 desc = util_format_description(format);
2169 if (!desc)
2170 return 0;
2171
2172 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2173 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2174 * for read-only access (with caveats surrounding bounds checks), but
2175 * obviously fails for write access which we have to implement for
2176 * shader images. Luckily, OpenGL doesn't expect this to be supported
2177 * anyway, and so the only impact is on PBO uploads / downloads, which
2178 * shouldn't be expected to be fast for GL_RGB anyway.
2179 */
2180 if (desc->block.bits == 3 * 8 ||
2181 desc->block.bits == 3 * 16) {
2182 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2183 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2184 if (!usage)
2185 return 0;
2186 }
2187 }
2188
2189 if (sscreen->info.chip_class >= GFX10) {
2190 const struct gfx10_format *fmt = &gfx10_format_table[format];
2191 if (!fmt->img_format || fmt->img_format >= 128)
2192 return 0;
2193 return usage;
2194 }
2195
2196 first_non_void = util_format_get_first_non_void_channel(format);
2197 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2198 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2199 return 0;
2200
2201 return usage;
2202 }
2203
2204 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2205 {
2206 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2207 si_translate_colorswap(format, false) != ~0U;
2208 }
2209
2210 static bool si_is_zs_format_supported(enum pipe_format format)
2211 {
2212 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2213 }
2214
2215 static bool si_is_format_supported(struct pipe_screen *screen,
2216 enum pipe_format format,
2217 enum pipe_texture_target target,
2218 unsigned sample_count,
2219 unsigned storage_sample_count,
2220 unsigned usage)
2221 {
2222 struct si_screen *sscreen = (struct si_screen *)screen;
2223 unsigned retval = 0;
2224
2225 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2226 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2227 return false;
2228 }
2229
2230 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2231 return false;
2232
2233 if (sample_count > 1) {
2234 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2235 return false;
2236
2237 if (usage & PIPE_BIND_SHADER_IMAGE)
2238 return false;
2239
2240 /* Only power-of-two sample counts are supported. */
2241 if (!util_is_power_of_two_or_zero(sample_count) ||
2242 !util_is_power_of_two_or_zero(storage_sample_count))
2243 return false;
2244
2245 /* MSAA support without framebuffer attachments. */
2246 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2247 return true;
2248
2249 if (!sscreen->info.has_eqaa_surface_allocator ||
2250 util_format_is_depth_or_stencil(format)) {
2251 /* Color without EQAA or depth/stencil. */
2252 if (sample_count > 8 ||
2253 sample_count != storage_sample_count)
2254 return false;
2255 } else {
2256 /* Color with EQAA. */
2257 if (sample_count > 16 ||
2258 storage_sample_count > 8)
2259 return false;
2260 }
2261 }
2262
2263 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2264 PIPE_BIND_SHADER_IMAGE)) {
2265 if (target == PIPE_BUFFER) {
2266 retval |= si_is_vertex_format_supported(
2267 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2268 PIPE_BIND_SHADER_IMAGE));
2269 } else {
2270 if (si_is_sampler_format_supported(screen, format))
2271 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2272 PIPE_BIND_SHADER_IMAGE);
2273 }
2274 }
2275
2276 if ((usage & (PIPE_BIND_RENDER_TARGET |
2277 PIPE_BIND_DISPLAY_TARGET |
2278 PIPE_BIND_SCANOUT |
2279 PIPE_BIND_SHARED |
2280 PIPE_BIND_BLENDABLE)) &&
2281 si_is_colorbuffer_format_supported(format)) {
2282 retval |= usage &
2283 (PIPE_BIND_RENDER_TARGET |
2284 PIPE_BIND_DISPLAY_TARGET |
2285 PIPE_BIND_SCANOUT |
2286 PIPE_BIND_SHARED);
2287 if (!util_format_is_pure_integer(format) &&
2288 !util_format_is_depth_or_stencil(format))
2289 retval |= usage & PIPE_BIND_BLENDABLE;
2290 }
2291
2292 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2293 si_is_zs_format_supported(format)) {
2294 retval |= PIPE_BIND_DEPTH_STENCIL;
2295 }
2296
2297 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2298 retval |= si_is_vertex_format_supported(screen, format,
2299 PIPE_BIND_VERTEX_BUFFER);
2300 }
2301
2302 if ((usage & PIPE_BIND_LINEAR) &&
2303 !util_format_is_compressed(format) &&
2304 !(usage & PIPE_BIND_DEPTH_STENCIL))
2305 retval |= PIPE_BIND_LINEAR;
2306
2307 return retval == usage;
2308 }
2309
2310 /*
2311 * framebuffer handling
2312 */
2313
2314 static void si_choose_spi_color_formats(struct si_surface *surf,
2315 unsigned format, unsigned swap,
2316 unsigned ntype, bool is_depth)
2317 {
2318 /* Alpha is needed for alpha-to-coverage.
2319 * Blending may be with or without alpha.
2320 */
2321 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2322 unsigned alpha = 0; /* exports alpha, but may not support blending */
2323 unsigned blend = 0; /* supports blending, but may not export alpha */
2324 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2325
2326 /* Choose the SPI color formats. These are required values for RB+.
2327 * Other chips have multiple choices, though they are not necessarily better.
2328 */
2329 switch (format) {
2330 case V_028C70_COLOR_5_6_5:
2331 case V_028C70_COLOR_1_5_5_5:
2332 case V_028C70_COLOR_5_5_5_1:
2333 case V_028C70_COLOR_4_4_4_4:
2334 case V_028C70_COLOR_10_11_11:
2335 case V_028C70_COLOR_11_11_10:
2336 case V_028C70_COLOR_8:
2337 case V_028C70_COLOR_8_8:
2338 case V_028C70_COLOR_8_8_8_8:
2339 case V_028C70_COLOR_10_10_10_2:
2340 case V_028C70_COLOR_2_10_10_10:
2341 if (ntype == V_028C70_NUMBER_UINT)
2342 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2343 else if (ntype == V_028C70_NUMBER_SINT)
2344 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2345 else
2346 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2347 break;
2348
2349 case V_028C70_COLOR_16:
2350 case V_028C70_COLOR_16_16:
2351 case V_028C70_COLOR_16_16_16_16:
2352 if (ntype == V_028C70_NUMBER_UNORM ||
2353 ntype == V_028C70_NUMBER_SNORM) {
2354 /* UNORM16 and SNORM16 don't support blending */
2355 if (ntype == V_028C70_NUMBER_UNORM)
2356 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2357 else
2358 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2359
2360 /* Use 32 bits per channel for blending. */
2361 if (format == V_028C70_COLOR_16) {
2362 if (swap == V_028C70_SWAP_STD) { /* R */
2363 blend = V_028714_SPI_SHADER_32_R;
2364 blend_alpha = V_028714_SPI_SHADER_32_AR;
2365 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2366 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2367 else
2368 assert(0);
2369 } else if (format == V_028C70_COLOR_16_16) {
2370 if (swap == V_028C70_SWAP_STD) { /* RG */
2371 blend = V_028714_SPI_SHADER_32_GR;
2372 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2373 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2374 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2375 else
2376 assert(0);
2377 } else /* 16_16_16_16 */
2378 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2379 } else if (ntype == V_028C70_NUMBER_UINT)
2380 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2381 else if (ntype == V_028C70_NUMBER_SINT)
2382 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2383 else if (ntype == V_028C70_NUMBER_FLOAT)
2384 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2385 else
2386 assert(0);
2387 break;
2388
2389 case V_028C70_COLOR_32:
2390 if (swap == V_028C70_SWAP_STD) { /* R */
2391 blend = normal = V_028714_SPI_SHADER_32_R;
2392 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2393 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2394 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2395 else
2396 assert(0);
2397 break;
2398
2399 case V_028C70_COLOR_32_32:
2400 if (swap == V_028C70_SWAP_STD) { /* RG */
2401 blend = normal = V_028714_SPI_SHADER_32_GR;
2402 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2403 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2404 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2405 else
2406 assert(0);
2407 break;
2408
2409 case V_028C70_COLOR_32_32_32_32:
2410 case V_028C70_COLOR_8_24:
2411 case V_028C70_COLOR_24_8:
2412 case V_028C70_COLOR_X24_8_32_FLOAT:
2413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2414 break;
2415
2416 default:
2417 assert(0);
2418 return;
2419 }
2420
2421 /* The DB->CB copy needs 32_ABGR. */
2422 if (is_depth)
2423 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2424
2425 surf->spi_shader_col_format = normal;
2426 surf->spi_shader_col_format_alpha = alpha;
2427 surf->spi_shader_col_format_blend = blend;
2428 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2429 }
2430
2431 static void si_initialize_color_surface(struct si_context *sctx,
2432 struct si_surface *surf)
2433 {
2434 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2435 unsigned color_info, color_attrib;
2436 unsigned format, swap, ntype, endian;
2437 const struct util_format_description *desc;
2438 int firstchan;
2439 unsigned blend_clamp = 0, blend_bypass = 0;
2440
2441 desc = util_format_description(surf->base.format);
2442 for (firstchan = 0; firstchan < 4; firstchan++) {
2443 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2444 break;
2445 }
2446 }
2447 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2448 ntype = V_028C70_NUMBER_FLOAT;
2449 } else {
2450 ntype = V_028C70_NUMBER_UNORM;
2451 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2452 ntype = V_028C70_NUMBER_SRGB;
2453 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2454 if (desc->channel[firstchan].pure_integer) {
2455 ntype = V_028C70_NUMBER_SINT;
2456 } else {
2457 assert(desc->channel[firstchan].normalized);
2458 ntype = V_028C70_NUMBER_SNORM;
2459 }
2460 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2461 if (desc->channel[firstchan].pure_integer) {
2462 ntype = V_028C70_NUMBER_UINT;
2463 } else {
2464 assert(desc->channel[firstchan].normalized);
2465 ntype = V_028C70_NUMBER_UNORM;
2466 }
2467 }
2468 }
2469
2470 format = si_translate_colorformat(surf->base.format);
2471 if (format == V_028C70_COLOR_INVALID) {
2472 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2473 }
2474 assert(format != V_028C70_COLOR_INVALID);
2475 swap = si_translate_colorswap(surf->base.format, false);
2476 endian = si_colorformat_endian_swap(format);
2477
2478 /* blend clamp should be set for all NORM/SRGB types */
2479 if (ntype == V_028C70_NUMBER_UNORM ||
2480 ntype == V_028C70_NUMBER_SNORM ||
2481 ntype == V_028C70_NUMBER_SRGB)
2482 blend_clamp = 1;
2483
2484 /* set blend bypass according to docs if SINT/UINT or
2485 8/24 COLOR variants */
2486 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2487 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2488 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2489 blend_clamp = 0;
2490 blend_bypass = 1;
2491 }
2492
2493 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2494 if (format == V_028C70_COLOR_8 ||
2495 format == V_028C70_COLOR_8_8 ||
2496 format == V_028C70_COLOR_8_8_8_8)
2497 surf->color_is_int8 = true;
2498 else if (format == V_028C70_COLOR_10_10_10_2 ||
2499 format == V_028C70_COLOR_2_10_10_10)
2500 surf->color_is_int10 = true;
2501 }
2502
2503 color_info = S_028C70_FORMAT(format) |
2504 S_028C70_COMP_SWAP(swap) |
2505 S_028C70_BLEND_CLAMP(blend_clamp) |
2506 S_028C70_BLEND_BYPASS(blend_bypass) |
2507 S_028C70_SIMPLE_FLOAT(1) |
2508 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2509 ntype != V_028C70_NUMBER_SNORM &&
2510 ntype != V_028C70_NUMBER_SRGB &&
2511 format != V_028C70_COLOR_8_24 &&
2512 format != V_028C70_COLOR_24_8) |
2513 S_028C70_NUMBER_TYPE(ntype) |
2514 S_028C70_ENDIAN(endian);
2515
2516 /* Intensity is implemented as Red, so treat it that way. */
2517 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2518 util_format_is_intensity(surf->base.format));
2519
2520 if (tex->buffer.b.b.nr_samples > 1) {
2521 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2522 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2523
2524 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2525 S_028C74_NUM_FRAGMENTS(log_fragments);
2526
2527 if (tex->fmask_offset) {
2528 color_info |= S_028C70_COMPRESSION(1);
2529 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2530
2531 if (sctx->chip_class == GFX6) {
2532 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2533 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2534 }
2535 }
2536 }
2537
2538 if (sctx->chip_class >= GFX10) {
2539 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2540
2541 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2542 64 for APU because all of our APUs to date use DIMMs which have
2543 a request granularity size of 64B while all other chips have a
2544 32B request size */
2545 if (!sctx->screen->info.has_dedicated_vram)
2546 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2547
2548 surf->cb_dcc_control =
2549 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2550 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2551 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2552 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2553 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2554 } else if (sctx->chip_class >= GFX8) {
2555 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2556 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2557
2558 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2559 64 for APU because all of our APUs to date use DIMMs which have
2560 a request granularity size of 64B while all other chips have a
2561 32B request size */
2562 if (!sctx->screen->info.has_dedicated_vram)
2563 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2564
2565 if (tex->buffer.b.b.nr_storage_samples > 1) {
2566 if (tex->surface.bpe == 1)
2567 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2568 else if (tex->surface.bpe == 2)
2569 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2570 }
2571
2572 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2573 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2574 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2575 }
2576
2577 /* This must be set for fast clear to work without FMASK. */
2578 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2579 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2580 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2581 }
2582
2583 /* GFX10 field has the same base shift as the GFX6 field */
2584 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2585 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2586 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2587
2588 if (sctx->chip_class >= GFX10) {
2589 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2590
2591 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2592 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2593 S_028EE0_RESOURCE_LEVEL(1);
2594 } else if (sctx->chip_class == GFX9) {
2595 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2596 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2597 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2598 }
2599
2600 if (sctx->chip_class >= GFX9) {
2601 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2602 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2603 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2604 }
2605
2606 surf->cb_color_view = color_view;
2607 surf->cb_color_info = color_info;
2608 surf->cb_color_attrib = color_attrib;
2609
2610 /* Determine pixel shader export format */
2611 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2612
2613 surf->color_initialized = true;
2614 }
2615
2616 static void si_init_depth_surface(struct si_context *sctx,
2617 struct si_surface *surf)
2618 {
2619 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2620 unsigned level = surf->base.u.tex.level;
2621 unsigned format, stencil_format;
2622 uint32_t z_info, s_info;
2623
2624 format = si_translate_dbformat(tex->db_render_format);
2625 stencil_format = tex->surface.has_stencil ?
2626 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2627
2628 assert(format != V_028040_Z_INVALID);
2629 if (format == V_028040_Z_INVALID)
2630 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2631
2632 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2633 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2634 surf->db_htile_data_base = 0;
2635 surf->db_htile_surface = 0;
2636
2637 if (sctx->chip_class >= GFX10) {
2638 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2639 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2640 }
2641
2642 if (sctx->chip_class >= GFX9) {
2643 assert(tex->surface.u.gfx9.surf_offset == 0);
2644 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2645 surf->db_stencil_base = (tex->buffer.gpu_address +
2646 tex->surface.u.gfx9.stencil_offset) >> 8;
2647 z_info = S_028038_FORMAT(format) |
2648 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2649 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2650 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2651 s_info = S_02803C_FORMAT(stencil_format) |
2652 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2653
2654 if (sctx->chip_class == GFX9) {
2655 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2656 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2657 }
2658 surf->db_depth_view |= S_028008_MIPID(level);
2659 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2660 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2661
2662 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2663 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2664 S_028038_ALLOW_EXPCLEAR(1);
2665
2666 if (tex->tc_compatible_htile) {
2667 unsigned max_zplanes = 4;
2668
2669 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2670 tex->buffer.b.b.nr_samples > 1)
2671 max_zplanes = 2;
2672
2673 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2674
2675 if (sctx->chip_class >= GFX10) {
2676 z_info |= S_028040_ITERATE_FLUSH(1);
2677 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2678 } else {
2679 z_info |= S_028038_ITERATE_FLUSH(1);
2680 s_info |= S_02803C_ITERATE_FLUSH(1);
2681 }
2682 }
2683
2684 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2685 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2686 * See that for explanation.
2687 */
2688 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2689 } else {
2690 /* Use all HTILE for depth if there's no stencil. */
2691 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2692 }
2693
2694 surf->db_htile_data_base = (tex->buffer.gpu_address +
2695 tex->htile_offset) >> 8;
2696 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2697 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2698 if (sctx->chip_class == GFX9) {
2699 surf->db_htile_surface |=
2700 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2701 }
2702 }
2703 } else {
2704 /* GFX6-GFX8 */
2705 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2706
2707 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2708
2709 surf->db_depth_base = (tex->buffer.gpu_address +
2710 tex->surface.u.legacy.level[level].offset) >> 8;
2711 surf->db_stencil_base = (tex->buffer.gpu_address +
2712 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2713
2714 z_info = S_028040_FORMAT(format) |
2715 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2716 s_info = S_028044_FORMAT(stencil_format);
2717 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2718
2719 if (sctx->chip_class >= GFX7) {
2720 struct radeon_info *info = &sctx->screen->info;
2721 unsigned index = tex->surface.u.legacy.tiling_index[level];
2722 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2723 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2724 unsigned tile_mode = info->si_tile_mode_array[index];
2725 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2726 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2727
2728 surf->db_depth_info |=
2729 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2730 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2731 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2732 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2733 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2734 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2735 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2736 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2737 } else {
2738 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2739 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2740 tile_mode_index = si_tile_mode_index(tex, level, true);
2741 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2742 }
2743
2744 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2745 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2746 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2747 levelinfo->nblk_y) / 64 - 1);
2748
2749 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2750 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2751 S_028040_ALLOW_EXPCLEAR(1);
2752
2753 if (tex->surface.has_stencil) {
2754 /* Workaround: For a not yet understood reason, the
2755 * combination of MSAA, fast stencil clear and stencil
2756 * decompress messes with subsequent stencil buffer
2757 * uses. Problem was reproduced on Verde, Bonaire,
2758 * Tonga, and Carrizo.
2759 *
2760 * Disabling EXPCLEAR works around the problem.
2761 *
2762 * Check piglit's arb_texture_multisample-stencil-clear
2763 * test if you want to try changing this.
2764 */
2765 if (tex->buffer.b.b.nr_samples <= 1)
2766 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2767 } else if (!tex->tc_compatible_htile) {
2768 /* Use all of the htile_buffer for depth if there's no stencil.
2769 * This must not be set when TC-compatible HTILE is enabled
2770 * due to a hw bug.
2771 */
2772 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2773 }
2774
2775 surf->db_htile_data_base = (tex->buffer.gpu_address +
2776 tex->htile_offset) >> 8;
2777 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2778
2779 if (tex->tc_compatible_htile) {
2780 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2781
2782 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2783 if (tex->buffer.b.b.nr_samples <= 1)
2784 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2785 else if (tex->buffer.b.b.nr_samples <= 4)
2786 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2787 else
2788 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2789 }
2790 }
2791 }
2792
2793 surf->db_z_info = z_info;
2794 surf->db_stencil_info = s_info;
2795
2796 surf->depth_initialized = true;
2797 }
2798
2799 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2800 {
2801 if (sctx->decompression_enabled)
2802 return;
2803
2804 if (sctx->framebuffer.state.zsbuf) {
2805 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2806 struct si_texture *tex = (struct si_texture *)surf->texture;
2807
2808 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2809
2810 if (tex->surface.has_stencil)
2811 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2812 }
2813
2814 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2815 while (compressed_cb_mask) {
2816 unsigned i = u_bit_scan(&compressed_cb_mask);
2817 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2818 struct si_texture *tex = (struct si_texture*)surf->texture;
2819
2820 if (tex->fmask_offset)
2821 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2822 if (tex->dcc_gather_statistics)
2823 tex->separate_dcc_dirty = true;
2824 }
2825 }
2826
2827 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2828 {
2829 for (int i = 0; i < state->nr_cbufs; ++i) {
2830 struct si_surface *surf = NULL;
2831 struct si_texture *tex;
2832
2833 if (!state->cbufs[i])
2834 continue;
2835 surf = (struct si_surface*)state->cbufs[i];
2836 tex = (struct si_texture*)surf->base.texture;
2837
2838 p_atomic_dec(&tex->framebuffers_bound);
2839 }
2840 }
2841
2842 static void si_set_framebuffer_state(struct pipe_context *ctx,
2843 const struct pipe_framebuffer_state *state)
2844 {
2845 struct si_context *sctx = (struct si_context *)ctx;
2846 struct si_surface *surf = NULL;
2847 struct si_texture *tex;
2848 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2849 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2850 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2851 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2852 bool old_has_stencil =
2853 old_has_zsbuf &&
2854 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2855 bool unbound = false;
2856 int i;
2857
2858 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2859 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2860 * We could implement the full workaround here, but it's a useless case.
2861 */
2862 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2863 unreachable("the framebuffer shouldn't have zero area");
2864 return;
2865 }
2866
2867 si_update_fb_dirtiness_after_rendering(sctx);
2868
2869 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2870 if (!sctx->framebuffer.state.cbufs[i])
2871 continue;
2872
2873 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2874 if (tex->dcc_gather_statistics)
2875 vi_separate_dcc_stop_query(sctx, tex);
2876 }
2877
2878 /* Disable DCC if the formats are incompatible. */
2879 for (i = 0; i < state->nr_cbufs; i++) {
2880 if (!state->cbufs[i])
2881 continue;
2882
2883 surf = (struct si_surface*)state->cbufs[i];
2884 tex = (struct si_texture*)surf->base.texture;
2885
2886 if (!surf->dcc_incompatible)
2887 continue;
2888
2889 /* Since the DCC decompression calls back into set_framebuffer-
2890 * _state, we need to unbind the framebuffer, so that
2891 * vi_separate_dcc_stop_query isn't called twice with the same
2892 * color buffer.
2893 */
2894 if (!unbound) {
2895 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2896 unbound = true;
2897 }
2898
2899 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2900 if (!si_texture_disable_dcc(sctx, tex))
2901 si_decompress_dcc(sctx, tex);
2902
2903 surf->dcc_incompatible = false;
2904 }
2905
2906 /* Only flush TC when changing the framebuffer state, because
2907 * the only client not using TC that can change textures is
2908 * the framebuffer.
2909 *
2910 * Wait for compute shaders because of possible transitions:
2911 * - FB write -> shader read
2912 * - shader write -> FB read
2913 *
2914 * DB caches are flushed on demand (using si_decompress_textures).
2915 *
2916 * When MSAA is enabled, CB and TC caches are flushed on demand
2917 * (after FMASK decompression). Shader write -> FB read transitions
2918 * cannot happen for MSAA textures, because MSAA shader images are
2919 * not supported.
2920 *
2921 * Only flush and wait for CB if there is actually a bound color buffer.
2922 */
2923 if (sctx->framebuffer.uncompressed_cb_mask) {
2924 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2925 sctx->framebuffer.CB_has_shader_readable_metadata,
2926 sctx->framebuffer.all_DCC_pipe_aligned);
2927 }
2928
2929 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2930
2931 /* u_blitter doesn't invoke depth decompression when it does multiple
2932 * blits in a row, but the only case when it matters for DB is when
2933 * doing generate_mipmap. So here we flush DB manually between
2934 * individual generate_mipmap blits.
2935 * Note that lower mipmap levels aren't compressed.
2936 */
2937 if (sctx->generate_mipmap_for_depth) {
2938 si_make_DB_shader_coherent(sctx, 1, false,
2939 sctx->framebuffer.DB_has_shader_readable_metadata);
2940 } else if (sctx->chip_class == GFX9) {
2941 /* It appears that DB metadata "leaks" in a sequence of:
2942 * - depth clear
2943 * - DCC decompress for shader image writes (with DB disabled)
2944 * - render with DEPTH_BEFORE_SHADER=1
2945 * Flushing DB metadata works around the problem.
2946 */
2947 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2948 }
2949
2950 /* Take the maximum of the old and new count. If the new count is lower,
2951 * dirtying is needed to disable the unbound colorbuffers.
2952 */
2953 sctx->framebuffer.dirty_cbufs |=
2954 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2955 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2956
2957 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2958 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2959
2960 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2961 sctx->framebuffer.spi_shader_col_format = 0;
2962 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2963 sctx->framebuffer.spi_shader_col_format_blend = 0;
2964 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2965 sctx->framebuffer.color_is_int8 = 0;
2966 sctx->framebuffer.color_is_int10 = 0;
2967
2968 sctx->framebuffer.compressed_cb_mask = 0;
2969 sctx->framebuffer.uncompressed_cb_mask = 0;
2970 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2971 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2972 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2973 sctx->framebuffer.any_dst_linear = false;
2974 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2975 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2976 sctx->framebuffer.all_DCC_pipe_aligned = true;
2977 sctx->framebuffer.min_bytes_per_pixel = 0;
2978
2979 for (i = 0; i < state->nr_cbufs; i++) {
2980 if (!state->cbufs[i])
2981 continue;
2982
2983 surf = (struct si_surface*)state->cbufs[i];
2984 tex = (struct si_texture*)surf->base.texture;
2985
2986 if (!surf->color_initialized) {
2987 si_initialize_color_surface(sctx, surf);
2988 }
2989
2990 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2991 sctx->framebuffer.spi_shader_col_format |=
2992 surf->spi_shader_col_format << (i * 4);
2993 sctx->framebuffer.spi_shader_col_format_alpha |=
2994 surf->spi_shader_col_format_alpha << (i * 4);
2995 sctx->framebuffer.spi_shader_col_format_blend |=
2996 surf->spi_shader_col_format_blend << (i * 4);
2997 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2998 surf->spi_shader_col_format_blend_alpha << (i * 4);
2999
3000 if (surf->color_is_int8)
3001 sctx->framebuffer.color_is_int8 |= 1 << i;
3002 if (surf->color_is_int10)
3003 sctx->framebuffer.color_is_int10 |= 1 << i;
3004
3005 if (tex->fmask_offset)
3006 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3007 else
3008 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3009
3010 /* Don't update nr_color_samples for non-AA buffers.
3011 * (e.g. destination of MSAA resolve)
3012 */
3013 if (tex->buffer.b.b.nr_samples >= 2 &&
3014 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3015 sctx->framebuffer.nr_color_samples =
3016 MIN2(sctx->framebuffer.nr_color_samples,
3017 tex->buffer.b.b.nr_storage_samples);
3018 sctx->framebuffer.nr_color_samples =
3019 MAX2(1, sctx->framebuffer.nr_color_samples);
3020 }
3021
3022 if (tex->surface.is_linear)
3023 sctx->framebuffer.any_dst_linear = true;
3024
3025 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3026 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3027
3028 if (sctx->chip_class >= GFX9 &&
3029 !tex->surface.u.gfx9.dcc.pipe_aligned)
3030 sctx->framebuffer.all_DCC_pipe_aligned = false;
3031 }
3032
3033 si_context_add_resource_size(sctx, surf->base.texture);
3034
3035 p_atomic_inc(&tex->framebuffers_bound);
3036
3037 if (tex->dcc_gather_statistics) {
3038 /* Dirty tracking must be enabled for DCC usage analysis. */
3039 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3040 vi_separate_dcc_start_query(sctx, tex);
3041 }
3042
3043 /* Update the minimum but don't keep 0. */
3044 if (!sctx->framebuffer.min_bytes_per_pixel ||
3045 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3046 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3047 }
3048
3049 /* For optimal DCC performance. */
3050 if (sctx->chip_class >= GFX10)
3051 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3052 else
3053 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3054
3055 struct si_texture *zstex = NULL;
3056
3057 if (state->zsbuf) {
3058 surf = (struct si_surface*)state->zsbuf;
3059 zstex = (struct si_texture*)surf->base.texture;
3060
3061 if (!surf->depth_initialized) {
3062 si_init_depth_surface(sctx, surf);
3063 }
3064
3065 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3066 PIPE_MASK_ZS))
3067 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3068
3069 si_context_add_resource_size(sctx, surf->base.texture);
3070
3071 /* Update the minimum but don't keep 0. */
3072 if (!sctx->framebuffer.min_bytes_per_pixel ||
3073 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3074 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
3075 }
3076
3077 si_update_ps_colorbuf0_slot(sctx);
3078 si_update_poly_offset_state(sctx);
3079 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3080 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3081
3082 if (sctx->screen->dpbb_allowed)
3083 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3084
3085 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3086 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3087
3088 if (sctx->screen->has_out_of_order_rast &&
3089 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3090 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3091 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3092 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3093
3094 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3095 struct pipe_constant_buffer constbuf = {0};
3096
3097 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3098 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3099
3100 constbuf.buffer = sctx->sample_pos_buffer;
3101
3102 /* Set sample locations as fragment shader constants. */
3103 switch (sctx->framebuffer.nr_samples) {
3104 case 1:
3105 constbuf.buffer_offset = 0;
3106 break;
3107 case 2:
3108 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3109 (ubyte*)sctx->sample_positions.x1;
3110 break;
3111 case 4:
3112 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3113 (ubyte*)sctx->sample_positions.x1;
3114 break;
3115 case 8:
3116 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3117 (ubyte*)sctx->sample_positions.x1;
3118 break;
3119 case 16:
3120 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3121 (ubyte*)sctx->sample_positions.x1;
3122 break;
3123 default:
3124 PRINT_ERR("Requested an invalid number of samples %i.\n",
3125 sctx->framebuffer.nr_samples);
3126 assert(0);
3127 }
3128 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3129 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3130
3131 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3132 }
3133
3134 sctx->do_update_shaders = true;
3135
3136 if (!sctx->decompression_enabled) {
3137 /* Prevent textures decompression when the framebuffer state
3138 * changes come from the decompression passes themselves.
3139 */
3140 sctx->need_check_render_feedback = true;
3141 }
3142 }
3143
3144 static void si_emit_framebuffer_state(struct si_context *sctx)
3145 {
3146 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3147 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3148 unsigned i, nr_cbufs = state->nr_cbufs;
3149 struct si_texture *tex = NULL;
3150 struct si_surface *cb = NULL;
3151 unsigned cb_color_info = 0;
3152
3153 /* Colorbuffers. */
3154 for (i = 0; i < nr_cbufs; i++) {
3155 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3156 unsigned cb_color_attrib;
3157
3158 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3159 continue;
3160
3161 cb = (struct si_surface*)state->cbufs[i];
3162 if (!cb) {
3163 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3164 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3165 continue;
3166 }
3167
3168 tex = (struct si_texture *)cb->base.texture;
3169 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3170 &tex->buffer, RADEON_USAGE_READWRITE,
3171 tex->buffer.b.b.nr_samples > 1 ?
3172 RADEON_PRIO_COLOR_BUFFER_MSAA :
3173 RADEON_PRIO_COLOR_BUFFER);
3174
3175 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3176 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3177 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3178 RADEON_PRIO_SEPARATE_META);
3179 }
3180
3181 if (tex->dcc_separate_buffer)
3182 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3183 tex->dcc_separate_buffer,
3184 RADEON_USAGE_READWRITE,
3185 RADEON_PRIO_SEPARATE_META);
3186
3187 /* Compute mutable surface parameters. */
3188 cb_color_base = tex->buffer.gpu_address >> 8;
3189 cb_color_fmask = 0;
3190 cb_color_cmask = tex->cmask_base_address_reg;
3191 cb_dcc_base = 0;
3192 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3193 cb_color_attrib = cb->cb_color_attrib;
3194
3195 if (cb->base.u.tex.level > 0)
3196 cb_color_info &= C_028C70_FAST_CLEAR;
3197
3198 if (tex->fmask_offset) {
3199 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3200 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3201 }
3202
3203 /* Set up DCC. */
3204 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3205 bool is_msaa_resolve_dst = state->cbufs[0] &&
3206 state->cbufs[0]->texture->nr_samples > 1 &&
3207 state->cbufs[1] == &cb->base &&
3208 state->cbufs[1]->texture->nr_samples <= 1;
3209
3210 if (!is_msaa_resolve_dst)
3211 cb_color_info |= S_028C70_DCC_ENABLE(1);
3212
3213 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3214 tex->dcc_offset) >> 8;
3215
3216 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3217 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3218 cb_dcc_base |= dcc_tile_swizzle;
3219 }
3220
3221 if (sctx->chip_class >= GFX10) {
3222 unsigned cb_color_attrib3;
3223
3224 /* Set mutable surface parameters. */
3225 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3226 cb_color_base |= tex->surface.tile_swizzle;
3227 if (!tex->fmask_offset)
3228 cb_color_fmask = cb_color_base;
3229 if (cb->base.u.tex.level > 0)
3230 cb_color_cmask = cb_color_base;
3231
3232 cb_color_attrib3 = cb->cb_color_attrib3 |
3233 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3234 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3235 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3236 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3237
3238 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3239 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3240 radeon_emit(cs, 0); /* hole */
3241 radeon_emit(cs, 0); /* hole */
3242 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3243 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3244 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3245 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3246 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3247 radeon_emit(cs, 0); /* hole */
3248 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3249 radeon_emit(cs, 0); /* hole */
3250 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3251 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3252 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3253
3254 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3255 cb_color_base >> 32);
3256 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3257 cb_color_cmask >> 32);
3258 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3259 cb_color_fmask >> 32);
3260 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3261 cb_dcc_base >> 32);
3262 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3263 cb->cb_color_attrib2);
3264 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3265 cb_color_attrib3);
3266 } else if (sctx->chip_class == GFX9) {
3267 struct gfx9_surf_meta_flags meta;
3268
3269 if (tex->dcc_offset)
3270 meta = tex->surface.u.gfx9.dcc;
3271 else
3272 meta = tex->surface.u.gfx9.cmask;
3273
3274 /* Set mutable surface parameters. */
3275 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3276 cb_color_base |= tex->surface.tile_swizzle;
3277 if (!tex->fmask_offset)
3278 cb_color_fmask = cb_color_base;
3279 if (cb->base.u.tex.level > 0)
3280 cb_color_cmask = cb_color_base;
3281 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3282 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3283 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3284 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3285
3286 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3287 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3288 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3289 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3290 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3291 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3292 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3293 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3294 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3295 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3296 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3297 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3298 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3299 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3300 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3301 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3302
3303 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3304 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3305 } else {
3306 /* Compute mutable surface parameters (GFX6-GFX8). */
3307 const struct legacy_surf_level *level_info =
3308 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3309 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3310 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3311
3312 cb_color_base += level_info->offset >> 8;
3313 /* Only macrotiled modes can set tile swizzle. */
3314 if (level_info->mode == RADEON_SURF_MODE_2D)
3315 cb_color_base |= tex->surface.tile_swizzle;
3316
3317 if (!tex->fmask_offset)
3318 cb_color_fmask = cb_color_base;
3319 if (cb->base.u.tex.level > 0)
3320 cb_color_cmask = cb_color_base;
3321 if (cb_dcc_base)
3322 cb_dcc_base += level_info->dcc_offset >> 8;
3323
3324 pitch_tile_max = level_info->nblk_x / 8 - 1;
3325 slice_tile_max = level_info->nblk_x *
3326 level_info->nblk_y / 64 - 1;
3327 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3328
3329 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3330 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3331 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3332
3333 if (tex->fmask_offset) {
3334 if (sctx->chip_class >= GFX7)
3335 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3336 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3337 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3338 } else {
3339 /* This must be set for fast clear to work without FMASK. */
3340 if (sctx->chip_class >= GFX7)
3341 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3342 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3343 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3344 }
3345
3346 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3347 sctx->chip_class >= GFX8 ? 14 : 13);
3348 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3349 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3350 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3351 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3352 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3353 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3354 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3355 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3356 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3357 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3358 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3359 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3360 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3361
3362 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3363 radeon_emit(cs, cb_dcc_base);
3364 }
3365 }
3366 for (; i < 8 ; i++)
3367 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3368 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3369
3370 /* ZS buffer. */
3371 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3372 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3373 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3374
3375 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3376 &tex->buffer, RADEON_USAGE_READWRITE,
3377 zb->base.texture->nr_samples > 1 ?
3378 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3379 RADEON_PRIO_DEPTH_BUFFER);
3380
3381 if (sctx->chip_class >= GFX10) {
3382 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3383 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3384
3385 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3386 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3387 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3388 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3389 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3390 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3391 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3392 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3393 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3394
3395 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3396 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3397 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3398 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3399 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3400 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3401 } else if (sctx->chip_class == GFX9) {
3402 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3403 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3404 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3405 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3406
3407 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3408 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3409 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3410 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3411 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3412 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3413 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3414 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3415 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3416 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3417 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3418 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3419
3420 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3421 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3422 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3423 } else {
3424 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3425
3426 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3427 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3428 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3429 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3430 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3431 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3432 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3433 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3434 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3435 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3436 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3437 }
3438
3439 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3440 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3441 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3442
3443 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3444 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3445 } else if (sctx->framebuffer.dirty_zsbuf) {
3446 if (sctx->chip_class == GFX9)
3447 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3448 else
3449 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3450
3451 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3452 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3453 }
3454
3455 /* Framebuffer dimensions. */
3456 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3457 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3458 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3459
3460 if (sctx->screen->dfsm_allowed) {
3461 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3462 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3463 }
3464
3465 sctx->framebuffer.dirty_cbufs = 0;
3466 sctx->framebuffer.dirty_zsbuf = false;
3467 }
3468
3469 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3470 {
3471 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3472 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3473 unsigned nr_samples = sctx->framebuffer.nr_samples;
3474 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3475
3476 /* Smoothing (only possible with nr_samples == 1) uses the same
3477 * sample locations as the MSAA it simulates.
3478 */
3479 if (nr_samples <= 1 && sctx->smoothing_enabled)
3480 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3481
3482 /* On Polaris, the small primitive filter uses the sample locations
3483 * even when MSAA is off, so we need to make sure they're set to 0.
3484 *
3485 * GFX10 uses sample locations unconditionally, so they always need
3486 * to be set up.
3487 */
3488 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3489 sctx->chip_class >= GFX10) &&
3490 nr_samples != sctx->sample_locs_num_samples) {
3491 sctx->sample_locs_num_samples = nr_samples;
3492 si_emit_sample_locations(cs, nr_samples);
3493 }
3494
3495 if (sctx->family >= CHIP_POLARIS10) {
3496 unsigned small_prim_filter_cntl =
3497 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3498 /* line bug */
3499 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3500
3501 /* The alternative of setting sample locations to 0 would
3502 * require a DB flush to avoid Z errors, see
3503 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3504 */
3505 if (has_msaa_sample_loc_bug &&
3506 sctx->framebuffer.nr_samples > 1 &&
3507 !rs->multisample_enable)
3508 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3509
3510 radeon_opt_set_context_reg(sctx,
3511 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3512 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3513 small_prim_filter_cntl);
3514 }
3515
3516 /* The exclusion bits can be set to improve rasterization efficiency
3517 * if no sample lies on the pixel boundary (-8 sample offset).
3518 */
3519 bool exclusion = sctx->chip_class >= GFX7 &&
3520 (!rs->multisample_enable || nr_samples != 16);
3521 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3522 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3523 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3524 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3525 }
3526
3527 static bool si_out_of_order_rasterization(struct si_context *sctx)
3528 {
3529 struct si_state_blend *blend = sctx->queued.named.blend;
3530 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3531
3532 if (!sctx->screen->has_out_of_order_rast)
3533 return false;
3534
3535 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3536
3537 colormask &= blend->cb_target_enabled_4bit;
3538
3539 /* Conservative: No logic op. */
3540 if (colormask && blend->logicop_enable)
3541 return false;
3542
3543 struct si_dsa_order_invariance dsa_order_invariant = {
3544 .zs = true, .pass_set = true, .pass_last = false
3545 };
3546
3547 if (sctx->framebuffer.state.zsbuf) {
3548 struct si_texture *zstex =
3549 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3550 bool has_stencil = zstex->surface.has_stencil;
3551 dsa_order_invariant = dsa->order_invariance[has_stencil];
3552 if (!dsa_order_invariant.zs)
3553 return false;
3554
3555 /* The set of PS invocations is always order invariant,
3556 * except when early Z/S tests are requested. */
3557 if (sctx->ps_shader.cso &&
3558 sctx->ps_shader.cso->info.writes_memory &&
3559 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3560 !dsa_order_invariant.pass_set)
3561 return false;
3562
3563 if (sctx->num_perfect_occlusion_queries != 0 &&
3564 !dsa_order_invariant.pass_set)
3565 return false;
3566 }
3567
3568 if (!colormask)
3569 return true;
3570
3571 unsigned blendmask = colormask & blend->blend_enable_4bit;
3572
3573 if (blendmask) {
3574 /* Only commutative blending. */
3575 if (blendmask & ~blend->commutative_4bit)
3576 return false;
3577
3578 if (!dsa_order_invariant.pass_set)
3579 return false;
3580 }
3581
3582 if (colormask & ~blendmask) {
3583 if (!dsa_order_invariant.pass_last)
3584 return false;
3585 }
3586
3587 return true;
3588 }
3589
3590 static void si_emit_msaa_config(struct si_context *sctx)
3591 {
3592 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3593 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3594 /* 33% faster rendering to linear color buffers */
3595 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3596 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3597 unsigned sc_mode_cntl_1 =
3598 S_028A4C_WALK_SIZE(dst_is_linear) |
3599 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3600 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3601 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3602 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3603 /* always 1: */
3604 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3605 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3606 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3607 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3608 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3609 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3610 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3611 S_028804_INCOHERENT_EQAA_READS(1) |
3612 S_028804_INTERPOLATE_COMP_Z(1) |
3613 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3614 unsigned coverage_samples, color_samples, z_samples;
3615 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3616
3617 /* S: Coverage samples (up to 16x):
3618 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3619 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3620 *
3621 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3622 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3623 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3624 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3625 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3626 * # Z samples).
3627 *
3628 * F: Color samples (up to 8x, must be <= coverage samples):
3629 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3630 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3631 *
3632 * Can be anything between coverage and color samples:
3633 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3634 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3635 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3636 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3637 * # All are currently set the same as coverage samples.
3638 *
3639 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3640 * flag for undefined color samples. A shader-based resolve must handle unknowns
3641 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3642 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3643 * useful. The CB resolve always drops unknowns.
3644 *
3645 * Sensible AA configurations:
3646 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3647 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3648 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3649 * EQAA 8s 8z 8f = 8x MSAA
3650 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3651 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3652 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3653 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3654 * EQAA 4s 4z 4f = 4x MSAA
3655 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3656 * EQAA 2s 2z 2f = 2x MSAA
3657 */
3658 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3659 coverage_samples = sctx->framebuffer.nr_samples;
3660 color_samples = sctx->framebuffer.nr_color_samples;
3661
3662 if (sctx->framebuffer.state.zsbuf) {
3663 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3664 z_samples = MAX2(1, z_samples);
3665 } else {
3666 z_samples = coverage_samples;
3667 }
3668 } else if (sctx->smoothing_enabled) {
3669 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3670 } else {
3671 coverage_samples = color_samples = z_samples = 1;
3672 }
3673
3674 /* Required by OpenGL line rasterization.
3675 *
3676 * TODO: We should also enable perpendicular endcaps for AA lines,
3677 * but that requires implementing line stippling in the pixel
3678 * shader. SC can only do line stippling with axis-aligned
3679 * endcaps.
3680 */
3681 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3682 unsigned sc_aa_config = 0;
3683
3684 if (coverage_samples > 1) {
3685 /* distance from the pixel center, indexed by log2(nr_samples) */
3686 static unsigned max_dist[] = {
3687 0, /* unused */
3688 4, /* 2x MSAA */
3689 6, /* 4x MSAA */
3690 7, /* 8x MSAA */
3691 8, /* 16x MSAA */
3692 };
3693 unsigned log_samples = util_logbase2(coverage_samples);
3694 unsigned log_z_samples = util_logbase2(z_samples);
3695 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3696 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3697
3698 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3699 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3700 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3701 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3702
3703 if (sctx->framebuffer.nr_samples > 1) {
3704 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3705 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3706 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3707 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3708 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3709 } else if (sctx->smoothing_enabled) {
3710 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3711 }
3712 }
3713
3714 unsigned initial_cdw = cs->current.cdw;
3715
3716 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3717 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3718 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3719 sc_aa_config);
3720 /* R_028804_DB_EQAA */
3721 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3722 db_eqaa);
3723 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3724 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3725 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3726
3727 if (initial_cdw != cs->current.cdw) {
3728 sctx->context_roll = true;
3729
3730 /* GFX9: Flush DFSM when the AA mode changes. */
3731 if (sctx->screen->dfsm_allowed) {
3732 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3733 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3734 }
3735 }
3736 }
3737
3738 void si_update_ps_iter_samples(struct si_context *sctx)
3739 {
3740 if (sctx->framebuffer.nr_samples > 1)
3741 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3742 if (sctx->screen->dpbb_allowed)
3743 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3744 }
3745
3746 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3747 {
3748 struct si_context *sctx = (struct si_context *)ctx;
3749
3750 /* The hardware can only do sample shading with 2^n samples. */
3751 min_samples = util_next_power_of_two(min_samples);
3752
3753 if (sctx->ps_iter_samples == min_samples)
3754 return;
3755
3756 sctx->ps_iter_samples = min_samples;
3757 sctx->do_update_shaders = true;
3758
3759 si_update_ps_iter_samples(sctx);
3760 }
3761
3762 /*
3763 * Samplers
3764 */
3765
3766 /**
3767 * Build the sampler view descriptor for a buffer texture.
3768 * @param state 256-bit descriptor; only the high 128 bits are filled in
3769 */
3770 void
3771 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3772 enum pipe_format format,
3773 unsigned offset, unsigned size,
3774 uint32_t *state)
3775 {
3776 const struct util_format_description *desc;
3777 unsigned stride;
3778 unsigned num_records;
3779
3780 desc = util_format_description(format);
3781 stride = desc->block.bits / 8;
3782
3783 num_records = size / stride;
3784 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3785
3786 /* The NUM_RECORDS field has a different meaning depending on the chip,
3787 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3788 *
3789 * GFX6-7,10:
3790 * - If STRIDE == 0, it's in byte units.
3791 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3792 *
3793 * GFX8:
3794 * - For SMEM and STRIDE == 0, it's in byte units.
3795 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3796 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3797 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3798 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3799 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3800 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3801 * That way the same descriptor can be used by both SMEM and VMEM.
3802 *
3803 * GFX9:
3804 * - For SMEM and STRIDE == 0, it's in byte units.
3805 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3806 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3807 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3808 */
3809 if (screen->info.chip_class == GFX9 && HAVE_LLVM < 0x0800)
3810 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3811 * from STRIDE to bytes. This works around it by setting
3812 * NUM_RECORDS to at least the size of one element, so that
3813 * the first element is readable when IDXEN == 0.
3814 */
3815 num_records = num_records ? MAX2(num_records, stride) : 0;
3816 else if (screen->info.chip_class == GFX8)
3817 num_records *= stride;
3818
3819 state[4] = 0;
3820 state[5] = S_008F04_STRIDE(stride);
3821 state[6] = num_records;
3822 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3823 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3824 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3825 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3826
3827 if (screen->info.chip_class >= GFX10) {
3828 const struct gfx10_format *fmt = &gfx10_format_table[format];
3829
3830 /* OOB_SELECT chooses the out-of-bounds check:
3831 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3832 * - 1: index >= NUM_RECORDS
3833 * - 2: NUM_RECORDS == 0
3834 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3835 * else: swizzle_address >= NUM_RECORDS
3836 */
3837 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3838 S_008F0C_OOB_SELECT(0) |
3839 S_008F0C_RESOURCE_LEVEL(1);
3840 } else {
3841 int first_non_void;
3842 unsigned num_format, data_format;
3843
3844 first_non_void = util_format_get_first_non_void_channel(format);
3845 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3846 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3847
3848 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3849 S_008F0C_DATA_FORMAT(data_format);
3850 }
3851 }
3852
3853 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3854 {
3855 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3856
3857 if (swizzle[3] == PIPE_SWIZZLE_X) {
3858 /* For the pre-defined border color values (white, opaque
3859 * black, transparent black), the only thing that matters is
3860 * that the alpha channel winds up in the correct place
3861 * (because the RGB channels are all the same) so either of
3862 * these enumerations will work.
3863 */
3864 if (swizzle[2] == PIPE_SWIZZLE_Y)
3865 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3866 else
3867 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3868 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3869 if (swizzle[1] == PIPE_SWIZZLE_Y)
3870 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3871 else
3872 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3873 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3874 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3875 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3876 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3877 }
3878
3879 return bc_swizzle;
3880 }
3881
3882 /**
3883 * Build the sampler view descriptor for a texture.
3884 */
3885 static void
3886 gfx10_make_texture_descriptor(struct si_screen *screen,
3887 struct si_texture *tex,
3888 bool sampler,
3889 enum pipe_texture_target target,
3890 enum pipe_format pipe_format,
3891 const unsigned char state_swizzle[4],
3892 unsigned first_level, unsigned last_level,
3893 unsigned first_layer, unsigned last_layer,
3894 unsigned width, unsigned height, unsigned depth,
3895 uint32_t *state,
3896 uint32_t *fmask_state)
3897 {
3898 struct pipe_resource *res = &tex->buffer.b.b;
3899 const struct util_format_description *desc;
3900 unsigned img_format;
3901 unsigned char swizzle[4];
3902 unsigned type;
3903 uint64_t va;
3904
3905 desc = util_format_description(pipe_format);
3906 img_format = gfx10_format_table[pipe_format].img_format;
3907
3908 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3909 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3910 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3911 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3912 bool is_stencil = false;
3913
3914 switch (pipe_format) {
3915 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3916 case PIPE_FORMAT_X32_S8X24_UINT:
3917 case PIPE_FORMAT_X8Z24_UNORM:
3918 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3919 is_stencil = true;
3920 break;
3921 case PIPE_FORMAT_X24S8_UINT:
3922 /*
3923 * X24S8 is implemented as an 8_8_8_8 data format, to
3924 * fix texture gathers. This affects at least
3925 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3926 */
3927 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3928 is_stencil = true;
3929 break;
3930 default:
3931 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3932 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3933 }
3934
3935 if (tex->upgraded_depth && !is_stencil) {
3936 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3937 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3938 }
3939 } else {
3940 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3941 }
3942
3943 if (!sampler &&
3944 (res->target == PIPE_TEXTURE_CUBE ||
3945 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3946 /* For the purpose of shader images, treat cube maps as 2D
3947 * arrays.
3948 */
3949 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3950 } else {
3951 type = si_tex_dim(screen, tex, target, res->nr_samples);
3952 }
3953
3954 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3955 height = 1;
3956 depth = res->array_size;
3957 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3958 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3959 if (sampler || res->target != PIPE_TEXTURE_3D)
3960 depth = res->array_size;
3961 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3962 depth = res->array_size / 6;
3963
3964 state[0] = 0;
3965 state[1] = S_00A004_FORMAT(img_format) |
3966 S_00A004_WIDTH_LO(width - 1);
3967 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3968 S_00A008_HEIGHT(height - 1) |
3969 S_00A008_RESOURCE_LEVEL(1);
3970 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3971 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3972 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3973 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3974 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3975 0 : first_level) |
3976 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3977 util_logbase2(res->nr_samples) :
3978 last_level) |
3979 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3980 S_00A00C_TYPE(type);
3981 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3982 * to know the total number of layers.
3983 */
3984 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3985 ? depth - 1 : last_layer) |
3986 S_00A010_BASE_ARRAY(first_layer);
3987 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3988 S_00A014_MAX_MIP(res->nr_samples > 1 ?
3989 util_logbase2(res->nr_samples) :
3990 tex->buffer.b.b.last_level) |
3991 S_00A014_PERF_MOD(4);
3992 state[6] = 0;
3993 state[7] = 0;
3994
3995 if (tex->dcc_offset) {
3996 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
3997 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
3998 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
3999 }
4000
4001 /* Initialize the sampler view for FMASK. */
4002 if (tex->fmask_offset) {
4003 uint32_t format;
4004
4005 va = tex->buffer.gpu_address + tex->fmask_offset;
4006
4007 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4008 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4009 case FMASK(2,1):
4010 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4011 break;
4012 case FMASK(2,2):
4013 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4014 break;
4015 case FMASK(4,1):
4016 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4017 break;
4018 case FMASK(4,2):
4019 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4020 break;
4021 case FMASK(4,4):
4022 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4023 break;
4024 case FMASK(8,1):
4025 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4026 break;
4027 case FMASK(8,2):
4028 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4029 break;
4030 case FMASK(8,4):
4031 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4032 break;
4033 case FMASK(8,8):
4034 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4035 break;
4036 case FMASK(16,1):
4037 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4038 break;
4039 case FMASK(16,2):
4040 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4041 break;
4042 case FMASK(16,4):
4043 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4044 break;
4045 case FMASK(16,8):
4046 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4047 break;
4048 default:
4049 unreachable("invalid nr_samples");
4050 }
4051 #undef FMASK
4052 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4053 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4054 S_00A004_FORMAT(format) |
4055 S_00A004_WIDTH_LO(width - 1);
4056 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4057 S_00A008_HEIGHT(height - 1) |
4058 S_00A008_RESOURCE_LEVEL(1);
4059 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4060 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4061 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4062 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4063 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4064 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4065 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4066 S_00A010_BASE_ARRAY(first_layer);
4067 fmask_state[5] = 0;
4068 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4069 fmask_state[7] = 0;
4070 }
4071 }
4072
4073 /**
4074 * Build the sampler view descriptor for a texture (SI-GFX9).
4075 */
4076 static void
4077 si_make_texture_descriptor(struct si_screen *screen,
4078 struct si_texture *tex,
4079 bool sampler,
4080 enum pipe_texture_target target,
4081 enum pipe_format pipe_format,
4082 const unsigned char state_swizzle[4],
4083 unsigned first_level, unsigned last_level,
4084 unsigned first_layer, unsigned last_layer,
4085 unsigned width, unsigned height, unsigned depth,
4086 uint32_t *state,
4087 uint32_t *fmask_state)
4088 {
4089 struct pipe_resource *res = &tex->buffer.b.b;
4090 const struct util_format_description *desc;
4091 unsigned char swizzle[4];
4092 int first_non_void;
4093 unsigned num_format, data_format, type, num_samples;
4094 uint64_t va;
4095
4096 desc = util_format_description(pipe_format);
4097
4098 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4099 MAX2(1, res->nr_samples) :
4100 MAX2(1, res->nr_storage_samples);
4101
4102 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4103 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4104 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4105 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4106
4107 switch (pipe_format) {
4108 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4109 case PIPE_FORMAT_X32_S8X24_UINT:
4110 case PIPE_FORMAT_X8Z24_UNORM:
4111 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4112 break;
4113 case PIPE_FORMAT_X24S8_UINT:
4114 /*
4115 * X24S8 is implemented as an 8_8_8_8 data format, to
4116 * fix texture gathers. This affects at least
4117 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4118 */
4119 if (screen->info.chip_class <= GFX8)
4120 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4121 else
4122 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4123 break;
4124 default:
4125 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4126 }
4127 } else {
4128 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4129 }
4130
4131 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4132
4133 switch (pipe_format) {
4134 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4135 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4136 break;
4137 default:
4138 if (first_non_void < 0) {
4139 if (util_format_is_compressed(pipe_format)) {
4140 switch (pipe_format) {
4141 case PIPE_FORMAT_DXT1_SRGB:
4142 case PIPE_FORMAT_DXT1_SRGBA:
4143 case PIPE_FORMAT_DXT3_SRGBA:
4144 case PIPE_FORMAT_DXT5_SRGBA:
4145 case PIPE_FORMAT_BPTC_SRGBA:
4146 case PIPE_FORMAT_ETC2_SRGB8:
4147 case PIPE_FORMAT_ETC2_SRGB8A1:
4148 case PIPE_FORMAT_ETC2_SRGBA8:
4149 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4150 break;
4151 case PIPE_FORMAT_RGTC1_SNORM:
4152 case PIPE_FORMAT_LATC1_SNORM:
4153 case PIPE_FORMAT_RGTC2_SNORM:
4154 case PIPE_FORMAT_LATC2_SNORM:
4155 case PIPE_FORMAT_ETC2_R11_SNORM:
4156 case PIPE_FORMAT_ETC2_RG11_SNORM:
4157 /* implies float, so use SNORM/UNORM to determine
4158 whether data is signed or not */
4159 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4160 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4161 break;
4162 default:
4163 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4164 break;
4165 }
4166 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4167 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4168 } else {
4169 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4170 }
4171 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4172 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4173 } else {
4174 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4175
4176 switch (desc->channel[first_non_void].type) {
4177 case UTIL_FORMAT_TYPE_FLOAT:
4178 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4179 break;
4180 case UTIL_FORMAT_TYPE_SIGNED:
4181 if (desc->channel[first_non_void].normalized)
4182 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4183 else if (desc->channel[first_non_void].pure_integer)
4184 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4185 else
4186 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4187 break;
4188 case UTIL_FORMAT_TYPE_UNSIGNED:
4189 if (desc->channel[first_non_void].normalized)
4190 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4191 else if (desc->channel[first_non_void].pure_integer)
4192 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4193 else
4194 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4195 }
4196 }
4197 }
4198
4199 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4200 if (data_format == ~0) {
4201 data_format = 0;
4202 }
4203
4204 /* S8 with Z32 HTILE needs a special format. */
4205 if (screen->info.chip_class == GFX9 &&
4206 pipe_format == PIPE_FORMAT_S8_UINT &&
4207 tex->tc_compatible_htile)
4208 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4209
4210 if (!sampler &&
4211 (res->target == PIPE_TEXTURE_CUBE ||
4212 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4213 (screen->info.chip_class <= GFX8 &&
4214 res->target == PIPE_TEXTURE_3D))) {
4215 /* For the purpose of shader images, treat cube maps and 3D
4216 * textures as 2D arrays. For 3D textures, the address
4217 * calculations for mipmaps are different, so we rely on the
4218 * caller to effectively disable mipmaps.
4219 */
4220 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4221
4222 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4223 } else {
4224 type = si_tex_dim(screen, tex, target, num_samples);
4225 }
4226
4227 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4228 height = 1;
4229 depth = res->array_size;
4230 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4231 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4232 if (sampler || res->target != PIPE_TEXTURE_3D)
4233 depth = res->array_size;
4234 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4235 depth = res->array_size / 6;
4236
4237 state[0] = 0;
4238 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4239 S_008F14_NUM_FORMAT(num_format));
4240 state[2] = (S_008F18_WIDTH(width - 1) |
4241 S_008F18_HEIGHT(height - 1) |
4242 S_008F18_PERF_MOD(4));
4243 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4244 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4245 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4246 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4247 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4248 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4249 util_logbase2(num_samples) :
4250 last_level) |
4251 S_008F1C_TYPE(type));
4252 state[4] = 0;
4253 state[5] = S_008F24_BASE_ARRAY(first_layer);
4254 state[6] = 0;
4255 state[7] = 0;
4256
4257 if (screen->info.chip_class == GFX9) {
4258 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4259
4260 /* Depth is the the last accessible layer on Gfx9.
4261 * The hw doesn't need to know the total number of layers.
4262 */
4263 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4264 state[4] |= S_008F20_DEPTH(depth - 1);
4265 else
4266 state[4] |= S_008F20_DEPTH(last_layer);
4267
4268 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4269 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4270 util_logbase2(num_samples) :
4271 tex->buffer.b.b.last_level);
4272 } else {
4273 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4274 state[4] |= S_008F20_DEPTH(depth - 1);
4275 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4276 }
4277
4278 if (tex->dcc_offset) {
4279 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4280 } else {
4281 /* The last dword is unused by hw. The shader uses it to clear
4282 * bits in the first dword of sampler state.
4283 */
4284 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4285 if (first_level == last_level)
4286 state[7] = C_008F30_MAX_ANISO_RATIO;
4287 else
4288 state[7] = 0xffffffff;
4289 }
4290 }
4291
4292 /* Initialize the sampler view for FMASK. */
4293 if (tex->fmask_offset) {
4294 uint32_t data_format, num_format;
4295
4296 va = tex->buffer.gpu_address + tex->fmask_offset;
4297
4298 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4299 if (screen->info.chip_class == GFX9) {
4300 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4301 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4302 case FMASK(2,1):
4303 num_format = V_008F14_IMG_FMASK_8_2_1;
4304 break;
4305 case FMASK(2,2):
4306 num_format = V_008F14_IMG_FMASK_8_2_2;
4307 break;
4308 case FMASK(4,1):
4309 num_format = V_008F14_IMG_FMASK_8_4_1;
4310 break;
4311 case FMASK(4,2):
4312 num_format = V_008F14_IMG_FMASK_8_4_2;
4313 break;
4314 case FMASK(4,4):
4315 num_format = V_008F14_IMG_FMASK_8_4_4;
4316 break;
4317 case FMASK(8,1):
4318 num_format = V_008F14_IMG_FMASK_8_8_1;
4319 break;
4320 case FMASK(8,2):
4321 num_format = V_008F14_IMG_FMASK_16_8_2;
4322 break;
4323 case FMASK(8,4):
4324 num_format = V_008F14_IMG_FMASK_32_8_4;
4325 break;
4326 case FMASK(8,8):
4327 num_format = V_008F14_IMG_FMASK_32_8_8;
4328 break;
4329 case FMASK(16,1):
4330 num_format = V_008F14_IMG_FMASK_16_16_1;
4331 break;
4332 case FMASK(16,2):
4333 num_format = V_008F14_IMG_FMASK_32_16_2;
4334 break;
4335 case FMASK(16,4):
4336 num_format = V_008F14_IMG_FMASK_64_16_4;
4337 break;
4338 case FMASK(16,8):
4339 num_format = V_008F14_IMG_FMASK_64_16_8;
4340 break;
4341 default:
4342 unreachable("invalid nr_samples");
4343 }
4344 } else {
4345 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4346 case FMASK(2,1):
4347 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4348 break;
4349 case FMASK(2,2):
4350 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4351 break;
4352 case FMASK(4,1):
4353 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4354 break;
4355 case FMASK(4,2):
4356 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4357 break;
4358 case FMASK(4,4):
4359 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4360 break;
4361 case FMASK(8,1):
4362 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4363 break;
4364 case FMASK(8,2):
4365 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4366 break;
4367 case FMASK(8,4):
4368 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4369 break;
4370 case FMASK(8,8):
4371 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4372 break;
4373 case FMASK(16,1):
4374 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4375 break;
4376 case FMASK(16,2):
4377 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4378 break;
4379 case FMASK(16,4):
4380 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4381 break;
4382 case FMASK(16,8):
4383 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4384 break;
4385 default:
4386 unreachable("invalid nr_samples");
4387 }
4388 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4389 }
4390 #undef FMASK
4391
4392 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4393 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4394 S_008F14_DATA_FORMAT(data_format) |
4395 S_008F14_NUM_FORMAT(num_format);
4396 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4397 S_008F18_HEIGHT(height - 1);
4398 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4399 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4400 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4401 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4402 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4403 fmask_state[4] = 0;
4404 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4405 fmask_state[6] = 0;
4406 fmask_state[7] = 0;
4407
4408 if (screen->info.chip_class == GFX9) {
4409 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4410 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4411 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4412 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4413 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4414 } else {
4415 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4416 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4417 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4418 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4419 }
4420 }
4421 }
4422
4423 /**
4424 * Create a sampler view.
4425 *
4426 * @param ctx context
4427 * @param texture texture
4428 * @param state sampler view template
4429 * @param width0 width0 override (for compressed textures as int)
4430 * @param height0 height0 override (for compressed textures as int)
4431 * @param force_level set the base address to the level (for compressed textures)
4432 */
4433 struct pipe_sampler_view *
4434 si_create_sampler_view_custom(struct pipe_context *ctx,
4435 struct pipe_resource *texture,
4436 const struct pipe_sampler_view *state,
4437 unsigned width0, unsigned height0,
4438 unsigned force_level)
4439 {
4440 struct si_context *sctx = (struct si_context*)ctx;
4441 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4442 struct si_texture *tex = (struct si_texture*)texture;
4443 unsigned base_level, first_level, last_level;
4444 unsigned char state_swizzle[4];
4445 unsigned height, depth, width;
4446 unsigned last_layer = state->u.tex.last_layer;
4447 enum pipe_format pipe_format;
4448 const struct legacy_surf_level *surflevel;
4449
4450 if (!view)
4451 return NULL;
4452
4453 /* initialize base object */
4454 view->base = *state;
4455 view->base.texture = NULL;
4456 view->base.reference.count = 1;
4457 view->base.context = ctx;
4458
4459 assert(texture);
4460 pipe_resource_reference(&view->base.texture, texture);
4461
4462 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4463 state->format == PIPE_FORMAT_S8X24_UINT ||
4464 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4465 state->format == PIPE_FORMAT_S8_UINT)
4466 view->is_stencil_sampler = true;
4467
4468 /* Buffer resource. */
4469 if (texture->target == PIPE_BUFFER) {
4470 si_make_buffer_descriptor(sctx->screen,
4471 si_resource(texture),
4472 state->format,
4473 state->u.buf.offset,
4474 state->u.buf.size,
4475 view->state);
4476 return &view->base;
4477 }
4478
4479 state_swizzle[0] = state->swizzle_r;
4480 state_swizzle[1] = state->swizzle_g;
4481 state_swizzle[2] = state->swizzle_b;
4482 state_swizzle[3] = state->swizzle_a;
4483
4484 base_level = 0;
4485 first_level = state->u.tex.first_level;
4486 last_level = state->u.tex.last_level;
4487 width = width0;
4488 height = height0;
4489 depth = texture->depth0;
4490
4491 if (sctx->chip_class <= GFX8 && force_level) {
4492 assert(force_level == first_level &&
4493 force_level == last_level);
4494 base_level = force_level;
4495 first_level = 0;
4496 last_level = 0;
4497 width = u_minify(width, force_level);
4498 height = u_minify(height, force_level);
4499 depth = u_minify(depth, force_level);
4500 }
4501
4502 /* This is not needed if state trackers set last_layer correctly. */
4503 if (state->target == PIPE_TEXTURE_1D ||
4504 state->target == PIPE_TEXTURE_2D ||
4505 state->target == PIPE_TEXTURE_RECT ||
4506 state->target == PIPE_TEXTURE_CUBE)
4507 last_layer = state->u.tex.first_layer;
4508
4509 /* Texturing with separate depth and stencil. */
4510 pipe_format = state->format;
4511
4512 /* Depth/stencil texturing sometimes needs separate texture. */
4513 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4514 if (!tex->flushed_depth_texture &&
4515 !si_init_flushed_depth_texture(ctx, texture)) {
4516 pipe_resource_reference(&view->base.texture, NULL);
4517 FREE(view);
4518 return NULL;
4519 }
4520
4521 assert(tex->flushed_depth_texture);
4522
4523 /* Override format for the case where the flushed texture
4524 * contains only Z or only S.
4525 */
4526 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4527 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4528
4529 tex = tex->flushed_depth_texture;
4530 }
4531
4532 surflevel = tex->surface.u.legacy.level;
4533
4534 if (tex->db_compatible) {
4535 if (!view->is_stencil_sampler)
4536 pipe_format = tex->db_render_format;
4537
4538 switch (pipe_format) {
4539 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4540 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4541 break;
4542 case PIPE_FORMAT_X8Z24_UNORM:
4543 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4544 /* Z24 is always stored like this for DB
4545 * compatibility.
4546 */
4547 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4548 break;
4549 case PIPE_FORMAT_X24S8_UINT:
4550 case PIPE_FORMAT_S8X24_UINT:
4551 case PIPE_FORMAT_X32_S8X24_UINT:
4552 pipe_format = PIPE_FORMAT_S8_UINT;
4553 surflevel = tex->surface.u.legacy.stencil_level;
4554 break;
4555 default:;
4556 }
4557 }
4558
4559 view->dcc_incompatible =
4560 vi_dcc_formats_are_incompatible(texture,
4561 state->u.tex.first_level,
4562 state->format);
4563
4564 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4565 state->target, pipe_format, state_swizzle,
4566 first_level, last_level,
4567 state->u.tex.first_layer, last_layer,
4568 width, height, depth,
4569 view->state, view->fmask_state);
4570
4571 const struct util_format_description *desc = util_format_description(pipe_format);
4572 view->is_integer = false;
4573
4574 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4575 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4576 continue;
4577
4578 /* Whether the number format is {U,S}{SCALED,INT} */
4579 view->is_integer =
4580 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4581 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4582 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4583 break;
4584 }
4585
4586 view->base_level_info = &surflevel[base_level];
4587 view->base_level = base_level;
4588 view->block_width = util_format_get_blockwidth(pipe_format);
4589 return &view->base;
4590 }
4591
4592 static struct pipe_sampler_view *
4593 si_create_sampler_view(struct pipe_context *ctx,
4594 struct pipe_resource *texture,
4595 const struct pipe_sampler_view *state)
4596 {
4597 return si_create_sampler_view_custom(ctx, texture, state,
4598 texture ? texture->width0 : 0,
4599 texture ? texture->height0 : 0, 0);
4600 }
4601
4602 static void si_sampler_view_destroy(struct pipe_context *ctx,
4603 struct pipe_sampler_view *state)
4604 {
4605 struct si_sampler_view *view = (struct si_sampler_view *)state;
4606
4607 pipe_resource_reference(&state->texture, NULL);
4608 FREE(view);
4609 }
4610
4611 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4612 {
4613 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4614 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4615 (linear_filter &&
4616 (wrap == PIPE_TEX_WRAP_CLAMP ||
4617 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4618 }
4619
4620 static uint32_t si_translate_border_color(struct si_context *sctx,
4621 const struct pipe_sampler_state *state,
4622 const union pipe_color_union *color,
4623 bool is_integer)
4624 {
4625 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4626 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4627
4628 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4629 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4630 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4631 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4632
4633 #define simple_border_types(elt) \
4634 do { \
4635 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4636 color->elt[2] == 0 && color->elt[3] == 0) \
4637 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4638 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4639 color->elt[2] == 0 && color->elt[3] == 1) \
4640 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4641 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4642 color->elt[2] == 1 && color->elt[3] == 1) \
4643 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4644 } while (false)
4645
4646 if (is_integer)
4647 simple_border_types(ui);
4648 else
4649 simple_border_types(f);
4650
4651 #undef simple_border_types
4652
4653 int i;
4654
4655 /* Check if the border has been uploaded already. */
4656 for (i = 0; i < sctx->border_color_count; i++)
4657 if (memcmp(&sctx->border_color_table[i], color,
4658 sizeof(*color)) == 0)
4659 break;
4660
4661 if (i >= SI_MAX_BORDER_COLORS) {
4662 /* Getting 4096 unique border colors is very unlikely. */
4663 fprintf(stderr, "radeonsi: The border color table is full. "
4664 "Any new border colors will be just black. "
4665 "Please file a bug.\n");
4666 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4667 }
4668
4669 if (i == sctx->border_color_count) {
4670 /* Upload a new border color. */
4671 memcpy(&sctx->border_color_table[i], color,
4672 sizeof(*color));
4673 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4674 color, sizeof(*color));
4675 sctx->border_color_count++;
4676 }
4677
4678 return S_008F3C_BORDER_COLOR_PTR(i) |
4679 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4680 }
4681
4682 static inline int S_FIXED(float value, unsigned frac_bits)
4683 {
4684 return value * (1 << frac_bits);
4685 }
4686
4687 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4688 {
4689 if (filter == PIPE_TEX_FILTER_LINEAR)
4690 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4691 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4692 else
4693 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4694 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4695 }
4696
4697 static inline unsigned si_tex_aniso_filter(unsigned filter)
4698 {
4699 if (filter < 2)
4700 return 0;
4701 if (filter < 4)
4702 return 1;
4703 if (filter < 8)
4704 return 2;
4705 if (filter < 16)
4706 return 3;
4707 return 4;
4708 }
4709
4710 static void *si_create_sampler_state(struct pipe_context *ctx,
4711 const struct pipe_sampler_state *state)
4712 {
4713 struct si_context *sctx = (struct si_context *)ctx;
4714 struct si_screen *sscreen = sctx->screen;
4715 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4716 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4717 : state->max_anisotropy;
4718 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4719 union pipe_color_union clamped_border_color;
4720
4721 if (!rstate) {
4722 return NULL;
4723 }
4724
4725 #ifndef NDEBUG
4726 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4727 #endif
4728 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4729 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4730 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4731 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4732 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4733 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4734 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4735 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4736 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4737 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4738 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4739 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4740 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4741 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4742 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4743 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4744 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4745 S_008F38_MIP_POINT_PRECLAMP(0));
4746 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4747
4748 if (sscreen->info.chip_class >= GFX10) {
4749 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4750 } else {
4751 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4752 S_008F38_FILTER_PREC_FIX(1) |
4753 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4754 }
4755
4756 /* Create sampler resource for integer textures. */
4757 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4758 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4759
4760 /* Create sampler resource for upgraded depth textures. */
4761 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4762
4763 for (unsigned i = 0; i < 4; ++i) {
4764 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4765 * when the border color is 1.0. */
4766 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4767 }
4768
4769 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4770 if (sscreen->info.chip_class <= GFX9)
4771 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4772 } else {
4773 rstate->upgraded_depth_val[3] =
4774 si_translate_border_color(sctx, state, &clamped_border_color, false);
4775 }
4776
4777 return rstate;
4778 }
4779
4780 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4781 {
4782 struct si_context *sctx = (struct si_context *)ctx;
4783
4784 if (sctx->sample_mask == (uint16_t)sample_mask)
4785 return;
4786
4787 sctx->sample_mask = sample_mask;
4788 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4789 }
4790
4791 static void si_emit_sample_mask(struct si_context *sctx)
4792 {
4793 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4794 unsigned mask = sctx->sample_mask;
4795
4796 /* Needed for line and polygon smoothing as well as for the Polaris
4797 * small primitive filter. We expect the state tracker to take care of
4798 * this for us.
4799 */
4800 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4801 (mask & 1 && sctx->blitter->running));
4802
4803 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4804 radeon_emit(cs, mask | (mask << 16));
4805 radeon_emit(cs, mask | (mask << 16));
4806 }
4807
4808 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4809 {
4810 #ifndef NDEBUG
4811 struct si_sampler_state *s = state;
4812
4813 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4814 s->magic = 0;
4815 #endif
4816 free(state);
4817 }
4818
4819 /*
4820 * Vertex elements & buffers
4821 */
4822
4823 struct si_fast_udiv_info32
4824 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4825 {
4826 struct util_fast_udiv_info info =
4827 util_compute_fast_udiv_info(D, num_bits, 32);
4828
4829 struct si_fast_udiv_info32 result = {
4830 info.multiplier,
4831 info.pre_shift,
4832 info.post_shift,
4833 info.increment,
4834 };
4835 return result;
4836 }
4837
4838 static void *si_create_vertex_elements(struct pipe_context *ctx,
4839 unsigned count,
4840 const struct pipe_vertex_element *elements)
4841 {
4842 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4843 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4844 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4845 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4846 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4847 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4848 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4849 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4850 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4851 int i;
4852
4853 assert(count <= SI_MAX_ATTRIBS);
4854 if (!v)
4855 return NULL;
4856
4857 v->count = count;
4858 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4859
4860 for (i = 0; i < count; ++i) {
4861 const struct util_format_description *desc;
4862 const struct util_format_channel_description *channel;
4863 int first_non_void;
4864 unsigned vbo_index = elements[i].vertex_buffer_index;
4865
4866 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4867 FREE(v);
4868 return NULL;
4869 }
4870
4871 unsigned instance_divisor = elements[i].instance_divisor;
4872 if (instance_divisor) {
4873 v->uses_instance_divisors = true;
4874
4875 if (instance_divisor == 1) {
4876 v->instance_divisor_is_one |= 1u << i;
4877 } else {
4878 v->instance_divisor_is_fetched |= 1u << i;
4879 divisor_factors[i] =
4880 si_compute_fast_udiv_info32(instance_divisor, 32);
4881 }
4882 }
4883
4884 if (!used[vbo_index]) {
4885 v->first_vb_use_mask |= 1 << i;
4886 used[vbo_index] = true;
4887 }
4888
4889 desc = util_format_description(elements[i].src_format);
4890 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4891 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4892
4893 v->format_size[i] = desc->block.bits / 8;
4894 v->src_offset[i] = elements[i].src_offset;
4895 v->vertex_buffer_index[i] = vbo_index;
4896
4897 bool always_fix = false;
4898 union si_vs_fix_fetch fix_fetch;
4899 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4900
4901 fix_fetch.bits = 0;
4902 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4903
4904 if (channel) {
4905 switch (channel->type) {
4906 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4907 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4908 case UTIL_FORMAT_TYPE_SIGNED: {
4909 if (channel->pure_integer)
4910 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4911 else if (channel->normalized)
4912 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4913 else
4914 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4915 break;
4916 }
4917 case UTIL_FORMAT_TYPE_UNSIGNED: {
4918 if (channel->pure_integer)
4919 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4920 else if (channel->normalized)
4921 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4922 else
4923 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4924 break;
4925 }
4926 default: unreachable("bad format type");
4927 }
4928 } else {
4929 switch (elements[i].src_format) {
4930 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4931 default: unreachable("bad other format");
4932 }
4933 }
4934
4935 if (desc->channel[0].size == 10) {
4936 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4937 log_hw_load_size = 2;
4938
4939 /* The hardware always treats the 2-bit alpha channel as
4940 * unsigned, so a shader workaround is needed. The affected
4941 * chips are GFX8 and older except Stoney (GFX8.1).
4942 */
4943 always_fix = sscreen->info.chip_class <= GFX8 &&
4944 sscreen->info.family != CHIP_STONEY &&
4945 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4946 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4947 fix_fetch.u.log_size = 3; /* special encoding */
4948 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4949 log_hw_load_size = 2;
4950 } else {
4951 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4952 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4953
4954 /* Always fix up:
4955 * - doubles (multiple loads + truncate to float)
4956 * - 32-bit requiring a conversion
4957 */
4958 always_fix =
4959 (fix_fetch.u.log_size == 3) ||
4960 (fix_fetch.u.log_size == 2 &&
4961 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4962 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4963 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4964
4965 /* Also fixup 8_8_8 and 16_16_16. */
4966 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4967 always_fix = true;
4968 log_hw_load_size = fix_fetch.u.log_size;
4969 }
4970 }
4971
4972 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4973 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4974 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4975 fix_fetch.u.reverse = 1;
4976 }
4977
4978 /* Force the workaround for unaligned access here already if the
4979 * offset relative to the vertex buffer base is unaligned.
4980 *
4981 * There is a theoretical case in which this is too conservative:
4982 * if the vertex buffer's offset is also unaligned in just the
4983 * right way, we end up with an aligned address after all.
4984 * However, this case should be extremely rare in practice (it
4985 * won't happen in well-behaved applications), and taking it
4986 * into account would complicate the fast path (where everything
4987 * is nicely aligned).
4988 */
4989 bool check_alignment =
4990 log_hw_load_size >= 1 &&
4991 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
4992 bool opencode = sscreen->options.vs_fetch_always_opencode;
4993
4994 if (check_alignment &&
4995 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4996 opencode = true;
4997
4998 if (always_fix || check_alignment || opencode)
4999 v->fix_fetch[i] = fix_fetch.bits;
5000
5001 if (opencode)
5002 v->fix_fetch_opencode |= 1 << i;
5003 if (opencode || always_fix)
5004 v->fix_fetch_always |= 1 << i;
5005
5006 if (check_alignment && !opencode) {
5007 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5008
5009 v->fix_fetch_unaligned |= 1 << i;
5010 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5011 v->vb_alignment_check_mask |= 1 << vbo_index;
5012 }
5013
5014 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5015 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5016 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5017 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5018
5019 if (sscreen->info.chip_class >= GFX10) {
5020 const struct gfx10_format *fmt =
5021 &gfx10_format_table[elements[i].src_format];
5022 assert(fmt->img_format != 0 && fmt->img_format < 128);
5023 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5024 S_008F0C_RESOURCE_LEVEL(1);
5025 } else {
5026 unsigned data_format, num_format;
5027 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5028 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5029 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5030 S_008F0C_DATA_FORMAT(data_format);
5031 }
5032 }
5033
5034 if (v->instance_divisor_is_fetched) {
5035 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5036
5037 v->instance_divisor_factor_buffer =
5038 (struct si_resource*)
5039 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5040 num_divisors * sizeof(divisor_factors[0]));
5041 if (!v->instance_divisor_factor_buffer) {
5042 FREE(v);
5043 return NULL;
5044 }
5045 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5046 NULL, PIPE_TRANSFER_WRITE);
5047 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5048 }
5049 return v;
5050 }
5051
5052 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5053 {
5054 struct si_context *sctx = (struct si_context *)ctx;
5055 struct si_vertex_elements *old = sctx->vertex_elements;
5056 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5057
5058 sctx->vertex_elements = v;
5059 sctx->vertex_buffers_dirty = true;
5060
5061 if (v &&
5062 (!old ||
5063 old->count != v->count ||
5064 old->uses_instance_divisors != v->uses_instance_divisors ||
5065 /* we don't check which divisors changed */
5066 v->uses_instance_divisors ||
5067 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5068 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5069 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5070 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5071 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5072 * functions of fix_fetch and the src_offset alignment.
5073 * If they change and fix_fetch doesn't, it must be due to different
5074 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5075 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5076 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5077 sctx->do_update_shaders = true;
5078
5079 if (v && v->instance_divisor_is_fetched) {
5080 struct pipe_constant_buffer cb;
5081
5082 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5083 cb.user_buffer = NULL;
5084 cb.buffer_offset = 0;
5085 cb.buffer_size = 0xffffffff;
5086 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5087 }
5088 }
5089
5090 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5091 {
5092 struct si_context *sctx = (struct si_context *)ctx;
5093 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5094
5095 if (sctx->vertex_elements == state)
5096 sctx->vertex_elements = NULL;
5097 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5098 FREE(state);
5099 }
5100
5101 static void si_set_vertex_buffers(struct pipe_context *ctx,
5102 unsigned start_slot, unsigned count,
5103 const struct pipe_vertex_buffer *buffers)
5104 {
5105 struct si_context *sctx = (struct si_context *)ctx;
5106 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5107 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5108 uint32_t unaligned = orig_unaligned;
5109 int i;
5110
5111 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5112
5113 if (buffers) {
5114 for (i = 0; i < count; i++) {
5115 const struct pipe_vertex_buffer *src = buffers + i;
5116 struct pipe_vertex_buffer *dsti = dst + i;
5117 struct pipe_resource *buf = src->buffer.resource;
5118
5119 pipe_resource_reference(&dsti->buffer.resource, buf);
5120 dsti->buffer_offset = src->buffer_offset;
5121 dsti->stride = src->stride;
5122 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5123 unaligned |= 1 << (start_slot + i);
5124 else
5125 unaligned &= ~(1 << (start_slot + i));
5126
5127 si_context_add_resource_size(sctx, buf);
5128 if (buf)
5129 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5130 }
5131 } else {
5132 for (i = 0; i < count; i++) {
5133 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5134 }
5135 unaligned &= ~u_bit_consecutive(start_slot, count);
5136 }
5137 sctx->vertex_buffers_dirty = true;
5138 sctx->vertex_buffer_unaligned = unaligned;
5139
5140 /* Check whether alignment may have changed in a way that requires
5141 * shader changes. This check is conservative: a vertex buffer can only
5142 * trigger a shader change if the misalignment amount changes (e.g.
5143 * from byte-aligned to short-aligned), but we only keep track of
5144 * whether buffers are at least dword-aligned, since that should always
5145 * be the case in well-behaved applications anyway.
5146 */
5147 if (sctx->vertex_elements &&
5148 (sctx->vertex_elements->vb_alignment_check_mask &
5149 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5150 sctx->do_update_shaders = true;
5151 }
5152
5153 /*
5154 * Misc
5155 */
5156
5157 static void si_set_tess_state(struct pipe_context *ctx,
5158 const float default_outer_level[4],
5159 const float default_inner_level[2])
5160 {
5161 struct si_context *sctx = (struct si_context *)ctx;
5162 struct pipe_constant_buffer cb;
5163 float array[8];
5164
5165 memcpy(array, default_outer_level, sizeof(float) * 4);
5166 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5167
5168 cb.buffer = NULL;
5169 cb.user_buffer = NULL;
5170 cb.buffer_size = sizeof(array);
5171
5172 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5173 (void*)array, sizeof(array),
5174 &cb.buffer_offset);
5175
5176 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5177 pipe_resource_reference(&cb.buffer, NULL);
5178 }
5179
5180 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5181 {
5182 struct si_context *sctx = (struct si_context *)ctx;
5183
5184 si_update_fb_dirtiness_after_rendering(sctx);
5185
5186 /* Multisample surfaces are flushed in si_decompress_textures. */
5187 if (sctx->framebuffer.uncompressed_cb_mask) {
5188 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5189 sctx->framebuffer.CB_has_shader_readable_metadata,
5190 sctx->framebuffer.all_DCC_pipe_aligned);
5191 }
5192 }
5193
5194 /* This only ensures coherency for shader image/buffer stores. */
5195 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5196 {
5197 struct si_context *sctx = (struct si_context *)ctx;
5198
5199 if (!(flags & ~PIPE_BARRIER_UPDATE))
5200 return;
5201
5202 /* Subsequent commands must wait for all shader invocations to
5203 * complete. */
5204 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5205 SI_CONTEXT_CS_PARTIAL_FLUSH;
5206
5207 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5208 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5209 SI_CONTEXT_INV_VCACHE;
5210
5211 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5212 PIPE_BARRIER_SHADER_BUFFER |
5213 PIPE_BARRIER_TEXTURE |
5214 PIPE_BARRIER_IMAGE |
5215 PIPE_BARRIER_STREAMOUT_BUFFER |
5216 PIPE_BARRIER_GLOBAL_BUFFER)) {
5217 /* As far as I can tell, L1 contents are written back to L2
5218 * automatically at end of shader, but the contents of other
5219 * L1 caches might still be stale. */
5220 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5221 }
5222
5223 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5224 /* Indices are read through TC L2 since GFX8.
5225 * L1 isn't used.
5226 */
5227 if (sctx->screen->info.chip_class <= GFX7)
5228 sctx->flags |= SI_CONTEXT_WB_L2;
5229 }
5230
5231 /* MSAA color, any depth and any stencil are flushed in
5232 * si_decompress_textures when needed.
5233 */
5234 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5235 sctx->framebuffer.uncompressed_cb_mask) {
5236 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5237
5238 if (sctx->chip_class <= GFX8)
5239 sctx->flags |= SI_CONTEXT_WB_L2;
5240 }
5241
5242 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5243 if (sctx->screen->info.chip_class <= GFX8 &&
5244 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5245 sctx->flags |= SI_CONTEXT_WB_L2;
5246 }
5247
5248 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5249 {
5250 struct pipe_blend_state blend;
5251
5252 memset(&blend, 0, sizeof(blend));
5253 blend.independent_blend_enable = true;
5254 blend.rt[0].colormask = 0xf;
5255 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5256 }
5257
5258 static void si_init_config(struct si_context *sctx);
5259
5260 void si_init_state_compute_functions(struct si_context *sctx)
5261 {
5262 sctx->b.create_sampler_state = si_create_sampler_state;
5263 sctx->b.delete_sampler_state = si_delete_sampler_state;
5264 sctx->b.create_sampler_view = si_create_sampler_view;
5265 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5266 sctx->b.memory_barrier = si_memory_barrier;
5267 }
5268
5269 void si_init_state_functions(struct si_context *sctx)
5270 {
5271 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5272 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5273 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5274 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5275 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5276 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5277 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5278 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5279 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5280 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5281 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5282
5283 sctx->b.create_blend_state = si_create_blend_state;
5284 sctx->b.bind_blend_state = si_bind_blend_state;
5285 sctx->b.delete_blend_state = si_delete_blend_state;
5286 sctx->b.set_blend_color = si_set_blend_color;
5287
5288 sctx->b.create_rasterizer_state = si_create_rs_state;
5289 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5290 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5291
5292 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5293 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5294 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5295
5296 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5297 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5298 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5299 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5300 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5301
5302 sctx->b.set_clip_state = si_set_clip_state;
5303 sctx->b.set_stencil_ref = si_set_stencil_ref;
5304
5305 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5306
5307 sctx->b.set_sample_mask = si_set_sample_mask;
5308
5309 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5310 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5311 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5312 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5313
5314 sctx->b.texture_barrier = si_texture_barrier;
5315 sctx->b.set_min_samples = si_set_min_samples;
5316 sctx->b.set_tess_state = si_set_tess_state;
5317
5318 sctx->b.set_active_query_state = si_set_active_query_state;
5319
5320 si_init_config(sctx);
5321 }
5322
5323 void si_init_screen_state_functions(struct si_screen *sscreen)
5324 {
5325 sscreen->b.is_format_supported = si_is_format_supported;
5326
5327 if (sscreen->info.chip_class >= GFX10) {
5328 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5329 } else {
5330 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5331 }
5332 }
5333
5334 static void si_set_grbm_gfx_index(struct si_context *sctx,
5335 struct si_pm4_state *pm4, unsigned value)
5336 {
5337 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5338 R_00802C_GRBM_GFX_INDEX;
5339 si_pm4_set_reg(pm4, reg, value);
5340 }
5341
5342 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5343 struct si_pm4_state *pm4, unsigned se)
5344 {
5345 assert(se == ~0 || se < sctx->screen->info.max_se);
5346 si_set_grbm_gfx_index(sctx, pm4,
5347 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5348 S_030800_SE_INDEX(se)) |
5349 S_030800_SH_BROADCAST_WRITES(1) |
5350 S_030800_INSTANCE_BROADCAST_WRITES(1));
5351 }
5352
5353 static void
5354 si_write_harvested_raster_configs(struct si_context *sctx,
5355 struct si_pm4_state *pm4,
5356 unsigned raster_config,
5357 unsigned raster_config_1)
5358 {
5359 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5360 unsigned raster_config_se[4];
5361 unsigned se;
5362
5363 ac_get_harvested_configs(&sctx->screen->info,
5364 raster_config,
5365 &raster_config_1,
5366 raster_config_se);
5367
5368 for (se = 0; se < num_se; se++) {
5369 si_set_grbm_gfx_index_se(sctx, pm4, se);
5370 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5371 }
5372 si_set_grbm_gfx_index(sctx, pm4, ~0);
5373
5374 if (sctx->chip_class >= GFX7) {
5375 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5376 }
5377 }
5378
5379 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5380 {
5381 struct si_screen *sscreen = sctx->screen;
5382 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5383 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5384 unsigned raster_config = sscreen->pa_sc_raster_config;
5385 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5386
5387 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5388 /* Always use the default config when all backends are enabled
5389 * (or when we failed to determine the enabled backends).
5390 */
5391 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5392 raster_config);
5393 if (sctx->chip_class >= GFX7)
5394 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5395 raster_config_1);
5396 } else {
5397 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5398 }
5399 }
5400
5401 static void si_init_config(struct si_context *sctx)
5402 {
5403 struct si_screen *sscreen = sctx->screen;
5404 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5405 bool has_clear_state = sscreen->has_clear_state;
5406 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5407
5408 if (!pm4)
5409 return;
5410
5411 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5412 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5413 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5414 si_pm4_cmd_end(pm4, false);
5415
5416 if (has_clear_state) {
5417 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5418 si_pm4_cmd_add(pm4, 0);
5419 si_pm4_cmd_end(pm4, false);
5420 }
5421
5422 if (sctx->chip_class <= GFX8)
5423 si_set_raster_config(sctx, pm4);
5424
5425 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5426 if (!has_clear_state)
5427 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5428
5429 /* FIXME calculate these values somehow ??? */
5430 if (sctx->chip_class <= GFX8) {
5431 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5432 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5433 }
5434
5435 if (!has_clear_state) {
5436 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5437 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5438 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5439 }
5440
5441 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5442 if (!has_clear_state)
5443 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5444 if (sctx->chip_class < GFX7)
5445 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5446 S_008A14_CLIP_VTX_REORDER_ENA(1));
5447
5448 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5449 * I don't know why. Deduced by trial and error.
5450 */
5451 if (sctx->chip_class <= GFX7 || !has_clear_state) {
5452 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5453 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5454 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5455 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5456 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5457 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5458 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5459 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5460 }
5461
5462 if (!has_clear_state) {
5463 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5464 S_028230_ER_TRI(0xA) |
5465 S_028230_ER_POINT(0xA) |
5466 S_028230_ER_RECT(0xA) |
5467 /* Required by DX10_DIAMOND_TEST_ENA: */
5468 S_028230_ER_LINE_LR(0x1A) |
5469 S_028230_ER_LINE_RL(0x26) |
5470 S_028230_ER_LINE_TB(0xA) |
5471 S_028230_ER_LINE_BT(0xA));
5472 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5473 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5474 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5475 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5476 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5477 }
5478
5479 if (sctx->chip_class >= GFX10) {
5480 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5481 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5482 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5483 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5484 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5485 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5486 } else if (sctx->chip_class == GFX9) {
5487 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5488 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5489 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5490 } else {
5491 /* These registers, when written, also overwrite the CLEAR_STATE
5492 * context, so we can't rely on CLEAR_STATE setting them.
5493 * It would be an issue if there was another UMD changing them.
5494 */
5495 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5496 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5497 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5498 }
5499
5500 if (sctx->chip_class >= GFX7) {
5501 if (sctx->chip_class >= GFX10) {
5502 /* Logical CUs 16 - 31 */
5503 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5504 S_00B404_CU_EN(0xffff));
5505 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5506 S_00B104_CU_EN(0xffff));
5507 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5508 S_00B004_CU_EN(0xffff));
5509 }
5510
5511 if (sctx->chip_class >= GFX9) {
5512 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5513 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5514 } else {
5515 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5516 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5517 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5518 S_00B41C_WAVE_LIMIT(0x3F));
5519 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5520 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5521
5522 /* If this is 0, Bonaire can hang even if GS isn't being used.
5523 * Other chips are unaffected. These are suboptimal values,
5524 * but we don't use on-chip GS.
5525 */
5526 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5527 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5528 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5529 }
5530
5531 /* Compute LATE_ALLOC_VS.LIMIT. */
5532 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5533 unsigned late_alloc_limit; /* The limit is per SH. */
5534
5535 if (sctx->family == CHIP_KABINI) {
5536 late_alloc_limit = 0; /* Potential hang on Kabini. */
5537 } else if (num_cu_per_sh <= 4) {
5538 /* Too few available compute units per SH. Disallowing
5539 * VS to run on one CU could hurt us more than late VS
5540 * allocation would help.
5541 *
5542 * 2 is the highest safe number that allows us to keep
5543 * all CUs enabled.
5544 */
5545 late_alloc_limit = 2;
5546 } else {
5547 /* This is a good initial value, allowing 1 late_alloc
5548 * wave per SIMD on num_cu - 2.
5549 */
5550 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5551 }
5552
5553 unsigned cu_mask_vs = 0xffff;
5554 unsigned cu_mask_gs = 0xffff;
5555
5556 if (late_alloc_limit > 2) {
5557 if (sctx->chip_class >= GFX10) {
5558 /* CU2 & CU3 disabled because of the dual CU design */
5559 cu_mask_vs = 0xfff3;
5560 cu_mask_gs = 0xfff3; /* NGG only */
5561 } else {
5562 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5563 }
5564 }
5565
5566 /* VS can't execute on one CU if the limit is > 2. */
5567 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5568 S_00B118_CU_EN(cu_mask_vs) |
5569 S_00B118_WAVE_LIMIT(0x3F));
5570 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5571 S_00B11C_LIMIT(late_alloc_limit));
5572
5573 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5574 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5575
5576 if (sctx->chip_class >= GFX10) {
5577 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5578 S_00B204_CU_EN(0xffff) |
5579 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit));
5580 }
5581
5582 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5583 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5584 }
5585
5586 if (sctx->chip_class >= GFX10) {
5587 /* Break up a pixel wave if it contains deallocs for more than
5588 * half the parameter cache.
5589 *
5590 * To avoid a deadlock where pixel waves aren't launched
5591 * because they're waiting for more pixels while the frontend
5592 * is stuck waiting for PC space, the maximum allowed value is
5593 * the size of the PC minus the largest possible allocation for
5594 * a single primitive shader subgroup.
5595 */
5596 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5597 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5598 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5599 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5600 sscreen->info.pa_sc_tile_steering_override);
5601
5602 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5603 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5604 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5605 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5606 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5607 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5608 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5609 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
5610
5611 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5612 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5613 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5614 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5615 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5616 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5617 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5618 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
5619 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5620 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5621
5622 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5623 S_00B0C0_SOFT_GROUPING_EN(1) |
5624 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5625 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5626
5627 }
5628
5629 if (sctx->chip_class >= GFX8) {
5630 unsigned vgt_tess_distribution;
5631
5632 vgt_tess_distribution =
5633 S_028B50_ACCUM_ISOLINE(32) |
5634 S_028B50_ACCUM_TRI(11) |
5635 S_028B50_ACCUM_QUAD(11) |
5636 S_028B50_DONUT_SPLIT(16);
5637
5638 /* Testing with Unigine Heaven extreme tesselation yielded best results
5639 * with TRAP_SPLIT = 3.
5640 */
5641 if (sctx->family == CHIP_FIJI ||
5642 sctx->family >= CHIP_POLARIS10)
5643 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5644
5645 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5646 } else if (!has_clear_state) {
5647 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5648 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5649 }
5650
5651 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5652 if (sctx->chip_class >= GFX7) {
5653 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5654 S_028084_ADDRESS(border_color_va >> 40));
5655 }
5656 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5657 RADEON_PRIO_BORDER_COLORS);
5658
5659 if (sctx->chip_class >= GFX9) {
5660 unsigned num_se = sscreen->info.max_se;
5661 unsigned pc_lines = 0;
5662 unsigned max_alloc_count = 0;
5663
5664 switch (sctx->family) {
5665 case CHIP_VEGA10:
5666 case CHIP_VEGA12:
5667 case CHIP_VEGA20:
5668 pc_lines = 2048;
5669 break;
5670 case CHIP_RAVEN:
5671 case CHIP_RAVEN2:
5672 case CHIP_NAVI10:
5673 case CHIP_NAVI12:
5674 pc_lines = 1024;
5675 break;
5676 case CHIP_NAVI14:
5677 pc_lines = 512;
5678 break;
5679 default:
5680 assert(0);
5681 }
5682
5683 if (sctx->chip_class >= GFX10) {
5684 max_alloc_count = pc_lines / 3;
5685 } else {
5686 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
5687 }
5688
5689 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5690 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
5691 S_028C48_MAX_PRIM_PER_BATCH(1023));
5692 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5693 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5694 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5695 }
5696
5697 si_pm4_upload_indirect_buffer(sctx, pm4);
5698 sctx->init_config = pm4;
5699 }