radeonsi: make sure that blend state != NULL and remove all NULL checking
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit &
86 blend->cb_target_mask;
87 unsigned i;
88
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
92 *
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
94 */
95 if (blend->dual_src_blend &&
96 sctx->ps_shader.cso &&
97 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
98 cb_target_mask = 0;
99
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
102 */
103 if (sctx->screen->dpbb_allowed &&
104 sctx->last_cb_target_mask != cb_target_mask) {
105 sctx->last_cb_target_mask = cb_target_mask;
106
107 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
108 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
109 }
110
111 unsigned initial_cdw = cs->current.cdw;
112 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
113 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
114
115 if (sctx->chip_class >= GFX8) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
119 */
120 bool oc_disable = blend->dcc_msaa_corruption_4bit & cb_target_mask &&
121 sctx->framebuffer.nr_samples >= 2;
122 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
123
124 radeon_opt_set_context_reg(
125 sctx, R_028424_CB_DCC_CONTROL,
126 SI_TRACKED_CB_DCC_CONTROL,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
131 }
132
133 /* RB+ register settings. */
134 if (sctx->screen->rbplus_allowed) {
135 unsigned spi_shader_col_format =
136 sctx->ps_shader.cso ?
137 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
138 unsigned sx_ps_downconvert = 0;
139 unsigned sx_blend_opt_epsilon = 0;
140 unsigned sx_blend_opt_control = 0;
141
142 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
143 struct si_surface *surf =
144 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
145 unsigned format, swap, spi_format, colormask;
146 bool has_alpha, has_rgb;
147
148 if (!surf) {
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
152 * enable RB+.
153 */
154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
155 continue;
156 }
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 break;
253
254 case V_028C70_COLOR_2_10_10_10:
255 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
256 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
257 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
258 }
259 break;
260 }
261 }
262
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
265 */
266 if (!sx_ps_downconvert)
267 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
268
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
271 SI_TRACKED_SX_PS_DOWNCONVERT,
272 sx_ps_downconvert, sx_blend_opt_epsilon,
273 sx_blend_opt_control);
274 }
275 if (initial_cdw != cs->current.cdw)
276 sctx->context_roll = true;
277 }
278
279 /*
280 * Blender functions
281 */
282
283 static uint32_t si_translate_blend_function(int blend_func)
284 {
285 switch (blend_func) {
286 case PIPE_BLEND_ADD:
287 return V_028780_COMB_DST_PLUS_SRC;
288 case PIPE_BLEND_SUBTRACT:
289 return V_028780_COMB_SRC_MINUS_DST;
290 case PIPE_BLEND_REVERSE_SUBTRACT:
291 return V_028780_COMB_DST_MINUS_SRC;
292 case PIPE_BLEND_MIN:
293 return V_028780_COMB_MIN_DST_SRC;
294 case PIPE_BLEND_MAX:
295 return V_028780_COMB_MAX_DST_SRC;
296 default:
297 PRINT_ERR("Unknown blend function %d\n", blend_func);
298 assert(0);
299 break;
300 }
301 return 0;
302 }
303
304 static uint32_t si_translate_blend_factor(int blend_fact)
305 {
306 switch (blend_fact) {
307 case PIPE_BLENDFACTOR_ONE:
308 return V_028780_BLEND_ONE;
309 case PIPE_BLENDFACTOR_SRC_COLOR:
310 return V_028780_BLEND_SRC_COLOR;
311 case PIPE_BLENDFACTOR_SRC_ALPHA:
312 return V_028780_BLEND_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_DST_ALPHA:
314 return V_028780_BLEND_DST_ALPHA;
315 case PIPE_BLENDFACTOR_DST_COLOR:
316 return V_028780_BLEND_DST_COLOR;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE;
319 case PIPE_BLENDFACTOR_CONST_COLOR:
320 return V_028780_BLEND_CONSTANT_COLOR;
321 case PIPE_BLENDFACTOR_CONST_ALPHA:
322 return V_028780_BLEND_CONSTANT_ALPHA;
323 case PIPE_BLENDFACTOR_ZERO:
324 return V_028780_BLEND_ZERO;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
337 case PIPE_BLENDFACTOR_SRC1_COLOR:
338 return V_028780_BLEND_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA:
340 return V_028780_BLEND_SRC1_ALPHA;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
342 return V_028780_BLEND_INV_SRC1_COLOR;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
344 return V_028780_BLEND_INV_SRC1_ALPHA;
345 default:
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
347 assert(0);
348 break;
349 }
350 return 0;
351 }
352
353 static uint32_t si_translate_blend_opt_function(int blend_func)
354 {
355 switch (blend_func) {
356 case PIPE_BLEND_ADD:
357 return V_028760_OPT_COMB_ADD;
358 case PIPE_BLEND_SUBTRACT:
359 return V_028760_OPT_COMB_SUBTRACT;
360 case PIPE_BLEND_REVERSE_SUBTRACT:
361 return V_028760_OPT_COMB_REVSUBTRACT;
362 case PIPE_BLEND_MIN:
363 return V_028760_OPT_COMB_MIN;
364 case PIPE_BLEND_MAX:
365 return V_028760_OPT_COMB_MAX;
366 default:
367 return V_028760_OPT_COMB_BLEND_DISABLED;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
372 {
373 switch (blend_fact) {
374 case PIPE_BLENDFACTOR_ZERO:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
376 case PIPE_BLENDFACTOR_ONE:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
378 case PIPE_BLENDFACTOR_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
382 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
384 case PIPE_BLENDFACTOR_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
389 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
391 default:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
393 }
394 }
395
396 static void si_blend_check_commutativity(struct si_screen *sscreen,
397 struct si_state_blend *blend,
398 enum pipe_blend_func func,
399 enum pipe_blendfactor src,
400 enum pipe_blendfactor dst,
401 unsigned chanmask)
402 {
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed =
405 (1u << PIPE_BLENDFACTOR_ONE) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_ZERO) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
420
421 if (dst == PIPE_BLENDFACTOR_ONE &&
422 (src_allowed & (1u << src))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
425 * rounding.
426 *
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
430 * setting.
431 */
432 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
433 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
434 blend->commutative_4bit |= chanmask;
435 }
436 }
437
438 /**
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
441 */
442 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
443 unsigned *dst_factor, unsigned expected_dst,
444 unsigned replacement_src)
445 {
446 if (*src_factor == expected_dst &&
447 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
448 *src_factor = PIPE_BLENDFACTOR_ZERO;
449 *dst_factor = replacement_src;
450
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func == PIPE_BLEND_SUBTRACT)
453 *func = PIPE_BLEND_REVERSE_SUBTRACT;
454 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
455 *func = PIPE_BLEND_SUBTRACT;
456 }
457 }
458
459 static bool si_blend_factor_uses_dst(unsigned factor)
460 {
461 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
462 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
464 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
465 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
466 }
467
468 static void *si_create_blend_state_mode(struct pipe_context *ctx,
469 const struct pipe_blend_state *state,
470 unsigned mode)
471 {
472 struct si_context *sctx = (struct si_context*)ctx;
473 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
474 struct si_pm4_state *pm4 = &blend->pm4;
475 uint32_t sx_mrt_blend_opt[8] = {0};
476 uint32_t color_control = 0;
477 bool logicop_enable = state->logicop_enable &&
478 state->logicop_func != PIPE_LOGICOP_COPY;
479
480 if (!blend)
481 return NULL;
482
483 blend->alpha_to_coverage = state->alpha_to_coverage;
484 blend->alpha_to_one = state->alpha_to_one;
485 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
486 blend->logicop_enable = logicop_enable;
487
488 if (logicop_enable) {
489 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
490 } else {
491 color_control |= S_028808_ROP3(0xcc);
492 }
493
494 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
501
502 if (state->alpha_to_coverage)
503 blend->need_src_alpha_4bit |= 0xf;
504
505 blend->cb_target_mask = 0;
506 blend->cb_target_enabled_4bit = 0;
507
508 for (int i = 0; i < 8; i++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j = state->independent_blend_enable ? i : 0;
511
512 unsigned eqRGB = state->rt[j].rgb_func;
513 unsigned srcRGB = state->rt[j].rgb_src_factor;
514 unsigned dstRGB = state->rt[j].rgb_dst_factor;
515 unsigned eqA = state->rt[j].alpha_func;
516 unsigned srcA = state->rt[j].alpha_src_factor;
517 unsigned dstA = state->rt[j].alpha_dst_factor;
518
519 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
520 unsigned blend_cntl = 0;
521
522 sx_mrt_blend_opt[i] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
525
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i >= 1 && blend->dual_src_blend) {
528 /* Vulkan does this for dual source blending. */
529 if (i == 1)
530 blend_cntl |= S_028780_ENABLE(1);
531
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
538 */
539 if (blend->dual_src_blend &&
540 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
541 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544 continue;
545 }
546
547 /* cb_render_state will disable unused ones */
548 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
549 if (state->rt[j].colormask)
550 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
551
552 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
553 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
554 continue;
555 }
556
557 si_blend_check_commutativity(sctx->screen, blend,
558 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
559 si_blend_check_commutativity(sctx->screen, blend,
560 eqA, srcA, dstA, 0x8 << (4 * i));
561
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
564 *
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
567 */
568 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
569 PIPE_BLENDFACTOR_DST_COLOR,
570 PIPE_BLENDFACTOR_SRC_COLOR);
571 si_blend_remove_dst(&eqA, &srcA, &dstA,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_ALPHA,
576 PIPE_BLENDFACTOR_SRC_ALPHA);
577
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
580 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
581 srcA_opt = si_translate_blend_opt_factor(srcA, true);
582 dstA_opt = si_translate_blend_opt_factor(dstA, true);
583
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB))
586 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
587 if (si_blend_factor_uses_dst(srcA))
588 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
589
590 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
591 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
592 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
594 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
595
596 /* Set the final value. */
597 sx_mrt_blend_opt[i] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt) |
602 S_028760_ALPHA_DST_OPT(dstA_opt) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
604
605 /* Set blend state. */
606 blend_cntl |= S_028780_ENABLE(1);
607 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
608 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
609 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
610
611 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
612 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
614 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
615 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
616 }
617 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
618
619 blend->blend_enable_4bit |= 0xfu << (i * 4);
620
621 if (sctx->family <= CHIP_NAVI14)
622 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (sctx->family <= CHIP_NAVI14 && logicop_enable)
635 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
636
637 if (blend->cb_target_mask) {
638 color_control |= S_028808_MODE(mode);
639 } else {
640 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
641 }
642
643 if (sctx->screen->rbplus_allowed) {
644 /* Disable RB+ blend optimizations for dual source blending.
645 * Vulkan does this.
646 */
647 if (blend->dual_src_blend) {
648 for (int i = 0; i < 8; i++) {
649 sx_mrt_blend_opt[i] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
652 }
653 }
654
655 for (int i = 0; i < 8; i++)
656 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
657 sx_mrt_blend_opt[i]);
658
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend->dual_src_blend || logicop_enable ||
661 mode == V_028808_CB_RESOLVE)
662 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
663 }
664
665 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
666 return blend;
667 }
668
669 static void *si_create_blend_state(struct pipe_context *ctx,
670 const struct pipe_blend_state *state)
671 {
672 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
673 }
674
675 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
676 {
677 struct si_context *sctx = (struct si_context *)ctx;
678 struct si_state_blend *old_blend = sctx->queued.named.blend;
679 struct si_state_blend *blend = (struct si_state_blend *)state;
680
681 if (!blend)
682 blend = (struct si_state_blend *)sctx->noop_blend;
683
684 si_pm4_bind_state(sctx, blend, blend);
685
686 if (old_blend->cb_target_mask != blend->cb_target_mask ||
687 old_blend->dual_src_blend != blend->dual_src_blend ||
688 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
689 sctx->framebuffer.nr_samples >= 2 &&
690 sctx->screen->dcc_msaa_allowed))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
692
693 if (old_blend->cb_target_mask != blend->cb_target_mask ||
694 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
695 old_blend->alpha_to_one != blend->alpha_to_one ||
696 old_blend->dual_src_blend != blend->dual_src_blend ||
697 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
698 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
699 sctx->do_update_shaders = true;
700
701 if (sctx->screen->dpbb_allowed &&
702 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
709 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
710 old_blend->commutative_4bit != blend->commutative_4bit ||
711 old_blend->logicop_enable != blend->logicop_enable)))
712 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
713 }
714
715 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
719 }
720
721 static void si_set_blend_color(struct pipe_context *ctx,
722 const struct pipe_blend_color *state)
723 {
724 struct si_context *sctx = (struct si_context *)ctx;
725 static const struct pipe_blend_color zeros;
726
727 sctx->blend_color.state = *state;
728 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
729 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
730 }
731
732 static void si_emit_blend_color(struct si_context *sctx)
733 {
734 struct radeon_cmdbuf *cs = sctx->gfx_cs;
735
736 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
737 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
738 }
739
740 /*
741 * Clipping
742 */
743
744 static void si_set_clip_state(struct pipe_context *ctx,
745 const struct pipe_clip_state *state)
746 {
747 struct si_context *sctx = (struct si_context *)ctx;
748 struct pipe_constant_buffer cb;
749 static const struct pipe_clip_state zeros;
750
751 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
752 return;
753
754 sctx->clip_state.state = *state;
755 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
756 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
757
758 cb.buffer = NULL;
759 cb.user_buffer = state->ucp;
760 cb.buffer_offset = 0;
761 cb.buffer_size = 4*4*8;
762 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
763 pipe_resource_reference(&cb.buffer, NULL);
764 }
765
766 static void si_emit_clip_state(struct si_context *sctx)
767 {
768 struct radeon_cmdbuf *cs = sctx->gfx_cs;
769
770 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
771 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
772 }
773
774 static void si_emit_clip_regs(struct si_context *sctx)
775 {
776 struct si_shader *vs = si_get_vs_state(sctx);
777 struct si_shader_selector *vs_sel = vs->selector;
778 struct tgsi_shader_info *info = &vs_sel->info;
779 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
780 unsigned window_space =
781 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
782 unsigned clipdist_mask = vs_sel->clipdist_mask;
783 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
784 unsigned culldist_mask = vs_sel->culldist_mask;
785 unsigned total_mask;
786
787 if (vs->key.opt.clip_disable) {
788 assert(!info->culldist_writemask);
789 clipdist_mask = 0;
790 culldist_mask = 0;
791 }
792 total_mask = clipdist_mask | culldist_mask;
793
794 /* Clip distances on points have no effect, so need to be implemented
795 * as cull distances. This applies for the clipvertex case as well.
796 *
797 * Setting this for primitives other than points should have no adverse
798 * effects.
799 */
800 clipdist_mask &= rs->clip_plane_enable;
801 culldist_mask |= clipdist_mask;
802
803 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
804 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
805 SI_TRACKED_PA_CL_VS_OUT_CNTL,
806 vs_sel->pa_cl_vs_out_cntl |
807 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
808 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
809 clipdist_mask | (culldist_mask << 8));
810 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
811 SI_TRACKED_PA_CL_CLIP_CNTL,
812 rs->pa_cl_clip_cntl |
813 ucp_mask |
814 S_028810_CLIP_DISABLE(window_space));
815
816 if (initial_cdw != sctx->gfx_cs->current.cdw)
817 sctx->context_roll = true;
818 }
819
820 /*
821 * inferred state between framebuffer and rasterizer
822 */
823 static void si_update_poly_offset_state(struct si_context *sctx)
824 {
825 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
826
827 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
828 si_pm4_bind_state(sctx, poly_offset, NULL);
829 return;
830 }
831
832 /* Use the user format, not db_render_format, so that the polygon
833 * offset behaves as expected by applications.
834 */
835 switch (sctx->framebuffer.state.zsbuf->texture->format) {
836 case PIPE_FORMAT_Z16_UNORM:
837 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
838 break;
839 default: /* 24-bit */
840 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
841 break;
842 case PIPE_FORMAT_Z32_FLOAT:
843 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
844 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
845 break;
846 }
847 }
848
849 /*
850 * Rasterizer
851 */
852
853 static uint32_t si_translate_fill(uint32_t func)
854 {
855 switch(func) {
856 case PIPE_POLYGON_MODE_FILL:
857 return V_028814_X_DRAW_TRIANGLES;
858 case PIPE_POLYGON_MODE_LINE:
859 return V_028814_X_DRAW_LINES;
860 case PIPE_POLYGON_MODE_POINT:
861 return V_028814_X_DRAW_POINTS;
862 default:
863 assert(0);
864 return V_028814_X_DRAW_POINTS;
865 }
866 }
867
868 static void *si_create_rs_state(struct pipe_context *ctx,
869 const struct pipe_rasterizer_state *state)
870 {
871 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
872 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
873 struct si_pm4_state *pm4 = &rs->pm4;
874 unsigned tmp, i;
875 float psize_min, psize_max;
876
877 if (!rs) {
878 return NULL;
879 }
880
881 if (!state->front_ccw) {
882 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
883 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
884 } else {
885 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
886 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
887 }
888 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
889 rs->provoking_vertex_first = state->flatshade_first;
890 rs->scissor_enable = state->scissor;
891 rs->clip_halfz = state->clip_halfz;
892 rs->two_side = state->light_twoside;
893 rs->multisample_enable = state->multisample;
894 rs->force_persample_interp = state->force_persample_interp;
895 rs->clip_plane_enable = state->clip_plane_enable;
896 rs->half_pixel_center = state->half_pixel_center;
897 rs->line_stipple_enable = state->line_stipple_enable;
898 rs->poly_stipple_enable = state->poly_stipple_enable;
899 rs->line_smooth = state->line_smooth;
900 rs->line_width = state->line_width;
901 rs->poly_smooth = state->poly_smooth;
902 rs->uses_poly_offset = state->offset_point || state->offset_line ||
903 state->offset_tri;
904 rs->clamp_fragment_color = state->clamp_fragment_color;
905 rs->clamp_vertex_color = state->clamp_vertex_color;
906 rs->flatshade = state->flatshade;
907 rs->flatshade_first = state->flatshade_first;
908 rs->sprite_coord_enable = state->sprite_coord_enable;
909 rs->rasterizer_discard = state->rasterizer_discard;
910 rs->pa_sc_line_stipple = state->line_stipple_enable ?
911 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
912 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
913 rs->pa_cl_clip_cntl =
914 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
915 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
916 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
917 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
918 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
919
920 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
921 S_0286D4_FLAT_SHADE_ENA(1) |
922 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
923 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
924 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
925 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
926 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
927 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
928
929 /* point size 12.4 fixed point */
930 tmp = (unsigned)(state->point_size * 8.0);
931 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
932
933 if (state->point_size_per_vertex) {
934 psize_min = util_get_min_point_size(state);
935 psize_max = SI_MAX_POINT_SIZE;
936 } else {
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min = state->point_size;
939 psize_max = state->point_size;
940 }
941 rs->max_point_size = psize_max;
942
943 /* Divide by two, because 0.5 = 1 pixel. */
944 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
945 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
946 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
947
948 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
949 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
950 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
951 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
952 S_028A48_MSAA_ENABLE(state->multisample ||
953 state->poly_smooth ||
954 state->line_smooth) |
955 S_028A48_VPORT_SCISSOR_ENABLE(1) |
956 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
957
958 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
959 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
960 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
961 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
962 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
963 S_028814_FACE(!state->front_ccw) |
964 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
965 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
966 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
967 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
968 state->fill_back != PIPE_POLYGON_MODE_FILL) |
969 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
970 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
971
972 if (!rs->uses_poly_offset)
973 return rs;
974
975 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
976 if (!rs->pm4_poly_offset) {
977 FREE(rs);
978 return NULL;
979 }
980
981 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
982 for (i = 0; i < 3; i++) {
983 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
984 float offset_units = state->offset_units;
985 float offset_scale = state->offset_scale * 16.0f;
986 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
987
988 if (!state->offset_units_unscaled) {
989 switch (i) {
990 case 0: /* 16-bit zbuffer */
991 offset_units *= 4.0f;
992 pa_su_poly_offset_db_fmt_cntl =
993 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
994 break;
995 case 1: /* 24-bit zbuffer */
996 offset_units *= 2.0f;
997 pa_su_poly_offset_db_fmt_cntl =
998 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
999 break;
1000 case 2: /* 32-bit zbuffer */
1001 offset_units *= 1.0f;
1002 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1003 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1004 break;
1005 }
1006 }
1007
1008 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1009 fui(offset_scale));
1010 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1011 fui(offset_units));
1012 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1013 fui(offset_scale));
1014 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1015 fui(offset_units));
1016 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1017 pa_su_poly_offset_db_fmt_cntl);
1018 }
1019
1020 return rs;
1021 }
1022
1023 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1024 {
1025 struct si_context *sctx = (struct si_context *)ctx;
1026 struct si_state_rasterizer *old_rs =
1027 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1028 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1029
1030 if (!state)
1031 return;
1032
1033 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1034 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1035
1036 /* Update the small primitive filter workaround if necessary. */
1037 if (sctx->screen->has_msaa_sample_loc_bug &&
1038 sctx->framebuffer.nr_samples > 1)
1039 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1040 }
1041
1042 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1043 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1044
1045 si_pm4_bind_state(sctx, rasterizer, rs);
1046 si_update_poly_offset_state(sctx);
1047
1048 if (!old_rs ||
1049 old_rs->scissor_enable != rs->scissor_enable)
1050 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1051
1052 if (!old_rs ||
1053 old_rs->line_width != rs->line_width ||
1054 old_rs->max_point_size != rs->max_point_size ||
1055 old_rs->half_pixel_center != rs->half_pixel_center)
1056 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1057
1058 if (!old_rs ||
1059 old_rs->clip_halfz != rs->clip_halfz)
1060 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1061
1062 if (!old_rs ||
1063 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1064 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1065 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1066
1067 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1068 rs->line_stipple_enable;
1069
1070 if (!old_rs ||
1071 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1072 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1073 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1074 old_rs->flatshade != rs->flatshade ||
1075 old_rs->two_side != rs->two_side ||
1076 old_rs->multisample_enable != rs->multisample_enable ||
1077 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1078 old_rs->poly_smooth != rs->poly_smooth ||
1079 old_rs->line_smooth != rs->line_smooth ||
1080 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1081 old_rs->force_persample_interp != rs->force_persample_interp)
1082 sctx->do_update_shaders = true;
1083 }
1084
1085 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1086 {
1087 struct si_context *sctx = (struct si_context *)ctx;
1088 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1089
1090 if (sctx->queued.named.rasterizer == state)
1091 si_pm4_bind_state(sctx, poly_offset, NULL);
1092
1093 FREE(rs->pm4_poly_offset);
1094 si_pm4_delete_state(sctx, rasterizer, rs);
1095 }
1096
1097 /*
1098 * infeered state between dsa and stencil ref
1099 */
1100 static void si_emit_stencil_ref(struct si_context *sctx)
1101 {
1102 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1103 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1104 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1105
1106 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1107 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1108 S_028430_STENCILMASK(dsa->valuemask[0]) |
1109 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1110 S_028430_STENCILOPVAL(1));
1111 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1112 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1113 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1114 S_028434_STENCILOPVAL_BF(1));
1115 }
1116
1117 static void si_set_stencil_ref(struct pipe_context *ctx,
1118 const struct pipe_stencil_ref *state)
1119 {
1120 struct si_context *sctx = (struct si_context *)ctx;
1121
1122 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1123 return;
1124
1125 sctx->stencil_ref.state = *state;
1126 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1127 }
1128
1129
1130 /*
1131 * DSA
1132 */
1133
1134 static uint32_t si_translate_stencil_op(int s_op)
1135 {
1136 switch (s_op) {
1137 case PIPE_STENCIL_OP_KEEP:
1138 return V_02842C_STENCIL_KEEP;
1139 case PIPE_STENCIL_OP_ZERO:
1140 return V_02842C_STENCIL_ZERO;
1141 case PIPE_STENCIL_OP_REPLACE:
1142 return V_02842C_STENCIL_REPLACE_TEST;
1143 case PIPE_STENCIL_OP_INCR:
1144 return V_02842C_STENCIL_ADD_CLAMP;
1145 case PIPE_STENCIL_OP_DECR:
1146 return V_02842C_STENCIL_SUB_CLAMP;
1147 case PIPE_STENCIL_OP_INCR_WRAP:
1148 return V_02842C_STENCIL_ADD_WRAP;
1149 case PIPE_STENCIL_OP_DECR_WRAP:
1150 return V_02842C_STENCIL_SUB_WRAP;
1151 case PIPE_STENCIL_OP_INVERT:
1152 return V_02842C_STENCIL_INVERT;
1153 default:
1154 PRINT_ERR("Unknown stencil op %d", s_op);
1155 assert(0);
1156 break;
1157 }
1158 return 0;
1159 }
1160
1161 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1162 {
1163 return s->enabled && s->writemask &&
1164 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1165 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1166 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1167 }
1168
1169 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1170 {
1171 /* REPLACE is normally order invariant, except when the stencil
1172 * reference value is written by the fragment shader. Tracking this
1173 * interaction does not seem worth the effort, so be conservative. */
1174 return op != PIPE_STENCIL_OP_INCR &&
1175 op != PIPE_STENCIL_OP_DECR &&
1176 op != PIPE_STENCIL_OP_REPLACE;
1177 }
1178
1179 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1180 * invariant in the sense that the set of passing fragments as well as the
1181 * final stencil buffer result does not depend on the order of fragments. */
1182 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1183 {
1184 return !state->enabled || !state->writemask ||
1185 /* The following assumes that Z writes are disabled. */
1186 (state->func == PIPE_FUNC_ALWAYS &&
1187 si_order_invariant_stencil_op(state->zpass_op) &&
1188 si_order_invariant_stencil_op(state->zfail_op)) ||
1189 (state->func == PIPE_FUNC_NEVER &&
1190 si_order_invariant_stencil_op(state->fail_op));
1191 }
1192
1193 static void *si_create_dsa_state(struct pipe_context *ctx,
1194 const struct pipe_depth_stencil_alpha_state *state)
1195 {
1196 struct si_context *sctx = (struct si_context *)ctx;
1197 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1198 struct si_pm4_state *pm4 = &dsa->pm4;
1199 unsigned db_depth_control;
1200 uint32_t db_stencil_control = 0;
1201
1202 if (!dsa) {
1203 return NULL;
1204 }
1205
1206 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1207 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1208 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1209 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1210
1211 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1212 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1213 S_028800_ZFUNC(state->depth.func) |
1214 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1215
1216 /* stencil */
1217 if (state->stencil[0].enabled) {
1218 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1219 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1220 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1221 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1222 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1223
1224 if (state->stencil[1].enabled) {
1225 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1226 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1227 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1228 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1229 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1230 }
1231 }
1232
1233 /* alpha */
1234 if (state->alpha.enabled) {
1235 dsa->alpha_func = state->alpha.func;
1236
1237 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1238 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1239 } else {
1240 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1241 }
1242
1243 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1244 if (state->stencil[0].enabled)
1245 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1246 if (state->depth.bounds_test) {
1247 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1248 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1249 }
1250
1251 dsa->depth_enabled = state->depth.enabled;
1252 dsa->depth_write_enabled = state->depth.enabled &&
1253 state->depth.writemask;
1254 dsa->stencil_enabled = state->stencil[0].enabled;
1255 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1256 (si_dsa_writes_stencil(&state->stencil[0]) ||
1257 si_dsa_writes_stencil(&state->stencil[1]));
1258 dsa->db_can_write = dsa->depth_write_enabled ||
1259 dsa->stencil_write_enabled;
1260
1261 bool zfunc_is_ordered =
1262 state->depth.func == PIPE_FUNC_NEVER ||
1263 state->depth.func == PIPE_FUNC_LESS ||
1264 state->depth.func == PIPE_FUNC_LEQUAL ||
1265 state->depth.func == PIPE_FUNC_GREATER ||
1266 state->depth.func == PIPE_FUNC_GEQUAL;
1267
1268 bool nozwrite_and_order_invariant_stencil =
1269 !dsa->db_can_write ||
1270 (!dsa->depth_write_enabled &&
1271 si_order_invariant_stencil_state(&state->stencil[0]) &&
1272 si_order_invariant_stencil_state(&state->stencil[1]));
1273
1274 dsa->order_invariance[1].zs =
1275 nozwrite_and_order_invariant_stencil ||
1276 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1277 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1278
1279 dsa->order_invariance[1].pass_set =
1280 nozwrite_and_order_invariant_stencil ||
1281 (!dsa->stencil_write_enabled &&
1282 (state->depth.func == PIPE_FUNC_ALWAYS ||
1283 state->depth.func == PIPE_FUNC_NEVER));
1284 dsa->order_invariance[0].pass_set =
1285 !dsa->depth_write_enabled ||
1286 (state->depth.func == PIPE_FUNC_ALWAYS ||
1287 state->depth.func == PIPE_FUNC_NEVER);
1288
1289 dsa->order_invariance[1].pass_last =
1290 sctx->screen->assume_no_z_fights &&
1291 !dsa->stencil_write_enabled &&
1292 dsa->depth_write_enabled && zfunc_is_ordered;
1293 dsa->order_invariance[0].pass_last =
1294 sctx->screen->assume_no_z_fights &&
1295 dsa->depth_write_enabled && zfunc_is_ordered;
1296
1297 return dsa;
1298 }
1299
1300 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1301 {
1302 struct si_context *sctx = (struct si_context *)ctx;
1303 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1304 struct si_state_dsa *dsa = state;
1305
1306 if (!state)
1307 return;
1308
1309 si_pm4_bind_state(sctx, dsa, dsa);
1310
1311 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1312 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1313 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1314 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1315 }
1316
1317 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1318 sctx->do_update_shaders = true;
1319
1320 if (sctx->screen->dpbb_allowed &&
1321 (!old_dsa ||
1322 (old_dsa->depth_enabled != dsa->depth_enabled ||
1323 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1324 old_dsa->db_can_write != dsa->db_can_write)))
1325 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1326
1327 if (sctx->screen->has_out_of_order_rast &&
1328 (!old_dsa ||
1329 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1330 sizeof(old_dsa->order_invariance))))
1331 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1332 }
1333
1334 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1335 {
1336 struct si_context *sctx = (struct si_context *)ctx;
1337 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1338 }
1339
1340 static void *si_create_db_flush_dsa(struct si_context *sctx)
1341 {
1342 struct pipe_depth_stencil_alpha_state dsa = {};
1343
1344 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1345 }
1346
1347 /* DB RENDER STATE */
1348
1349 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1350 {
1351 struct si_context *sctx = (struct si_context*)ctx;
1352
1353 /* Pipeline stat & streamout queries. */
1354 if (enable) {
1355 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1356 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1357 } else {
1358 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1359 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1360 }
1361
1362 /* Occlusion queries. */
1363 if (sctx->occlusion_queries_disabled != !enable) {
1364 sctx->occlusion_queries_disabled = !enable;
1365 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1366 }
1367 }
1368
1369 void si_set_occlusion_query_state(struct si_context *sctx,
1370 bool old_perfect_enable)
1371 {
1372 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1373
1374 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1375
1376 if (perfect_enable != old_perfect_enable)
1377 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1378 }
1379
1380 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1381 {
1382 st->saved_compute = sctx->cs_shader_state.program;
1383
1384 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1385 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1386
1387 st->saved_ssbo_writable_mask = 0;
1388
1389 for (unsigned i = 0; i < 3; i++) {
1390 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1391 (1u << si_get_shaderbuf_slot(i)))
1392 st->saved_ssbo_writable_mask |= 1 << i;
1393 }
1394 }
1395
1396 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1397 {
1398 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1399
1400 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1401 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1402
1403 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1404 st->saved_ssbo_writable_mask);
1405 for (unsigned i = 0; i < 3; ++i)
1406 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1407 }
1408
1409 static void si_emit_db_render_state(struct si_context *sctx)
1410 {
1411 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1412 unsigned db_shader_control, db_render_control, db_count_control;
1413 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1414
1415 /* DB_RENDER_CONTROL */
1416 if (sctx->dbcb_depth_copy_enabled ||
1417 sctx->dbcb_stencil_copy_enabled) {
1418 db_render_control =
1419 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1420 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1421 S_028000_COPY_CENTROID(1) |
1422 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1423 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1424 db_render_control =
1425 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1426 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1427 } else {
1428 db_render_control =
1429 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1430 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1431 }
1432
1433 /* DB_COUNT_CONTROL (occlusion queries) */
1434 if (sctx->num_occlusion_queries > 0 &&
1435 !sctx->occlusion_queries_disabled) {
1436 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1437 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1438
1439 if (sctx->chip_class >= GFX7) {
1440 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1441
1442 /* Stoney doesn't increment occlusion query counters
1443 * if the sample rate is 16x. Use 8x sample rate instead.
1444 */
1445 if (sctx->family == CHIP_STONEY)
1446 log_sample_rate = MIN2(log_sample_rate, 3);
1447
1448 db_count_control =
1449 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1450 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1451 S_028004_SAMPLE_RATE(log_sample_rate) |
1452 S_028004_ZPASS_ENABLE(1) |
1453 S_028004_SLICE_EVEN_ENABLE(1) |
1454 S_028004_SLICE_ODD_ENABLE(1);
1455 } else {
1456 db_count_control =
1457 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1458 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1459 }
1460 } else {
1461 /* Disable occlusion queries. */
1462 if (sctx->chip_class >= GFX7) {
1463 db_count_control = 0;
1464 } else {
1465 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1466 }
1467 }
1468
1469 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1470 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1471 db_count_control);
1472
1473 /* DB_RENDER_OVERRIDE2 */
1474 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1475 SI_TRACKED_DB_RENDER_OVERRIDE2,
1476 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1477 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1478 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1479
1480 db_shader_control = sctx->ps_db_shader_control;
1481
1482 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1483 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1484 db_shader_control &= C_02880C_Z_ORDER;
1485 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1486 }
1487
1488 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1489 if (!rs->multisample_enable)
1490 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1491
1492 if (sctx->screen->has_rbplus &&
1493 !sctx->screen->rbplus_allowed)
1494 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1495
1496 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1497 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1498
1499 if (initial_cdw != sctx->gfx_cs->current.cdw)
1500 sctx->context_roll = true;
1501 }
1502
1503 /*
1504 * format translation
1505 */
1506 static uint32_t si_translate_colorformat(enum pipe_format format)
1507 {
1508 const struct util_format_description *desc = util_format_description(format);
1509 if (!desc)
1510 return V_028C70_COLOR_INVALID;
1511
1512 #define HAS_SIZE(x,y,z,w) \
1513 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1514 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1515
1516 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1517 return V_028C70_COLOR_10_11_11;
1518
1519 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1520 return V_028C70_COLOR_INVALID;
1521
1522 /* hw cannot support mixed formats (except depth/stencil, since
1523 * stencil is not written to). */
1524 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1525 return V_028C70_COLOR_INVALID;
1526
1527 switch (desc->nr_channels) {
1528 case 1:
1529 switch (desc->channel[0].size) {
1530 case 8:
1531 return V_028C70_COLOR_8;
1532 case 16:
1533 return V_028C70_COLOR_16;
1534 case 32:
1535 return V_028C70_COLOR_32;
1536 }
1537 break;
1538 case 2:
1539 if (desc->channel[0].size == desc->channel[1].size) {
1540 switch (desc->channel[0].size) {
1541 case 8:
1542 return V_028C70_COLOR_8_8;
1543 case 16:
1544 return V_028C70_COLOR_16_16;
1545 case 32:
1546 return V_028C70_COLOR_32_32;
1547 }
1548 } else if (HAS_SIZE(8,24,0,0)) {
1549 return V_028C70_COLOR_24_8;
1550 } else if (HAS_SIZE(24,8,0,0)) {
1551 return V_028C70_COLOR_8_24;
1552 }
1553 break;
1554 case 3:
1555 if (HAS_SIZE(5,6,5,0)) {
1556 return V_028C70_COLOR_5_6_5;
1557 } else if (HAS_SIZE(32,8,24,0)) {
1558 return V_028C70_COLOR_X24_8_32_FLOAT;
1559 }
1560 break;
1561 case 4:
1562 if (desc->channel[0].size == desc->channel[1].size &&
1563 desc->channel[0].size == desc->channel[2].size &&
1564 desc->channel[0].size == desc->channel[3].size) {
1565 switch (desc->channel[0].size) {
1566 case 4:
1567 return V_028C70_COLOR_4_4_4_4;
1568 case 8:
1569 return V_028C70_COLOR_8_8_8_8;
1570 case 16:
1571 return V_028C70_COLOR_16_16_16_16;
1572 case 32:
1573 return V_028C70_COLOR_32_32_32_32;
1574 }
1575 } else if (HAS_SIZE(5,5,5,1)) {
1576 return V_028C70_COLOR_1_5_5_5;
1577 } else if (HAS_SIZE(1,5,5,5)) {
1578 return V_028C70_COLOR_5_5_5_1;
1579 } else if (HAS_SIZE(10,10,10,2)) {
1580 return V_028C70_COLOR_2_10_10_10;
1581 }
1582 break;
1583 }
1584 return V_028C70_COLOR_INVALID;
1585 }
1586
1587 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1588 {
1589 if (SI_BIG_ENDIAN) {
1590 switch(colorformat) {
1591 /* 8-bit buffers. */
1592 case V_028C70_COLOR_8:
1593 return V_028C70_ENDIAN_NONE;
1594
1595 /* 16-bit buffers. */
1596 case V_028C70_COLOR_5_6_5:
1597 case V_028C70_COLOR_1_5_5_5:
1598 case V_028C70_COLOR_4_4_4_4:
1599 case V_028C70_COLOR_16:
1600 case V_028C70_COLOR_8_8:
1601 return V_028C70_ENDIAN_8IN16;
1602
1603 /* 32-bit buffers. */
1604 case V_028C70_COLOR_8_8_8_8:
1605 case V_028C70_COLOR_2_10_10_10:
1606 case V_028C70_COLOR_8_24:
1607 case V_028C70_COLOR_24_8:
1608 case V_028C70_COLOR_16_16:
1609 return V_028C70_ENDIAN_8IN32;
1610
1611 /* 64-bit buffers. */
1612 case V_028C70_COLOR_16_16_16_16:
1613 return V_028C70_ENDIAN_8IN16;
1614
1615 case V_028C70_COLOR_32_32:
1616 return V_028C70_ENDIAN_8IN32;
1617
1618 /* 128-bit buffers. */
1619 case V_028C70_COLOR_32_32_32_32:
1620 return V_028C70_ENDIAN_8IN32;
1621 default:
1622 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1623 }
1624 } else {
1625 return V_028C70_ENDIAN_NONE;
1626 }
1627 }
1628
1629 static uint32_t si_translate_dbformat(enum pipe_format format)
1630 {
1631 switch (format) {
1632 case PIPE_FORMAT_Z16_UNORM:
1633 return V_028040_Z_16;
1634 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1635 case PIPE_FORMAT_X8Z24_UNORM:
1636 case PIPE_FORMAT_Z24X8_UNORM:
1637 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1638 return V_028040_Z_24; /* deprecated on AMD GCN */
1639 case PIPE_FORMAT_Z32_FLOAT:
1640 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1641 return V_028040_Z_32_FLOAT;
1642 default:
1643 return V_028040_Z_INVALID;
1644 }
1645 }
1646
1647 /*
1648 * Texture translation
1649 */
1650
1651 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1652 enum pipe_format format,
1653 const struct util_format_description *desc,
1654 int first_non_void)
1655 {
1656 struct si_screen *sscreen = (struct si_screen*)screen;
1657 bool uniform = true;
1658 int i;
1659
1660 assert(sscreen->info.chip_class <= GFX9);
1661
1662 /* Colorspace (return non-RGB formats directly). */
1663 switch (desc->colorspace) {
1664 /* Depth stencil formats */
1665 case UTIL_FORMAT_COLORSPACE_ZS:
1666 switch (format) {
1667 case PIPE_FORMAT_Z16_UNORM:
1668 return V_008F14_IMG_DATA_FORMAT_16;
1669 case PIPE_FORMAT_X24S8_UINT:
1670 case PIPE_FORMAT_S8X24_UINT:
1671 /*
1672 * Implemented as an 8_8_8_8 data format to fix texture
1673 * gathers in stencil sampling. This affects at least
1674 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1675 */
1676 if (sscreen->info.chip_class <= GFX8)
1677 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1678
1679 if (format == PIPE_FORMAT_X24S8_UINT)
1680 return V_008F14_IMG_DATA_FORMAT_8_24;
1681 else
1682 return V_008F14_IMG_DATA_FORMAT_24_8;
1683 case PIPE_FORMAT_Z24X8_UNORM:
1684 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1685 return V_008F14_IMG_DATA_FORMAT_8_24;
1686 case PIPE_FORMAT_X8Z24_UNORM:
1687 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1688 return V_008F14_IMG_DATA_FORMAT_24_8;
1689 case PIPE_FORMAT_S8_UINT:
1690 return V_008F14_IMG_DATA_FORMAT_8;
1691 case PIPE_FORMAT_Z32_FLOAT:
1692 return V_008F14_IMG_DATA_FORMAT_32;
1693 case PIPE_FORMAT_X32_S8X24_UINT:
1694 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1695 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1696 default:
1697 goto out_unknown;
1698 }
1699
1700 case UTIL_FORMAT_COLORSPACE_YUV:
1701 goto out_unknown; /* TODO */
1702
1703 case UTIL_FORMAT_COLORSPACE_SRGB:
1704 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1705 goto out_unknown;
1706 break;
1707
1708 default:
1709 break;
1710 }
1711
1712 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1713 if (!sscreen->info.has_format_bc1_through_bc7)
1714 goto out_unknown;
1715
1716 switch (format) {
1717 case PIPE_FORMAT_RGTC1_SNORM:
1718 case PIPE_FORMAT_LATC1_SNORM:
1719 case PIPE_FORMAT_RGTC1_UNORM:
1720 case PIPE_FORMAT_LATC1_UNORM:
1721 return V_008F14_IMG_DATA_FORMAT_BC4;
1722 case PIPE_FORMAT_RGTC2_SNORM:
1723 case PIPE_FORMAT_LATC2_SNORM:
1724 case PIPE_FORMAT_RGTC2_UNORM:
1725 case PIPE_FORMAT_LATC2_UNORM:
1726 return V_008F14_IMG_DATA_FORMAT_BC5;
1727 default:
1728 goto out_unknown;
1729 }
1730 }
1731
1732 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1733 (sscreen->info.family == CHIP_STONEY ||
1734 sscreen->info.family == CHIP_VEGA10 ||
1735 sscreen->info.family == CHIP_RAVEN)) {
1736 switch (format) {
1737 case PIPE_FORMAT_ETC1_RGB8:
1738 case PIPE_FORMAT_ETC2_RGB8:
1739 case PIPE_FORMAT_ETC2_SRGB8:
1740 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1741 case PIPE_FORMAT_ETC2_RGB8A1:
1742 case PIPE_FORMAT_ETC2_SRGB8A1:
1743 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1744 case PIPE_FORMAT_ETC2_RGBA8:
1745 case PIPE_FORMAT_ETC2_SRGBA8:
1746 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1747 case PIPE_FORMAT_ETC2_R11_UNORM:
1748 case PIPE_FORMAT_ETC2_R11_SNORM:
1749 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1750 case PIPE_FORMAT_ETC2_RG11_UNORM:
1751 case PIPE_FORMAT_ETC2_RG11_SNORM:
1752 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1753 default:
1754 goto out_unknown;
1755 }
1756 }
1757
1758 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1759 if (!sscreen->info.has_format_bc1_through_bc7)
1760 goto out_unknown;
1761
1762 switch (format) {
1763 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1764 case PIPE_FORMAT_BPTC_SRGBA:
1765 return V_008F14_IMG_DATA_FORMAT_BC7;
1766 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1767 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1768 return V_008F14_IMG_DATA_FORMAT_BC6;
1769 default:
1770 goto out_unknown;
1771 }
1772 }
1773
1774 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1775 switch (format) {
1776 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1777 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1778 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1779 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1780 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1781 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1782 default:
1783 goto out_unknown;
1784 }
1785 }
1786
1787 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1788 if (!sscreen->info.has_format_bc1_through_bc7)
1789 goto out_unknown;
1790
1791 switch (format) {
1792 case PIPE_FORMAT_DXT1_RGB:
1793 case PIPE_FORMAT_DXT1_RGBA:
1794 case PIPE_FORMAT_DXT1_SRGB:
1795 case PIPE_FORMAT_DXT1_SRGBA:
1796 return V_008F14_IMG_DATA_FORMAT_BC1;
1797 case PIPE_FORMAT_DXT3_RGBA:
1798 case PIPE_FORMAT_DXT3_SRGBA:
1799 return V_008F14_IMG_DATA_FORMAT_BC2;
1800 case PIPE_FORMAT_DXT5_RGBA:
1801 case PIPE_FORMAT_DXT5_SRGBA:
1802 return V_008F14_IMG_DATA_FORMAT_BC3;
1803 default:
1804 goto out_unknown;
1805 }
1806 }
1807
1808 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1809 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1810 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1811 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1812 }
1813
1814 /* R8G8Bx_SNORM - TODO CxV8U8 */
1815
1816 /* hw cannot support mixed formats (except depth/stencil, since only
1817 * depth is read).*/
1818 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1819 goto out_unknown;
1820
1821 /* See whether the components are of the same size. */
1822 for (i = 1; i < desc->nr_channels; i++) {
1823 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1824 }
1825
1826 /* Non-uniform formats. */
1827 if (!uniform) {
1828 switch(desc->nr_channels) {
1829 case 3:
1830 if (desc->channel[0].size == 5 &&
1831 desc->channel[1].size == 6 &&
1832 desc->channel[2].size == 5) {
1833 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1834 }
1835 goto out_unknown;
1836 case 4:
1837 if (desc->channel[0].size == 5 &&
1838 desc->channel[1].size == 5 &&
1839 desc->channel[2].size == 5 &&
1840 desc->channel[3].size == 1) {
1841 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1842 }
1843 if (desc->channel[0].size == 1 &&
1844 desc->channel[1].size == 5 &&
1845 desc->channel[2].size == 5 &&
1846 desc->channel[3].size == 5) {
1847 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1848 }
1849 if (desc->channel[0].size == 10 &&
1850 desc->channel[1].size == 10 &&
1851 desc->channel[2].size == 10 &&
1852 desc->channel[3].size == 2) {
1853 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1854 }
1855 goto out_unknown;
1856 }
1857 goto out_unknown;
1858 }
1859
1860 if (first_non_void < 0 || first_non_void > 3)
1861 goto out_unknown;
1862
1863 /* uniform formats */
1864 switch (desc->channel[first_non_void].size) {
1865 case 4:
1866 switch (desc->nr_channels) {
1867 #if 0 /* Not supported for render targets */
1868 case 2:
1869 return V_008F14_IMG_DATA_FORMAT_4_4;
1870 #endif
1871 case 4:
1872 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1873 }
1874 break;
1875 case 8:
1876 switch (desc->nr_channels) {
1877 case 1:
1878 return V_008F14_IMG_DATA_FORMAT_8;
1879 case 2:
1880 return V_008F14_IMG_DATA_FORMAT_8_8;
1881 case 4:
1882 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1883 }
1884 break;
1885 case 16:
1886 switch (desc->nr_channels) {
1887 case 1:
1888 return V_008F14_IMG_DATA_FORMAT_16;
1889 case 2:
1890 return V_008F14_IMG_DATA_FORMAT_16_16;
1891 case 4:
1892 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1893 }
1894 break;
1895 case 32:
1896 switch (desc->nr_channels) {
1897 case 1:
1898 return V_008F14_IMG_DATA_FORMAT_32;
1899 case 2:
1900 return V_008F14_IMG_DATA_FORMAT_32_32;
1901 #if 0 /* Not supported for render targets */
1902 case 3:
1903 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1904 #endif
1905 case 4:
1906 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1907 }
1908 }
1909
1910 out_unknown:
1911 return ~0;
1912 }
1913
1914 static unsigned si_tex_wrap(unsigned wrap)
1915 {
1916 switch (wrap) {
1917 default:
1918 case PIPE_TEX_WRAP_REPEAT:
1919 return V_008F30_SQ_TEX_WRAP;
1920 case PIPE_TEX_WRAP_CLAMP:
1921 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1922 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1923 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1924 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1925 return V_008F30_SQ_TEX_CLAMP_BORDER;
1926 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1927 return V_008F30_SQ_TEX_MIRROR;
1928 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1929 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1930 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1931 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1932 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1933 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1934 }
1935 }
1936
1937 static unsigned si_tex_mipfilter(unsigned filter)
1938 {
1939 switch (filter) {
1940 case PIPE_TEX_MIPFILTER_NEAREST:
1941 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1942 case PIPE_TEX_MIPFILTER_LINEAR:
1943 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1944 default:
1945 case PIPE_TEX_MIPFILTER_NONE:
1946 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1947 }
1948 }
1949
1950 static unsigned si_tex_compare(unsigned compare)
1951 {
1952 switch (compare) {
1953 default:
1954 case PIPE_FUNC_NEVER:
1955 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1956 case PIPE_FUNC_LESS:
1957 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1958 case PIPE_FUNC_EQUAL:
1959 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1960 case PIPE_FUNC_LEQUAL:
1961 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1962 case PIPE_FUNC_GREATER:
1963 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1964 case PIPE_FUNC_NOTEQUAL:
1965 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1966 case PIPE_FUNC_GEQUAL:
1967 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1968 case PIPE_FUNC_ALWAYS:
1969 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1970 }
1971 }
1972
1973 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1974 unsigned view_target, unsigned nr_samples)
1975 {
1976 unsigned res_target = tex->buffer.b.b.target;
1977
1978 if (view_target == PIPE_TEXTURE_CUBE ||
1979 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1980 res_target = view_target;
1981 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1982 else if (res_target == PIPE_TEXTURE_CUBE ||
1983 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1984 res_target = PIPE_TEXTURE_2D_ARRAY;
1985
1986 /* GFX9 allocates 1D textures as 2D. */
1987 if ((res_target == PIPE_TEXTURE_1D ||
1988 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1989 sscreen->info.chip_class == GFX9 &&
1990 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1991 if (res_target == PIPE_TEXTURE_1D)
1992 res_target = PIPE_TEXTURE_2D;
1993 else
1994 res_target = PIPE_TEXTURE_2D_ARRAY;
1995 }
1996
1997 switch (res_target) {
1998 default:
1999 case PIPE_TEXTURE_1D:
2000 return V_008F1C_SQ_RSRC_IMG_1D;
2001 case PIPE_TEXTURE_1D_ARRAY:
2002 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2003 case PIPE_TEXTURE_2D:
2004 case PIPE_TEXTURE_RECT:
2005 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2006 V_008F1C_SQ_RSRC_IMG_2D;
2007 case PIPE_TEXTURE_2D_ARRAY:
2008 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2009 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2010 case PIPE_TEXTURE_3D:
2011 return V_008F1C_SQ_RSRC_IMG_3D;
2012 case PIPE_TEXTURE_CUBE:
2013 case PIPE_TEXTURE_CUBE_ARRAY:
2014 return V_008F1C_SQ_RSRC_IMG_CUBE;
2015 }
2016 }
2017
2018 /*
2019 * Format support testing
2020 */
2021
2022 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2023 {
2024 struct si_screen *sscreen = (struct si_screen *)screen;
2025
2026 if (sscreen->info.chip_class >= GFX10) {
2027 const struct gfx10_format *fmt = &gfx10_format_table[format];
2028 if (!fmt->img_format || fmt->buffers_only)
2029 return false;
2030 return true;
2031 }
2032
2033 const struct util_format_description *desc = util_format_description(format);
2034 if (!desc)
2035 return false;
2036
2037 return si_translate_texformat(screen, format, desc,
2038 util_format_get_first_non_void_channel(format)) != ~0U;
2039 }
2040
2041 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2042 const struct util_format_description *desc,
2043 int first_non_void)
2044 {
2045 int i;
2046
2047 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2048
2049 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2050 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2051
2052 assert(first_non_void >= 0);
2053
2054 if (desc->nr_channels == 4 &&
2055 desc->channel[0].size == 10 &&
2056 desc->channel[1].size == 10 &&
2057 desc->channel[2].size == 10 &&
2058 desc->channel[3].size == 2)
2059 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2060
2061 /* See whether the components are of the same size. */
2062 for (i = 0; i < desc->nr_channels; i++) {
2063 if (desc->channel[first_non_void].size != desc->channel[i].size)
2064 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2065 }
2066
2067 switch (desc->channel[first_non_void].size) {
2068 case 8:
2069 switch (desc->nr_channels) {
2070 case 1:
2071 case 3: /* 3 loads */
2072 return V_008F0C_BUF_DATA_FORMAT_8;
2073 case 2:
2074 return V_008F0C_BUF_DATA_FORMAT_8_8;
2075 case 4:
2076 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2077 }
2078 break;
2079 case 16:
2080 switch (desc->nr_channels) {
2081 case 1:
2082 case 3: /* 3 loads */
2083 return V_008F0C_BUF_DATA_FORMAT_16;
2084 case 2:
2085 return V_008F0C_BUF_DATA_FORMAT_16_16;
2086 case 4:
2087 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2088 }
2089 break;
2090 case 32:
2091 switch (desc->nr_channels) {
2092 case 1:
2093 return V_008F0C_BUF_DATA_FORMAT_32;
2094 case 2:
2095 return V_008F0C_BUF_DATA_FORMAT_32_32;
2096 case 3:
2097 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2098 case 4:
2099 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2100 }
2101 break;
2102 case 64:
2103 /* Legacy double formats. */
2104 switch (desc->nr_channels) {
2105 case 1: /* 1 load */
2106 return V_008F0C_BUF_DATA_FORMAT_32_32;
2107 case 2: /* 1 load */
2108 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2109 case 3: /* 3 loads */
2110 return V_008F0C_BUF_DATA_FORMAT_32_32;
2111 case 4: /* 2 loads */
2112 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2113 }
2114 break;
2115 }
2116
2117 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2118 }
2119
2120 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2121 const struct util_format_description *desc,
2122 int first_non_void)
2123 {
2124 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2125
2126 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2127 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2128
2129 assert(first_non_void >= 0);
2130
2131 switch (desc->channel[first_non_void].type) {
2132 case UTIL_FORMAT_TYPE_SIGNED:
2133 case UTIL_FORMAT_TYPE_FIXED:
2134 if (desc->channel[first_non_void].size >= 32 ||
2135 desc->channel[first_non_void].pure_integer)
2136 return V_008F0C_BUF_NUM_FORMAT_SINT;
2137 else if (desc->channel[first_non_void].normalized)
2138 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2139 else
2140 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2141 break;
2142 case UTIL_FORMAT_TYPE_UNSIGNED:
2143 if (desc->channel[first_non_void].size >= 32 ||
2144 desc->channel[first_non_void].pure_integer)
2145 return V_008F0C_BUF_NUM_FORMAT_UINT;
2146 else if (desc->channel[first_non_void].normalized)
2147 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2148 else
2149 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2150 break;
2151 case UTIL_FORMAT_TYPE_FLOAT:
2152 default:
2153 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2154 }
2155 }
2156
2157 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2158 enum pipe_format format,
2159 unsigned usage)
2160 {
2161 struct si_screen *sscreen = (struct si_screen *)screen;
2162 const struct util_format_description *desc;
2163 int first_non_void;
2164 unsigned data_format;
2165
2166 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2167 PIPE_BIND_SAMPLER_VIEW |
2168 PIPE_BIND_VERTEX_BUFFER)) == 0);
2169
2170 desc = util_format_description(format);
2171 if (!desc)
2172 return 0;
2173
2174 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2175 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2176 * for read-only access (with caveats surrounding bounds checks), but
2177 * obviously fails for write access which we have to implement for
2178 * shader images. Luckily, OpenGL doesn't expect this to be supported
2179 * anyway, and so the only impact is on PBO uploads / downloads, which
2180 * shouldn't be expected to be fast for GL_RGB anyway.
2181 */
2182 if (desc->block.bits == 3 * 8 ||
2183 desc->block.bits == 3 * 16) {
2184 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2185 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2186 if (!usage)
2187 return 0;
2188 }
2189 }
2190
2191 if (sscreen->info.chip_class >= GFX10) {
2192 const struct gfx10_format *fmt = &gfx10_format_table[format];
2193 if (!fmt->img_format || fmt->img_format >= 128)
2194 return 0;
2195 return usage;
2196 }
2197
2198 first_non_void = util_format_get_first_non_void_channel(format);
2199 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2200 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2201 return 0;
2202
2203 return usage;
2204 }
2205
2206 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2207 {
2208 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2209 si_translate_colorswap(format, false) != ~0U;
2210 }
2211
2212 static bool si_is_zs_format_supported(enum pipe_format format)
2213 {
2214 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2215 }
2216
2217 static bool si_is_format_supported(struct pipe_screen *screen,
2218 enum pipe_format format,
2219 enum pipe_texture_target target,
2220 unsigned sample_count,
2221 unsigned storage_sample_count,
2222 unsigned usage)
2223 {
2224 struct si_screen *sscreen = (struct si_screen *)screen;
2225 unsigned retval = 0;
2226
2227 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2228 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2229 return false;
2230 }
2231
2232 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2233 return false;
2234
2235 if (sample_count > 1) {
2236 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2237 return false;
2238
2239 if (usage & PIPE_BIND_SHADER_IMAGE)
2240 return false;
2241
2242 /* Only power-of-two sample counts are supported. */
2243 if (!util_is_power_of_two_or_zero(sample_count) ||
2244 !util_is_power_of_two_or_zero(storage_sample_count))
2245 return false;
2246
2247 /* MSAA support without framebuffer attachments. */
2248 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2249 return true;
2250
2251 if (!sscreen->info.has_eqaa_surface_allocator ||
2252 util_format_is_depth_or_stencil(format)) {
2253 /* Color without EQAA or depth/stencil. */
2254 if (sample_count > 8 ||
2255 sample_count != storage_sample_count)
2256 return false;
2257 } else {
2258 /* Color with EQAA. */
2259 if (sample_count > 16 ||
2260 storage_sample_count > 8)
2261 return false;
2262 }
2263 }
2264
2265 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2266 PIPE_BIND_SHADER_IMAGE)) {
2267 if (target == PIPE_BUFFER) {
2268 retval |= si_is_vertex_format_supported(
2269 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2270 PIPE_BIND_SHADER_IMAGE));
2271 } else {
2272 if (si_is_sampler_format_supported(screen, format))
2273 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2274 PIPE_BIND_SHADER_IMAGE);
2275 }
2276 }
2277
2278 if ((usage & (PIPE_BIND_RENDER_TARGET |
2279 PIPE_BIND_DISPLAY_TARGET |
2280 PIPE_BIND_SCANOUT |
2281 PIPE_BIND_SHARED |
2282 PIPE_BIND_BLENDABLE)) &&
2283 si_is_colorbuffer_format_supported(format)) {
2284 retval |= usage &
2285 (PIPE_BIND_RENDER_TARGET |
2286 PIPE_BIND_DISPLAY_TARGET |
2287 PIPE_BIND_SCANOUT |
2288 PIPE_BIND_SHARED);
2289 if (!util_format_is_pure_integer(format) &&
2290 !util_format_is_depth_or_stencil(format))
2291 retval |= usage & PIPE_BIND_BLENDABLE;
2292 }
2293
2294 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2295 si_is_zs_format_supported(format)) {
2296 retval |= PIPE_BIND_DEPTH_STENCIL;
2297 }
2298
2299 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2300 retval |= si_is_vertex_format_supported(screen, format,
2301 PIPE_BIND_VERTEX_BUFFER);
2302 }
2303
2304 if ((usage & PIPE_BIND_LINEAR) &&
2305 !util_format_is_compressed(format) &&
2306 !(usage & PIPE_BIND_DEPTH_STENCIL))
2307 retval |= PIPE_BIND_LINEAR;
2308
2309 return retval == usage;
2310 }
2311
2312 /*
2313 * framebuffer handling
2314 */
2315
2316 static void si_choose_spi_color_formats(struct si_surface *surf,
2317 unsigned format, unsigned swap,
2318 unsigned ntype, bool is_depth)
2319 {
2320 /* Alpha is needed for alpha-to-coverage.
2321 * Blending may be with or without alpha.
2322 */
2323 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2324 unsigned alpha = 0; /* exports alpha, but may not support blending */
2325 unsigned blend = 0; /* supports blending, but may not export alpha */
2326 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2327
2328 /* Choose the SPI color formats. These are required values for RB+.
2329 * Other chips have multiple choices, though they are not necessarily better.
2330 */
2331 switch (format) {
2332 case V_028C70_COLOR_5_6_5:
2333 case V_028C70_COLOR_1_5_5_5:
2334 case V_028C70_COLOR_5_5_5_1:
2335 case V_028C70_COLOR_4_4_4_4:
2336 case V_028C70_COLOR_10_11_11:
2337 case V_028C70_COLOR_11_11_10:
2338 case V_028C70_COLOR_8:
2339 case V_028C70_COLOR_8_8:
2340 case V_028C70_COLOR_8_8_8_8:
2341 case V_028C70_COLOR_10_10_10_2:
2342 case V_028C70_COLOR_2_10_10_10:
2343 if (ntype == V_028C70_NUMBER_UINT)
2344 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2345 else if (ntype == V_028C70_NUMBER_SINT)
2346 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2347 else
2348 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2349 break;
2350
2351 case V_028C70_COLOR_16:
2352 case V_028C70_COLOR_16_16:
2353 case V_028C70_COLOR_16_16_16_16:
2354 if (ntype == V_028C70_NUMBER_UNORM ||
2355 ntype == V_028C70_NUMBER_SNORM) {
2356 /* UNORM16 and SNORM16 don't support blending */
2357 if (ntype == V_028C70_NUMBER_UNORM)
2358 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2359 else
2360 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2361
2362 /* Use 32 bits per channel for blending. */
2363 if (format == V_028C70_COLOR_16) {
2364 if (swap == V_028C70_SWAP_STD) { /* R */
2365 blend = V_028714_SPI_SHADER_32_R;
2366 blend_alpha = V_028714_SPI_SHADER_32_AR;
2367 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2368 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2369 else
2370 assert(0);
2371 } else if (format == V_028C70_COLOR_16_16) {
2372 if (swap == V_028C70_SWAP_STD) { /* RG */
2373 blend = V_028714_SPI_SHADER_32_GR;
2374 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2375 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2376 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2377 else
2378 assert(0);
2379 } else /* 16_16_16_16 */
2380 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2381 } else if (ntype == V_028C70_NUMBER_UINT)
2382 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2383 else if (ntype == V_028C70_NUMBER_SINT)
2384 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2385 else if (ntype == V_028C70_NUMBER_FLOAT)
2386 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2387 else
2388 assert(0);
2389 break;
2390
2391 case V_028C70_COLOR_32:
2392 if (swap == V_028C70_SWAP_STD) { /* R */
2393 blend = normal = V_028714_SPI_SHADER_32_R;
2394 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2395 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2396 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2397 else
2398 assert(0);
2399 break;
2400
2401 case V_028C70_COLOR_32_32:
2402 if (swap == V_028C70_SWAP_STD) { /* RG */
2403 blend = normal = V_028714_SPI_SHADER_32_GR;
2404 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2405 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2406 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2407 else
2408 assert(0);
2409 break;
2410
2411 case V_028C70_COLOR_32_32_32_32:
2412 case V_028C70_COLOR_8_24:
2413 case V_028C70_COLOR_24_8:
2414 case V_028C70_COLOR_X24_8_32_FLOAT:
2415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2416 break;
2417
2418 default:
2419 assert(0);
2420 return;
2421 }
2422
2423 /* The DB->CB copy needs 32_ABGR. */
2424 if (is_depth)
2425 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2426
2427 surf->spi_shader_col_format = normal;
2428 surf->spi_shader_col_format_alpha = alpha;
2429 surf->spi_shader_col_format_blend = blend;
2430 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2431 }
2432
2433 static void si_initialize_color_surface(struct si_context *sctx,
2434 struct si_surface *surf)
2435 {
2436 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2437 unsigned color_info, color_attrib;
2438 unsigned format, swap, ntype, endian;
2439 const struct util_format_description *desc;
2440 int firstchan;
2441 unsigned blend_clamp = 0, blend_bypass = 0;
2442
2443 desc = util_format_description(surf->base.format);
2444 for (firstchan = 0; firstchan < 4; firstchan++) {
2445 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2446 break;
2447 }
2448 }
2449 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2450 ntype = V_028C70_NUMBER_FLOAT;
2451 } else {
2452 ntype = V_028C70_NUMBER_UNORM;
2453 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2454 ntype = V_028C70_NUMBER_SRGB;
2455 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2456 if (desc->channel[firstchan].pure_integer) {
2457 ntype = V_028C70_NUMBER_SINT;
2458 } else {
2459 assert(desc->channel[firstchan].normalized);
2460 ntype = V_028C70_NUMBER_SNORM;
2461 }
2462 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2463 if (desc->channel[firstchan].pure_integer) {
2464 ntype = V_028C70_NUMBER_UINT;
2465 } else {
2466 assert(desc->channel[firstchan].normalized);
2467 ntype = V_028C70_NUMBER_UNORM;
2468 }
2469 }
2470 }
2471
2472 format = si_translate_colorformat(surf->base.format);
2473 if (format == V_028C70_COLOR_INVALID) {
2474 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2475 }
2476 assert(format != V_028C70_COLOR_INVALID);
2477 swap = si_translate_colorswap(surf->base.format, false);
2478 endian = si_colorformat_endian_swap(format);
2479
2480 /* blend clamp should be set for all NORM/SRGB types */
2481 if (ntype == V_028C70_NUMBER_UNORM ||
2482 ntype == V_028C70_NUMBER_SNORM ||
2483 ntype == V_028C70_NUMBER_SRGB)
2484 blend_clamp = 1;
2485
2486 /* set blend bypass according to docs if SINT/UINT or
2487 8/24 COLOR variants */
2488 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2489 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2490 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2491 blend_clamp = 0;
2492 blend_bypass = 1;
2493 }
2494
2495 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2496 if (format == V_028C70_COLOR_8 ||
2497 format == V_028C70_COLOR_8_8 ||
2498 format == V_028C70_COLOR_8_8_8_8)
2499 surf->color_is_int8 = true;
2500 else if (format == V_028C70_COLOR_10_10_10_2 ||
2501 format == V_028C70_COLOR_2_10_10_10)
2502 surf->color_is_int10 = true;
2503 }
2504
2505 color_info = S_028C70_FORMAT(format) |
2506 S_028C70_COMP_SWAP(swap) |
2507 S_028C70_BLEND_CLAMP(blend_clamp) |
2508 S_028C70_BLEND_BYPASS(blend_bypass) |
2509 S_028C70_SIMPLE_FLOAT(1) |
2510 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2511 ntype != V_028C70_NUMBER_SNORM &&
2512 ntype != V_028C70_NUMBER_SRGB &&
2513 format != V_028C70_COLOR_8_24 &&
2514 format != V_028C70_COLOR_24_8) |
2515 S_028C70_NUMBER_TYPE(ntype) |
2516 S_028C70_ENDIAN(endian);
2517
2518 /* Intensity is implemented as Red, so treat it that way. */
2519 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2520 util_format_is_intensity(surf->base.format));
2521
2522 if (tex->buffer.b.b.nr_samples > 1) {
2523 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2524 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2525
2526 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2527 S_028C74_NUM_FRAGMENTS(log_fragments);
2528
2529 if (tex->fmask_offset) {
2530 color_info |= S_028C70_COMPRESSION(1);
2531 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2532
2533 if (sctx->chip_class == GFX6) {
2534 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2535 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2536 }
2537 }
2538 }
2539
2540 if (sctx->chip_class >= GFX10) {
2541 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2542
2543 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2544 64 for APU because all of our APUs to date use DIMMs which have
2545 a request granularity size of 64B while all other chips have a
2546 32B request size */
2547 if (!sctx->screen->info.has_dedicated_vram)
2548 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2549
2550 surf->cb_dcc_control =
2551 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2552 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2553 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2554 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2555 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2556 } else if (sctx->chip_class >= GFX8) {
2557 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2558 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2559
2560 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2561 64 for APU because all of our APUs to date use DIMMs which have
2562 a request granularity size of 64B while all other chips have a
2563 32B request size */
2564 if (!sctx->screen->info.has_dedicated_vram)
2565 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2566
2567 if (tex->buffer.b.b.nr_storage_samples > 1) {
2568 if (tex->surface.bpe == 1)
2569 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2570 else if (tex->surface.bpe == 2)
2571 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2572 }
2573
2574 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2575 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2576 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2577 }
2578
2579 /* This must be set for fast clear to work without FMASK. */
2580 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2581 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2582 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2583 }
2584
2585 /* GFX10 field has the same base shift as the GFX6 field */
2586 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2587 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2588 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2589
2590 if (sctx->chip_class >= GFX10) {
2591 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2592
2593 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2594 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2595 S_028EE0_RESOURCE_LEVEL(1);
2596 } else if (sctx->chip_class == GFX9) {
2597 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2598 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2599 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2600 }
2601
2602 if (sctx->chip_class >= GFX9) {
2603 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2604 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2605 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2606 }
2607
2608 surf->cb_color_view = color_view;
2609 surf->cb_color_info = color_info;
2610 surf->cb_color_attrib = color_attrib;
2611
2612 /* Determine pixel shader export format */
2613 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2614
2615 surf->color_initialized = true;
2616 }
2617
2618 static void si_init_depth_surface(struct si_context *sctx,
2619 struct si_surface *surf)
2620 {
2621 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2622 unsigned level = surf->base.u.tex.level;
2623 unsigned format, stencil_format;
2624 uint32_t z_info, s_info;
2625
2626 format = si_translate_dbformat(tex->db_render_format);
2627 stencil_format = tex->surface.has_stencil ?
2628 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2629
2630 assert(format != V_028040_Z_INVALID);
2631 if (format == V_028040_Z_INVALID)
2632 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2633
2634 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2635 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2636 surf->db_htile_data_base = 0;
2637 surf->db_htile_surface = 0;
2638
2639 if (sctx->chip_class >= GFX10) {
2640 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2641 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2642 }
2643
2644 if (sctx->chip_class >= GFX9) {
2645 assert(tex->surface.u.gfx9.surf_offset == 0);
2646 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2647 surf->db_stencil_base = (tex->buffer.gpu_address +
2648 tex->surface.u.gfx9.stencil_offset) >> 8;
2649 z_info = S_028038_FORMAT(format) |
2650 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2651 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2652 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2653 s_info = S_02803C_FORMAT(stencil_format) |
2654 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2655
2656 if (sctx->chip_class == GFX9) {
2657 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2658 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2659 }
2660 surf->db_depth_view |= S_028008_MIPID(level);
2661 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2662 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2663
2664 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2665 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2666 S_028038_ALLOW_EXPCLEAR(1);
2667
2668 if (tex->tc_compatible_htile) {
2669 unsigned max_zplanes = 4;
2670
2671 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2672 tex->buffer.b.b.nr_samples > 1)
2673 max_zplanes = 2;
2674
2675 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2676
2677 if (sctx->chip_class >= GFX10) {
2678 z_info |= S_028040_ITERATE_FLUSH(1);
2679 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2680 } else {
2681 z_info |= S_028038_ITERATE_FLUSH(1);
2682 s_info |= S_02803C_ITERATE_FLUSH(1);
2683 }
2684 }
2685
2686 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2687 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2688 * See that for explanation.
2689 */
2690 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2691 } else {
2692 /* Use all HTILE for depth if there's no stencil. */
2693 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2694 }
2695
2696 surf->db_htile_data_base = (tex->buffer.gpu_address +
2697 tex->htile_offset) >> 8;
2698 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2699 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2700 if (sctx->chip_class == GFX9) {
2701 surf->db_htile_surface |=
2702 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2703 }
2704 }
2705 } else {
2706 /* GFX6-GFX8 */
2707 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2708
2709 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2710
2711 surf->db_depth_base = (tex->buffer.gpu_address +
2712 tex->surface.u.legacy.level[level].offset) >> 8;
2713 surf->db_stencil_base = (tex->buffer.gpu_address +
2714 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2715
2716 z_info = S_028040_FORMAT(format) |
2717 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2718 s_info = S_028044_FORMAT(stencil_format);
2719 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2720
2721 if (sctx->chip_class >= GFX7) {
2722 struct radeon_info *info = &sctx->screen->info;
2723 unsigned index = tex->surface.u.legacy.tiling_index[level];
2724 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2725 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2726 unsigned tile_mode = info->si_tile_mode_array[index];
2727 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2728 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2729
2730 surf->db_depth_info |=
2731 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2732 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2733 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2734 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2735 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2736 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2737 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2738 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2739 } else {
2740 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2741 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2742 tile_mode_index = si_tile_mode_index(tex, level, true);
2743 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2744 }
2745
2746 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2747 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2748 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2749 levelinfo->nblk_y) / 64 - 1);
2750
2751 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2752 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2753 S_028040_ALLOW_EXPCLEAR(1);
2754
2755 if (tex->surface.has_stencil) {
2756 /* Workaround: For a not yet understood reason, the
2757 * combination of MSAA, fast stencil clear and stencil
2758 * decompress messes with subsequent stencil buffer
2759 * uses. Problem was reproduced on Verde, Bonaire,
2760 * Tonga, and Carrizo.
2761 *
2762 * Disabling EXPCLEAR works around the problem.
2763 *
2764 * Check piglit's arb_texture_multisample-stencil-clear
2765 * test if you want to try changing this.
2766 */
2767 if (tex->buffer.b.b.nr_samples <= 1)
2768 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2769 } else if (!tex->tc_compatible_htile) {
2770 /* Use all of the htile_buffer for depth if there's no stencil.
2771 * This must not be set when TC-compatible HTILE is enabled
2772 * due to a hw bug.
2773 */
2774 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2775 }
2776
2777 surf->db_htile_data_base = (tex->buffer.gpu_address +
2778 tex->htile_offset) >> 8;
2779 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2780
2781 if (tex->tc_compatible_htile) {
2782 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2783
2784 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2785 if (tex->buffer.b.b.nr_samples <= 1)
2786 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2787 else if (tex->buffer.b.b.nr_samples <= 4)
2788 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2789 else
2790 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2791 }
2792 }
2793 }
2794
2795 surf->db_z_info = z_info;
2796 surf->db_stencil_info = s_info;
2797
2798 surf->depth_initialized = true;
2799 }
2800
2801 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2802 {
2803 if (sctx->decompression_enabled)
2804 return;
2805
2806 if (sctx->framebuffer.state.zsbuf) {
2807 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2808 struct si_texture *tex = (struct si_texture *)surf->texture;
2809
2810 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2811
2812 if (tex->surface.has_stencil)
2813 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2814 }
2815
2816 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2817 while (compressed_cb_mask) {
2818 unsigned i = u_bit_scan(&compressed_cb_mask);
2819 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2820 struct si_texture *tex = (struct si_texture*)surf->texture;
2821
2822 if (tex->fmask_offset)
2823 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2824 if (tex->dcc_gather_statistics)
2825 tex->separate_dcc_dirty = true;
2826 }
2827 }
2828
2829 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2830 {
2831 for (int i = 0; i < state->nr_cbufs; ++i) {
2832 struct si_surface *surf = NULL;
2833 struct si_texture *tex;
2834
2835 if (!state->cbufs[i])
2836 continue;
2837 surf = (struct si_surface*)state->cbufs[i];
2838 tex = (struct si_texture*)surf->base.texture;
2839
2840 p_atomic_dec(&tex->framebuffers_bound);
2841 }
2842 }
2843
2844 static void si_set_framebuffer_state(struct pipe_context *ctx,
2845 const struct pipe_framebuffer_state *state)
2846 {
2847 struct si_context *sctx = (struct si_context *)ctx;
2848 struct si_surface *surf = NULL;
2849 struct si_texture *tex;
2850 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2851 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2852 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2853 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2854 bool old_has_stencil =
2855 old_has_zsbuf &&
2856 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2857 bool unbound = false;
2858 int i;
2859
2860 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2861 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2862 * We could implement the full workaround here, but it's a useless case.
2863 */
2864 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2865 unreachable("the framebuffer shouldn't have zero area");
2866 return;
2867 }
2868
2869 si_update_fb_dirtiness_after_rendering(sctx);
2870
2871 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2872 if (!sctx->framebuffer.state.cbufs[i])
2873 continue;
2874
2875 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2876 if (tex->dcc_gather_statistics)
2877 vi_separate_dcc_stop_query(sctx, tex);
2878 }
2879
2880 /* Disable DCC if the formats are incompatible. */
2881 for (i = 0; i < state->nr_cbufs; i++) {
2882 if (!state->cbufs[i])
2883 continue;
2884
2885 surf = (struct si_surface*)state->cbufs[i];
2886 tex = (struct si_texture*)surf->base.texture;
2887
2888 if (!surf->dcc_incompatible)
2889 continue;
2890
2891 /* Since the DCC decompression calls back into set_framebuffer-
2892 * _state, we need to unbind the framebuffer, so that
2893 * vi_separate_dcc_stop_query isn't called twice with the same
2894 * color buffer.
2895 */
2896 if (!unbound) {
2897 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2898 unbound = true;
2899 }
2900
2901 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2902 if (!si_texture_disable_dcc(sctx, tex))
2903 si_decompress_dcc(sctx, tex);
2904
2905 surf->dcc_incompatible = false;
2906 }
2907
2908 /* Only flush TC when changing the framebuffer state, because
2909 * the only client not using TC that can change textures is
2910 * the framebuffer.
2911 *
2912 * Wait for compute shaders because of possible transitions:
2913 * - FB write -> shader read
2914 * - shader write -> FB read
2915 *
2916 * DB caches are flushed on demand (using si_decompress_textures).
2917 *
2918 * When MSAA is enabled, CB and TC caches are flushed on demand
2919 * (after FMASK decompression). Shader write -> FB read transitions
2920 * cannot happen for MSAA textures, because MSAA shader images are
2921 * not supported.
2922 *
2923 * Only flush and wait for CB if there is actually a bound color buffer.
2924 */
2925 if (sctx->framebuffer.uncompressed_cb_mask) {
2926 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2927 sctx->framebuffer.CB_has_shader_readable_metadata,
2928 sctx->framebuffer.all_DCC_pipe_aligned);
2929 }
2930
2931 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2932
2933 /* u_blitter doesn't invoke depth decompression when it does multiple
2934 * blits in a row, but the only case when it matters for DB is when
2935 * doing generate_mipmap. So here we flush DB manually between
2936 * individual generate_mipmap blits.
2937 * Note that lower mipmap levels aren't compressed.
2938 */
2939 if (sctx->generate_mipmap_for_depth) {
2940 si_make_DB_shader_coherent(sctx, 1, false,
2941 sctx->framebuffer.DB_has_shader_readable_metadata);
2942 } else if (sctx->chip_class == GFX9) {
2943 /* It appears that DB metadata "leaks" in a sequence of:
2944 * - depth clear
2945 * - DCC decompress for shader image writes (with DB disabled)
2946 * - render with DEPTH_BEFORE_SHADER=1
2947 * Flushing DB metadata works around the problem.
2948 */
2949 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2950 }
2951
2952 /* Take the maximum of the old and new count. If the new count is lower,
2953 * dirtying is needed to disable the unbound colorbuffers.
2954 */
2955 sctx->framebuffer.dirty_cbufs |=
2956 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2957 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2958
2959 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2960 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2961
2962 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2963 sctx->framebuffer.spi_shader_col_format = 0;
2964 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2965 sctx->framebuffer.spi_shader_col_format_blend = 0;
2966 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2967 sctx->framebuffer.color_is_int8 = 0;
2968 sctx->framebuffer.color_is_int10 = 0;
2969
2970 sctx->framebuffer.compressed_cb_mask = 0;
2971 sctx->framebuffer.uncompressed_cb_mask = 0;
2972 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2973 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2974 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2975 sctx->framebuffer.any_dst_linear = false;
2976 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2977 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2978 sctx->framebuffer.all_DCC_pipe_aligned = true;
2979 sctx->framebuffer.min_bytes_per_pixel = 0;
2980
2981 for (i = 0; i < state->nr_cbufs; i++) {
2982 if (!state->cbufs[i])
2983 continue;
2984
2985 surf = (struct si_surface*)state->cbufs[i];
2986 tex = (struct si_texture*)surf->base.texture;
2987
2988 if (!surf->color_initialized) {
2989 si_initialize_color_surface(sctx, surf);
2990 }
2991
2992 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2993 sctx->framebuffer.spi_shader_col_format |=
2994 surf->spi_shader_col_format << (i * 4);
2995 sctx->framebuffer.spi_shader_col_format_alpha |=
2996 surf->spi_shader_col_format_alpha << (i * 4);
2997 sctx->framebuffer.spi_shader_col_format_blend |=
2998 surf->spi_shader_col_format_blend << (i * 4);
2999 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
3000 surf->spi_shader_col_format_blend_alpha << (i * 4);
3001
3002 if (surf->color_is_int8)
3003 sctx->framebuffer.color_is_int8 |= 1 << i;
3004 if (surf->color_is_int10)
3005 sctx->framebuffer.color_is_int10 |= 1 << i;
3006
3007 if (tex->fmask_offset)
3008 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3009 else
3010 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3011
3012 /* Don't update nr_color_samples for non-AA buffers.
3013 * (e.g. destination of MSAA resolve)
3014 */
3015 if (tex->buffer.b.b.nr_samples >= 2 &&
3016 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3017 sctx->framebuffer.nr_color_samples =
3018 MIN2(sctx->framebuffer.nr_color_samples,
3019 tex->buffer.b.b.nr_storage_samples);
3020 sctx->framebuffer.nr_color_samples =
3021 MAX2(1, sctx->framebuffer.nr_color_samples);
3022 }
3023
3024 if (tex->surface.is_linear)
3025 sctx->framebuffer.any_dst_linear = true;
3026
3027 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3028 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3029
3030 if (sctx->chip_class >= GFX9 &&
3031 !tex->surface.u.gfx9.dcc.pipe_aligned)
3032 sctx->framebuffer.all_DCC_pipe_aligned = false;
3033 }
3034
3035 si_context_add_resource_size(sctx, surf->base.texture);
3036
3037 p_atomic_inc(&tex->framebuffers_bound);
3038
3039 if (tex->dcc_gather_statistics) {
3040 /* Dirty tracking must be enabled for DCC usage analysis. */
3041 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3042 vi_separate_dcc_start_query(sctx, tex);
3043 }
3044
3045 /* Update the minimum but don't keep 0. */
3046 if (!sctx->framebuffer.min_bytes_per_pixel ||
3047 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3048 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3049 }
3050
3051 /* For optimal DCC performance. */
3052 if (sctx->chip_class >= GFX10)
3053 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3054 else
3055 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3056
3057 struct si_texture *zstex = NULL;
3058
3059 if (state->zsbuf) {
3060 surf = (struct si_surface*)state->zsbuf;
3061 zstex = (struct si_texture*)surf->base.texture;
3062
3063 if (!surf->depth_initialized) {
3064 si_init_depth_surface(sctx, surf);
3065 }
3066
3067 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3068 PIPE_MASK_ZS))
3069 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3070
3071 si_context_add_resource_size(sctx, surf->base.texture);
3072
3073 /* Update the minimum but don't keep 0. */
3074 if (!sctx->framebuffer.min_bytes_per_pixel ||
3075 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3076 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
3077 }
3078
3079 si_update_ps_colorbuf0_slot(sctx);
3080 si_update_poly_offset_state(sctx);
3081 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3082 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3083
3084 if (sctx->screen->dpbb_allowed)
3085 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3086
3087 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3088 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3089
3090 if (sctx->screen->has_out_of_order_rast &&
3091 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3092 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3093 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3094 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3095
3096 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3097 struct pipe_constant_buffer constbuf = {0};
3098
3099 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3100 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3101
3102 constbuf.buffer = sctx->sample_pos_buffer;
3103
3104 /* Set sample locations as fragment shader constants. */
3105 switch (sctx->framebuffer.nr_samples) {
3106 case 1:
3107 constbuf.buffer_offset = 0;
3108 break;
3109 case 2:
3110 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3111 (ubyte*)sctx->sample_positions.x1;
3112 break;
3113 case 4:
3114 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3115 (ubyte*)sctx->sample_positions.x1;
3116 break;
3117 case 8:
3118 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3119 (ubyte*)sctx->sample_positions.x1;
3120 break;
3121 case 16:
3122 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3123 (ubyte*)sctx->sample_positions.x1;
3124 break;
3125 default:
3126 PRINT_ERR("Requested an invalid number of samples %i.\n",
3127 sctx->framebuffer.nr_samples);
3128 assert(0);
3129 }
3130 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3131 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3132
3133 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3134 }
3135
3136 sctx->do_update_shaders = true;
3137
3138 if (!sctx->decompression_enabled) {
3139 /* Prevent textures decompression when the framebuffer state
3140 * changes come from the decompression passes themselves.
3141 */
3142 sctx->need_check_render_feedback = true;
3143 }
3144 }
3145
3146 static void si_emit_framebuffer_state(struct si_context *sctx)
3147 {
3148 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3149 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3150 unsigned i, nr_cbufs = state->nr_cbufs;
3151 struct si_texture *tex = NULL;
3152 struct si_surface *cb = NULL;
3153 unsigned cb_color_info = 0;
3154
3155 /* Colorbuffers. */
3156 for (i = 0; i < nr_cbufs; i++) {
3157 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3158 unsigned cb_color_attrib;
3159
3160 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3161 continue;
3162
3163 cb = (struct si_surface*)state->cbufs[i];
3164 if (!cb) {
3165 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3166 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3167 continue;
3168 }
3169
3170 tex = (struct si_texture *)cb->base.texture;
3171 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3172 &tex->buffer, RADEON_USAGE_READWRITE,
3173 tex->buffer.b.b.nr_samples > 1 ?
3174 RADEON_PRIO_COLOR_BUFFER_MSAA :
3175 RADEON_PRIO_COLOR_BUFFER);
3176
3177 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3178 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3179 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3180 RADEON_PRIO_SEPARATE_META);
3181 }
3182
3183 if (tex->dcc_separate_buffer)
3184 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3185 tex->dcc_separate_buffer,
3186 RADEON_USAGE_READWRITE,
3187 RADEON_PRIO_SEPARATE_META);
3188
3189 /* Compute mutable surface parameters. */
3190 cb_color_base = tex->buffer.gpu_address >> 8;
3191 cb_color_fmask = 0;
3192 cb_color_cmask = tex->cmask_base_address_reg;
3193 cb_dcc_base = 0;
3194 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3195 cb_color_attrib = cb->cb_color_attrib;
3196
3197 if (cb->base.u.tex.level > 0)
3198 cb_color_info &= C_028C70_FAST_CLEAR;
3199
3200 if (tex->fmask_offset) {
3201 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3202 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3203 }
3204
3205 /* Set up DCC. */
3206 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3207 bool is_msaa_resolve_dst = state->cbufs[0] &&
3208 state->cbufs[0]->texture->nr_samples > 1 &&
3209 state->cbufs[1] == &cb->base &&
3210 state->cbufs[1]->texture->nr_samples <= 1;
3211
3212 if (!is_msaa_resolve_dst)
3213 cb_color_info |= S_028C70_DCC_ENABLE(1);
3214
3215 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3216 tex->dcc_offset) >> 8;
3217
3218 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3219 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3220 cb_dcc_base |= dcc_tile_swizzle;
3221 }
3222
3223 if (sctx->chip_class >= GFX10) {
3224 unsigned cb_color_attrib3;
3225
3226 /* Set mutable surface parameters. */
3227 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3228 cb_color_base |= tex->surface.tile_swizzle;
3229 if (!tex->fmask_offset)
3230 cb_color_fmask = cb_color_base;
3231 if (cb->base.u.tex.level > 0)
3232 cb_color_cmask = cb_color_base;
3233
3234 cb_color_attrib3 = cb->cb_color_attrib3 |
3235 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3236 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3237 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3238 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3239
3240 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3241 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3242 radeon_emit(cs, 0); /* hole */
3243 radeon_emit(cs, 0); /* hole */
3244 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3245 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3246 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3247 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3248 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3249 radeon_emit(cs, 0); /* hole */
3250 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3251 radeon_emit(cs, 0); /* hole */
3252 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3253 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3254 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3255
3256 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3257 cb_color_base >> 32);
3258 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3259 cb_color_cmask >> 32);
3260 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3261 cb_color_fmask >> 32);
3262 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3263 cb_dcc_base >> 32);
3264 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3265 cb->cb_color_attrib2);
3266 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3267 cb_color_attrib3);
3268 } else if (sctx->chip_class == GFX9) {
3269 struct gfx9_surf_meta_flags meta;
3270
3271 if (tex->dcc_offset)
3272 meta = tex->surface.u.gfx9.dcc;
3273 else
3274 meta = tex->surface.u.gfx9.cmask;
3275
3276 /* Set mutable surface parameters. */
3277 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3278 cb_color_base |= tex->surface.tile_swizzle;
3279 if (!tex->fmask_offset)
3280 cb_color_fmask = cb_color_base;
3281 if (cb->base.u.tex.level > 0)
3282 cb_color_cmask = cb_color_base;
3283 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3284 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3285 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3286 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3287
3288 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3289 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3290 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3291 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3292 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3293 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3294 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3295 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3296 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3297 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3298 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3299 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3300 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3301 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3302 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3303 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3304
3305 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3306 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3307 } else {
3308 /* Compute mutable surface parameters (GFX6-GFX8). */
3309 const struct legacy_surf_level *level_info =
3310 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3311 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3312 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3313
3314 cb_color_base += level_info->offset >> 8;
3315 /* Only macrotiled modes can set tile swizzle. */
3316 if (level_info->mode == RADEON_SURF_MODE_2D)
3317 cb_color_base |= tex->surface.tile_swizzle;
3318
3319 if (!tex->fmask_offset)
3320 cb_color_fmask = cb_color_base;
3321 if (cb->base.u.tex.level > 0)
3322 cb_color_cmask = cb_color_base;
3323 if (cb_dcc_base)
3324 cb_dcc_base += level_info->dcc_offset >> 8;
3325
3326 pitch_tile_max = level_info->nblk_x / 8 - 1;
3327 slice_tile_max = level_info->nblk_x *
3328 level_info->nblk_y / 64 - 1;
3329 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3330
3331 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3332 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3333 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3334
3335 if (tex->fmask_offset) {
3336 if (sctx->chip_class >= GFX7)
3337 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3338 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3339 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3340 } else {
3341 /* This must be set for fast clear to work without FMASK. */
3342 if (sctx->chip_class >= GFX7)
3343 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3344 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3345 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3346 }
3347
3348 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3349 sctx->chip_class >= GFX8 ? 14 : 13);
3350 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3351 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3352 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3353 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3354 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3355 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3356 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3357 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3358 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3359 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3360 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3361 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3362 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3363
3364 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3365 radeon_emit(cs, cb_dcc_base);
3366 }
3367 }
3368 for (; i < 8 ; i++)
3369 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3370 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3371
3372 /* ZS buffer. */
3373 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3374 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3375 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3376
3377 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3378 &tex->buffer, RADEON_USAGE_READWRITE,
3379 zb->base.texture->nr_samples > 1 ?
3380 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3381 RADEON_PRIO_DEPTH_BUFFER);
3382
3383 if (sctx->chip_class >= GFX10) {
3384 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3385 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3386
3387 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3388 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3389 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3390 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3391 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3392 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3393 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3394 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3395 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3396
3397 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3398 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3399 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3400 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3401 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3402 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3403 } else if (sctx->chip_class == GFX9) {
3404 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3405 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3406 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3407 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3408
3409 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3410 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3411 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3412 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3413 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3414 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3415 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3416 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3417 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3418 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3419 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3420 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3421
3422 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3423 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3424 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3425 } else {
3426 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3427
3428 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3429 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3430 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3431 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3432 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3433 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3434 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3435 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3436 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3437 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3438 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3439 }
3440
3441 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3442 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3443 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3444
3445 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3446 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3447 } else if (sctx->framebuffer.dirty_zsbuf) {
3448 if (sctx->chip_class == GFX9)
3449 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3450 else
3451 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3452
3453 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3454 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3455 }
3456
3457 /* Framebuffer dimensions. */
3458 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3459 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3460 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3461
3462 if (sctx->screen->dfsm_allowed) {
3463 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3464 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3465 }
3466
3467 sctx->framebuffer.dirty_cbufs = 0;
3468 sctx->framebuffer.dirty_zsbuf = false;
3469 }
3470
3471 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3472 {
3473 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3474 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3475 unsigned nr_samples = sctx->framebuffer.nr_samples;
3476 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3477
3478 /* Smoothing (only possible with nr_samples == 1) uses the same
3479 * sample locations as the MSAA it simulates.
3480 */
3481 if (nr_samples <= 1 && sctx->smoothing_enabled)
3482 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3483
3484 /* On Polaris, the small primitive filter uses the sample locations
3485 * even when MSAA is off, so we need to make sure they're set to 0.
3486 *
3487 * GFX10 uses sample locations unconditionally, so they always need
3488 * to be set up.
3489 */
3490 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3491 sctx->chip_class >= GFX10) &&
3492 nr_samples != sctx->sample_locs_num_samples) {
3493 sctx->sample_locs_num_samples = nr_samples;
3494 si_emit_sample_locations(cs, nr_samples);
3495 }
3496
3497 if (sctx->family >= CHIP_POLARIS10) {
3498 unsigned small_prim_filter_cntl =
3499 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3500 /* line bug */
3501 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3502
3503 /* The alternative of setting sample locations to 0 would
3504 * require a DB flush to avoid Z errors, see
3505 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3506 */
3507 if (has_msaa_sample_loc_bug &&
3508 sctx->framebuffer.nr_samples > 1 &&
3509 !rs->multisample_enable)
3510 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3511
3512 radeon_opt_set_context_reg(sctx,
3513 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3514 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3515 small_prim_filter_cntl);
3516 }
3517
3518 /* The exclusion bits can be set to improve rasterization efficiency
3519 * if no sample lies on the pixel boundary (-8 sample offset).
3520 */
3521 bool exclusion = sctx->chip_class >= GFX7 &&
3522 (!rs->multisample_enable || nr_samples != 16);
3523 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3524 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3525 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3526 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3527 }
3528
3529 static bool si_out_of_order_rasterization(struct si_context *sctx)
3530 {
3531 struct si_state_blend *blend = sctx->queued.named.blend;
3532 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3533
3534 if (!sctx->screen->has_out_of_order_rast)
3535 return false;
3536
3537 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3538
3539 colormask &= blend->cb_target_enabled_4bit;
3540
3541 /* Conservative: No logic op. */
3542 if (colormask && blend->logicop_enable)
3543 return false;
3544
3545 struct si_dsa_order_invariance dsa_order_invariant = {
3546 .zs = true, .pass_set = true, .pass_last = false
3547 };
3548
3549 if (sctx->framebuffer.state.zsbuf) {
3550 struct si_texture *zstex =
3551 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3552 bool has_stencil = zstex->surface.has_stencil;
3553 dsa_order_invariant = dsa->order_invariance[has_stencil];
3554 if (!dsa_order_invariant.zs)
3555 return false;
3556
3557 /* The set of PS invocations is always order invariant,
3558 * except when early Z/S tests are requested. */
3559 if (sctx->ps_shader.cso &&
3560 sctx->ps_shader.cso->info.writes_memory &&
3561 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3562 !dsa_order_invariant.pass_set)
3563 return false;
3564
3565 if (sctx->num_perfect_occlusion_queries != 0 &&
3566 !dsa_order_invariant.pass_set)
3567 return false;
3568 }
3569
3570 if (!colormask)
3571 return true;
3572
3573 unsigned blendmask = colormask & blend->blend_enable_4bit;
3574
3575 if (blendmask) {
3576 /* Only commutative blending. */
3577 if (blendmask & ~blend->commutative_4bit)
3578 return false;
3579
3580 if (!dsa_order_invariant.pass_set)
3581 return false;
3582 }
3583
3584 if (colormask & ~blendmask) {
3585 if (!dsa_order_invariant.pass_last)
3586 return false;
3587 }
3588
3589 return true;
3590 }
3591
3592 static void si_emit_msaa_config(struct si_context *sctx)
3593 {
3594 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3595 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3596 /* 33% faster rendering to linear color buffers */
3597 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3598 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3599 unsigned sc_mode_cntl_1 =
3600 S_028A4C_WALK_SIZE(dst_is_linear) |
3601 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3602 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3603 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3604 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3605 /* always 1: */
3606 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3607 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3608 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3609 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3610 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3611 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3612 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3613 S_028804_INCOHERENT_EQAA_READS(1) |
3614 S_028804_INTERPOLATE_COMP_Z(1) |
3615 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3616 unsigned coverage_samples, color_samples, z_samples;
3617 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3618
3619 /* S: Coverage samples (up to 16x):
3620 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3621 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3622 *
3623 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3624 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3625 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3626 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3627 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3628 * # Z samples).
3629 *
3630 * F: Color samples (up to 8x, must be <= coverage samples):
3631 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3632 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3633 *
3634 * Can be anything between coverage and color samples:
3635 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3636 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3637 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3638 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3639 * # All are currently set the same as coverage samples.
3640 *
3641 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3642 * flag for undefined color samples. A shader-based resolve must handle unknowns
3643 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3644 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3645 * useful. The CB resolve always drops unknowns.
3646 *
3647 * Sensible AA configurations:
3648 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3649 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3650 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3651 * EQAA 8s 8z 8f = 8x MSAA
3652 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3653 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3654 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3655 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3656 * EQAA 4s 4z 4f = 4x MSAA
3657 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3658 * EQAA 2s 2z 2f = 2x MSAA
3659 */
3660 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3661 coverage_samples = sctx->framebuffer.nr_samples;
3662 color_samples = sctx->framebuffer.nr_color_samples;
3663
3664 if (sctx->framebuffer.state.zsbuf) {
3665 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3666 z_samples = MAX2(1, z_samples);
3667 } else {
3668 z_samples = coverage_samples;
3669 }
3670 } else if (sctx->smoothing_enabled) {
3671 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3672 } else {
3673 coverage_samples = color_samples = z_samples = 1;
3674 }
3675
3676 /* Required by OpenGL line rasterization.
3677 *
3678 * TODO: We should also enable perpendicular endcaps for AA lines,
3679 * but that requires implementing line stippling in the pixel
3680 * shader. SC can only do line stippling with axis-aligned
3681 * endcaps.
3682 */
3683 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3684 unsigned sc_aa_config = 0;
3685
3686 if (coverage_samples > 1) {
3687 /* distance from the pixel center, indexed by log2(nr_samples) */
3688 static unsigned max_dist[] = {
3689 0, /* unused */
3690 4, /* 2x MSAA */
3691 6, /* 4x MSAA */
3692 7, /* 8x MSAA */
3693 8, /* 16x MSAA */
3694 };
3695 unsigned log_samples = util_logbase2(coverage_samples);
3696 unsigned log_z_samples = util_logbase2(z_samples);
3697 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3698 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3699
3700 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3701 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3702 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3703 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3704
3705 if (sctx->framebuffer.nr_samples > 1) {
3706 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3707 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3708 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3709 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3710 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3711 } else if (sctx->smoothing_enabled) {
3712 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3713 }
3714 }
3715
3716 unsigned initial_cdw = cs->current.cdw;
3717
3718 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3719 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3720 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3721 sc_aa_config);
3722 /* R_028804_DB_EQAA */
3723 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3724 db_eqaa);
3725 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3726 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3727 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3728
3729 if (initial_cdw != cs->current.cdw) {
3730 sctx->context_roll = true;
3731
3732 /* GFX9: Flush DFSM when the AA mode changes. */
3733 if (sctx->screen->dfsm_allowed) {
3734 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3735 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3736 }
3737 }
3738 }
3739
3740 void si_update_ps_iter_samples(struct si_context *sctx)
3741 {
3742 if (sctx->framebuffer.nr_samples > 1)
3743 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3744 if (sctx->screen->dpbb_allowed)
3745 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3746 }
3747
3748 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3749 {
3750 struct si_context *sctx = (struct si_context *)ctx;
3751
3752 /* The hardware can only do sample shading with 2^n samples. */
3753 min_samples = util_next_power_of_two(min_samples);
3754
3755 if (sctx->ps_iter_samples == min_samples)
3756 return;
3757
3758 sctx->ps_iter_samples = min_samples;
3759 sctx->do_update_shaders = true;
3760
3761 si_update_ps_iter_samples(sctx);
3762 }
3763
3764 /*
3765 * Samplers
3766 */
3767
3768 /**
3769 * Build the sampler view descriptor for a buffer texture.
3770 * @param state 256-bit descriptor; only the high 128 bits are filled in
3771 */
3772 void
3773 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3774 enum pipe_format format,
3775 unsigned offset, unsigned size,
3776 uint32_t *state)
3777 {
3778 const struct util_format_description *desc;
3779 unsigned stride;
3780 unsigned num_records;
3781
3782 desc = util_format_description(format);
3783 stride = desc->block.bits / 8;
3784
3785 num_records = size / stride;
3786 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3787
3788 /* The NUM_RECORDS field has a different meaning depending on the chip,
3789 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3790 *
3791 * GFX6-7,10:
3792 * - If STRIDE == 0, it's in byte units.
3793 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3794 *
3795 * GFX8:
3796 * - For SMEM and STRIDE == 0, it's in byte units.
3797 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3798 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3799 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3800 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3801 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3802 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3803 * That way the same descriptor can be used by both SMEM and VMEM.
3804 *
3805 * GFX9:
3806 * - For SMEM and STRIDE == 0, it's in byte units.
3807 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3808 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3809 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3810 */
3811 if (screen->info.chip_class == GFX9 && HAVE_LLVM < 0x0800)
3812 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3813 * from STRIDE to bytes. This works around it by setting
3814 * NUM_RECORDS to at least the size of one element, so that
3815 * the first element is readable when IDXEN == 0.
3816 */
3817 num_records = num_records ? MAX2(num_records, stride) : 0;
3818 else if (screen->info.chip_class == GFX8)
3819 num_records *= stride;
3820
3821 state[4] = 0;
3822 state[5] = S_008F04_STRIDE(stride);
3823 state[6] = num_records;
3824 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3825 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3826 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3827 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3828
3829 if (screen->info.chip_class >= GFX10) {
3830 const struct gfx10_format *fmt = &gfx10_format_table[format];
3831
3832 /* OOB_SELECT chooses the out-of-bounds check:
3833 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3834 * - 1: index >= NUM_RECORDS
3835 * - 2: NUM_RECORDS == 0
3836 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3837 * else: swizzle_address >= NUM_RECORDS
3838 */
3839 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3840 S_008F0C_OOB_SELECT(0) |
3841 S_008F0C_RESOURCE_LEVEL(1);
3842 } else {
3843 int first_non_void;
3844 unsigned num_format, data_format;
3845
3846 first_non_void = util_format_get_first_non_void_channel(format);
3847 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3848 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3849
3850 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3851 S_008F0C_DATA_FORMAT(data_format);
3852 }
3853 }
3854
3855 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3856 {
3857 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3858
3859 if (swizzle[3] == PIPE_SWIZZLE_X) {
3860 /* For the pre-defined border color values (white, opaque
3861 * black, transparent black), the only thing that matters is
3862 * that the alpha channel winds up in the correct place
3863 * (because the RGB channels are all the same) so either of
3864 * these enumerations will work.
3865 */
3866 if (swizzle[2] == PIPE_SWIZZLE_Y)
3867 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3868 else
3869 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3870 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3871 if (swizzle[1] == PIPE_SWIZZLE_Y)
3872 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3873 else
3874 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3875 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3876 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3877 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3878 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3879 }
3880
3881 return bc_swizzle;
3882 }
3883
3884 /**
3885 * Build the sampler view descriptor for a texture.
3886 */
3887 static void
3888 gfx10_make_texture_descriptor(struct si_screen *screen,
3889 struct si_texture *tex,
3890 bool sampler,
3891 enum pipe_texture_target target,
3892 enum pipe_format pipe_format,
3893 const unsigned char state_swizzle[4],
3894 unsigned first_level, unsigned last_level,
3895 unsigned first_layer, unsigned last_layer,
3896 unsigned width, unsigned height, unsigned depth,
3897 uint32_t *state,
3898 uint32_t *fmask_state)
3899 {
3900 struct pipe_resource *res = &tex->buffer.b.b;
3901 const struct util_format_description *desc;
3902 unsigned img_format;
3903 unsigned char swizzle[4];
3904 unsigned type;
3905 uint64_t va;
3906
3907 desc = util_format_description(pipe_format);
3908 img_format = gfx10_format_table[pipe_format].img_format;
3909
3910 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3911 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3912 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3913 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3914 bool is_stencil = false;
3915
3916 switch (pipe_format) {
3917 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3918 case PIPE_FORMAT_X32_S8X24_UINT:
3919 case PIPE_FORMAT_X8Z24_UNORM:
3920 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3921 is_stencil = true;
3922 break;
3923 case PIPE_FORMAT_X24S8_UINT:
3924 /*
3925 * X24S8 is implemented as an 8_8_8_8 data format, to
3926 * fix texture gathers. This affects at least
3927 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3928 */
3929 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3930 is_stencil = true;
3931 break;
3932 default:
3933 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3934 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3935 }
3936
3937 if (tex->upgraded_depth && !is_stencil) {
3938 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3939 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3940 }
3941 } else {
3942 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3943 }
3944
3945 if (!sampler &&
3946 (res->target == PIPE_TEXTURE_CUBE ||
3947 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3948 /* For the purpose of shader images, treat cube maps as 2D
3949 * arrays.
3950 */
3951 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3952 } else {
3953 type = si_tex_dim(screen, tex, target, res->nr_samples);
3954 }
3955
3956 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3957 height = 1;
3958 depth = res->array_size;
3959 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3960 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3961 if (sampler || res->target != PIPE_TEXTURE_3D)
3962 depth = res->array_size;
3963 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3964 depth = res->array_size / 6;
3965
3966 state[0] = 0;
3967 state[1] = S_00A004_FORMAT(img_format) |
3968 S_00A004_WIDTH_LO(width - 1);
3969 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3970 S_00A008_HEIGHT(height - 1) |
3971 S_00A008_RESOURCE_LEVEL(1);
3972 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3973 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3974 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3975 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3976 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3977 0 : first_level) |
3978 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3979 util_logbase2(res->nr_samples) :
3980 last_level) |
3981 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3982 S_00A00C_TYPE(type);
3983 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3984 * to know the total number of layers.
3985 */
3986 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3987 ? depth - 1 : last_layer) |
3988 S_00A010_BASE_ARRAY(first_layer);
3989 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3990 S_00A014_MAX_MIP(res->nr_samples > 1 ?
3991 util_logbase2(res->nr_samples) :
3992 tex->buffer.b.b.last_level) |
3993 S_00A014_PERF_MOD(4);
3994 state[6] = 0;
3995 state[7] = 0;
3996
3997 if (tex->dcc_offset) {
3998 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
3999 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
4000 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4001 }
4002
4003 /* Initialize the sampler view for FMASK. */
4004 if (tex->fmask_offset) {
4005 uint32_t format;
4006
4007 va = tex->buffer.gpu_address + tex->fmask_offset;
4008
4009 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4010 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4011 case FMASK(2,1):
4012 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4013 break;
4014 case FMASK(2,2):
4015 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4016 break;
4017 case FMASK(4,1):
4018 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4019 break;
4020 case FMASK(4,2):
4021 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4022 break;
4023 case FMASK(4,4):
4024 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4025 break;
4026 case FMASK(8,1):
4027 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4028 break;
4029 case FMASK(8,2):
4030 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4031 break;
4032 case FMASK(8,4):
4033 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4034 break;
4035 case FMASK(8,8):
4036 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4037 break;
4038 case FMASK(16,1):
4039 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4040 break;
4041 case FMASK(16,2):
4042 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4043 break;
4044 case FMASK(16,4):
4045 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4046 break;
4047 case FMASK(16,8):
4048 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4049 break;
4050 default:
4051 unreachable("invalid nr_samples");
4052 }
4053 #undef FMASK
4054 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4055 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4056 S_00A004_FORMAT(format) |
4057 S_00A004_WIDTH_LO(width - 1);
4058 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4059 S_00A008_HEIGHT(height - 1) |
4060 S_00A008_RESOURCE_LEVEL(1);
4061 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4062 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4063 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4064 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4065 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4066 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4067 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4068 S_00A010_BASE_ARRAY(first_layer);
4069 fmask_state[5] = 0;
4070 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4071 fmask_state[7] = 0;
4072 }
4073 }
4074
4075 /**
4076 * Build the sampler view descriptor for a texture (SI-GFX9).
4077 */
4078 static void
4079 si_make_texture_descriptor(struct si_screen *screen,
4080 struct si_texture *tex,
4081 bool sampler,
4082 enum pipe_texture_target target,
4083 enum pipe_format pipe_format,
4084 const unsigned char state_swizzle[4],
4085 unsigned first_level, unsigned last_level,
4086 unsigned first_layer, unsigned last_layer,
4087 unsigned width, unsigned height, unsigned depth,
4088 uint32_t *state,
4089 uint32_t *fmask_state)
4090 {
4091 struct pipe_resource *res = &tex->buffer.b.b;
4092 const struct util_format_description *desc;
4093 unsigned char swizzle[4];
4094 int first_non_void;
4095 unsigned num_format, data_format, type, num_samples;
4096 uint64_t va;
4097
4098 desc = util_format_description(pipe_format);
4099
4100 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4101 MAX2(1, res->nr_samples) :
4102 MAX2(1, res->nr_storage_samples);
4103
4104 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4105 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4106 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4107 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4108
4109 switch (pipe_format) {
4110 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4111 case PIPE_FORMAT_X32_S8X24_UINT:
4112 case PIPE_FORMAT_X8Z24_UNORM:
4113 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4114 break;
4115 case PIPE_FORMAT_X24S8_UINT:
4116 /*
4117 * X24S8 is implemented as an 8_8_8_8 data format, to
4118 * fix texture gathers. This affects at least
4119 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4120 */
4121 if (screen->info.chip_class <= GFX8)
4122 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4123 else
4124 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4125 break;
4126 default:
4127 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4128 }
4129 } else {
4130 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4131 }
4132
4133 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4134
4135 switch (pipe_format) {
4136 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4137 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4138 break;
4139 default:
4140 if (first_non_void < 0) {
4141 if (util_format_is_compressed(pipe_format)) {
4142 switch (pipe_format) {
4143 case PIPE_FORMAT_DXT1_SRGB:
4144 case PIPE_FORMAT_DXT1_SRGBA:
4145 case PIPE_FORMAT_DXT3_SRGBA:
4146 case PIPE_FORMAT_DXT5_SRGBA:
4147 case PIPE_FORMAT_BPTC_SRGBA:
4148 case PIPE_FORMAT_ETC2_SRGB8:
4149 case PIPE_FORMAT_ETC2_SRGB8A1:
4150 case PIPE_FORMAT_ETC2_SRGBA8:
4151 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4152 break;
4153 case PIPE_FORMAT_RGTC1_SNORM:
4154 case PIPE_FORMAT_LATC1_SNORM:
4155 case PIPE_FORMAT_RGTC2_SNORM:
4156 case PIPE_FORMAT_LATC2_SNORM:
4157 case PIPE_FORMAT_ETC2_R11_SNORM:
4158 case PIPE_FORMAT_ETC2_RG11_SNORM:
4159 /* implies float, so use SNORM/UNORM to determine
4160 whether data is signed or not */
4161 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4162 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4163 break;
4164 default:
4165 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4166 break;
4167 }
4168 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4169 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4170 } else {
4171 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4172 }
4173 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4174 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4175 } else {
4176 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4177
4178 switch (desc->channel[first_non_void].type) {
4179 case UTIL_FORMAT_TYPE_FLOAT:
4180 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4181 break;
4182 case UTIL_FORMAT_TYPE_SIGNED:
4183 if (desc->channel[first_non_void].normalized)
4184 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4185 else if (desc->channel[first_non_void].pure_integer)
4186 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4187 else
4188 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4189 break;
4190 case UTIL_FORMAT_TYPE_UNSIGNED:
4191 if (desc->channel[first_non_void].normalized)
4192 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4193 else if (desc->channel[first_non_void].pure_integer)
4194 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4195 else
4196 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4197 }
4198 }
4199 }
4200
4201 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4202 if (data_format == ~0) {
4203 data_format = 0;
4204 }
4205
4206 /* S8 with Z32 HTILE needs a special format. */
4207 if (screen->info.chip_class == GFX9 &&
4208 pipe_format == PIPE_FORMAT_S8_UINT &&
4209 tex->tc_compatible_htile)
4210 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4211
4212 if (!sampler &&
4213 (res->target == PIPE_TEXTURE_CUBE ||
4214 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4215 (screen->info.chip_class <= GFX8 &&
4216 res->target == PIPE_TEXTURE_3D))) {
4217 /* For the purpose of shader images, treat cube maps and 3D
4218 * textures as 2D arrays. For 3D textures, the address
4219 * calculations for mipmaps are different, so we rely on the
4220 * caller to effectively disable mipmaps.
4221 */
4222 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4223
4224 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4225 } else {
4226 type = si_tex_dim(screen, tex, target, num_samples);
4227 }
4228
4229 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4230 height = 1;
4231 depth = res->array_size;
4232 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4233 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4234 if (sampler || res->target != PIPE_TEXTURE_3D)
4235 depth = res->array_size;
4236 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4237 depth = res->array_size / 6;
4238
4239 state[0] = 0;
4240 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4241 S_008F14_NUM_FORMAT(num_format));
4242 state[2] = (S_008F18_WIDTH(width - 1) |
4243 S_008F18_HEIGHT(height - 1) |
4244 S_008F18_PERF_MOD(4));
4245 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4246 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4247 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4248 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4249 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4250 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4251 util_logbase2(num_samples) :
4252 last_level) |
4253 S_008F1C_TYPE(type));
4254 state[4] = 0;
4255 state[5] = S_008F24_BASE_ARRAY(first_layer);
4256 state[6] = 0;
4257 state[7] = 0;
4258
4259 if (screen->info.chip_class == GFX9) {
4260 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4261
4262 /* Depth is the the last accessible layer on Gfx9.
4263 * The hw doesn't need to know the total number of layers.
4264 */
4265 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4266 state[4] |= S_008F20_DEPTH(depth - 1);
4267 else
4268 state[4] |= S_008F20_DEPTH(last_layer);
4269
4270 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4271 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4272 util_logbase2(num_samples) :
4273 tex->buffer.b.b.last_level);
4274 } else {
4275 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4276 state[4] |= S_008F20_DEPTH(depth - 1);
4277 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4278 }
4279
4280 if (tex->dcc_offset) {
4281 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4282 } else {
4283 /* The last dword is unused by hw. The shader uses it to clear
4284 * bits in the first dword of sampler state.
4285 */
4286 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4287 if (first_level == last_level)
4288 state[7] = C_008F30_MAX_ANISO_RATIO;
4289 else
4290 state[7] = 0xffffffff;
4291 }
4292 }
4293
4294 /* Initialize the sampler view for FMASK. */
4295 if (tex->fmask_offset) {
4296 uint32_t data_format, num_format;
4297
4298 va = tex->buffer.gpu_address + tex->fmask_offset;
4299
4300 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4301 if (screen->info.chip_class == GFX9) {
4302 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4303 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4304 case FMASK(2,1):
4305 num_format = V_008F14_IMG_FMASK_8_2_1;
4306 break;
4307 case FMASK(2,2):
4308 num_format = V_008F14_IMG_FMASK_8_2_2;
4309 break;
4310 case FMASK(4,1):
4311 num_format = V_008F14_IMG_FMASK_8_4_1;
4312 break;
4313 case FMASK(4,2):
4314 num_format = V_008F14_IMG_FMASK_8_4_2;
4315 break;
4316 case FMASK(4,4):
4317 num_format = V_008F14_IMG_FMASK_8_4_4;
4318 break;
4319 case FMASK(8,1):
4320 num_format = V_008F14_IMG_FMASK_8_8_1;
4321 break;
4322 case FMASK(8,2):
4323 num_format = V_008F14_IMG_FMASK_16_8_2;
4324 break;
4325 case FMASK(8,4):
4326 num_format = V_008F14_IMG_FMASK_32_8_4;
4327 break;
4328 case FMASK(8,8):
4329 num_format = V_008F14_IMG_FMASK_32_8_8;
4330 break;
4331 case FMASK(16,1):
4332 num_format = V_008F14_IMG_FMASK_16_16_1;
4333 break;
4334 case FMASK(16,2):
4335 num_format = V_008F14_IMG_FMASK_32_16_2;
4336 break;
4337 case FMASK(16,4):
4338 num_format = V_008F14_IMG_FMASK_64_16_4;
4339 break;
4340 case FMASK(16,8):
4341 num_format = V_008F14_IMG_FMASK_64_16_8;
4342 break;
4343 default:
4344 unreachable("invalid nr_samples");
4345 }
4346 } else {
4347 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4348 case FMASK(2,1):
4349 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4350 break;
4351 case FMASK(2,2):
4352 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4353 break;
4354 case FMASK(4,1):
4355 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4356 break;
4357 case FMASK(4,2):
4358 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4359 break;
4360 case FMASK(4,4):
4361 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4362 break;
4363 case FMASK(8,1):
4364 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4365 break;
4366 case FMASK(8,2):
4367 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4368 break;
4369 case FMASK(8,4):
4370 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4371 break;
4372 case FMASK(8,8):
4373 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4374 break;
4375 case FMASK(16,1):
4376 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4377 break;
4378 case FMASK(16,2):
4379 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4380 break;
4381 case FMASK(16,4):
4382 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4383 break;
4384 case FMASK(16,8):
4385 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4386 break;
4387 default:
4388 unreachable("invalid nr_samples");
4389 }
4390 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4391 }
4392 #undef FMASK
4393
4394 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4395 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4396 S_008F14_DATA_FORMAT(data_format) |
4397 S_008F14_NUM_FORMAT(num_format);
4398 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4399 S_008F18_HEIGHT(height - 1);
4400 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4401 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4402 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4403 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4404 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4405 fmask_state[4] = 0;
4406 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4407 fmask_state[6] = 0;
4408 fmask_state[7] = 0;
4409
4410 if (screen->info.chip_class == GFX9) {
4411 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4412 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4413 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4414 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4415 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4416 } else {
4417 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4418 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4419 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4420 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4421 }
4422 }
4423 }
4424
4425 /**
4426 * Create a sampler view.
4427 *
4428 * @param ctx context
4429 * @param texture texture
4430 * @param state sampler view template
4431 * @param width0 width0 override (for compressed textures as int)
4432 * @param height0 height0 override (for compressed textures as int)
4433 * @param force_level set the base address to the level (for compressed textures)
4434 */
4435 struct pipe_sampler_view *
4436 si_create_sampler_view_custom(struct pipe_context *ctx,
4437 struct pipe_resource *texture,
4438 const struct pipe_sampler_view *state,
4439 unsigned width0, unsigned height0,
4440 unsigned force_level)
4441 {
4442 struct si_context *sctx = (struct si_context*)ctx;
4443 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4444 struct si_texture *tex = (struct si_texture*)texture;
4445 unsigned base_level, first_level, last_level;
4446 unsigned char state_swizzle[4];
4447 unsigned height, depth, width;
4448 unsigned last_layer = state->u.tex.last_layer;
4449 enum pipe_format pipe_format;
4450 const struct legacy_surf_level *surflevel;
4451
4452 if (!view)
4453 return NULL;
4454
4455 /* initialize base object */
4456 view->base = *state;
4457 view->base.texture = NULL;
4458 view->base.reference.count = 1;
4459 view->base.context = ctx;
4460
4461 assert(texture);
4462 pipe_resource_reference(&view->base.texture, texture);
4463
4464 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4465 state->format == PIPE_FORMAT_S8X24_UINT ||
4466 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4467 state->format == PIPE_FORMAT_S8_UINT)
4468 view->is_stencil_sampler = true;
4469
4470 /* Buffer resource. */
4471 if (texture->target == PIPE_BUFFER) {
4472 si_make_buffer_descriptor(sctx->screen,
4473 si_resource(texture),
4474 state->format,
4475 state->u.buf.offset,
4476 state->u.buf.size,
4477 view->state);
4478 return &view->base;
4479 }
4480
4481 state_swizzle[0] = state->swizzle_r;
4482 state_swizzle[1] = state->swizzle_g;
4483 state_swizzle[2] = state->swizzle_b;
4484 state_swizzle[3] = state->swizzle_a;
4485
4486 base_level = 0;
4487 first_level = state->u.tex.first_level;
4488 last_level = state->u.tex.last_level;
4489 width = width0;
4490 height = height0;
4491 depth = texture->depth0;
4492
4493 if (sctx->chip_class <= GFX8 && force_level) {
4494 assert(force_level == first_level &&
4495 force_level == last_level);
4496 base_level = force_level;
4497 first_level = 0;
4498 last_level = 0;
4499 width = u_minify(width, force_level);
4500 height = u_minify(height, force_level);
4501 depth = u_minify(depth, force_level);
4502 }
4503
4504 /* This is not needed if state trackers set last_layer correctly. */
4505 if (state->target == PIPE_TEXTURE_1D ||
4506 state->target == PIPE_TEXTURE_2D ||
4507 state->target == PIPE_TEXTURE_RECT ||
4508 state->target == PIPE_TEXTURE_CUBE)
4509 last_layer = state->u.tex.first_layer;
4510
4511 /* Texturing with separate depth and stencil. */
4512 pipe_format = state->format;
4513
4514 /* Depth/stencil texturing sometimes needs separate texture. */
4515 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4516 if (!tex->flushed_depth_texture &&
4517 !si_init_flushed_depth_texture(ctx, texture)) {
4518 pipe_resource_reference(&view->base.texture, NULL);
4519 FREE(view);
4520 return NULL;
4521 }
4522
4523 assert(tex->flushed_depth_texture);
4524
4525 /* Override format for the case where the flushed texture
4526 * contains only Z or only S.
4527 */
4528 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4529 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4530
4531 tex = tex->flushed_depth_texture;
4532 }
4533
4534 surflevel = tex->surface.u.legacy.level;
4535
4536 if (tex->db_compatible) {
4537 if (!view->is_stencil_sampler)
4538 pipe_format = tex->db_render_format;
4539
4540 switch (pipe_format) {
4541 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4542 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4543 break;
4544 case PIPE_FORMAT_X8Z24_UNORM:
4545 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4546 /* Z24 is always stored like this for DB
4547 * compatibility.
4548 */
4549 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4550 break;
4551 case PIPE_FORMAT_X24S8_UINT:
4552 case PIPE_FORMAT_S8X24_UINT:
4553 case PIPE_FORMAT_X32_S8X24_UINT:
4554 pipe_format = PIPE_FORMAT_S8_UINT;
4555 surflevel = tex->surface.u.legacy.stencil_level;
4556 break;
4557 default:;
4558 }
4559 }
4560
4561 view->dcc_incompatible =
4562 vi_dcc_formats_are_incompatible(texture,
4563 state->u.tex.first_level,
4564 state->format);
4565
4566 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4567 state->target, pipe_format, state_swizzle,
4568 first_level, last_level,
4569 state->u.tex.first_layer, last_layer,
4570 width, height, depth,
4571 view->state, view->fmask_state);
4572
4573 const struct util_format_description *desc = util_format_description(pipe_format);
4574 view->is_integer = false;
4575
4576 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4577 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4578 continue;
4579
4580 /* Whether the number format is {U,S}{SCALED,INT} */
4581 view->is_integer =
4582 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4583 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4584 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4585 break;
4586 }
4587
4588 view->base_level_info = &surflevel[base_level];
4589 view->base_level = base_level;
4590 view->block_width = util_format_get_blockwidth(pipe_format);
4591 return &view->base;
4592 }
4593
4594 static struct pipe_sampler_view *
4595 si_create_sampler_view(struct pipe_context *ctx,
4596 struct pipe_resource *texture,
4597 const struct pipe_sampler_view *state)
4598 {
4599 return si_create_sampler_view_custom(ctx, texture, state,
4600 texture ? texture->width0 : 0,
4601 texture ? texture->height0 : 0, 0);
4602 }
4603
4604 static void si_sampler_view_destroy(struct pipe_context *ctx,
4605 struct pipe_sampler_view *state)
4606 {
4607 struct si_sampler_view *view = (struct si_sampler_view *)state;
4608
4609 pipe_resource_reference(&state->texture, NULL);
4610 FREE(view);
4611 }
4612
4613 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4614 {
4615 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4616 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4617 (linear_filter &&
4618 (wrap == PIPE_TEX_WRAP_CLAMP ||
4619 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4620 }
4621
4622 static uint32_t si_translate_border_color(struct si_context *sctx,
4623 const struct pipe_sampler_state *state,
4624 const union pipe_color_union *color,
4625 bool is_integer)
4626 {
4627 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4628 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4629
4630 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4631 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4632 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4633 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4634
4635 #define simple_border_types(elt) \
4636 do { \
4637 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4638 color->elt[2] == 0 && color->elt[3] == 0) \
4639 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4640 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4641 color->elt[2] == 0 && color->elt[3] == 1) \
4642 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4643 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4644 color->elt[2] == 1 && color->elt[3] == 1) \
4645 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4646 } while (false)
4647
4648 if (is_integer)
4649 simple_border_types(ui);
4650 else
4651 simple_border_types(f);
4652
4653 #undef simple_border_types
4654
4655 int i;
4656
4657 /* Check if the border has been uploaded already. */
4658 for (i = 0; i < sctx->border_color_count; i++)
4659 if (memcmp(&sctx->border_color_table[i], color,
4660 sizeof(*color)) == 0)
4661 break;
4662
4663 if (i >= SI_MAX_BORDER_COLORS) {
4664 /* Getting 4096 unique border colors is very unlikely. */
4665 fprintf(stderr, "radeonsi: The border color table is full. "
4666 "Any new border colors will be just black. "
4667 "Please file a bug.\n");
4668 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4669 }
4670
4671 if (i == sctx->border_color_count) {
4672 /* Upload a new border color. */
4673 memcpy(&sctx->border_color_table[i], color,
4674 sizeof(*color));
4675 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4676 color, sizeof(*color));
4677 sctx->border_color_count++;
4678 }
4679
4680 return S_008F3C_BORDER_COLOR_PTR(i) |
4681 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4682 }
4683
4684 static inline int S_FIXED(float value, unsigned frac_bits)
4685 {
4686 return value * (1 << frac_bits);
4687 }
4688
4689 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4690 {
4691 if (filter == PIPE_TEX_FILTER_LINEAR)
4692 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4693 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4694 else
4695 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4696 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4697 }
4698
4699 static inline unsigned si_tex_aniso_filter(unsigned filter)
4700 {
4701 if (filter < 2)
4702 return 0;
4703 if (filter < 4)
4704 return 1;
4705 if (filter < 8)
4706 return 2;
4707 if (filter < 16)
4708 return 3;
4709 return 4;
4710 }
4711
4712 static void *si_create_sampler_state(struct pipe_context *ctx,
4713 const struct pipe_sampler_state *state)
4714 {
4715 struct si_context *sctx = (struct si_context *)ctx;
4716 struct si_screen *sscreen = sctx->screen;
4717 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4718 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4719 : state->max_anisotropy;
4720 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4721 union pipe_color_union clamped_border_color;
4722
4723 if (!rstate) {
4724 return NULL;
4725 }
4726
4727 #ifndef NDEBUG
4728 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4729 #endif
4730 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4731 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4732 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4733 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4734 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4735 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4736 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4737 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4738 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4739 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4740 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4741 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4742 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4743 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4744 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4745 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4746 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4747 S_008F38_MIP_POINT_PRECLAMP(0));
4748 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4749
4750 if (sscreen->info.chip_class >= GFX10) {
4751 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4752 } else {
4753 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4754 S_008F38_FILTER_PREC_FIX(1) |
4755 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4756 }
4757
4758 /* Create sampler resource for integer textures. */
4759 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4760 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4761
4762 /* Create sampler resource for upgraded depth textures. */
4763 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4764
4765 for (unsigned i = 0; i < 4; ++i) {
4766 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4767 * when the border color is 1.0. */
4768 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4769 }
4770
4771 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4772 if (sscreen->info.chip_class <= GFX9)
4773 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4774 } else {
4775 rstate->upgraded_depth_val[3] =
4776 si_translate_border_color(sctx, state, &clamped_border_color, false);
4777 }
4778
4779 return rstate;
4780 }
4781
4782 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4783 {
4784 struct si_context *sctx = (struct si_context *)ctx;
4785
4786 if (sctx->sample_mask == (uint16_t)sample_mask)
4787 return;
4788
4789 sctx->sample_mask = sample_mask;
4790 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4791 }
4792
4793 static void si_emit_sample_mask(struct si_context *sctx)
4794 {
4795 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4796 unsigned mask = sctx->sample_mask;
4797
4798 /* Needed for line and polygon smoothing as well as for the Polaris
4799 * small primitive filter. We expect the state tracker to take care of
4800 * this for us.
4801 */
4802 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4803 (mask & 1 && sctx->blitter->running));
4804
4805 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4806 radeon_emit(cs, mask | (mask << 16));
4807 radeon_emit(cs, mask | (mask << 16));
4808 }
4809
4810 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4811 {
4812 #ifndef NDEBUG
4813 struct si_sampler_state *s = state;
4814
4815 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4816 s->magic = 0;
4817 #endif
4818 free(state);
4819 }
4820
4821 /*
4822 * Vertex elements & buffers
4823 */
4824
4825 struct si_fast_udiv_info32
4826 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4827 {
4828 struct util_fast_udiv_info info =
4829 util_compute_fast_udiv_info(D, num_bits, 32);
4830
4831 struct si_fast_udiv_info32 result = {
4832 info.multiplier,
4833 info.pre_shift,
4834 info.post_shift,
4835 info.increment,
4836 };
4837 return result;
4838 }
4839
4840 static void *si_create_vertex_elements(struct pipe_context *ctx,
4841 unsigned count,
4842 const struct pipe_vertex_element *elements)
4843 {
4844 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4845 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4846 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4847 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4848 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4849 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4850 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4851 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4852 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4853 int i;
4854
4855 assert(count <= SI_MAX_ATTRIBS);
4856 if (!v)
4857 return NULL;
4858
4859 v->count = count;
4860 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4861
4862 for (i = 0; i < count; ++i) {
4863 const struct util_format_description *desc;
4864 const struct util_format_channel_description *channel;
4865 int first_non_void;
4866 unsigned vbo_index = elements[i].vertex_buffer_index;
4867
4868 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4869 FREE(v);
4870 return NULL;
4871 }
4872
4873 unsigned instance_divisor = elements[i].instance_divisor;
4874 if (instance_divisor) {
4875 v->uses_instance_divisors = true;
4876
4877 if (instance_divisor == 1) {
4878 v->instance_divisor_is_one |= 1u << i;
4879 } else {
4880 v->instance_divisor_is_fetched |= 1u << i;
4881 divisor_factors[i] =
4882 si_compute_fast_udiv_info32(instance_divisor, 32);
4883 }
4884 }
4885
4886 if (!used[vbo_index]) {
4887 v->first_vb_use_mask |= 1 << i;
4888 used[vbo_index] = true;
4889 }
4890
4891 desc = util_format_description(elements[i].src_format);
4892 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4893 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4894
4895 v->format_size[i] = desc->block.bits / 8;
4896 v->src_offset[i] = elements[i].src_offset;
4897 v->vertex_buffer_index[i] = vbo_index;
4898
4899 bool always_fix = false;
4900 union si_vs_fix_fetch fix_fetch;
4901 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4902
4903 fix_fetch.bits = 0;
4904 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4905
4906 if (channel) {
4907 switch (channel->type) {
4908 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4909 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4910 case UTIL_FORMAT_TYPE_SIGNED: {
4911 if (channel->pure_integer)
4912 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4913 else if (channel->normalized)
4914 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4915 else
4916 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4917 break;
4918 }
4919 case UTIL_FORMAT_TYPE_UNSIGNED: {
4920 if (channel->pure_integer)
4921 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4922 else if (channel->normalized)
4923 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4924 else
4925 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4926 break;
4927 }
4928 default: unreachable("bad format type");
4929 }
4930 } else {
4931 switch (elements[i].src_format) {
4932 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4933 default: unreachable("bad other format");
4934 }
4935 }
4936
4937 if (desc->channel[0].size == 10) {
4938 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4939 log_hw_load_size = 2;
4940
4941 /* The hardware always treats the 2-bit alpha channel as
4942 * unsigned, so a shader workaround is needed. The affected
4943 * chips are GFX8 and older except Stoney (GFX8.1).
4944 */
4945 always_fix = sscreen->info.chip_class <= GFX8 &&
4946 sscreen->info.family != CHIP_STONEY &&
4947 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4948 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4949 fix_fetch.u.log_size = 3; /* special encoding */
4950 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4951 log_hw_load_size = 2;
4952 } else {
4953 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4954 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4955
4956 /* Always fix up:
4957 * - doubles (multiple loads + truncate to float)
4958 * - 32-bit requiring a conversion
4959 */
4960 always_fix =
4961 (fix_fetch.u.log_size == 3) ||
4962 (fix_fetch.u.log_size == 2 &&
4963 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4964 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4965 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4966
4967 /* Also fixup 8_8_8 and 16_16_16. */
4968 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4969 always_fix = true;
4970 log_hw_load_size = fix_fetch.u.log_size;
4971 }
4972 }
4973
4974 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4975 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4976 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4977 fix_fetch.u.reverse = 1;
4978 }
4979
4980 /* Force the workaround for unaligned access here already if the
4981 * offset relative to the vertex buffer base is unaligned.
4982 *
4983 * There is a theoretical case in which this is too conservative:
4984 * if the vertex buffer's offset is also unaligned in just the
4985 * right way, we end up with an aligned address after all.
4986 * However, this case should be extremely rare in practice (it
4987 * won't happen in well-behaved applications), and taking it
4988 * into account would complicate the fast path (where everything
4989 * is nicely aligned).
4990 */
4991 bool check_alignment =
4992 log_hw_load_size >= 1 &&
4993 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
4994 bool opencode = sscreen->options.vs_fetch_always_opencode;
4995
4996 if (check_alignment &&
4997 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4998 opencode = true;
4999
5000 if (always_fix || check_alignment || opencode)
5001 v->fix_fetch[i] = fix_fetch.bits;
5002
5003 if (opencode)
5004 v->fix_fetch_opencode |= 1 << i;
5005 if (opencode || always_fix)
5006 v->fix_fetch_always |= 1 << i;
5007
5008 if (check_alignment && !opencode) {
5009 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5010
5011 v->fix_fetch_unaligned |= 1 << i;
5012 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5013 v->vb_alignment_check_mask |= 1 << vbo_index;
5014 }
5015
5016 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5017 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5018 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5019 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5020
5021 if (sscreen->info.chip_class >= GFX10) {
5022 const struct gfx10_format *fmt =
5023 &gfx10_format_table[elements[i].src_format];
5024 assert(fmt->img_format != 0 && fmt->img_format < 128);
5025 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5026 S_008F0C_RESOURCE_LEVEL(1);
5027 } else {
5028 unsigned data_format, num_format;
5029 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5030 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5031 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5032 S_008F0C_DATA_FORMAT(data_format);
5033 }
5034 }
5035
5036 if (v->instance_divisor_is_fetched) {
5037 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5038
5039 v->instance_divisor_factor_buffer =
5040 (struct si_resource*)
5041 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5042 num_divisors * sizeof(divisor_factors[0]));
5043 if (!v->instance_divisor_factor_buffer) {
5044 FREE(v);
5045 return NULL;
5046 }
5047 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5048 NULL, PIPE_TRANSFER_WRITE);
5049 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5050 }
5051 return v;
5052 }
5053
5054 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5055 {
5056 struct si_context *sctx = (struct si_context *)ctx;
5057 struct si_vertex_elements *old = sctx->vertex_elements;
5058 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5059
5060 sctx->vertex_elements = v;
5061 sctx->vertex_buffers_dirty = true;
5062
5063 if (v &&
5064 (!old ||
5065 old->count != v->count ||
5066 old->uses_instance_divisors != v->uses_instance_divisors ||
5067 /* we don't check which divisors changed */
5068 v->uses_instance_divisors ||
5069 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5070 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5071 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5072 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5073 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5074 * functions of fix_fetch and the src_offset alignment.
5075 * If they change and fix_fetch doesn't, it must be due to different
5076 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5077 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5078 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5079 sctx->do_update_shaders = true;
5080
5081 if (v && v->instance_divisor_is_fetched) {
5082 struct pipe_constant_buffer cb;
5083
5084 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5085 cb.user_buffer = NULL;
5086 cb.buffer_offset = 0;
5087 cb.buffer_size = 0xffffffff;
5088 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5089 }
5090 }
5091
5092 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5093 {
5094 struct si_context *sctx = (struct si_context *)ctx;
5095 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5096
5097 if (sctx->vertex_elements == state)
5098 sctx->vertex_elements = NULL;
5099 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5100 FREE(state);
5101 }
5102
5103 static void si_set_vertex_buffers(struct pipe_context *ctx,
5104 unsigned start_slot, unsigned count,
5105 const struct pipe_vertex_buffer *buffers)
5106 {
5107 struct si_context *sctx = (struct si_context *)ctx;
5108 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5109 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5110 uint32_t unaligned = orig_unaligned;
5111 int i;
5112
5113 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5114
5115 if (buffers) {
5116 for (i = 0; i < count; i++) {
5117 const struct pipe_vertex_buffer *src = buffers + i;
5118 struct pipe_vertex_buffer *dsti = dst + i;
5119 struct pipe_resource *buf = src->buffer.resource;
5120
5121 pipe_resource_reference(&dsti->buffer.resource, buf);
5122 dsti->buffer_offset = src->buffer_offset;
5123 dsti->stride = src->stride;
5124 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5125 unaligned |= 1 << (start_slot + i);
5126 else
5127 unaligned &= ~(1 << (start_slot + i));
5128
5129 si_context_add_resource_size(sctx, buf);
5130 if (buf)
5131 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5132 }
5133 } else {
5134 for (i = 0; i < count; i++) {
5135 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5136 }
5137 unaligned &= ~u_bit_consecutive(start_slot, count);
5138 }
5139 sctx->vertex_buffers_dirty = true;
5140 sctx->vertex_buffer_unaligned = unaligned;
5141
5142 /* Check whether alignment may have changed in a way that requires
5143 * shader changes. This check is conservative: a vertex buffer can only
5144 * trigger a shader change if the misalignment amount changes (e.g.
5145 * from byte-aligned to short-aligned), but we only keep track of
5146 * whether buffers are at least dword-aligned, since that should always
5147 * be the case in well-behaved applications anyway.
5148 */
5149 if (sctx->vertex_elements &&
5150 (sctx->vertex_elements->vb_alignment_check_mask &
5151 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5152 sctx->do_update_shaders = true;
5153 }
5154
5155 /*
5156 * Misc
5157 */
5158
5159 static void si_set_tess_state(struct pipe_context *ctx,
5160 const float default_outer_level[4],
5161 const float default_inner_level[2])
5162 {
5163 struct si_context *sctx = (struct si_context *)ctx;
5164 struct pipe_constant_buffer cb;
5165 float array[8];
5166
5167 memcpy(array, default_outer_level, sizeof(float) * 4);
5168 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5169
5170 cb.buffer = NULL;
5171 cb.user_buffer = NULL;
5172 cb.buffer_size = sizeof(array);
5173
5174 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5175 (void*)array, sizeof(array),
5176 &cb.buffer_offset);
5177
5178 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5179 pipe_resource_reference(&cb.buffer, NULL);
5180 }
5181
5182 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5183 {
5184 struct si_context *sctx = (struct si_context *)ctx;
5185
5186 si_update_fb_dirtiness_after_rendering(sctx);
5187
5188 /* Multisample surfaces are flushed in si_decompress_textures. */
5189 if (sctx->framebuffer.uncompressed_cb_mask) {
5190 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5191 sctx->framebuffer.CB_has_shader_readable_metadata,
5192 sctx->framebuffer.all_DCC_pipe_aligned);
5193 }
5194 }
5195
5196 /* This only ensures coherency for shader image/buffer stores. */
5197 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5198 {
5199 struct si_context *sctx = (struct si_context *)ctx;
5200
5201 if (!(flags & ~PIPE_BARRIER_UPDATE))
5202 return;
5203
5204 /* Subsequent commands must wait for all shader invocations to
5205 * complete. */
5206 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5207 SI_CONTEXT_CS_PARTIAL_FLUSH;
5208
5209 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5210 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5211 SI_CONTEXT_INV_VCACHE;
5212
5213 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5214 PIPE_BARRIER_SHADER_BUFFER |
5215 PIPE_BARRIER_TEXTURE |
5216 PIPE_BARRIER_IMAGE |
5217 PIPE_BARRIER_STREAMOUT_BUFFER |
5218 PIPE_BARRIER_GLOBAL_BUFFER)) {
5219 /* As far as I can tell, L1 contents are written back to L2
5220 * automatically at end of shader, but the contents of other
5221 * L1 caches might still be stale. */
5222 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5223 }
5224
5225 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5226 /* Indices are read through TC L2 since GFX8.
5227 * L1 isn't used.
5228 */
5229 if (sctx->screen->info.chip_class <= GFX7)
5230 sctx->flags |= SI_CONTEXT_WB_L2;
5231 }
5232
5233 /* MSAA color, any depth and any stencil are flushed in
5234 * si_decompress_textures when needed.
5235 */
5236 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5237 sctx->framebuffer.uncompressed_cb_mask) {
5238 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5239
5240 if (sctx->chip_class <= GFX8)
5241 sctx->flags |= SI_CONTEXT_WB_L2;
5242 }
5243
5244 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5245 if (sctx->screen->info.chip_class <= GFX8 &&
5246 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5247 sctx->flags |= SI_CONTEXT_WB_L2;
5248 }
5249
5250 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5251 {
5252 struct pipe_blend_state blend;
5253
5254 memset(&blend, 0, sizeof(blend));
5255 blend.independent_blend_enable = true;
5256 blend.rt[0].colormask = 0xf;
5257 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5258 }
5259
5260 static void si_init_config(struct si_context *sctx);
5261
5262 void si_init_state_compute_functions(struct si_context *sctx)
5263 {
5264 sctx->b.create_sampler_state = si_create_sampler_state;
5265 sctx->b.delete_sampler_state = si_delete_sampler_state;
5266 sctx->b.create_sampler_view = si_create_sampler_view;
5267 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5268 sctx->b.memory_barrier = si_memory_barrier;
5269 }
5270
5271 void si_init_state_functions(struct si_context *sctx)
5272 {
5273 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5274 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5275 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5276 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5277 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5278 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5279 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5280 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5281 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5282 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5283 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5284
5285 sctx->b.create_blend_state = si_create_blend_state;
5286 sctx->b.bind_blend_state = si_bind_blend_state;
5287 sctx->b.delete_blend_state = si_delete_blend_state;
5288 sctx->b.set_blend_color = si_set_blend_color;
5289
5290 sctx->b.create_rasterizer_state = si_create_rs_state;
5291 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5292 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5293
5294 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5295 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5296 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5297
5298 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5299 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5300 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5301 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5302 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5303
5304 sctx->b.set_clip_state = si_set_clip_state;
5305 sctx->b.set_stencil_ref = si_set_stencil_ref;
5306
5307 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5308
5309 sctx->b.set_sample_mask = si_set_sample_mask;
5310
5311 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5312 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5313 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5314 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5315
5316 sctx->b.texture_barrier = si_texture_barrier;
5317 sctx->b.set_min_samples = si_set_min_samples;
5318 sctx->b.set_tess_state = si_set_tess_state;
5319
5320 sctx->b.set_active_query_state = si_set_active_query_state;
5321
5322 si_init_config(sctx);
5323 }
5324
5325 void si_init_screen_state_functions(struct si_screen *sscreen)
5326 {
5327 sscreen->b.is_format_supported = si_is_format_supported;
5328
5329 if (sscreen->info.chip_class >= GFX10) {
5330 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5331 } else {
5332 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5333 }
5334 }
5335
5336 static void si_set_grbm_gfx_index(struct si_context *sctx,
5337 struct si_pm4_state *pm4, unsigned value)
5338 {
5339 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5340 R_00802C_GRBM_GFX_INDEX;
5341 si_pm4_set_reg(pm4, reg, value);
5342 }
5343
5344 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5345 struct si_pm4_state *pm4, unsigned se)
5346 {
5347 assert(se == ~0 || se < sctx->screen->info.max_se);
5348 si_set_grbm_gfx_index(sctx, pm4,
5349 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5350 S_030800_SE_INDEX(se)) |
5351 S_030800_SH_BROADCAST_WRITES(1) |
5352 S_030800_INSTANCE_BROADCAST_WRITES(1));
5353 }
5354
5355 static void
5356 si_write_harvested_raster_configs(struct si_context *sctx,
5357 struct si_pm4_state *pm4,
5358 unsigned raster_config,
5359 unsigned raster_config_1)
5360 {
5361 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5362 unsigned raster_config_se[4];
5363 unsigned se;
5364
5365 ac_get_harvested_configs(&sctx->screen->info,
5366 raster_config,
5367 &raster_config_1,
5368 raster_config_se);
5369
5370 for (se = 0; se < num_se; se++) {
5371 si_set_grbm_gfx_index_se(sctx, pm4, se);
5372 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5373 }
5374 si_set_grbm_gfx_index(sctx, pm4, ~0);
5375
5376 if (sctx->chip_class >= GFX7) {
5377 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5378 }
5379 }
5380
5381 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5382 {
5383 struct si_screen *sscreen = sctx->screen;
5384 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5385 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5386 unsigned raster_config = sscreen->pa_sc_raster_config;
5387 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5388
5389 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5390 /* Always use the default config when all backends are enabled
5391 * (or when we failed to determine the enabled backends).
5392 */
5393 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5394 raster_config);
5395 if (sctx->chip_class >= GFX7)
5396 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5397 raster_config_1);
5398 } else {
5399 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5400 }
5401 }
5402
5403 static void si_init_config(struct si_context *sctx)
5404 {
5405 struct si_screen *sscreen = sctx->screen;
5406 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5407 bool has_clear_state = sscreen->has_clear_state;
5408 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5409
5410 if (!pm4)
5411 return;
5412
5413 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5414 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5415 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5416 si_pm4_cmd_end(pm4, false);
5417
5418 if (has_clear_state) {
5419 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5420 si_pm4_cmd_add(pm4, 0);
5421 si_pm4_cmd_end(pm4, false);
5422 }
5423
5424 if (sctx->chip_class <= GFX8)
5425 si_set_raster_config(sctx, pm4);
5426
5427 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5428 if (!has_clear_state)
5429 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5430
5431 /* FIXME calculate these values somehow ??? */
5432 if (sctx->chip_class <= GFX8) {
5433 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5434 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5435 }
5436
5437 if (!has_clear_state) {
5438 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5439 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5440 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5441 }
5442
5443 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5444 if (!has_clear_state)
5445 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5446 if (sctx->chip_class < GFX7)
5447 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5448 S_008A14_CLIP_VTX_REORDER_ENA(1));
5449
5450 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5451 * I don't know why. Deduced by trial and error.
5452 */
5453 if (sctx->chip_class <= GFX7 || !has_clear_state) {
5454 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5455 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5456 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5457 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5458 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5459 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5460 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5461 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5462 }
5463
5464 if (!has_clear_state) {
5465 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5466 S_028230_ER_TRI(0xA) |
5467 S_028230_ER_POINT(0xA) |
5468 S_028230_ER_RECT(0xA) |
5469 /* Required by DX10_DIAMOND_TEST_ENA: */
5470 S_028230_ER_LINE_LR(0x1A) |
5471 S_028230_ER_LINE_RL(0x26) |
5472 S_028230_ER_LINE_TB(0xA) |
5473 S_028230_ER_LINE_BT(0xA));
5474 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5475 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5476 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5477 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5478 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5479 }
5480
5481 if (sctx->chip_class >= GFX10) {
5482 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5483 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5484 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5485 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5486 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5487 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5488 } else if (sctx->chip_class == GFX9) {
5489 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5490 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5491 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5492 } else {
5493 /* These registers, when written, also overwrite the CLEAR_STATE
5494 * context, so we can't rely on CLEAR_STATE setting them.
5495 * It would be an issue if there was another UMD changing them.
5496 */
5497 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5498 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5499 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5500 }
5501
5502 if (sctx->chip_class >= GFX7) {
5503 if (sctx->chip_class >= GFX10) {
5504 /* Logical CUs 16 - 31 */
5505 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5506 S_00B404_CU_EN(0xffff));
5507 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5508 S_00B104_CU_EN(0xffff));
5509 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5510 S_00B004_CU_EN(0xffff));
5511 }
5512
5513 if (sctx->chip_class >= GFX9) {
5514 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5515 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5516 } else {
5517 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5518 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5519 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5520 S_00B41C_WAVE_LIMIT(0x3F));
5521 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5522 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5523
5524 /* If this is 0, Bonaire can hang even if GS isn't being used.
5525 * Other chips are unaffected. These are suboptimal values,
5526 * but we don't use on-chip GS.
5527 */
5528 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5529 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5530 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5531 }
5532
5533 /* Compute LATE_ALLOC_VS.LIMIT. */
5534 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5535 unsigned late_alloc_limit; /* The limit is per SH. */
5536
5537 if (sctx->family == CHIP_KABINI) {
5538 late_alloc_limit = 0; /* Potential hang on Kabini. */
5539 } else if (num_cu_per_sh <= 4) {
5540 /* Too few available compute units per SH. Disallowing
5541 * VS to run on one CU could hurt us more than late VS
5542 * allocation would help.
5543 *
5544 * 2 is the highest safe number that allows us to keep
5545 * all CUs enabled.
5546 */
5547 late_alloc_limit = 2;
5548 } else {
5549 /* This is a good initial value, allowing 1 late_alloc
5550 * wave per SIMD on num_cu - 2.
5551 */
5552 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5553 }
5554
5555 unsigned cu_mask_vs = 0xffff;
5556 unsigned cu_mask_gs = 0xffff;
5557
5558 if (late_alloc_limit > 2) {
5559 if (sctx->chip_class >= GFX10) {
5560 /* CU2 & CU3 disabled because of the dual CU design */
5561 cu_mask_vs = 0xfff3;
5562 cu_mask_gs = 0xfff3; /* NGG only */
5563 } else {
5564 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5565 }
5566 }
5567
5568 /* VS can't execute on one CU if the limit is > 2. */
5569 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5570 S_00B118_CU_EN(cu_mask_vs) |
5571 S_00B118_WAVE_LIMIT(0x3F));
5572 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5573 S_00B11C_LIMIT(late_alloc_limit));
5574
5575 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5576 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5577
5578 if (sctx->chip_class >= GFX10) {
5579 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5580 S_00B204_CU_EN(0xffff) |
5581 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit));
5582 }
5583
5584 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5585 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5586 }
5587
5588 if (sctx->chip_class >= GFX10) {
5589 /* Break up a pixel wave if it contains deallocs for more than
5590 * half the parameter cache.
5591 *
5592 * To avoid a deadlock where pixel waves aren't launched
5593 * because they're waiting for more pixels while the frontend
5594 * is stuck waiting for PC space, the maximum allowed value is
5595 * the size of the PC minus the largest possible allocation for
5596 * a single primitive shader subgroup.
5597 */
5598 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5599 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5600 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5601 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5602 sscreen->info.pa_sc_tile_steering_override);
5603
5604 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5605 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5606 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5607 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5608 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5609 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5610 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5611 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
5612
5613 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5614 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5615 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5616 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5617 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5618 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5619 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5620 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
5621 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5622 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5623
5624 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5625 S_00B0C0_SOFT_GROUPING_EN(1) |
5626 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5627 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5628
5629 }
5630
5631 if (sctx->chip_class >= GFX8) {
5632 unsigned vgt_tess_distribution;
5633
5634 vgt_tess_distribution =
5635 S_028B50_ACCUM_ISOLINE(32) |
5636 S_028B50_ACCUM_TRI(11) |
5637 S_028B50_ACCUM_QUAD(11) |
5638 S_028B50_DONUT_SPLIT(16);
5639
5640 /* Testing with Unigine Heaven extreme tesselation yielded best results
5641 * with TRAP_SPLIT = 3.
5642 */
5643 if (sctx->family == CHIP_FIJI ||
5644 sctx->family >= CHIP_POLARIS10)
5645 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5646
5647 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5648 } else if (!has_clear_state) {
5649 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5650 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5651 }
5652
5653 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5654 if (sctx->chip_class >= GFX7) {
5655 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5656 S_028084_ADDRESS(border_color_va >> 40));
5657 }
5658 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5659 RADEON_PRIO_BORDER_COLORS);
5660
5661 if (sctx->chip_class >= GFX9) {
5662 unsigned num_se = sscreen->info.max_se;
5663 unsigned pc_lines = 0;
5664 unsigned max_alloc_count = 0;
5665
5666 switch (sctx->family) {
5667 case CHIP_VEGA10:
5668 case CHIP_VEGA12:
5669 case CHIP_VEGA20:
5670 pc_lines = 2048;
5671 break;
5672 case CHIP_RAVEN:
5673 case CHIP_RAVEN2:
5674 case CHIP_NAVI10:
5675 case CHIP_NAVI12:
5676 pc_lines = 1024;
5677 break;
5678 case CHIP_NAVI14:
5679 pc_lines = 512;
5680 break;
5681 default:
5682 assert(0);
5683 }
5684
5685 if (sctx->chip_class >= GFX10) {
5686 max_alloc_count = pc_lines / 3;
5687 } else {
5688 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
5689 }
5690
5691 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5692 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
5693 S_028C48_MAX_PRIM_PER_BATCH(1023));
5694 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5695 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5696 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5697 }
5698
5699 si_pm4_upload_indirect_buffer(sctx, pm4);
5700 sctx->init_config = pm4;
5701 }