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radeonsi/gfx10: enable the workaround for unaligned vertex fetch
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
86 unsigned i;
87
88 if (blend)
89 cb_target_mask &= blend->cb_target_mask;
90
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
94 *
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
96 */
97 if (blend && blend->dual_src_blend &&
98 sctx->ps_shader.cso &&
99 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
100 cb_target_mask = 0;
101
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
104 */
105 if (sctx->screen->dfsm_allowed &&
106 sctx->last_cb_target_mask != cb_target_mask) {
107 sctx->last_cb_target_mask = cb_target_mask;
108
109 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
110 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
111 }
112
113 unsigned initial_cdw = cs->current.cdw;
114 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
115 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
116
117 if (sctx->chip_class >= GFX8) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
121 */
122 bool oc_disable = blend &&
123 blend->blend_enable_4bit & cb_target_mask &&
124 sctx->framebuffer.nr_samples >= 2;
125 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
126
127 radeon_opt_set_context_reg(
128 sctx, R_028424_CB_DCC_CONTROL,
129 SI_TRACKED_CB_DCC_CONTROL,
130 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
131 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
132 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
133 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
134 }
135
136 /* RB+ register settings. */
137 if (sctx->screen->rbplus_allowed) {
138 unsigned spi_shader_col_format =
139 sctx->ps_shader.cso ?
140 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
141 unsigned sx_ps_downconvert = 0;
142 unsigned sx_blend_opt_epsilon = 0;
143 unsigned sx_blend_opt_control = 0;
144
145 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
146 struct si_surface *surf =
147 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
148 unsigned format, swap, spi_format, colormask;
149 bool has_alpha, has_rgb;
150
151 if (!surf)
152 continue;
153
154 format = G_028C70_FORMAT(surf->cb_color_info);
155 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
156 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
157 colormask = (cb_target_mask >> (i * 4)) & 0xf;
158
159 /* Set if RGB and A are present. */
160 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
161
162 if (format == V_028C70_COLOR_8 ||
163 format == V_028C70_COLOR_16 ||
164 format == V_028C70_COLOR_32)
165 has_rgb = !has_alpha;
166 else
167 has_rgb = true;
168
169 /* Check the colormask and export format. */
170 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
171 has_rgb = false;
172 if (!(colormask & PIPE_MASK_A))
173 has_alpha = false;
174
175 if (spi_format == V_028714_SPI_SHADER_ZERO) {
176 has_rgb = false;
177 has_alpha = false;
178 }
179
180 /* Disable value checking for disabled channels. */
181 if (!has_rgb)
182 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
183 if (!has_alpha)
184 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
185
186 /* Enable down-conversion for 32bpp and smaller formats. */
187 switch (format) {
188 case V_028C70_COLOR_8:
189 case V_028C70_COLOR_8_8:
190 case V_028C70_COLOR_8_8_8_8:
191 /* For 1 and 2-channel formats, use the superset thereof. */
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
193 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
194 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
195 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
196 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
197 }
198 break;
199
200 case V_028C70_COLOR_5_6_5:
201 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
202 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
203 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
204 }
205 break;
206
207 case V_028C70_COLOR_1_5_5_5:
208 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
210 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
211 }
212 break;
213
214 case V_028C70_COLOR_4_4_4_4:
215 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
216 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
217 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
218 }
219 break;
220
221 case V_028C70_COLOR_32:
222 if (swap == V_028C70_SWAP_STD &&
223 spi_format == V_028714_SPI_SHADER_32_R)
224 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
225 else if (swap == V_028C70_SWAP_ALT_REV &&
226 spi_format == V_028714_SPI_SHADER_32_AR)
227 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
228 break;
229
230 case V_028C70_COLOR_16:
231 case V_028C70_COLOR_16_16:
232 /* For 1-channel formats, use the superset thereof. */
233 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
234 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
235 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
236 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
237 if (swap == V_028C70_SWAP_STD ||
238 swap == V_028C70_SWAP_STD_REV)
239 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
240 else
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
242 }
243 break;
244
245 case V_028C70_COLOR_10_11_11:
246 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
247 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
248 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
249 }
250 break;
251
252 case V_028C70_COLOR_2_10_10_10:
253 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
254 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
255 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
256 }
257 break;
258 }
259 }
260
261 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
262 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
263 SI_TRACKED_SX_PS_DOWNCONVERT,
264 sx_ps_downconvert, sx_blend_opt_epsilon,
265 sx_blend_opt_control);
266 }
267 if (initial_cdw != cs->current.cdw)
268 sctx->context_roll = true;
269 }
270
271 /*
272 * Blender functions
273 */
274
275 static uint32_t si_translate_blend_function(int blend_func)
276 {
277 switch (blend_func) {
278 case PIPE_BLEND_ADD:
279 return V_028780_COMB_DST_PLUS_SRC;
280 case PIPE_BLEND_SUBTRACT:
281 return V_028780_COMB_SRC_MINUS_DST;
282 case PIPE_BLEND_REVERSE_SUBTRACT:
283 return V_028780_COMB_DST_MINUS_SRC;
284 case PIPE_BLEND_MIN:
285 return V_028780_COMB_MIN_DST_SRC;
286 case PIPE_BLEND_MAX:
287 return V_028780_COMB_MAX_DST_SRC;
288 default:
289 PRINT_ERR("Unknown blend function %d\n", blend_func);
290 assert(0);
291 break;
292 }
293 return 0;
294 }
295
296 static uint32_t si_translate_blend_factor(int blend_fact)
297 {
298 switch (blend_fact) {
299 case PIPE_BLENDFACTOR_ONE:
300 return V_028780_BLEND_ONE;
301 case PIPE_BLENDFACTOR_SRC_COLOR:
302 return V_028780_BLEND_SRC_COLOR;
303 case PIPE_BLENDFACTOR_SRC_ALPHA:
304 return V_028780_BLEND_SRC_ALPHA;
305 case PIPE_BLENDFACTOR_DST_ALPHA:
306 return V_028780_BLEND_DST_ALPHA;
307 case PIPE_BLENDFACTOR_DST_COLOR:
308 return V_028780_BLEND_DST_COLOR;
309 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
310 return V_028780_BLEND_SRC_ALPHA_SATURATE;
311 case PIPE_BLENDFACTOR_CONST_COLOR:
312 return V_028780_BLEND_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_CONST_ALPHA:
314 return V_028780_BLEND_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_ZERO:
316 return V_028780_BLEND_ZERO;
317 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
318 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
319 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
321 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
322 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
323 case PIPE_BLENDFACTOR_INV_DST_COLOR:
324 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
325 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
326 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
327 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
329 case PIPE_BLENDFACTOR_SRC1_COLOR:
330 return V_028780_BLEND_SRC1_COLOR;
331 case PIPE_BLENDFACTOR_SRC1_ALPHA:
332 return V_028780_BLEND_SRC1_ALPHA;
333 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
334 return V_028780_BLEND_INV_SRC1_COLOR;
335 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
336 return V_028780_BLEND_INV_SRC1_ALPHA;
337 default:
338 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
339 assert(0);
340 break;
341 }
342 return 0;
343 }
344
345 static uint32_t si_translate_blend_opt_function(int blend_func)
346 {
347 switch (blend_func) {
348 case PIPE_BLEND_ADD:
349 return V_028760_OPT_COMB_ADD;
350 case PIPE_BLEND_SUBTRACT:
351 return V_028760_OPT_COMB_SUBTRACT;
352 case PIPE_BLEND_REVERSE_SUBTRACT:
353 return V_028760_OPT_COMB_REVSUBTRACT;
354 case PIPE_BLEND_MIN:
355 return V_028760_OPT_COMB_MIN;
356 case PIPE_BLEND_MAX:
357 return V_028760_OPT_COMB_MAX;
358 default:
359 return V_028760_OPT_COMB_BLEND_DISABLED;
360 }
361 }
362
363 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
364 {
365 switch (blend_fact) {
366 case PIPE_BLENDFACTOR_ZERO:
367 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
368 case PIPE_BLENDFACTOR_ONE:
369 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
370 case PIPE_BLENDFACTOR_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
372 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
373 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
375 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
376 case PIPE_BLENDFACTOR_SRC_ALPHA:
377 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
378 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
379 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
380 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
381 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
382 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
383 default:
384 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
385 }
386 }
387
388 static void si_blend_check_commutativity(struct si_screen *sscreen,
389 struct si_state_blend *blend,
390 enum pipe_blend_func func,
391 enum pipe_blendfactor src,
392 enum pipe_blendfactor dst,
393 unsigned chanmask)
394 {
395 /* Src factor is allowed when it does not depend on Dst */
396 static const uint32_t src_allowed =
397 (1u << PIPE_BLENDFACTOR_ONE) |
398 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
399 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
400 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
401 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
402 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
403 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
404 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
405 (1u << PIPE_BLENDFACTOR_ZERO) |
406 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
409 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
410 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
411 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
412
413 if (dst == PIPE_BLENDFACTOR_ONE &&
414 (src_allowed & (1u << src))) {
415 /* Addition is commutative, but floating point addition isn't
416 * associative: subtle changes can be introduced via different
417 * rounding.
418 *
419 * Out-of-order is also non-deterministic, which means that
420 * this breaks OpenGL invariance requirements. So only enable
421 * out-of-order additive blending if explicitly allowed by a
422 * setting.
423 */
424 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
425 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
426 blend->commutative_4bit |= chanmask;
427 }
428 }
429
430 /**
431 * Get rid of DST in the blend factors by commuting the operands:
432 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
433 */
434 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
435 unsigned *dst_factor, unsigned expected_dst,
436 unsigned replacement_src)
437 {
438 if (*src_factor == expected_dst &&
439 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
440 *src_factor = PIPE_BLENDFACTOR_ZERO;
441 *dst_factor = replacement_src;
442
443 /* Commuting the operands requires reversing subtractions. */
444 if (*func == PIPE_BLEND_SUBTRACT)
445 *func = PIPE_BLEND_REVERSE_SUBTRACT;
446 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
447 *func = PIPE_BLEND_SUBTRACT;
448 }
449 }
450
451 static bool si_blend_factor_uses_dst(unsigned factor)
452 {
453 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
454 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
455 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
456 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
457 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
458 }
459
460 static void *si_create_blend_state_mode(struct pipe_context *ctx,
461 const struct pipe_blend_state *state,
462 unsigned mode)
463 {
464 struct si_context *sctx = (struct si_context*)ctx;
465 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
466 struct si_pm4_state *pm4 = &blend->pm4;
467 uint32_t sx_mrt_blend_opt[8] = {0};
468 uint32_t color_control = 0;
469
470 if (!blend)
471 return NULL;
472
473 blend->alpha_to_coverage = state->alpha_to_coverage;
474 blend->alpha_to_one = state->alpha_to_one;
475 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
476 blend->logicop_enable = state->logicop_enable;
477
478 if (state->logicop_enable) {
479 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
480 } else {
481 color_control |= S_028808_ROP3(0xcc);
482 }
483
484 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
485 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
486 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
487 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
488 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
489 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
490 S_028B70_OFFSET_ROUND(1));
491
492 if (state->alpha_to_coverage)
493 blend->need_src_alpha_4bit |= 0xf;
494
495 blend->cb_target_mask = 0;
496 blend->cb_target_enabled_4bit = 0;
497
498 for (int i = 0; i < 8; i++) {
499 /* state->rt entries > 0 only written if independent blending */
500 const int j = state->independent_blend_enable ? i : 0;
501
502 unsigned eqRGB = state->rt[j].rgb_func;
503 unsigned srcRGB = state->rt[j].rgb_src_factor;
504 unsigned dstRGB = state->rt[j].rgb_dst_factor;
505 unsigned eqA = state->rt[j].alpha_func;
506 unsigned srcA = state->rt[j].alpha_src_factor;
507 unsigned dstA = state->rt[j].alpha_dst_factor;
508
509 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
510 unsigned blend_cntl = 0;
511
512 sx_mrt_blend_opt[i] =
513 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
514 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
515
516 /* Only set dual source blending for MRT0 to avoid a hang. */
517 if (i >= 1 && blend->dual_src_blend) {
518 /* Vulkan does this for dual source blending. */
519 if (i == 1)
520 blend_cntl |= S_028780_ENABLE(1);
521
522 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
523 continue;
524 }
525
526 /* Only addition and subtraction equations are supported with
527 * dual source blending.
528 */
529 if (blend->dual_src_blend &&
530 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
531 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
532 assert(!"Unsupported equation for dual source blending");
533 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
534 continue;
535 }
536
537 /* cb_render_state will disable unused ones */
538 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
539 if (state->rt[j].colormask)
540 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
541
542 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544 continue;
545 }
546
547 si_blend_check_commutativity(sctx->screen, blend,
548 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
549 si_blend_check_commutativity(sctx->screen, blend,
550 eqA, srcA, dstA, 0x8 << (4 * i));
551
552 /* Blending optimizations for RB+.
553 * These transformations don't change the behavior.
554 *
555 * First, get rid of DST in the blend factors:
556 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
557 */
558 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
559 PIPE_BLENDFACTOR_DST_COLOR,
560 PIPE_BLENDFACTOR_SRC_COLOR);
561 si_blend_remove_dst(&eqA, &srcA, &dstA,
562 PIPE_BLENDFACTOR_DST_COLOR,
563 PIPE_BLENDFACTOR_SRC_COLOR);
564 si_blend_remove_dst(&eqA, &srcA, &dstA,
565 PIPE_BLENDFACTOR_DST_ALPHA,
566 PIPE_BLENDFACTOR_SRC_ALPHA);
567
568 /* Look up the ideal settings from tables. */
569 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
570 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
571 srcA_opt = si_translate_blend_opt_factor(srcA, true);
572 dstA_opt = si_translate_blend_opt_factor(dstA, true);
573
574 /* Handle interdependencies. */
575 if (si_blend_factor_uses_dst(srcRGB))
576 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
577 if (si_blend_factor_uses_dst(srcA))
578 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
579
580 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
581 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
582 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
583 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
584 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
585
586 /* Set the final value. */
587 sx_mrt_blend_opt[i] =
588 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
589 S_028760_COLOR_DST_OPT(dstRGB_opt) |
590 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
591 S_028760_ALPHA_SRC_OPT(srcA_opt) |
592 S_028760_ALPHA_DST_OPT(dstA_opt) |
593 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
594
595 /* Set blend state. */
596 blend_cntl |= S_028780_ENABLE(1);
597 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
598 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
599 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
600
601 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
602 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
603 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
604 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
605 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
606 }
607 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
608
609 blend->blend_enable_4bit |= 0xfu << (i * 4);
610
611 /* This is only important for formats without alpha. */
612 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
613 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
614 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
615 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
616 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
617 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
618 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
619 }
620
621 if (blend->cb_target_mask) {
622 color_control |= S_028808_MODE(mode);
623 } else {
624 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
625 }
626
627 if (sctx->screen->rbplus_allowed) {
628 /* Disable RB+ blend optimizations for dual source blending.
629 * Vulkan does this.
630 */
631 if (blend->dual_src_blend) {
632 for (int i = 0; i < 8; i++) {
633 sx_mrt_blend_opt[i] =
634 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
635 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
636 }
637 }
638
639 for (int i = 0; i < 8; i++)
640 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
641 sx_mrt_blend_opt[i]);
642
643 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
644 if (blend->dual_src_blend || state->logicop_enable ||
645 mode == V_028808_CB_RESOLVE)
646 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
647 }
648
649 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
650 return blend;
651 }
652
653 static void *si_create_blend_state(struct pipe_context *ctx,
654 const struct pipe_blend_state *state)
655 {
656 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
657 }
658
659 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
660 {
661 struct si_context *sctx = (struct si_context *)ctx;
662 struct si_state_blend *old_blend = sctx->queued.named.blend;
663 struct si_state_blend *blend = (struct si_state_blend *)state;
664
665 if (!state)
666 return;
667
668 si_pm4_bind_state(sctx, blend, state);
669
670 if (!old_blend ||
671 old_blend->cb_target_mask != blend->cb_target_mask ||
672 old_blend->dual_src_blend != blend->dual_src_blend ||
673 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
674 sctx->framebuffer.nr_samples >= 2 &&
675 sctx->screen->dcc_msaa_allowed))
676 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
677
678 if (!old_blend ||
679 old_blend->cb_target_mask != blend->cb_target_mask ||
680 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
681 old_blend->alpha_to_one != blend->alpha_to_one ||
682 old_blend->dual_src_blend != blend->dual_src_blend ||
683 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
684 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
685 sctx->do_update_shaders = true;
686
687 if (sctx->screen->dpbb_allowed &&
688 (!old_blend ||
689 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
690 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
691 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
692 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
693
694 if (sctx->screen->has_out_of_order_rast &&
695 (!old_blend ||
696 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
697 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
698 old_blend->commutative_4bit != blend->commutative_4bit ||
699 old_blend->logicop_enable != blend->logicop_enable)))
700 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
701 }
702
703 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
704 {
705 struct si_context *sctx = (struct si_context *)ctx;
706 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
707 }
708
709 static void si_set_blend_color(struct pipe_context *ctx,
710 const struct pipe_blend_color *state)
711 {
712 struct si_context *sctx = (struct si_context *)ctx;
713 static const struct pipe_blend_color zeros;
714
715 sctx->blend_color.state = *state;
716 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
717 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
718 }
719
720 static void si_emit_blend_color(struct si_context *sctx)
721 {
722 struct radeon_cmdbuf *cs = sctx->gfx_cs;
723
724 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
725 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
726 }
727
728 /*
729 * Clipping
730 */
731
732 static void si_set_clip_state(struct pipe_context *ctx,
733 const struct pipe_clip_state *state)
734 {
735 struct si_context *sctx = (struct si_context *)ctx;
736 struct pipe_constant_buffer cb;
737 static const struct pipe_clip_state zeros;
738
739 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->clip_state.state = *state;
743 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
744 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
745
746 cb.buffer = NULL;
747 cb.user_buffer = state->ucp;
748 cb.buffer_offset = 0;
749 cb.buffer_size = 4*4*8;
750 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
751 pipe_resource_reference(&cb.buffer, NULL);
752 }
753
754 static void si_emit_clip_state(struct si_context *sctx)
755 {
756 struct radeon_cmdbuf *cs = sctx->gfx_cs;
757
758 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
759 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
760 }
761
762 static void si_emit_clip_regs(struct si_context *sctx)
763 {
764 struct si_shader *vs = si_get_vs_state(sctx);
765 struct si_shader_selector *vs_sel = vs->selector;
766 struct tgsi_shader_info *info = &vs_sel->info;
767 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
768 unsigned window_space =
769 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
770 unsigned clipdist_mask = vs_sel->clipdist_mask;
771 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
772 unsigned culldist_mask = vs_sel->culldist_mask;
773 unsigned total_mask;
774
775 if (vs->key.opt.clip_disable) {
776 assert(!info->culldist_writemask);
777 clipdist_mask = 0;
778 culldist_mask = 0;
779 }
780 total_mask = clipdist_mask | culldist_mask;
781
782 /* Clip distances on points have no effect, so need to be implemented
783 * as cull distances. This applies for the clipvertex case as well.
784 *
785 * Setting this for primitives other than points should have no adverse
786 * effects.
787 */
788 clipdist_mask &= rs->clip_plane_enable;
789 culldist_mask |= clipdist_mask;
790
791 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
792 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
793 SI_TRACKED_PA_CL_VS_OUT_CNTL,
794 vs_sel->pa_cl_vs_out_cntl |
795 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
796 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
797 clipdist_mask | (culldist_mask << 8));
798 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
799 SI_TRACKED_PA_CL_CLIP_CNTL,
800 rs->pa_cl_clip_cntl |
801 ucp_mask |
802 S_028810_CLIP_DISABLE(window_space));
803
804 if (initial_cdw != sctx->gfx_cs->current.cdw)
805 sctx->context_roll = true;
806 }
807
808 /*
809 * inferred state between framebuffer and rasterizer
810 */
811 static void si_update_poly_offset_state(struct si_context *sctx)
812 {
813 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
814
815 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
816 si_pm4_bind_state(sctx, poly_offset, NULL);
817 return;
818 }
819
820 /* Use the user format, not db_render_format, so that the polygon
821 * offset behaves as expected by applications.
822 */
823 switch (sctx->framebuffer.state.zsbuf->texture->format) {
824 case PIPE_FORMAT_Z16_UNORM:
825 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
826 break;
827 default: /* 24-bit */
828 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
829 break;
830 case PIPE_FORMAT_Z32_FLOAT:
831 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
832 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
833 break;
834 }
835 }
836
837 /*
838 * Rasterizer
839 */
840
841 static uint32_t si_translate_fill(uint32_t func)
842 {
843 switch(func) {
844 case PIPE_POLYGON_MODE_FILL:
845 return V_028814_X_DRAW_TRIANGLES;
846 case PIPE_POLYGON_MODE_LINE:
847 return V_028814_X_DRAW_LINES;
848 case PIPE_POLYGON_MODE_POINT:
849 return V_028814_X_DRAW_POINTS;
850 default:
851 assert(0);
852 return V_028814_X_DRAW_POINTS;
853 }
854 }
855
856 static void *si_create_rs_state(struct pipe_context *ctx,
857 const struct pipe_rasterizer_state *state)
858 {
859 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
860 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
861 struct si_pm4_state *pm4 = &rs->pm4;
862 unsigned tmp, i;
863 float psize_min, psize_max;
864
865 if (!rs) {
866 return NULL;
867 }
868
869 if (!state->front_ccw) {
870 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
871 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
872 } else {
873 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
874 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
875 }
876 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
877 rs->provoking_vertex_first = state->flatshade_first;
878 rs->scissor_enable = state->scissor;
879 rs->clip_halfz = state->clip_halfz;
880 rs->two_side = state->light_twoside;
881 rs->multisample_enable = state->multisample;
882 rs->force_persample_interp = state->force_persample_interp;
883 rs->clip_plane_enable = state->clip_plane_enable;
884 rs->half_pixel_center = state->half_pixel_center;
885 rs->line_stipple_enable = state->line_stipple_enable;
886 rs->poly_stipple_enable = state->poly_stipple_enable;
887 rs->line_smooth = state->line_smooth;
888 rs->line_width = state->line_width;
889 rs->poly_smooth = state->poly_smooth;
890 rs->uses_poly_offset = state->offset_point || state->offset_line ||
891 state->offset_tri;
892 rs->clamp_fragment_color = state->clamp_fragment_color;
893 rs->clamp_vertex_color = state->clamp_vertex_color;
894 rs->flatshade = state->flatshade;
895 rs->sprite_coord_enable = state->sprite_coord_enable;
896 rs->rasterizer_discard = state->rasterizer_discard;
897 rs->pa_sc_line_stipple = state->line_stipple_enable ?
898 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
899 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
900 rs->pa_cl_clip_cntl =
901 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
902 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
903 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
904 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
905 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
906
907 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
908 S_0286D4_FLAT_SHADE_ENA(1) |
909 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
910 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
911 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
912 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
913 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
914 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
915
916 /* point size 12.4 fixed point */
917 tmp = (unsigned)(state->point_size * 8.0);
918 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
919
920 if (state->point_size_per_vertex) {
921 psize_min = util_get_min_point_size(state);
922 psize_max = SI_MAX_POINT_SIZE;
923 } else {
924 /* Force the point size to be as if the vertex output was disabled. */
925 psize_min = state->point_size;
926 psize_max = state->point_size;
927 }
928 rs->max_point_size = psize_max;
929
930 /* Divide by two, because 0.5 = 1 pixel. */
931 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
932 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
933 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
934
935 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
936 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
937 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
938 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
939 S_028A48_MSAA_ENABLE(state->multisample ||
940 state->poly_smooth ||
941 state->line_smooth) |
942 S_028A48_VPORT_SCISSOR_ENABLE(1) |
943 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
944
945 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
946 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
947 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
948 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
949 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
950 S_028814_FACE(!state->front_ccw) |
951 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
952 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
953 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
954 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
955 state->fill_back != PIPE_POLYGON_MODE_FILL) |
956 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
957 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
958
959 if (!rs->uses_poly_offset)
960 return rs;
961
962 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
963 if (!rs->pm4_poly_offset) {
964 FREE(rs);
965 return NULL;
966 }
967
968 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
969 for (i = 0; i < 3; i++) {
970 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
971 float offset_units = state->offset_units;
972 float offset_scale = state->offset_scale * 16.0f;
973 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
974
975 if (!state->offset_units_unscaled) {
976 switch (i) {
977 case 0: /* 16-bit zbuffer */
978 offset_units *= 4.0f;
979 pa_su_poly_offset_db_fmt_cntl =
980 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
981 break;
982 case 1: /* 24-bit zbuffer */
983 offset_units *= 2.0f;
984 pa_su_poly_offset_db_fmt_cntl =
985 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
986 break;
987 case 2: /* 32-bit zbuffer */
988 offset_units *= 1.0f;
989 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
990 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
991 break;
992 }
993 }
994
995 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
996 fui(offset_scale));
997 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
998 fui(offset_units));
999 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1000 fui(offset_scale));
1001 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1002 fui(offset_units));
1003 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1004 pa_su_poly_offset_db_fmt_cntl);
1005 }
1006
1007 return rs;
1008 }
1009
1010 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1011 {
1012 struct si_context *sctx = (struct si_context *)ctx;
1013 struct si_state_rasterizer *old_rs =
1014 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1015 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1016
1017 if (!state)
1018 return;
1019
1020 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1021 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1022
1023 /* Update the small primitive filter workaround if necessary. */
1024 if (sctx->screen->has_msaa_sample_loc_bug &&
1025 sctx->framebuffer.nr_samples > 1)
1026 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1027 }
1028
1029 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1030 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1031
1032 si_pm4_bind_state(sctx, rasterizer, rs);
1033 si_update_poly_offset_state(sctx);
1034
1035 if (!old_rs ||
1036 old_rs->scissor_enable != rs->scissor_enable)
1037 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1038
1039 if (!old_rs ||
1040 old_rs->line_width != rs->line_width ||
1041 old_rs->max_point_size != rs->max_point_size ||
1042 old_rs->half_pixel_center != rs->half_pixel_center)
1043 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1044
1045 if (!old_rs ||
1046 old_rs->clip_halfz != rs->clip_halfz)
1047 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1048
1049 if (!old_rs ||
1050 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1051 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1052 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1053
1054 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1055 rs->line_stipple_enable;
1056
1057 if (!old_rs ||
1058 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1059 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1060 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1061 old_rs->flatshade != rs->flatshade ||
1062 old_rs->two_side != rs->two_side ||
1063 old_rs->multisample_enable != rs->multisample_enable ||
1064 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1065 old_rs->poly_smooth != rs->poly_smooth ||
1066 old_rs->line_smooth != rs->line_smooth ||
1067 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1068 old_rs->force_persample_interp != rs->force_persample_interp)
1069 sctx->do_update_shaders = true;
1070 }
1071
1072 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1073 {
1074 struct si_context *sctx = (struct si_context *)ctx;
1075 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1076
1077 if (sctx->queued.named.rasterizer == state)
1078 si_pm4_bind_state(sctx, poly_offset, NULL);
1079
1080 FREE(rs->pm4_poly_offset);
1081 si_pm4_delete_state(sctx, rasterizer, rs);
1082 }
1083
1084 /*
1085 * infeered state between dsa and stencil ref
1086 */
1087 static void si_emit_stencil_ref(struct si_context *sctx)
1088 {
1089 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1090 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1091 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1092
1093 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1094 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1095 S_028430_STENCILMASK(dsa->valuemask[0]) |
1096 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1097 S_028430_STENCILOPVAL(1));
1098 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1099 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1100 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1101 S_028434_STENCILOPVAL_BF(1));
1102 }
1103
1104 static void si_set_stencil_ref(struct pipe_context *ctx,
1105 const struct pipe_stencil_ref *state)
1106 {
1107 struct si_context *sctx = (struct si_context *)ctx;
1108
1109 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1110 return;
1111
1112 sctx->stencil_ref.state = *state;
1113 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1114 }
1115
1116
1117 /*
1118 * DSA
1119 */
1120
1121 static uint32_t si_translate_stencil_op(int s_op)
1122 {
1123 switch (s_op) {
1124 case PIPE_STENCIL_OP_KEEP:
1125 return V_02842C_STENCIL_KEEP;
1126 case PIPE_STENCIL_OP_ZERO:
1127 return V_02842C_STENCIL_ZERO;
1128 case PIPE_STENCIL_OP_REPLACE:
1129 return V_02842C_STENCIL_REPLACE_TEST;
1130 case PIPE_STENCIL_OP_INCR:
1131 return V_02842C_STENCIL_ADD_CLAMP;
1132 case PIPE_STENCIL_OP_DECR:
1133 return V_02842C_STENCIL_SUB_CLAMP;
1134 case PIPE_STENCIL_OP_INCR_WRAP:
1135 return V_02842C_STENCIL_ADD_WRAP;
1136 case PIPE_STENCIL_OP_DECR_WRAP:
1137 return V_02842C_STENCIL_SUB_WRAP;
1138 case PIPE_STENCIL_OP_INVERT:
1139 return V_02842C_STENCIL_INVERT;
1140 default:
1141 PRINT_ERR("Unknown stencil op %d", s_op);
1142 assert(0);
1143 break;
1144 }
1145 return 0;
1146 }
1147
1148 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1149 {
1150 return s->enabled && s->writemask &&
1151 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1152 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1153 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1154 }
1155
1156 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1157 {
1158 /* REPLACE is normally order invariant, except when the stencil
1159 * reference value is written by the fragment shader. Tracking this
1160 * interaction does not seem worth the effort, so be conservative. */
1161 return op != PIPE_STENCIL_OP_INCR &&
1162 op != PIPE_STENCIL_OP_DECR &&
1163 op != PIPE_STENCIL_OP_REPLACE;
1164 }
1165
1166 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1167 * invariant in the sense that the set of passing fragments as well as the
1168 * final stencil buffer result does not depend on the order of fragments. */
1169 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1170 {
1171 return !state->enabled || !state->writemask ||
1172 /* The following assumes that Z writes are disabled. */
1173 (state->func == PIPE_FUNC_ALWAYS &&
1174 si_order_invariant_stencil_op(state->zpass_op) &&
1175 si_order_invariant_stencil_op(state->zfail_op)) ||
1176 (state->func == PIPE_FUNC_NEVER &&
1177 si_order_invariant_stencil_op(state->fail_op));
1178 }
1179
1180 static void *si_create_dsa_state(struct pipe_context *ctx,
1181 const struct pipe_depth_stencil_alpha_state *state)
1182 {
1183 struct si_context *sctx = (struct si_context *)ctx;
1184 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1185 struct si_pm4_state *pm4 = &dsa->pm4;
1186 unsigned db_depth_control;
1187 uint32_t db_stencil_control = 0;
1188
1189 if (!dsa) {
1190 return NULL;
1191 }
1192
1193 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1194 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1195 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1196 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1197
1198 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1199 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1200 S_028800_ZFUNC(state->depth.func) |
1201 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1202
1203 /* stencil */
1204 if (state->stencil[0].enabled) {
1205 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1206 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1207 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1208 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1209 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1210
1211 if (state->stencil[1].enabled) {
1212 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1213 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1214 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1215 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1216 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1217 }
1218 }
1219
1220 /* alpha */
1221 if (state->alpha.enabled) {
1222 dsa->alpha_func = state->alpha.func;
1223
1224 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1225 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1226 } else {
1227 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1228 }
1229
1230 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1231 if (state->stencil[0].enabled)
1232 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1233 if (state->depth.bounds_test) {
1234 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1235 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1236 }
1237
1238 dsa->depth_enabled = state->depth.enabled;
1239 dsa->depth_write_enabled = state->depth.enabled &&
1240 state->depth.writemask;
1241 dsa->stencil_enabled = state->stencil[0].enabled;
1242 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1243 (si_dsa_writes_stencil(&state->stencil[0]) ||
1244 si_dsa_writes_stencil(&state->stencil[1]));
1245 dsa->db_can_write = dsa->depth_write_enabled ||
1246 dsa->stencil_write_enabled;
1247
1248 bool zfunc_is_ordered =
1249 state->depth.func == PIPE_FUNC_NEVER ||
1250 state->depth.func == PIPE_FUNC_LESS ||
1251 state->depth.func == PIPE_FUNC_LEQUAL ||
1252 state->depth.func == PIPE_FUNC_GREATER ||
1253 state->depth.func == PIPE_FUNC_GEQUAL;
1254
1255 bool nozwrite_and_order_invariant_stencil =
1256 !dsa->db_can_write ||
1257 (!dsa->depth_write_enabled &&
1258 si_order_invariant_stencil_state(&state->stencil[0]) &&
1259 si_order_invariant_stencil_state(&state->stencil[1]));
1260
1261 dsa->order_invariance[1].zs =
1262 nozwrite_and_order_invariant_stencil ||
1263 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1264 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1265
1266 dsa->order_invariance[1].pass_set =
1267 nozwrite_and_order_invariant_stencil ||
1268 (!dsa->stencil_write_enabled &&
1269 (state->depth.func == PIPE_FUNC_ALWAYS ||
1270 state->depth.func == PIPE_FUNC_NEVER));
1271 dsa->order_invariance[0].pass_set =
1272 !dsa->depth_write_enabled ||
1273 (state->depth.func == PIPE_FUNC_ALWAYS ||
1274 state->depth.func == PIPE_FUNC_NEVER);
1275
1276 dsa->order_invariance[1].pass_last =
1277 sctx->screen->assume_no_z_fights &&
1278 !dsa->stencil_write_enabled &&
1279 dsa->depth_write_enabled && zfunc_is_ordered;
1280 dsa->order_invariance[0].pass_last =
1281 sctx->screen->assume_no_z_fights &&
1282 dsa->depth_write_enabled && zfunc_is_ordered;
1283
1284 return dsa;
1285 }
1286
1287 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1288 {
1289 struct si_context *sctx = (struct si_context *)ctx;
1290 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1291 struct si_state_dsa *dsa = state;
1292
1293 if (!state)
1294 return;
1295
1296 si_pm4_bind_state(sctx, dsa, dsa);
1297
1298 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1299 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1300 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1301 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1302 }
1303
1304 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1305 sctx->do_update_shaders = true;
1306
1307 if (sctx->screen->dpbb_allowed &&
1308 (!old_dsa ||
1309 (old_dsa->depth_enabled != dsa->depth_enabled ||
1310 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1311 old_dsa->db_can_write != dsa->db_can_write)))
1312 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1313
1314 if (sctx->screen->has_out_of_order_rast &&
1315 (!old_dsa ||
1316 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1317 sizeof(old_dsa->order_invariance))))
1318 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1319 }
1320
1321 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1322 {
1323 struct si_context *sctx = (struct si_context *)ctx;
1324 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1325 }
1326
1327 static void *si_create_db_flush_dsa(struct si_context *sctx)
1328 {
1329 struct pipe_depth_stencil_alpha_state dsa = {};
1330
1331 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1332 }
1333
1334 /* DB RENDER STATE */
1335
1336 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1337 {
1338 struct si_context *sctx = (struct si_context*)ctx;
1339
1340 /* Pipeline stat & streamout queries. */
1341 if (enable) {
1342 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1343 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1344 } else {
1345 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1346 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1347 }
1348
1349 /* Occlusion queries. */
1350 if (sctx->occlusion_queries_disabled != !enable) {
1351 sctx->occlusion_queries_disabled = !enable;
1352 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1353 }
1354 }
1355
1356 void si_set_occlusion_query_state(struct si_context *sctx,
1357 bool old_perfect_enable)
1358 {
1359 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1360
1361 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1362
1363 if (perfect_enable != old_perfect_enable)
1364 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1365 }
1366
1367 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1368 {
1369 st->saved_compute = sctx->cs_shader_state.program;
1370
1371 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1372 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1373
1374 st->saved_ssbo_writable_mask = 0;
1375
1376 for (unsigned i = 0; i < 3; i++) {
1377 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1378 (1u << si_get_shaderbuf_slot(i)))
1379 st->saved_ssbo_writable_mask |= 1 << i;
1380 }
1381 }
1382
1383 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1384 {
1385 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1386
1387 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1388 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1389
1390 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1391 st->saved_ssbo_writable_mask);
1392 for (unsigned i = 0; i < 3; ++i)
1393 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1394 }
1395
1396 static void si_emit_db_render_state(struct si_context *sctx)
1397 {
1398 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1399 unsigned db_shader_control, db_render_control, db_count_control;
1400 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1401
1402 /* DB_RENDER_CONTROL */
1403 if (sctx->dbcb_depth_copy_enabled ||
1404 sctx->dbcb_stencil_copy_enabled) {
1405 db_render_control =
1406 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1407 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1408 S_028000_COPY_CENTROID(1) |
1409 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1410 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1411 db_render_control =
1412 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1413 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1414 } else {
1415 db_render_control =
1416 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1417 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1418 }
1419
1420 /* DB_COUNT_CONTROL (occlusion queries) */
1421 if (sctx->num_occlusion_queries > 0 &&
1422 !sctx->occlusion_queries_disabled) {
1423 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1424
1425 if (sctx->chip_class >= GFX7) {
1426 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1427
1428 /* Stoney doesn't increment occlusion query counters
1429 * if the sample rate is 16x. Use 8x sample rate instead.
1430 */
1431 if (sctx->family == CHIP_STONEY)
1432 log_sample_rate = MIN2(log_sample_rate, 3);
1433
1434 db_count_control =
1435 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1436 S_028004_SAMPLE_RATE(log_sample_rate) |
1437 S_028004_ZPASS_ENABLE(1) |
1438 S_028004_SLICE_EVEN_ENABLE(1) |
1439 S_028004_SLICE_ODD_ENABLE(1);
1440 } else {
1441 db_count_control =
1442 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1443 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1444 }
1445 } else {
1446 /* Disable occlusion queries. */
1447 if (sctx->chip_class >= GFX7) {
1448 db_count_control = 0;
1449 } else {
1450 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1451 }
1452 }
1453
1454 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1455 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1456 db_count_control);
1457
1458 /* DB_RENDER_OVERRIDE2 */
1459 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1460 SI_TRACKED_DB_RENDER_OVERRIDE2,
1461 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1462 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1463 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1464
1465 db_shader_control = sctx->ps_db_shader_control;
1466
1467 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1468 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1469 db_shader_control &= C_02880C_Z_ORDER;
1470 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1471 }
1472
1473 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1474 if (!rs->multisample_enable)
1475 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1476
1477 if (sctx->screen->has_rbplus &&
1478 !sctx->screen->rbplus_allowed)
1479 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1480
1481 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1482 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1483
1484 if (initial_cdw != sctx->gfx_cs->current.cdw)
1485 sctx->context_roll = true;
1486 }
1487
1488 /*
1489 * format translation
1490 */
1491 static uint32_t si_translate_colorformat(enum pipe_format format)
1492 {
1493 const struct util_format_description *desc = util_format_description(format);
1494 if (!desc)
1495 return V_028C70_COLOR_INVALID;
1496
1497 #define HAS_SIZE(x,y,z,w) \
1498 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1499 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1500
1501 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1502 return V_028C70_COLOR_10_11_11;
1503
1504 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1505 return V_028C70_COLOR_INVALID;
1506
1507 /* hw cannot support mixed formats (except depth/stencil, since
1508 * stencil is not written to). */
1509 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1510 return V_028C70_COLOR_INVALID;
1511
1512 switch (desc->nr_channels) {
1513 case 1:
1514 switch (desc->channel[0].size) {
1515 case 8:
1516 return V_028C70_COLOR_8;
1517 case 16:
1518 return V_028C70_COLOR_16;
1519 case 32:
1520 return V_028C70_COLOR_32;
1521 }
1522 break;
1523 case 2:
1524 if (desc->channel[0].size == desc->channel[1].size) {
1525 switch (desc->channel[0].size) {
1526 case 8:
1527 return V_028C70_COLOR_8_8;
1528 case 16:
1529 return V_028C70_COLOR_16_16;
1530 case 32:
1531 return V_028C70_COLOR_32_32;
1532 }
1533 } else if (HAS_SIZE(8,24,0,0)) {
1534 return V_028C70_COLOR_24_8;
1535 } else if (HAS_SIZE(24,8,0,0)) {
1536 return V_028C70_COLOR_8_24;
1537 }
1538 break;
1539 case 3:
1540 if (HAS_SIZE(5,6,5,0)) {
1541 return V_028C70_COLOR_5_6_5;
1542 } else if (HAS_SIZE(32,8,24,0)) {
1543 return V_028C70_COLOR_X24_8_32_FLOAT;
1544 }
1545 break;
1546 case 4:
1547 if (desc->channel[0].size == desc->channel[1].size &&
1548 desc->channel[0].size == desc->channel[2].size &&
1549 desc->channel[0].size == desc->channel[3].size) {
1550 switch (desc->channel[0].size) {
1551 case 4:
1552 return V_028C70_COLOR_4_4_4_4;
1553 case 8:
1554 return V_028C70_COLOR_8_8_8_8;
1555 case 16:
1556 return V_028C70_COLOR_16_16_16_16;
1557 case 32:
1558 return V_028C70_COLOR_32_32_32_32;
1559 }
1560 } else if (HAS_SIZE(5,5,5,1)) {
1561 return V_028C70_COLOR_1_5_5_5;
1562 } else if (HAS_SIZE(1,5,5,5)) {
1563 return V_028C70_COLOR_5_5_5_1;
1564 } else if (HAS_SIZE(10,10,10,2)) {
1565 return V_028C70_COLOR_2_10_10_10;
1566 }
1567 break;
1568 }
1569 return V_028C70_COLOR_INVALID;
1570 }
1571
1572 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1573 {
1574 if (SI_BIG_ENDIAN) {
1575 switch(colorformat) {
1576 /* 8-bit buffers. */
1577 case V_028C70_COLOR_8:
1578 return V_028C70_ENDIAN_NONE;
1579
1580 /* 16-bit buffers. */
1581 case V_028C70_COLOR_5_6_5:
1582 case V_028C70_COLOR_1_5_5_5:
1583 case V_028C70_COLOR_4_4_4_4:
1584 case V_028C70_COLOR_16:
1585 case V_028C70_COLOR_8_8:
1586 return V_028C70_ENDIAN_8IN16;
1587
1588 /* 32-bit buffers. */
1589 case V_028C70_COLOR_8_8_8_8:
1590 case V_028C70_COLOR_2_10_10_10:
1591 case V_028C70_COLOR_8_24:
1592 case V_028C70_COLOR_24_8:
1593 case V_028C70_COLOR_16_16:
1594 return V_028C70_ENDIAN_8IN32;
1595
1596 /* 64-bit buffers. */
1597 case V_028C70_COLOR_16_16_16_16:
1598 return V_028C70_ENDIAN_8IN16;
1599
1600 case V_028C70_COLOR_32_32:
1601 return V_028C70_ENDIAN_8IN32;
1602
1603 /* 128-bit buffers. */
1604 case V_028C70_COLOR_32_32_32_32:
1605 return V_028C70_ENDIAN_8IN32;
1606 default:
1607 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1608 }
1609 } else {
1610 return V_028C70_ENDIAN_NONE;
1611 }
1612 }
1613
1614 static uint32_t si_translate_dbformat(enum pipe_format format)
1615 {
1616 switch (format) {
1617 case PIPE_FORMAT_Z16_UNORM:
1618 return V_028040_Z_16;
1619 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1620 case PIPE_FORMAT_X8Z24_UNORM:
1621 case PIPE_FORMAT_Z24X8_UNORM:
1622 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1623 return V_028040_Z_24; /* deprecated on AMD GCN */
1624 case PIPE_FORMAT_Z32_FLOAT:
1625 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1626 return V_028040_Z_32_FLOAT;
1627 default:
1628 return V_028040_Z_INVALID;
1629 }
1630 }
1631
1632 /*
1633 * Texture translation
1634 */
1635
1636 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1637 enum pipe_format format,
1638 const struct util_format_description *desc,
1639 int first_non_void)
1640 {
1641 struct si_screen *sscreen = (struct si_screen*)screen;
1642 bool uniform = true;
1643 int i;
1644
1645 assert(sscreen->info.chip_class <= GFX9);
1646
1647 /* Colorspace (return non-RGB formats directly). */
1648 switch (desc->colorspace) {
1649 /* Depth stencil formats */
1650 case UTIL_FORMAT_COLORSPACE_ZS:
1651 switch (format) {
1652 case PIPE_FORMAT_Z16_UNORM:
1653 return V_008F14_IMG_DATA_FORMAT_16;
1654 case PIPE_FORMAT_X24S8_UINT:
1655 case PIPE_FORMAT_S8X24_UINT:
1656 /*
1657 * Implemented as an 8_8_8_8 data format to fix texture
1658 * gathers in stencil sampling. This affects at least
1659 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1660 */
1661 if (sscreen->info.chip_class <= GFX8)
1662 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1663
1664 if (format == PIPE_FORMAT_X24S8_UINT)
1665 return V_008F14_IMG_DATA_FORMAT_8_24;
1666 else
1667 return V_008F14_IMG_DATA_FORMAT_24_8;
1668 case PIPE_FORMAT_Z24X8_UNORM:
1669 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1670 return V_008F14_IMG_DATA_FORMAT_8_24;
1671 case PIPE_FORMAT_X8Z24_UNORM:
1672 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1673 return V_008F14_IMG_DATA_FORMAT_24_8;
1674 case PIPE_FORMAT_S8_UINT:
1675 return V_008F14_IMG_DATA_FORMAT_8;
1676 case PIPE_FORMAT_Z32_FLOAT:
1677 return V_008F14_IMG_DATA_FORMAT_32;
1678 case PIPE_FORMAT_X32_S8X24_UINT:
1679 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1680 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1681 default:
1682 goto out_unknown;
1683 }
1684
1685 case UTIL_FORMAT_COLORSPACE_YUV:
1686 goto out_unknown; /* TODO */
1687
1688 case UTIL_FORMAT_COLORSPACE_SRGB:
1689 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1690 goto out_unknown;
1691 break;
1692
1693 default:
1694 break;
1695 }
1696
1697 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1698 if (!sscreen->info.has_format_bc1_through_bc7)
1699 goto out_unknown;
1700
1701 switch (format) {
1702 case PIPE_FORMAT_RGTC1_SNORM:
1703 case PIPE_FORMAT_LATC1_SNORM:
1704 case PIPE_FORMAT_RGTC1_UNORM:
1705 case PIPE_FORMAT_LATC1_UNORM:
1706 return V_008F14_IMG_DATA_FORMAT_BC4;
1707 case PIPE_FORMAT_RGTC2_SNORM:
1708 case PIPE_FORMAT_LATC2_SNORM:
1709 case PIPE_FORMAT_RGTC2_UNORM:
1710 case PIPE_FORMAT_LATC2_UNORM:
1711 return V_008F14_IMG_DATA_FORMAT_BC5;
1712 default:
1713 goto out_unknown;
1714 }
1715 }
1716
1717 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1718 (sscreen->info.family == CHIP_STONEY ||
1719 sscreen->info.family == CHIP_VEGA10 ||
1720 sscreen->info.family == CHIP_RAVEN)) {
1721 switch (format) {
1722 case PIPE_FORMAT_ETC1_RGB8:
1723 case PIPE_FORMAT_ETC2_RGB8:
1724 case PIPE_FORMAT_ETC2_SRGB8:
1725 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1726 case PIPE_FORMAT_ETC2_RGB8A1:
1727 case PIPE_FORMAT_ETC2_SRGB8A1:
1728 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1729 case PIPE_FORMAT_ETC2_RGBA8:
1730 case PIPE_FORMAT_ETC2_SRGBA8:
1731 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1732 case PIPE_FORMAT_ETC2_R11_UNORM:
1733 case PIPE_FORMAT_ETC2_R11_SNORM:
1734 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1735 case PIPE_FORMAT_ETC2_RG11_UNORM:
1736 case PIPE_FORMAT_ETC2_RG11_SNORM:
1737 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1738 default:
1739 goto out_unknown;
1740 }
1741 }
1742
1743 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1744 if (!sscreen->info.has_format_bc1_through_bc7)
1745 goto out_unknown;
1746
1747 switch (format) {
1748 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1749 case PIPE_FORMAT_BPTC_SRGBA:
1750 return V_008F14_IMG_DATA_FORMAT_BC7;
1751 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1752 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1753 return V_008F14_IMG_DATA_FORMAT_BC6;
1754 default:
1755 goto out_unknown;
1756 }
1757 }
1758
1759 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1760 switch (format) {
1761 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1762 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1763 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1764 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1765 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1766 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1767 default:
1768 goto out_unknown;
1769 }
1770 }
1771
1772 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1773 if (!sscreen->info.has_format_bc1_through_bc7)
1774 goto out_unknown;
1775
1776 switch (format) {
1777 case PIPE_FORMAT_DXT1_RGB:
1778 case PIPE_FORMAT_DXT1_RGBA:
1779 case PIPE_FORMAT_DXT1_SRGB:
1780 case PIPE_FORMAT_DXT1_SRGBA:
1781 return V_008F14_IMG_DATA_FORMAT_BC1;
1782 case PIPE_FORMAT_DXT3_RGBA:
1783 case PIPE_FORMAT_DXT3_SRGBA:
1784 return V_008F14_IMG_DATA_FORMAT_BC2;
1785 case PIPE_FORMAT_DXT5_RGBA:
1786 case PIPE_FORMAT_DXT5_SRGBA:
1787 return V_008F14_IMG_DATA_FORMAT_BC3;
1788 default:
1789 goto out_unknown;
1790 }
1791 }
1792
1793 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1794 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1795 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1796 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1797 }
1798
1799 /* R8G8Bx_SNORM - TODO CxV8U8 */
1800
1801 /* hw cannot support mixed formats (except depth/stencil, since only
1802 * depth is read).*/
1803 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1804 goto out_unknown;
1805
1806 /* See whether the components are of the same size. */
1807 for (i = 1; i < desc->nr_channels; i++) {
1808 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1809 }
1810
1811 /* Non-uniform formats. */
1812 if (!uniform) {
1813 switch(desc->nr_channels) {
1814 case 3:
1815 if (desc->channel[0].size == 5 &&
1816 desc->channel[1].size == 6 &&
1817 desc->channel[2].size == 5) {
1818 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1819 }
1820 goto out_unknown;
1821 case 4:
1822 if (desc->channel[0].size == 5 &&
1823 desc->channel[1].size == 5 &&
1824 desc->channel[2].size == 5 &&
1825 desc->channel[3].size == 1) {
1826 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1827 }
1828 if (desc->channel[0].size == 1 &&
1829 desc->channel[1].size == 5 &&
1830 desc->channel[2].size == 5 &&
1831 desc->channel[3].size == 5) {
1832 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1833 }
1834 if (desc->channel[0].size == 10 &&
1835 desc->channel[1].size == 10 &&
1836 desc->channel[2].size == 10 &&
1837 desc->channel[3].size == 2) {
1838 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1839 }
1840 goto out_unknown;
1841 }
1842 goto out_unknown;
1843 }
1844
1845 if (first_non_void < 0 || first_non_void > 3)
1846 goto out_unknown;
1847
1848 /* uniform formats */
1849 switch (desc->channel[first_non_void].size) {
1850 case 4:
1851 switch (desc->nr_channels) {
1852 #if 0 /* Not supported for render targets */
1853 case 2:
1854 return V_008F14_IMG_DATA_FORMAT_4_4;
1855 #endif
1856 case 4:
1857 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1858 }
1859 break;
1860 case 8:
1861 switch (desc->nr_channels) {
1862 case 1:
1863 return V_008F14_IMG_DATA_FORMAT_8;
1864 case 2:
1865 return V_008F14_IMG_DATA_FORMAT_8_8;
1866 case 4:
1867 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1868 }
1869 break;
1870 case 16:
1871 switch (desc->nr_channels) {
1872 case 1:
1873 return V_008F14_IMG_DATA_FORMAT_16;
1874 case 2:
1875 return V_008F14_IMG_DATA_FORMAT_16_16;
1876 case 4:
1877 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1878 }
1879 break;
1880 case 32:
1881 switch (desc->nr_channels) {
1882 case 1:
1883 return V_008F14_IMG_DATA_FORMAT_32;
1884 case 2:
1885 return V_008F14_IMG_DATA_FORMAT_32_32;
1886 #if 0 /* Not supported for render targets */
1887 case 3:
1888 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1889 #endif
1890 case 4:
1891 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1892 }
1893 }
1894
1895 out_unknown:
1896 return ~0;
1897 }
1898
1899 static unsigned si_tex_wrap(unsigned wrap)
1900 {
1901 switch (wrap) {
1902 default:
1903 case PIPE_TEX_WRAP_REPEAT:
1904 return V_008F30_SQ_TEX_WRAP;
1905 case PIPE_TEX_WRAP_CLAMP:
1906 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1907 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1908 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1909 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1910 return V_008F30_SQ_TEX_CLAMP_BORDER;
1911 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1912 return V_008F30_SQ_TEX_MIRROR;
1913 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1914 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1915 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1916 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1917 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1918 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1919 }
1920 }
1921
1922 static unsigned si_tex_mipfilter(unsigned filter)
1923 {
1924 switch (filter) {
1925 case PIPE_TEX_MIPFILTER_NEAREST:
1926 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1927 case PIPE_TEX_MIPFILTER_LINEAR:
1928 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1929 default:
1930 case PIPE_TEX_MIPFILTER_NONE:
1931 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1932 }
1933 }
1934
1935 static unsigned si_tex_compare(unsigned compare)
1936 {
1937 switch (compare) {
1938 default:
1939 case PIPE_FUNC_NEVER:
1940 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1941 case PIPE_FUNC_LESS:
1942 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1943 case PIPE_FUNC_EQUAL:
1944 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1945 case PIPE_FUNC_LEQUAL:
1946 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1947 case PIPE_FUNC_GREATER:
1948 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1949 case PIPE_FUNC_NOTEQUAL:
1950 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1951 case PIPE_FUNC_GEQUAL:
1952 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1953 case PIPE_FUNC_ALWAYS:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1955 }
1956 }
1957
1958 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1959 unsigned view_target, unsigned nr_samples)
1960 {
1961 unsigned res_target = tex->buffer.b.b.target;
1962
1963 if (view_target == PIPE_TEXTURE_CUBE ||
1964 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1965 res_target = view_target;
1966 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1967 else if (res_target == PIPE_TEXTURE_CUBE ||
1968 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1969 res_target = PIPE_TEXTURE_2D_ARRAY;
1970
1971 /* GFX9 allocates 1D textures as 2D. */
1972 if ((res_target == PIPE_TEXTURE_1D ||
1973 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1974 sscreen->info.chip_class >= GFX9 &&
1975 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1976 if (res_target == PIPE_TEXTURE_1D)
1977 res_target = PIPE_TEXTURE_2D;
1978 else
1979 res_target = PIPE_TEXTURE_2D_ARRAY;
1980 }
1981
1982 switch (res_target) {
1983 default:
1984 case PIPE_TEXTURE_1D:
1985 return V_008F1C_SQ_RSRC_IMG_1D;
1986 case PIPE_TEXTURE_1D_ARRAY:
1987 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1988 case PIPE_TEXTURE_2D:
1989 case PIPE_TEXTURE_RECT:
1990 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1991 V_008F1C_SQ_RSRC_IMG_2D;
1992 case PIPE_TEXTURE_2D_ARRAY:
1993 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1994 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1995 case PIPE_TEXTURE_3D:
1996 return V_008F1C_SQ_RSRC_IMG_3D;
1997 case PIPE_TEXTURE_CUBE:
1998 case PIPE_TEXTURE_CUBE_ARRAY:
1999 return V_008F1C_SQ_RSRC_IMG_CUBE;
2000 }
2001 }
2002
2003 /*
2004 * Format support testing
2005 */
2006
2007 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2008 {
2009 struct si_screen *sscreen = (struct si_screen *)screen;
2010
2011 if (sscreen->info.chip_class >= GFX10) {
2012 const struct gfx10_format *fmt = &gfx10_format_table[format];
2013 if (!fmt->img_format || fmt->buffers_only)
2014 return false;
2015 return true;
2016 }
2017
2018 const struct util_format_description *desc = util_format_description(format);
2019 if (!desc)
2020 return false;
2021
2022 return si_translate_texformat(screen, format, desc,
2023 util_format_get_first_non_void_channel(format)) != ~0U;
2024 }
2025
2026 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2027 const struct util_format_description *desc,
2028 int first_non_void)
2029 {
2030 int i;
2031
2032 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2033
2034 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2035 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2036
2037 assert(first_non_void >= 0);
2038
2039 if (desc->nr_channels == 4 &&
2040 desc->channel[0].size == 10 &&
2041 desc->channel[1].size == 10 &&
2042 desc->channel[2].size == 10 &&
2043 desc->channel[3].size == 2)
2044 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2045
2046 /* See whether the components are of the same size. */
2047 for (i = 0; i < desc->nr_channels; i++) {
2048 if (desc->channel[first_non_void].size != desc->channel[i].size)
2049 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2050 }
2051
2052 switch (desc->channel[first_non_void].size) {
2053 case 8:
2054 switch (desc->nr_channels) {
2055 case 1:
2056 case 3: /* 3 loads */
2057 return V_008F0C_BUF_DATA_FORMAT_8;
2058 case 2:
2059 return V_008F0C_BUF_DATA_FORMAT_8_8;
2060 case 4:
2061 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2062 }
2063 break;
2064 case 16:
2065 switch (desc->nr_channels) {
2066 case 1:
2067 case 3: /* 3 loads */
2068 return V_008F0C_BUF_DATA_FORMAT_16;
2069 case 2:
2070 return V_008F0C_BUF_DATA_FORMAT_16_16;
2071 case 4:
2072 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2073 }
2074 break;
2075 case 32:
2076 switch (desc->nr_channels) {
2077 case 1:
2078 return V_008F0C_BUF_DATA_FORMAT_32;
2079 case 2:
2080 return V_008F0C_BUF_DATA_FORMAT_32_32;
2081 case 3:
2082 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2083 case 4:
2084 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2085 }
2086 break;
2087 case 64:
2088 /* Legacy double formats. */
2089 switch (desc->nr_channels) {
2090 case 1: /* 1 load */
2091 return V_008F0C_BUF_DATA_FORMAT_32_32;
2092 case 2: /* 1 load */
2093 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2094 case 3: /* 3 loads */
2095 return V_008F0C_BUF_DATA_FORMAT_32_32;
2096 case 4: /* 2 loads */
2097 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2098 }
2099 break;
2100 }
2101
2102 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2103 }
2104
2105 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2106 const struct util_format_description *desc,
2107 int first_non_void)
2108 {
2109 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2110
2111 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2112 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2113
2114 assert(first_non_void >= 0);
2115
2116 switch (desc->channel[first_non_void].type) {
2117 case UTIL_FORMAT_TYPE_SIGNED:
2118 case UTIL_FORMAT_TYPE_FIXED:
2119 if (desc->channel[first_non_void].size >= 32 ||
2120 desc->channel[first_non_void].pure_integer)
2121 return V_008F0C_BUF_NUM_FORMAT_SINT;
2122 else if (desc->channel[first_non_void].normalized)
2123 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2124 else
2125 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2126 break;
2127 case UTIL_FORMAT_TYPE_UNSIGNED:
2128 if (desc->channel[first_non_void].size >= 32 ||
2129 desc->channel[first_non_void].pure_integer)
2130 return V_008F0C_BUF_NUM_FORMAT_UINT;
2131 else if (desc->channel[first_non_void].normalized)
2132 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2133 else
2134 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2135 break;
2136 case UTIL_FORMAT_TYPE_FLOAT:
2137 default:
2138 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2139 }
2140 }
2141
2142 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2143 enum pipe_format format,
2144 unsigned usage)
2145 {
2146 struct si_screen *sscreen = (struct si_screen *)screen;
2147 const struct util_format_description *desc;
2148 int first_non_void;
2149 unsigned data_format;
2150
2151 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2152 PIPE_BIND_SAMPLER_VIEW |
2153 PIPE_BIND_VERTEX_BUFFER)) == 0);
2154
2155 desc = util_format_description(format);
2156 if (!desc)
2157 return 0;
2158
2159 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2160 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2161 * for read-only access (with caveats surrounding bounds checks), but
2162 * obviously fails for write access which we have to implement for
2163 * shader images. Luckily, OpenGL doesn't expect this to be supported
2164 * anyway, and so the only impact is on PBO uploads / downloads, which
2165 * shouldn't be expected to be fast for GL_RGB anyway.
2166 */
2167 if (desc->block.bits == 3 * 8 ||
2168 desc->block.bits == 3 * 16) {
2169 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2170 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2171 if (!usage)
2172 return 0;
2173 }
2174 }
2175
2176 if (sscreen->info.chip_class >= GFX10) {
2177 const struct gfx10_format *fmt = &gfx10_format_table[format];
2178 if (!fmt->img_format || fmt->img_format >= 128)
2179 return 0;
2180 return usage;
2181 }
2182
2183 first_non_void = util_format_get_first_non_void_channel(format);
2184 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2185 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2186 return 0;
2187
2188 return usage;
2189 }
2190
2191 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2192 {
2193 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2194 si_translate_colorswap(format, false) != ~0U;
2195 }
2196
2197 static bool si_is_zs_format_supported(enum pipe_format format)
2198 {
2199 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2200 }
2201
2202 static boolean si_is_format_supported(struct pipe_screen *screen,
2203 enum pipe_format format,
2204 enum pipe_texture_target target,
2205 unsigned sample_count,
2206 unsigned storage_sample_count,
2207 unsigned usage)
2208 {
2209 struct si_screen *sscreen = (struct si_screen *)screen;
2210 unsigned retval = 0;
2211
2212 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2213 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2214 return false;
2215 }
2216
2217 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2218 return false;
2219
2220 if (sample_count > 1) {
2221 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2222 return false;
2223
2224 if (usage & PIPE_BIND_SHADER_IMAGE)
2225 return false;
2226
2227 /* Only power-of-two sample counts are supported. */
2228 if (!util_is_power_of_two_or_zero(sample_count) ||
2229 !util_is_power_of_two_or_zero(storage_sample_count))
2230 return false;
2231
2232 /* MSAA support without framebuffer attachments. */
2233 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2234 return true;
2235
2236 if (!sscreen->info.has_eqaa_surface_allocator ||
2237 util_format_is_depth_or_stencil(format)) {
2238 /* Color without EQAA or depth/stencil. */
2239 if (sample_count > 8 ||
2240 sample_count != storage_sample_count)
2241 return false;
2242 } else {
2243 /* Color with EQAA. */
2244 if (sample_count > 16 ||
2245 storage_sample_count > 8)
2246 return false;
2247 }
2248 }
2249
2250 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2251 PIPE_BIND_SHADER_IMAGE)) {
2252 if (target == PIPE_BUFFER) {
2253 retval |= si_is_vertex_format_supported(
2254 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2255 PIPE_BIND_SHADER_IMAGE));
2256 } else {
2257 if (si_is_sampler_format_supported(screen, format))
2258 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2259 PIPE_BIND_SHADER_IMAGE);
2260 }
2261 }
2262
2263 if ((usage & (PIPE_BIND_RENDER_TARGET |
2264 PIPE_BIND_DISPLAY_TARGET |
2265 PIPE_BIND_SCANOUT |
2266 PIPE_BIND_SHARED |
2267 PIPE_BIND_BLENDABLE)) &&
2268 si_is_colorbuffer_format_supported(format)) {
2269 retval |= usage &
2270 (PIPE_BIND_RENDER_TARGET |
2271 PIPE_BIND_DISPLAY_TARGET |
2272 PIPE_BIND_SCANOUT |
2273 PIPE_BIND_SHARED);
2274 if (!util_format_is_pure_integer(format) &&
2275 !util_format_is_depth_or_stencil(format))
2276 retval |= usage & PIPE_BIND_BLENDABLE;
2277 }
2278
2279 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2280 si_is_zs_format_supported(format)) {
2281 retval |= PIPE_BIND_DEPTH_STENCIL;
2282 }
2283
2284 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2285 retval |= si_is_vertex_format_supported(screen, format,
2286 PIPE_BIND_VERTEX_BUFFER);
2287 }
2288
2289 if ((usage & PIPE_BIND_LINEAR) &&
2290 !util_format_is_compressed(format) &&
2291 !(usage & PIPE_BIND_DEPTH_STENCIL))
2292 retval |= PIPE_BIND_LINEAR;
2293
2294 return retval == usage;
2295 }
2296
2297 /*
2298 * framebuffer handling
2299 */
2300
2301 static void si_choose_spi_color_formats(struct si_surface *surf,
2302 unsigned format, unsigned swap,
2303 unsigned ntype, bool is_depth)
2304 {
2305 /* Alpha is needed for alpha-to-coverage.
2306 * Blending may be with or without alpha.
2307 */
2308 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2309 unsigned alpha = 0; /* exports alpha, but may not support blending */
2310 unsigned blend = 0; /* supports blending, but may not export alpha */
2311 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2312
2313 /* Choose the SPI color formats. These are required values for RB+.
2314 * Other chips have multiple choices, though they are not necessarily better.
2315 */
2316 switch (format) {
2317 case V_028C70_COLOR_5_6_5:
2318 case V_028C70_COLOR_1_5_5_5:
2319 case V_028C70_COLOR_5_5_5_1:
2320 case V_028C70_COLOR_4_4_4_4:
2321 case V_028C70_COLOR_10_11_11:
2322 case V_028C70_COLOR_11_11_10:
2323 case V_028C70_COLOR_8:
2324 case V_028C70_COLOR_8_8:
2325 case V_028C70_COLOR_8_8_8_8:
2326 case V_028C70_COLOR_10_10_10_2:
2327 case V_028C70_COLOR_2_10_10_10:
2328 if (ntype == V_028C70_NUMBER_UINT)
2329 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2330 else if (ntype == V_028C70_NUMBER_SINT)
2331 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2332 else
2333 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2334 break;
2335
2336 case V_028C70_COLOR_16:
2337 case V_028C70_COLOR_16_16:
2338 case V_028C70_COLOR_16_16_16_16:
2339 if (ntype == V_028C70_NUMBER_UNORM ||
2340 ntype == V_028C70_NUMBER_SNORM) {
2341 /* UNORM16 and SNORM16 don't support blending */
2342 if (ntype == V_028C70_NUMBER_UNORM)
2343 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2344 else
2345 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2346
2347 /* Use 32 bits per channel for blending. */
2348 if (format == V_028C70_COLOR_16) {
2349 if (swap == V_028C70_SWAP_STD) { /* R */
2350 blend = V_028714_SPI_SHADER_32_R;
2351 blend_alpha = V_028714_SPI_SHADER_32_AR;
2352 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2353 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2354 else
2355 assert(0);
2356 } else if (format == V_028C70_COLOR_16_16) {
2357 if (swap == V_028C70_SWAP_STD) { /* RG */
2358 blend = V_028714_SPI_SHADER_32_GR;
2359 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2360 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2361 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2362 else
2363 assert(0);
2364 } else /* 16_16_16_16 */
2365 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2366 } else if (ntype == V_028C70_NUMBER_UINT)
2367 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2368 else if (ntype == V_028C70_NUMBER_SINT)
2369 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2370 else if (ntype == V_028C70_NUMBER_FLOAT)
2371 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2372 else
2373 assert(0);
2374 break;
2375
2376 case V_028C70_COLOR_32:
2377 if (swap == V_028C70_SWAP_STD) { /* R */
2378 blend = normal = V_028714_SPI_SHADER_32_R;
2379 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2380 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2381 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2382 else
2383 assert(0);
2384 break;
2385
2386 case V_028C70_COLOR_32_32:
2387 if (swap == V_028C70_SWAP_STD) { /* RG */
2388 blend = normal = V_028714_SPI_SHADER_32_GR;
2389 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2390 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2391 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2392 else
2393 assert(0);
2394 break;
2395
2396 case V_028C70_COLOR_32_32_32_32:
2397 case V_028C70_COLOR_8_24:
2398 case V_028C70_COLOR_24_8:
2399 case V_028C70_COLOR_X24_8_32_FLOAT:
2400 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2401 break;
2402
2403 default:
2404 assert(0);
2405 return;
2406 }
2407
2408 /* The DB->CB copy needs 32_ABGR. */
2409 if (is_depth)
2410 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2411
2412 surf->spi_shader_col_format = normal;
2413 surf->spi_shader_col_format_alpha = alpha;
2414 surf->spi_shader_col_format_blend = blend;
2415 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2416 }
2417
2418 static void si_initialize_color_surface(struct si_context *sctx,
2419 struct si_surface *surf)
2420 {
2421 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2422 unsigned color_info, color_attrib;
2423 unsigned format, swap, ntype, endian;
2424 const struct util_format_description *desc;
2425 int firstchan;
2426 unsigned blend_clamp = 0, blend_bypass = 0;
2427
2428 desc = util_format_description(surf->base.format);
2429 for (firstchan = 0; firstchan < 4; firstchan++) {
2430 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2431 break;
2432 }
2433 }
2434 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2435 ntype = V_028C70_NUMBER_FLOAT;
2436 } else {
2437 ntype = V_028C70_NUMBER_UNORM;
2438 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2439 ntype = V_028C70_NUMBER_SRGB;
2440 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2441 if (desc->channel[firstchan].pure_integer) {
2442 ntype = V_028C70_NUMBER_SINT;
2443 } else {
2444 assert(desc->channel[firstchan].normalized);
2445 ntype = V_028C70_NUMBER_SNORM;
2446 }
2447 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2448 if (desc->channel[firstchan].pure_integer) {
2449 ntype = V_028C70_NUMBER_UINT;
2450 } else {
2451 assert(desc->channel[firstchan].normalized);
2452 ntype = V_028C70_NUMBER_UNORM;
2453 }
2454 }
2455 }
2456
2457 format = si_translate_colorformat(surf->base.format);
2458 if (format == V_028C70_COLOR_INVALID) {
2459 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2460 }
2461 assert(format != V_028C70_COLOR_INVALID);
2462 swap = si_translate_colorswap(surf->base.format, false);
2463 endian = si_colorformat_endian_swap(format);
2464
2465 /* blend clamp should be set for all NORM/SRGB types */
2466 if (ntype == V_028C70_NUMBER_UNORM ||
2467 ntype == V_028C70_NUMBER_SNORM ||
2468 ntype == V_028C70_NUMBER_SRGB)
2469 blend_clamp = 1;
2470
2471 /* set blend bypass according to docs if SINT/UINT or
2472 8/24 COLOR variants */
2473 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2474 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2475 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2476 blend_clamp = 0;
2477 blend_bypass = 1;
2478 }
2479
2480 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2481 if (format == V_028C70_COLOR_8 ||
2482 format == V_028C70_COLOR_8_8 ||
2483 format == V_028C70_COLOR_8_8_8_8)
2484 surf->color_is_int8 = true;
2485 else if (format == V_028C70_COLOR_10_10_10_2 ||
2486 format == V_028C70_COLOR_2_10_10_10)
2487 surf->color_is_int10 = true;
2488 }
2489
2490 color_info = S_028C70_FORMAT(format) |
2491 S_028C70_COMP_SWAP(swap) |
2492 S_028C70_BLEND_CLAMP(blend_clamp) |
2493 S_028C70_BLEND_BYPASS(blend_bypass) |
2494 S_028C70_SIMPLE_FLOAT(1) |
2495 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2496 ntype != V_028C70_NUMBER_SNORM &&
2497 ntype != V_028C70_NUMBER_SRGB &&
2498 format != V_028C70_COLOR_8_24 &&
2499 format != V_028C70_COLOR_24_8) |
2500 S_028C70_NUMBER_TYPE(ntype) |
2501 S_028C70_ENDIAN(endian);
2502
2503 /* Intensity is implemented as Red, so treat it that way. */
2504 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2505 util_format_is_intensity(surf->base.format));
2506
2507 if (tex->buffer.b.b.nr_samples > 1) {
2508 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2509 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2510
2511 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2512 S_028C74_NUM_FRAGMENTS(log_fragments);
2513
2514 if (tex->fmask_offset) {
2515 color_info |= S_028C70_COMPRESSION(1);
2516 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2517
2518 if (sctx->chip_class == GFX6) {
2519 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2520 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2521 }
2522 }
2523 }
2524
2525 if (sctx->chip_class >= GFX10) {
2526 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2527
2528 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2529 64 for APU because all of our APUs to date use DIMMs which have
2530 a request granularity size of 64B while all other chips have a
2531 32B request size */
2532 if (!sctx->screen->info.has_dedicated_vram)
2533 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2534
2535 surf->cb_dcc_control =
2536 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2537 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2538 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2539 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2540 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2541 } else if (sctx->chip_class >= GFX8) {
2542 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2543 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2544
2545 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2546 64 for APU because all of our APUs to date use DIMMs which have
2547 a request granularity size of 64B while all other chips have a
2548 32B request size */
2549 if (!sctx->screen->info.has_dedicated_vram)
2550 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2551
2552 if (tex->buffer.b.b.nr_storage_samples > 1) {
2553 if (tex->surface.bpe == 1)
2554 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2555 else if (tex->surface.bpe == 2)
2556 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2557 }
2558
2559 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2560 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2561 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2562 }
2563
2564 /* This must be set for fast clear to work without FMASK. */
2565 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2566 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2567 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2568 }
2569
2570 /* GFX10 field has the same base shift as the GFX6 field */
2571 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2572 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2573 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2574
2575 if (sctx->chip_class >= GFX10) {
2576 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2577
2578 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2579 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2580 S_028EE0_RESOURCE_LEVEL(1);
2581 } else if (sctx->chip_class >= GFX9) {
2582 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2583 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2584 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2585 }
2586
2587 if (sctx->chip_class >= GFX9) {
2588 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2589 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2590 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2591 }
2592
2593 surf->cb_color_view = color_view;
2594 surf->cb_color_info = color_info;
2595 surf->cb_color_attrib = color_attrib;
2596
2597 /* Determine pixel shader export format */
2598 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2599
2600 surf->color_initialized = true;
2601 }
2602
2603 static void si_init_depth_surface(struct si_context *sctx,
2604 struct si_surface *surf)
2605 {
2606 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2607 unsigned level = surf->base.u.tex.level;
2608 unsigned format, stencil_format;
2609 uint32_t z_info, s_info;
2610
2611 format = si_translate_dbformat(tex->db_render_format);
2612 stencil_format = tex->surface.has_stencil ?
2613 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2614
2615 assert(format != V_028040_Z_INVALID);
2616 if (format == V_028040_Z_INVALID)
2617 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2618
2619 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2620 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2621 surf->db_htile_data_base = 0;
2622 surf->db_htile_surface = 0;
2623
2624 if (sctx->chip_class >= GFX10) {
2625 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2626 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2627 }
2628
2629 if (sctx->chip_class >= GFX9) {
2630 assert(tex->surface.u.gfx9.surf_offset == 0);
2631 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2632 surf->db_stencil_base = (tex->buffer.gpu_address +
2633 tex->surface.u.gfx9.stencil_offset) >> 8;
2634 z_info = S_028038_FORMAT(format) |
2635 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2636 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2637 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2638 s_info = S_02803C_FORMAT(stencil_format) |
2639 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2640
2641 if (sctx->chip_class == GFX9) {
2642 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2643 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2644 }
2645 surf->db_depth_view |= S_028008_MIPID(level);
2646 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2647 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2648
2649 if (si_htile_enabled(tex, level)) {
2650 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2651 S_028038_ALLOW_EXPCLEAR(1);
2652
2653 if (tex->tc_compatible_htile) {
2654 unsigned max_zplanes = 4;
2655
2656 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2657 tex->buffer.b.b.nr_samples > 1)
2658 max_zplanes = 2;
2659
2660 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2661
2662 if (sctx->chip_class >= GFX10) {
2663 z_info |= S_028040_ITERATE_FLUSH(1);
2664 s_info |= S_028044_ITERATE_FLUSH(1);
2665 } else {
2666 z_info |= S_028038_ITERATE_FLUSH(1);
2667 s_info |= S_02803C_ITERATE_FLUSH(1);
2668 }
2669 }
2670
2671 if (tex->surface.has_stencil) {
2672 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2673 * See that for explanation.
2674 */
2675 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2676 } else {
2677 /* Use all HTILE for depth if there's no stencil. */
2678 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2679 }
2680
2681 surf->db_htile_data_base = (tex->buffer.gpu_address +
2682 tex->htile_offset) >> 8;
2683 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2684 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2685 if (sctx->chip_class == GFX9) {
2686 surf->db_htile_surface |=
2687 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2688 }
2689 }
2690 } else {
2691 /* GFX6-GFX8 */
2692 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2693
2694 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2695
2696 surf->db_depth_base = (tex->buffer.gpu_address +
2697 tex->surface.u.legacy.level[level].offset) >> 8;
2698 surf->db_stencil_base = (tex->buffer.gpu_address +
2699 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2700
2701 z_info = S_028040_FORMAT(format) |
2702 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2703 s_info = S_028044_FORMAT(stencil_format);
2704 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2705
2706 if (sctx->chip_class >= GFX7) {
2707 struct radeon_info *info = &sctx->screen->info;
2708 unsigned index = tex->surface.u.legacy.tiling_index[level];
2709 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2710 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2711 unsigned tile_mode = info->si_tile_mode_array[index];
2712 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2713 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2714
2715 surf->db_depth_info |=
2716 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2717 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2718 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2719 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2720 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2721 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2722 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2723 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2724 } else {
2725 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2726 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2727 tile_mode_index = si_tile_mode_index(tex, level, true);
2728 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2729 }
2730
2731 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2732 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2733 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2734 levelinfo->nblk_y) / 64 - 1);
2735
2736 if (si_htile_enabled(tex, level)) {
2737 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2738 S_028040_ALLOW_EXPCLEAR(1);
2739
2740 if (tex->surface.has_stencil) {
2741 /* Workaround: For a not yet understood reason, the
2742 * combination of MSAA, fast stencil clear and stencil
2743 * decompress messes with subsequent stencil buffer
2744 * uses. Problem was reproduced on Verde, Bonaire,
2745 * Tonga, and Carrizo.
2746 *
2747 * Disabling EXPCLEAR works around the problem.
2748 *
2749 * Check piglit's arb_texture_multisample-stencil-clear
2750 * test if you want to try changing this.
2751 */
2752 if (tex->buffer.b.b.nr_samples <= 1)
2753 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2754 } else if (!tex->tc_compatible_htile) {
2755 /* Use all of the htile_buffer for depth if there's no stencil.
2756 * This must not be set when TC-compatible HTILE is enabled
2757 * due to a hw bug.
2758 */
2759 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2760 }
2761
2762 surf->db_htile_data_base = (tex->buffer.gpu_address +
2763 tex->htile_offset) >> 8;
2764 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2765
2766 if (tex->tc_compatible_htile) {
2767 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2768
2769 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2770 if (tex->buffer.b.b.nr_samples <= 1)
2771 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2772 else if (tex->buffer.b.b.nr_samples <= 4)
2773 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2774 else
2775 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2776 }
2777 }
2778 }
2779
2780 surf->db_z_info = z_info;
2781 surf->db_stencil_info = s_info;
2782
2783 surf->depth_initialized = true;
2784 }
2785
2786 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2787 {
2788 if (sctx->decompression_enabled)
2789 return;
2790
2791 if (sctx->framebuffer.state.zsbuf) {
2792 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2793 struct si_texture *tex = (struct si_texture *)surf->texture;
2794
2795 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2796
2797 if (tex->surface.has_stencil)
2798 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2799 }
2800
2801 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2802 while (compressed_cb_mask) {
2803 unsigned i = u_bit_scan(&compressed_cb_mask);
2804 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2805 struct si_texture *tex = (struct si_texture*)surf->texture;
2806
2807 if (tex->fmask_offset)
2808 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2809 if (tex->dcc_gather_statistics)
2810 tex->separate_dcc_dirty = true;
2811 }
2812 }
2813
2814 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2815 {
2816 for (int i = 0; i < state->nr_cbufs; ++i) {
2817 struct si_surface *surf = NULL;
2818 struct si_texture *tex;
2819
2820 if (!state->cbufs[i])
2821 continue;
2822 surf = (struct si_surface*)state->cbufs[i];
2823 tex = (struct si_texture*)surf->base.texture;
2824
2825 p_atomic_dec(&tex->framebuffers_bound);
2826 }
2827 }
2828
2829 static void si_set_framebuffer_state(struct pipe_context *ctx,
2830 const struct pipe_framebuffer_state *state)
2831 {
2832 struct si_context *sctx = (struct si_context *)ctx;
2833 struct si_surface *surf = NULL;
2834 struct si_texture *tex;
2835 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2836 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2837 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2838 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2839 bool old_has_stencil =
2840 old_has_zsbuf &&
2841 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2842 bool unbound = false;
2843 int i;
2844
2845 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2846 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2847 * We could implement the full workaround here, but it's a useless case.
2848 */
2849 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2850 unreachable("the framebuffer shouldn't have zero area");
2851 return;
2852 }
2853
2854 si_update_fb_dirtiness_after_rendering(sctx);
2855
2856 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2857 if (!sctx->framebuffer.state.cbufs[i])
2858 continue;
2859
2860 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2861 if (tex->dcc_gather_statistics)
2862 vi_separate_dcc_stop_query(sctx, tex);
2863 }
2864
2865 /* Disable DCC if the formats are incompatible. */
2866 for (i = 0; i < state->nr_cbufs; i++) {
2867 if (!state->cbufs[i])
2868 continue;
2869
2870 surf = (struct si_surface*)state->cbufs[i];
2871 tex = (struct si_texture*)surf->base.texture;
2872
2873 if (!surf->dcc_incompatible)
2874 continue;
2875
2876 /* Since the DCC decompression calls back into set_framebuffer-
2877 * _state, we need to unbind the framebuffer, so that
2878 * vi_separate_dcc_stop_query isn't called twice with the same
2879 * color buffer.
2880 */
2881 if (!unbound) {
2882 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2883 unbound = true;
2884 }
2885
2886 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2887 if (!si_texture_disable_dcc(sctx, tex))
2888 si_decompress_dcc(sctx, tex);
2889
2890 surf->dcc_incompatible = false;
2891 }
2892
2893 /* Only flush TC when changing the framebuffer state, because
2894 * the only client not using TC that can change textures is
2895 * the framebuffer.
2896 *
2897 * Wait for compute shaders because of possible transitions:
2898 * - FB write -> shader read
2899 * - shader write -> FB read
2900 *
2901 * DB caches are flushed on demand (using si_decompress_textures).
2902 *
2903 * When MSAA is enabled, CB and TC caches are flushed on demand
2904 * (after FMASK decompression). Shader write -> FB read transitions
2905 * cannot happen for MSAA textures, because MSAA shader images are
2906 * not supported.
2907 *
2908 * Only flush and wait for CB if there is actually a bound color buffer.
2909 */
2910 if (sctx->framebuffer.uncompressed_cb_mask) {
2911 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2912 sctx->framebuffer.CB_has_shader_readable_metadata,
2913 sctx->framebuffer.all_DCC_pipe_aligned);
2914 }
2915
2916 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2917
2918 /* u_blitter doesn't invoke depth decompression when it does multiple
2919 * blits in a row, but the only case when it matters for DB is when
2920 * doing generate_mipmap. So here we flush DB manually between
2921 * individual generate_mipmap blits.
2922 * Note that lower mipmap levels aren't compressed.
2923 */
2924 if (sctx->generate_mipmap_for_depth) {
2925 si_make_DB_shader_coherent(sctx, 1, false,
2926 sctx->framebuffer.DB_has_shader_readable_metadata);
2927 } else if (sctx->chip_class == GFX9) {
2928 /* It appears that DB metadata "leaks" in a sequence of:
2929 * - depth clear
2930 * - DCC decompress for shader image writes (with DB disabled)
2931 * - render with DEPTH_BEFORE_SHADER=1
2932 * Flushing DB metadata works around the problem.
2933 */
2934 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2935 }
2936
2937 /* Take the maximum of the old and new count. If the new count is lower,
2938 * dirtying is needed to disable the unbound colorbuffers.
2939 */
2940 sctx->framebuffer.dirty_cbufs |=
2941 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2942 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2943
2944 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2945 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2946
2947 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2948 sctx->framebuffer.spi_shader_col_format = 0;
2949 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2950 sctx->framebuffer.spi_shader_col_format_blend = 0;
2951 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2952 sctx->framebuffer.color_is_int8 = 0;
2953 sctx->framebuffer.color_is_int10 = 0;
2954
2955 sctx->framebuffer.compressed_cb_mask = 0;
2956 sctx->framebuffer.uncompressed_cb_mask = 0;
2957 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2958 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2959 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2960 sctx->framebuffer.any_dst_linear = false;
2961 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2962 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2963 sctx->framebuffer.all_DCC_pipe_aligned = true;
2964 unsigned num_bpp64_colorbufs = 0;
2965
2966 for (i = 0; i < state->nr_cbufs; i++) {
2967 if (!state->cbufs[i])
2968 continue;
2969
2970 surf = (struct si_surface*)state->cbufs[i];
2971 tex = (struct si_texture*)surf->base.texture;
2972
2973 if (!surf->color_initialized) {
2974 si_initialize_color_surface(sctx, surf);
2975 }
2976
2977 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2978 sctx->framebuffer.spi_shader_col_format |=
2979 surf->spi_shader_col_format << (i * 4);
2980 sctx->framebuffer.spi_shader_col_format_alpha |=
2981 surf->spi_shader_col_format_alpha << (i * 4);
2982 sctx->framebuffer.spi_shader_col_format_blend |=
2983 surf->spi_shader_col_format_blend << (i * 4);
2984 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2985 surf->spi_shader_col_format_blend_alpha << (i * 4);
2986
2987 if (surf->color_is_int8)
2988 sctx->framebuffer.color_is_int8 |= 1 << i;
2989 if (surf->color_is_int10)
2990 sctx->framebuffer.color_is_int10 |= 1 << i;
2991
2992 if (tex->fmask_offset)
2993 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2994 else
2995 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2996
2997 /* Don't update nr_color_samples for non-AA buffers.
2998 * (e.g. destination of MSAA resolve)
2999 */
3000 if (tex->buffer.b.b.nr_samples >= 2 &&
3001 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3002 sctx->framebuffer.nr_color_samples =
3003 MIN2(sctx->framebuffer.nr_color_samples,
3004 tex->buffer.b.b.nr_storage_samples);
3005 sctx->framebuffer.nr_color_samples =
3006 MAX2(1, sctx->framebuffer.nr_color_samples);
3007 }
3008
3009 if (tex->surface.is_linear)
3010 sctx->framebuffer.any_dst_linear = true;
3011 if (tex->surface.bpe >= 8)
3012 num_bpp64_colorbufs++;
3013
3014 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3015 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3016
3017 if (sctx->chip_class >= GFX9 &&
3018 !tex->surface.u.gfx9.dcc.pipe_aligned)
3019 sctx->framebuffer.all_DCC_pipe_aligned = false;
3020 }
3021
3022 si_context_add_resource_size(sctx, surf->base.texture);
3023
3024 p_atomic_inc(&tex->framebuffers_bound);
3025
3026 if (tex->dcc_gather_statistics) {
3027 /* Dirty tracking must be enabled for DCC usage analysis. */
3028 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3029 vi_separate_dcc_start_query(sctx, tex);
3030 }
3031 }
3032
3033 /* For optimal DCC performance. */
3034 if (sctx->chip_class == GFX8)
3035 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3036 else if (num_bpp64_colorbufs >= 5)
3037 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
3038 else
3039 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3040
3041 struct si_texture *zstex = NULL;
3042
3043 if (state->zsbuf) {
3044 surf = (struct si_surface*)state->zsbuf;
3045 zstex = (struct si_texture*)surf->base.texture;
3046
3047 if (!surf->depth_initialized) {
3048 si_init_depth_surface(sctx, surf);
3049 }
3050
3051 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
3052 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3053
3054 si_context_add_resource_size(sctx, surf->base.texture);
3055 }
3056
3057 si_update_ps_colorbuf0_slot(sctx);
3058 si_update_poly_offset_state(sctx);
3059 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3060 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3061
3062 if (sctx->screen->dpbb_allowed)
3063 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3064
3065 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3066 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3067
3068 if (sctx->screen->has_out_of_order_rast &&
3069 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3070 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3071 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3072 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3073
3074 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3075 struct pipe_constant_buffer constbuf = {0};
3076
3077 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3078 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3079
3080 constbuf.buffer = sctx->sample_pos_buffer;
3081
3082 /* Set sample locations as fragment shader constants. */
3083 switch (sctx->framebuffer.nr_samples) {
3084 case 1:
3085 constbuf.buffer_offset = 0;
3086 break;
3087 case 2:
3088 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3089 (ubyte*)sctx->sample_positions.x1;
3090 break;
3091 case 4:
3092 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3093 (ubyte*)sctx->sample_positions.x1;
3094 break;
3095 case 8:
3096 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3097 (ubyte*)sctx->sample_positions.x1;
3098 break;
3099 case 16:
3100 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3101 (ubyte*)sctx->sample_positions.x1;
3102 break;
3103 default:
3104 PRINT_ERR("Requested an invalid number of samples %i.\n",
3105 sctx->framebuffer.nr_samples);
3106 assert(0);
3107 }
3108 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3109 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3110
3111 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3112 }
3113
3114 sctx->do_update_shaders = true;
3115
3116 if (!sctx->decompression_enabled) {
3117 /* Prevent textures decompression when the framebuffer state
3118 * changes come from the decompression passes themselves.
3119 */
3120 sctx->need_check_render_feedback = true;
3121 }
3122 }
3123
3124 static void si_emit_framebuffer_state(struct si_context *sctx)
3125 {
3126 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3127 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3128 unsigned i, nr_cbufs = state->nr_cbufs;
3129 struct si_texture *tex = NULL;
3130 struct si_surface *cb = NULL;
3131 unsigned cb_color_info = 0;
3132
3133 /* Colorbuffers. */
3134 for (i = 0; i < nr_cbufs; i++) {
3135 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3136 unsigned cb_color_attrib;
3137
3138 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3139 continue;
3140
3141 cb = (struct si_surface*)state->cbufs[i];
3142 if (!cb) {
3143 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3144 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3145 continue;
3146 }
3147
3148 tex = (struct si_texture *)cb->base.texture;
3149 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3150 &tex->buffer, RADEON_USAGE_READWRITE,
3151 tex->buffer.b.b.nr_samples > 1 ?
3152 RADEON_PRIO_COLOR_BUFFER_MSAA :
3153 RADEON_PRIO_COLOR_BUFFER);
3154
3155 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3156 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3157 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3158 RADEON_PRIO_SEPARATE_META);
3159 }
3160
3161 if (tex->dcc_separate_buffer)
3162 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3163 tex->dcc_separate_buffer,
3164 RADEON_USAGE_READWRITE,
3165 RADEON_PRIO_SEPARATE_META);
3166
3167 /* Compute mutable surface parameters. */
3168 cb_color_base = tex->buffer.gpu_address >> 8;
3169 cb_color_fmask = 0;
3170 cb_color_cmask = tex->cmask_base_address_reg;
3171 cb_dcc_base = 0;
3172 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3173 cb_color_attrib = cb->cb_color_attrib;
3174
3175 if (cb->base.u.tex.level > 0)
3176 cb_color_info &= C_028C70_FAST_CLEAR;
3177
3178 if (tex->fmask_offset) {
3179 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3180 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3181 }
3182
3183 /* Set up DCC. */
3184 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3185 bool is_msaa_resolve_dst = state->cbufs[0] &&
3186 state->cbufs[0]->texture->nr_samples > 1 &&
3187 state->cbufs[1] == &cb->base &&
3188 state->cbufs[1]->texture->nr_samples <= 1;
3189
3190 if (!is_msaa_resolve_dst)
3191 cb_color_info |= S_028C70_DCC_ENABLE(1);
3192
3193 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3194 tex->dcc_offset) >> 8;
3195
3196 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3197 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3198 cb_dcc_base |= dcc_tile_swizzle;
3199 }
3200
3201 if (sctx->chip_class >= GFX10) {
3202 unsigned cb_color_attrib3;
3203
3204 /* Set mutable surface parameters. */
3205 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3206 cb_color_base |= tex->surface.tile_swizzle;
3207 if (!tex->fmask_offset)
3208 cb_color_fmask = cb_color_base;
3209 if (cb->base.u.tex.level > 0)
3210 cb_color_cmask = cb_color_base;
3211
3212 cb_color_attrib3 = cb->cb_color_attrib3 |
3213 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3214 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3215 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3216 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3217
3218 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3219 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3220 radeon_emit(cs, 0); /* hole */
3221 radeon_emit(cs, 0); /* hole */
3222 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3223 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3224 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3225 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3226 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3227 radeon_emit(cs, 0); /* hole */
3228 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3229 radeon_emit(cs, 0); /* hole */
3230 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3231 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3232 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3233
3234 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3235 cb_color_base >> 32);
3236 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3237 cb_color_cmask >> 32);
3238 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3239 cb_color_fmask >> 32);
3240 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3241 cb_dcc_base >> 32);
3242 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3243 cb->cb_color_attrib2);
3244 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3245 cb_color_attrib3);
3246 } else if (sctx->chip_class >= GFX9) {
3247 struct gfx9_surf_meta_flags meta;
3248
3249 if (tex->dcc_offset)
3250 meta = tex->surface.u.gfx9.dcc;
3251 else
3252 meta = tex->surface.u.gfx9.cmask;
3253
3254 /* Set mutable surface parameters. */
3255 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3256 cb_color_base |= tex->surface.tile_swizzle;
3257 if (!tex->fmask_offset)
3258 cb_color_fmask = cb_color_base;
3259 if (cb->base.u.tex.level > 0)
3260 cb_color_cmask = cb_color_base;
3261 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3262 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3263 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3264 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3265
3266 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3267 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3268 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3269 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3270 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3271 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3272 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3273 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3274 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3275 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3276 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3277 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3278 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3279 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3280 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3281 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3282
3283 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3284 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3285 } else {
3286 /* Compute mutable surface parameters (GFX6-GFX8). */
3287 const struct legacy_surf_level *level_info =
3288 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3289 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3290 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3291
3292 cb_color_base += level_info->offset >> 8;
3293 /* Only macrotiled modes can set tile swizzle. */
3294 if (level_info->mode == RADEON_SURF_MODE_2D)
3295 cb_color_base |= tex->surface.tile_swizzle;
3296
3297 if (!tex->fmask_offset)
3298 cb_color_fmask = cb_color_base;
3299 if (cb->base.u.tex.level > 0)
3300 cb_color_cmask = cb_color_base;
3301 if (cb_dcc_base)
3302 cb_dcc_base += level_info->dcc_offset >> 8;
3303
3304 pitch_tile_max = level_info->nblk_x / 8 - 1;
3305 slice_tile_max = level_info->nblk_x *
3306 level_info->nblk_y / 64 - 1;
3307 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3308
3309 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3310 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3311 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3312
3313 if (tex->fmask_offset) {
3314 if (sctx->chip_class >= GFX7)
3315 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3316 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3317 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3318 } else {
3319 /* This must be set for fast clear to work without FMASK. */
3320 if (sctx->chip_class >= GFX7)
3321 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3322 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3323 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3324 }
3325
3326 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3327 sctx->chip_class >= GFX8 ? 14 : 13);
3328 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3329 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3330 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3331 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3332 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3333 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3334 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3335 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3336 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3337 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3338 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3339 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3340 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3341
3342 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3343 radeon_emit(cs, cb_dcc_base);
3344 }
3345 }
3346 for (; i < 8 ; i++)
3347 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3348 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3349
3350 /* ZS buffer. */
3351 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3352 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3353 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3354
3355 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3356 &tex->buffer, RADEON_USAGE_READWRITE,
3357 zb->base.texture->nr_samples > 1 ?
3358 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3359 RADEON_PRIO_DEPTH_BUFFER);
3360
3361 if (sctx->chip_class >= GFX10) {
3362 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3363 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3364
3365 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3366 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3367 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3368 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3369 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3370 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3371 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3372 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3373 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3374
3375 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3376 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3377 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3378 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3379 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3380 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3381 } else if (sctx->chip_class >= GFX9) {
3382 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3383 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3384 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3385 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3386
3387 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3388 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3389 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3390 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3391 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3392 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3393 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3394 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3395 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3396 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3397 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3398 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3399
3400 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3401 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3402 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3403 } else {
3404 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3405
3406 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3407 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3408 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3409 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3410 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3411 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3412 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3413 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3414 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3415 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3416 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3417 }
3418
3419 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3420 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3421 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3422
3423 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3424 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3425 } else if (sctx->framebuffer.dirty_zsbuf) {
3426 if (sctx->chip_class == GFX9)
3427 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3428 else
3429 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3430
3431 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3432 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3433 }
3434
3435 /* Framebuffer dimensions. */
3436 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3437 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3438 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3439
3440 if (sctx->screen->dfsm_allowed) {
3441 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3442 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3443 }
3444
3445 sctx->framebuffer.dirty_cbufs = 0;
3446 sctx->framebuffer.dirty_zsbuf = false;
3447 }
3448
3449 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3450 {
3451 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3452 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3453 unsigned nr_samples = sctx->framebuffer.nr_samples;
3454 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3455
3456 /* Smoothing (only possible with nr_samples == 1) uses the same
3457 * sample locations as the MSAA it simulates.
3458 */
3459 if (nr_samples <= 1 && sctx->smoothing_enabled)
3460 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3461
3462 /* On Polaris, the small primitive filter uses the sample locations
3463 * even when MSAA is off, so we need to make sure they're set to 0.
3464 *
3465 * GFX10 uses sample locations unconditionally, so they always need
3466 * to be set up.
3467 */
3468 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3469 sctx->chip_class >= GFX10) &&
3470 nr_samples != sctx->sample_locs_num_samples) {
3471 sctx->sample_locs_num_samples = nr_samples;
3472 si_emit_sample_locations(cs, nr_samples);
3473 }
3474
3475 if (sctx->family >= CHIP_POLARIS10) {
3476 unsigned small_prim_filter_cntl =
3477 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3478 /* line bug */
3479 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3480
3481 /* The alternative of setting sample locations to 0 would
3482 * require a DB flush to avoid Z errors, see
3483 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3484 */
3485 if (has_msaa_sample_loc_bug &&
3486 sctx->framebuffer.nr_samples > 1 &&
3487 !rs->multisample_enable)
3488 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3489
3490 radeon_opt_set_context_reg(sctx,
3491 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3492 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3493 small_prim_filter_cntl);
3494 }
3495
3496 /* The exclusion bits can be set to improve rasterization efficiency
3497 * if no sample lies on the pixel boundary (-8 sample offset).
3498 */
3499 bool exclusion = sctx->chip_class >= GFX7 &&
3500 (!rs->multisample_enable || nr_samples != 16);
3501 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3502 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3503 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3504 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3505 }
3506
3507 static bool si_out_of_order_rasterization(struct si_context *sctx)
3508 {
3509 struct si_state_blend *blend = sctx->queued.named.blend;
3510 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3511
3512 if (!sctx->screen->has_out_of_order_rast)
3513 return false;
3514
3515 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3516
3517 if (blend) {
3518 colormask &= blend->cb_target_enabled_4bit;
3519 } else {
3520 colormask = 0;
3521 }
3522
3523 /* Conservative: No logic op. */
3524 if (colormask && blend->logicop_enable)
3525 return false;
3526
3527 struct si_dsa_order_invariance dsa_order_invariant = {
3528 .zs = true, .pass_set = true, .pass_last = false
3529 };
3530
3531 if (sctx->framebuffer.state.zsbuf) {
3532 struct si_texture *zstex =
3533 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3534 bool has_stencil = zstex->surface.has_stencil;
3535 dsa_order_invariant = dsa->order_invariance[has_stencil];
3536 if (!dsa_order_invariant.zs)
3537 return false;
3538
3539 /* The set of PS invocations is always order invariant,
3540 * except when early Z/S tests are requested. */
3541 if (sctx->ps_shader.cso &&
3542 sctx->ps_shader.cso->info.writes_memory &&
3543 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3544 !dsa_order_invariant.pass_set)
3545 return false;
3546
3547 if (sctx->num_perfect_occlusion_queries != 0 &&
3548 !dsa_order_invariant.pass_set)
3549 return false;
3550 }
3551
3552 if (!colormask)
3553 return true;
3554
3555 unsigned blendmask = colormask & blend->blend_enable_4bit;
3556
3557 if (blendmask) {
3558 /* Only commutative blending. */
3559 if (blendmask & ~blend->commutative_4bit)
3560 return false;
3561
3562 if (!dsa_order_invariant.pass_set)
3563 return false;
3564 }
3565
3566 if (colormask & ~blendmask) {
3567 if (!dsa_order_invariant.pass_last)
3568 return false;
3569 }
3570
3571 return true;
3572 }
3573
3574 static void si_emit_msaa_config(struct si_context *sctx)
3575 {
3576 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3577 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3578 /* 33% faster rendering to linear color buffers */
3579 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3580 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3581 unsigned sc_mode_cntl_1 =
3582 S_028A4C_WALK_SIZE(dst_is_linear) |
3583 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3584 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3585 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3586 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3587 /* always 1: */
3588 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3589 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3590 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3591 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3592 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3593 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3594 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3595 S_028804_INCOHERENT_EQAA_READS(1) |
3596 S_028804_INTERPOLATE_COMP_Z(1) |
3597 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3598 unsigned coverage_samples, color_samples, z_samples;
3599 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3600
3601 /* S: Coverage samples (up to 16x):
3602 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3603 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3604 *
3605 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3606 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3607 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3608 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3609 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3610 * # Z samples).
3611 *
3612 * F: Color samples (up to 8x, must be <= coverage samples):
3613 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3614 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3615 *
3616 * Can be anything between coverage and color samples:
3617 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3618 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3619 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3620 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3621 * # All are currently set the same as coverage samples.
3622 *
3623 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3624 * flag for undefined color samples. A shader-based resolve must handle unknowns
3625 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3626 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3627 * useful. The CB resolve always drops unknowns.
3628 *
3629 * Sensible AA configurations:
3630 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3631 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3632 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3633 * EQAA 8s 8z 8f = 8x MSAA
3634 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3635 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3636 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3637 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3638 * EQAA 4s 4z 4f = 4x MSAA
3639 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3640 * EQAA 2s 2z 2f = 2x MSAA
3641 */
3642 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3643 coverage_samples = sctx->framebuffer.nr_samples;
3644 color_samples = sctx->framebuffer.nr_color_samples;
3645
3646 if (sctx->framebuffer.state.zsbuf) {
3647 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3648 z_samples = MAX2(1, z_samples);
3649 } else {
3650 z_samples = coverage_samples;
3651 }
3652 } else if (sctx->smoothing_enabled) {
3653 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3654 } else {
3655 coverage_samples = color_samples = z_samples = 1;
3656 }
3657
3658 /* Required by OpenGL line rasterization.
3659 *
3660 * TODO: We should also enable perpendicular endcaps for AA lines,
3661 * but that requires implementing line stippling in the pixel
3662 * shader. SC can only do line stippling with axis-aligned
3663 * endcaps.
3664 */
3665 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3666 unsigned sc_aa_config = 0;
3667
3668 if (coverage_samples > 1) {
3669 /* distance from the pixel center, indexed by log2(nr_samples) */
3670 static unsigned max_dist[] = {
3671 0, /* unused */
3672 4, /* 2x MSAA */
3673 6, /* 4x MSAA */
3674 7, /* 8x MSAA */
3675 8, /* 16x MSAA */
3676 };
3677 unsigned log_samples = util_logbase2(coverage_samples);
3678 unsigned log_z_samples = util_logbase2(z_samples);
3679 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3680 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3681
3682 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3683 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3684 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3685 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3686
3687 if (sctx->framebuffer.nr_samples > 1) {
3688 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3689 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3690 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3691 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3692 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3693 } else if (sctx->smoothing_enabled) {
3694 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3695 }
3696 }
3697
3698 unsigned initial_cdw = cs->current.cdw;
3699
3700 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3701 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3702 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3703 sc_aa_config);
3704 /* R_028804_DB_EQAA */
3705 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3706 db_eqaa);
3707 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3708 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3709 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3710
3711 if (initial_cdw != cs->current.cdw) {
3712 sctx->context_roll = true;
3713
3714 /* GFX9: Flush DFSM when the AA mode changes. */
3715 if (sctx->screen->dfsm_allowed) {
3716 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3717 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3718 }
3719 }
3720 }
3721
3722 void si_update_ps_iter_samples(struct si_context *sctx)
3723 {
3724 if (sctx->framebuffer.nr_samples > 1)
3725 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3726 if (sctx->screen->dpbb_allowed)
3727 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3728 }
3729
3730 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3731 {
3732 struct si_context *sctx = (struct si_context *)ctx;
3733
3734 /* The hardware can only do sample shading with 2^n samples. */
3735 min_samples = util_next_power_of_two(min_samples);
3736
3737 if (sctx->ps_iter_samples == min_samples)
3738 return;
3739
3740 sctx->ps_iter_samples = min_samples;
3741 sctx->do_update_shaders = true;
3742
3743 si_update_ps_iter_samples(sctx);
3744 }
3745
3746 /*
3747 * Samplers
3748 */
3749
3750 /**
3751 * Build the sampler view descriptor for a buffer texture.
3752 * @param state 256-bit descriptor; only the high 128 bits are filled in
3753 */
3754 void
3755 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3756 enum pipe_format format,
3757 unsigned offset, unsigned size,
3758 uint32_t *state)
3759 {
3760 const struct util_format_description *desc;
3761 unsigned stride;
3762 unsigned num_records;
3763
3764 desc = util_format_description(format);
3765 stride = desc->block.bits / 8;
3766
3767 num_records = size / stride;
3768 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3769
3770 /* The NUM_RECORDS field has a different meaning depending on the chip,
3771 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3772 *
3773 * GFX6-7,10:
3774 * - If STRIDE == 0, it's in byte units.
3775 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3776 *
3777 * GFX8:
3778 * - For SMEM and STRIDE == 0, it's in byte units.
3779 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3780 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3781 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3782 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3783 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3784 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3785 * That way the same descriptor can be used by both SMEM and VMEM.
3786 *
3787 * GFX9:
3788 * - For SMEM and STRIDE == 0, it's in byte units.
3789 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3790 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3791 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3792 */
3793 if (screen->info.chip_class == GFX9 && HAVE_LLVM < 0x0800)
3794 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3795 * from STRIDE to bytes. This works around it by setting
3796 * NUM_RECORDS to at least the size of one element, so that
3797 * the first element is readable when IDXEN == 0.
3798 */
3799 num_records = num_records ? MAX2(num_records, stride) : 0;
3800 else if (screen->info.chip_class == GFX8)
3801 num_records *= stride;
3802
3803 state[4] = 0;
3804 state[5] = S_008F04_STRIDE(stride);
3805 state[6] = num_records;
3806 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3807 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3808 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3809 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3810
3811 if (screen->info.chip_class >= GFX10) {
3812 const struct gfx10_format *fmt = &gfx10_format_table[format];
3813
3814 /* OOB_SELECT chooses the out-of-bounds check:
3815 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3816 * - 1: index >= NUM_RECORDS
3817 * - 2: NUM_RECORDS == 0
3818 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3819 * else: swizzle_address >= NUM_RECORDS
3820 */
3821 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3822 S_008F0C_OOB_SELECT(0) |
3823 S_008F0C_RESOURCE_LEVEL(1);
3824 } else {
3825 int first_non_void;
3826 unsigned num_format, data_format;
3827
3828 first_non_void = util_format_get_first_non_void_channel(format);
3829 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3830 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3831
3832 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3833 S_008F0C_DATA_FORMAT(data_format);
3834 }
3835 }
3836
3837 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3838 {
3839 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3840
3841 if (swizzle[3] == PIPE_SWIZZLE_X) {
3842 /* For the pre-defined border color values (white, opaque
3843 * black, transparent black), the only thing that matters is
3844 * that the alpha channel winds up in the correct place
3845 * (because the RGB channels are all the same) so either of
3846 * these enumerations will work.
3847 */
3848 if (swizzle[2] == PIPE_SWIZZLE_Y)
3849 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3850 else
3851 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3852 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3853 if (swizzle[1] == PIPE_SWIZZLE_Y)
3854 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3855 else
3856 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3857 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3858 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3859 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3860 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3861 }
3862
3863 return bc_swizzle;
3864 }
3865
3866 /**
3867 * Build the sampler view descriptor for a texture.
3868 */
3869 static void
3870 gfx10_make_texture_descriptor(struct si_screen *screen,
3871 struct si_texture *tex,
3872 bool sampler,
3873 enum pipe_texture_target target,
3874 enum pipe_format pipe_format,
3875 const unsigned char state_swizzle[4],
3876 unsigned first_level, unsigned last_level,
3877 unsigned first_layer, unsigned last_layer,
3878 unsigned width, unsigned height, unsigned depth,
3879 uint32_t *state,
3880 uint32_t *fmask_state)
3881 {
3882 struct pipe_resource *res = &tex->buffer.b.b;
3883 const struct util_format_description *desc;
3884 unsigned img_format;
3885 unsigned char swizzle[4];
3886 unsigned type;
3887 uint64_t va;
3888
3889 desc = util_format_description(pipe_format);
3890 img_format = gfx10_format_table[pipe_format].img_format;
3891
3892 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3893 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3894 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3895 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3896 bool is_stencil = false;
3897
3898 switch (pipe_format) {
3899 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3900 case PIPE_FORMAT_X32_S8X24_UINT:
3901 case PIPE_FORMAT_X8Z24_UNORM:
3902 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3903 is_stencil = true;
3904 break;
3905 case PIPE_FORMAT_X24S8_UINT:
3906 /*
3907 * X24S8 is implemented as an 8_8_8_8 data format, to
3908 * fix texture gathers. This affects at least
3909 * GL45-CTS.texture_cube_map_array.sampling on VI.
3910 */
3911 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3912 is_stencil = true;
3913 break;
3914 default:
3915 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3916 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3917 }
3918
3919 if (tex->upgraded_depth && !is_stencil) {
3920 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3921 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3922 }
3923 } else {
3924 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3925 }
3926
3927 if (!sampler &&
3928 (res->target == PIPE_TEXTURE_CUBE ||
3929 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3930 /* For the purpose of shader images, treat cube maps as 2D
3931 * arrays.
3932 */
3933 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3934 } else {
3935 type = si_tex_dim(screen, tex, target, res->nr_samples);
3936 }
3937
3938 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3939 height = 1;
3940 depth = res->array_size;
3941 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3942 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3943 if (sampler || res->target != PIPE_TEXTURE_3D)
3944 depth = res->array_size;
3945 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3946 depth = res->array_size / 6;
3947
3948 state[0] = 0;
3949 state[1] = S_00A004_FORMAT(img_format) |
3950 S_00A004_WIDTH_LO(width - 1);
3951 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3952 S_00A008_HEIGHT(height - 1) |
3953 S_00A008_RESOURCE_LEVEL(1);
3954 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3955 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3956 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3957 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3958 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3959 0 : first_level) |
3960 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3961 util_logbase2(res->nr_samples) :
3962 last_level) |
3963 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3964 S_00A00C_TYPE(type);
3965 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3966 * to know the total number of layers.
3967 */
3968 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3969 ? depth - 1 : last_layer) |
3970 S_00A010_BASE_ARRAY(first_layer);
3971 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3972 S_00A014_MAX_MIP(res->nr_samples > 1 ?
3973 util_logbase2(res->nr_samples) :
3974 tex->buffer.b.b.last_level) |
3975 S_00A014_PERF_MOD(4);
3976 state[6] = 0;
3977 state[7] = 0;
3978
3979 if (tex->dcc_offset) {
3980 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
3981 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
3982 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3983 }
3984
3985 /* Initialize the sampler view for FMASK. */
3986 if (tex->fmask_offset) {
3987 uint32_t format;
3988
3989 va = tex->buffer.gpu_address + tex->fmask_offset;
3990
3991 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3992 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3993 case FMASK(2,1):
3994 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
3995 break;
3996 case FMASK(2,2):
3997 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
3998 break;
3999 case FMASK(4,1):
4000 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4001 break;
4002 case FMASK(4,2):
4003 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4004 break;
4005 case FMASK(4,4):
4006 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4007 break;
4008 case FMASK(8,1):
4009 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4010 break;
4011 case FMASK(8,2):
4012 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4013 break;
4014 case FMASK(8,4):
4015 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4016 break;
4017 case FMASK(8,8):
4018 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4019 break;
4020 case FMASK(16,1):
4021 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4022 break;
4023 case FMASK(16,2):
4024 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4025 break;
4026 case FMASK(16,4):
4027 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4028 break;
4029 case FMASK(16,8):
4030 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4031 break;
4032 default:
4033 unreachable("invalid nr_samples");
4034 }
4035 #undef FMASK
4036 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4037 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4038 S_00A004_FORMAT(format) |
4039 S_00A004_WIDTH_LO(width - 1);
4040 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4041 S_00A008_HEIGHT(height - 1) |
4042 S_00A008_RESOURCE_LEVEL(1);
4043 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4044 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4045 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4046 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4047 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4048 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4049 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4050 S_00A010_BASE_ARRAY(first_layer);
4051 fmask_state[5] = 0;
4052 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4053 fmask_state[7] = 0;
4054 }
4055 }
4056
4057 /**
4058 * Build the sampler view descriptor for a texture (SI-GFX9).
4059 */
4060 static void
4061 si_make_texture_descriptor(struct si_screen *screen,
4062 struct si_texture *tex,
4063 bool sampler,
4064 enum pipe_texture_target target,
4065 enum pipe_format pipe_format,
4066 const unsigned char state_swizzle[4],
4067 unsigned first_level, unsigned last_level,
4068 unsigned first_layer, unsigned last_layer,
4069 unsigned width, unsigned height, unsigned depth,
4070 uint32_t *state,
4071 uint32_t *fmask_state)
4072 {
4073 struct pipe_resource *res = &tex->buffer.b.b;
4074 const struct util_format_description *desc;
4075 unsigned char swizzle[4];
4076 int first_non_void;
4077 unsigned num_format, data_format, type, num_samples;
4078 uint64_t va;
4079
4080 desc = util_format_description(pipe_format);
4081
4082 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4083 MAX2(1, res->nr_samples) :
4084 MAX2(1, res->nr_storage_samples);
4085
4086 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4087 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4088 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4089 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4090
4091 switch (pipe_format) {
4092 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4093 case PIPE_FORMAT_X32_S8X24_UINT:
4094 case PIPE_FORMAT_X8Z24_UNORM:
4095 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4096 break;
4097 case PIPE_FORMAT_X24S8_UINT:
4098 /*
4099 * X24S8 is implemented as an 8_8_8_8 data format, to
4100 * fix texture gathers. This affects at least
4101 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4102 */
4103 if (screen->info.chip_class <= GFX8)
4104 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4105 else
4106 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4107 break;
4108 default:
4109 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4110 }
4111 } else {
4112 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4113 }
4114
4115 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4116
4117 switch (pipe_format) {
4118 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4119 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4120 break;
4121 default:
4122 if (first_non_void < 0) {
4123 if (util_format_is_compressed(pipe_format)) {
4124 switch (pipe_format) {
4125 case PIPE_FORMAT_DXT1_SRGB:
4126 case PIPE_FORMAT_DXT1_SRGBA:
4127 case PIPE_FORMAT_DXT3_SRGBA:
4128 case PIPE_FORMAT_DXT5_SRGBA:
4129 case PIPE_FORMAT_BPTC_SRGBA:
4130 case PIPE_FORMAT_ETC2_SRGB8:
4131 case PIPE_FORMAT_ETC2_SRGB8A1:
4132 case PIPE_FORMAT_ETC2_SRGBA8:
4133 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4134 break;
4135 case PIPE_FORMAT_RGTC1_SNORM:
4136 case PIPE_FORMAT_LATC1_SNORM:
4137 case PIPE_FORMAT_RGTC2_SNORM:
4138 case PIPE_FORMAT_LATC2_SNORM:
4139 case PIPE_FORMAT_ETC2_R11_SNORM:
4140 case PIPE_FORMAT_ETC2_RG11_SNORM:
4141 /* implies float, so use SNORM/UNORM to determine
4142 whether data is signed or not */
4143 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4144 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4145 break;
4146 default:
4147 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4148 break;
4149 }
4150 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4151 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4152 } else {
4153 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4154 }
4155 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4156 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4157 } else {
4158 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4159
4160 switch (desc->channel[first_non_void].type) {
4161 case UTIL_FORMAT_TYPE_FLOAT:
4162 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4163 break;
4164 case UTIL_FORMAT_TYPE_SIGNED:
4165 if (desc->channel[first_non_void].normalized)
4166 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4167 else if (desc->channel[first_non_void].pure_integer)
4168 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4169 else
4170 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4171 break;
4172 case UTIL_FORMAT_TYPE_UNSIGNED:
4173 if (desc->channel[first_non_void].normalized)
4174 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4175 else if (desc->channel[first_non_void].pure_integer)
4176 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4177 else
4178 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4179 }
4180 }
4181 }
4182
4183 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4184 if (data_format == ~0) {
4185 data_format = 0;
4186 }
4187
4188 /* S8 with Z32 HTILE needs a special format. */
4189 if (screen->info.chip_class >= GFX9 &&
4190 pipe_format == PIPE_FORMAT_S8_UINT &&
4191 tex->tc_compatible_htile)
4192 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4193
4194 if (!sampler &&
4195 (res->target == PIPE_TEXTURE_CUBE ||
4196 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4197 (screen->info.chip_class <= GFX8 &&
4198 res->target == PIPE_TEXTURE_3D))) {
4199 /* For the purpose of shader images, treat cube maps and 3D
4200 * textures as 2D arrays. For 3D textures, the address
4201 * calculations for mipmaps are different, so we rely on the
4202 * caller to effectively disable mipmaps.
4203 */
4204 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4205
4206 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4207 } else {
4208 type = si_tex_dim(screen, tex, target, num_samples);
4209 }
4210
4211 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4212 height = 1;
4213 depth = res->array_size;
4214 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4215 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4216 if (sampler || res->target != PIPE_TEXTURE_3D)
4217 depth = res->array_size;
4218 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4219 depth = res->array_size / 6;
4220
4221 state[0] = 0;
4222 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4223 S_008F14_NUM_FORMAT(num_format));
4224 state[2] = (S_008F18_WIDTH(width - 1) |
4225 S_008F18_HEIGHT(height - 1) |
4226 S_008F18_PERF_MOD(4));
4227 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4228 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4229 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4230 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4231 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4232 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4233 util_logbase2(num_samples) :
4234 last_level) |
4235 S_008F1C_TYPE(type));
4236 state[4] = 0;
4237 state[5] = S_008F24_BASE_ARRAY(first_layer);
4238 state[6] = 0;
4239 state[7] = 0;
4240
4241 if (screen->info.chip_class >= GFX9) {
4242 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4243
4244 /* Depth is the the last accessible layer on Gfx9.
4245 * The hw doesn't need to know the total number of layers.
4246 */
4247 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4248 state[4] |= S_008F20_DEPTH(depth - 1);
4249 else
4250 state[4] |= S_008F20_DEPTH(last_layer);
4251
4252 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4253 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4254 util_logbase2(num_samples) :
4255 tex->buffer.b.b.last_level);
4256 } else {
4257 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4258 state[4] |= S_008F20_DEPTH(depth - 1);
4259 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4260 }
4261
4262 if (tex->dcc_offset) {
4263 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
4264 } else {
4265 /* The last dword is unused by hw. The shader uses it to clear
4266 * bits in the first dword of sampler state.
4267 */
4268 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4269 if (first_level == last_level)
4270 state[7] = C_008F30_MAX_ANISO_RATIO;
4271 else
4272 state[7] = 0xffffffff;
4273 }
4274 }
4275
4276 /* Initialize the sampler view for FMASK. */
4277 if (tex->fmask_offset) {
4278 uint32_t data_format, num_format;
4279
4280 va = tex->buffer.gpu_address + tex->fmask_offset;
4281
4282 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4283 if (screen->info.chip_class >= GFX9) {
4284 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4285 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4286 case FMASK(2,1):
4287 num_format = V_008F14_IMG_FMASK_8_2_1;
4288 break;
4289 case FMASK(2,2):
4290 num_format = V_008F14_IMG_FMASK_8_2_2;
4291 break;
4292 case FMASK(4,1):
4293 num_format = V_008F14_IMG_FMASK_8_4_1;
4294 break;
4295 case FMASK(4,2):
4296 num_format = V_008F14_IMG_FMASK_8_4_2;
4297 break;
4298 case FMASK(4,4):
4299 num_format = V_008F14_IMG_FMASK_8_4_4;
4300 break;
4301 case FMASK(8,1):
4302 num_format = V_008F14_IMG_FMASK_8_8_1;
4303 break;
4304 case FMASK(8,2):
4305 num_format = V_008F14_IMG_FMASK_16_8_2;
4306 break;
4307 case FMASK(8,4):
4308 num_format = V_008F14_IMG_FMASK_32_8_4;
4309 break;
4310 case FMASK(8,8):
4311 num_format = V_008F14_IMG_FMASK_32_8_8;
4312 break;
4313 case FMASK(16,1):
4314 num_format = V_008F14_IMG_FMASK_16_16_1;
4315 break;
4316 case FMASK(16,2):
4317 num_format = V_008F14_IMG_FMASK_32_16_2;
4318 break;
4319 case FMASK(16,4):
4320 num_format = V_008F14_IMG_FMASK_64_16_4;
4321 break;
4322 case FMASK(16,8):
4323 num_format = V_008F14_IMG_FMASK_64_16_8;
4324 break;
4325 default:
4326 unreachable("invalid nr_samples");
4327 }
4328 } else {
4329 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4330 case FMASK(2,1):
4331 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4332 break;
4333 case FMASK(2,2):
4334 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4335 break;
4336 case FMASK(4,1):
4337 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4338 break;
4339 case FMASK(4,2):
4340 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4341 break;
4342 case FMASK(4,4):
4343 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4344 break;
4345 case FMASK(8,1):
4346 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4347 break;
4348 case FMASK(8,2):
4349 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4350 break;
4351 case FMASK(8,4):
4352 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4353 break;
4354 case FMASK(8,8):
4355 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4356 break;
4357 case FMASK(16,1):
4358 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4359 break;
4360 case FMASK(16,2):
4361 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4362 break;
4363 case FMASK(16,4):
4364 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4365 break;
4366 case FMASK(16,8):
4367 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4368 break;
4369 default:
4370 unreachable("invalid nr_samples");
4371 }
4372 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4373 }
4374 #undef FMASK
4375
4376 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4377 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4378 S_008F14_DATA_FORMAT(data_format) |
4379 S_008F14_NUM_FORMAT(num_format);
4380 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4381 S_008F18_HEIGHT(height - 1);
4382 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4383 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4384 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4385 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4386 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4387 fmask_state[4] = 0;
4388 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4389 fmask_state[6] = 0;
4390 fmask_state[7] = 0;
4391
4392 if (screen->info.chip_class >= GFX9) {
4393 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4394 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4395 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4396 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4397 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4398 } else {
4399 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4400 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4401 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4402 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4403 }
4404 }
4405 }
4406
4407 /**
4408 * Create a sampler view.
4409 *
4410 * @param ctx context
4411 * @param texture texture
4412 * @param state sampler view template
4413 * @param width0 width0 override (for compressed textures as int)
4414 * @param height0 height0 override (for compressed textures as int)
4415 * @param force_level set the base address to the level (for compressed textures)
4416 */
4417 struct pipe_sampler_view *
4418 si_create_sampler_view_custom(struct pipe_context *ctx,
4419 struct pipe_resource *texture,
4420 const struct pipe_sampler_view *state,
4421 unsigned width0, unsigned height0,
4422 unsigned force_level)
4423 {
4424 struct si_context *sctx = (struct si_context*)ctx;
4425 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4426 struct si_texture *tex = (struct si_texture*)texture;
4427 unsigned base_level, first_level, last_level;
4428 unsigned char state_swizzle[4];
4429 unsigned height, depth, width;
4430 unsigned last_layer = state->u.tex.last_layer;
4431 enum pipe_format pipe_format;
4432 const struct legacy_surf_level *surflevel;
4433
4434 if (!view)
4435 return NULL;
4436
4437 /* initialize base object */
4438 view->base = *state;
4439 view->base.texture = NULL;
4440 view->base.reference.count = 1;
4441 view->base.context = ctx;
4442
4443 assert(texture);
4444 pipe_resource_reference(&view->base.texture, texture);
4445
4446 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4447 state->format == PIPE_FORMAT_S8X24_UINT ||
4448 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4449 state->format == PIPE_FORMAT_S8_UINT)
4450 view->is_stencil_sampler = true;
4451
4452 /* Buffer resource. */
4453 if (texture->target == PIPE_BUFFER) {
4454 si_make_buffer_descriptor(sctx->screen,
4455 si_resource(texture),
4456 state->format,
4457 state->u.buf.offset,
4458 state->u.buf.size,
4459 view->state);
4460 return &view->base;
4461 }
4462
4463 state_swizzle[0] = state->swizzle_r;
4464 state_swizzle[1] = state->swizzle_g;
4465 state_swizzle[2] = state->swizzle_b;
4466 state_swizzle[3] = state->swizzle_a;
4467
4468 base_level = 0;
4469 first_level = state->u.tex.first_level;
4470 last_level = state->u.tex.last_level;
4471 width = width0;
4472 height = height0;
4473 depth = texture->depth0;
4474
4475 if (sctx->chip_class <= GFX8 && force_level) {
4476 assert(force_level == first_level &&
4477 force_level == last_level);
4478 base_level = force_level;
4479 first_level = 0;
4480 last_level = 0;
4481 width = u_minify(width, force_level);
4482 height = u_minify(height, force_level);
4483 depth = u_minify(depth, force_level);
4484 }
4485
4486 /* This is not needed if state trackers set last_layer correctly. */
4487 if (state->target == PIPE_TEXTURE_1D ||
4488 state->target == PIPE_TEXTURE_2D ||
4489 state->target == PIPE_TEXTURE_RECT ||
4490 state->target == PIPE_TEXTURE_CUBE)
4491 last_layer = state->u.tex.first_layer;
4492
4493 /* Texturing with separate depth and stencil. */
4494 pipe_format = state->format;
4495
4496 /* Depth/stencil texturing sometimes needs separate texture. */
4497 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4498 if (!tex->flushed_depth_texture &&
4499 !si_init_flushed_depth_texture(ctx, texture)) {
4500 pipe_resource_reference(&view->base.texture, NULL);
4501 FREE(view);
4502 return NULL;
4503 }
4504
4505 assert(tex->flushed_depth_texture);
4506
4507 /* Override format for the case where the flushed texture
4508 * contains only Z or only S.
4509 */
4510 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4511 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4512
4513 tex = tex->flushed_depth_texture;
4514 }
4515
4516 surflevel = tex->surface.u.legacy.level;
4517
4518 if (tex->db_compatible) {
4519 if (!view->is_stencil_sampler)
4520 pipe_format = tex->db_render_format;
4521
4522 switch (pipe_format) {
4523 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4524 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4525 break;
4526 case PIPE_FORMAT_X8Z24_UNORM:
4527 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4528 /* Z24 is always stored like this for DB
4529 * compatibility.
4530 */
4531 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4532 break;
4533 case PIPE_FORMAT_X24S8_UINT:
4534 case PIPE_FORMAT_S8X24_UINT:
4535 case PIPE_FORMAT_X32_S8X24_UINT:
4536 pipe_format = PIPE_FORMAT_S8_UINT;
4537 surflevel = tex->surface.u.legacy.stencil_level;
4538 break;
4539 default:;
4540 }
4541 }
4542
4543 view->dcc_incompatible =
4544 vi_dcc_formats_are_incompatible(texture,
4545 state->u.tex.first_level,
4546 state->format);
4547
4548 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4549 state->target, pipe_format, state_swizzle,
4550 first_level, last_level,
4551 state->u.tex.first_layer, last_layer,
4552 width, height, depth,
4553 view->state, view->fmask_state);
4554
4555 const struct util_format_description *desc = util_format_description(pipe_format);
4556 view->is_integer = false;
4557
4558 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4559 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4560 continue;
4561
4562 /* Whether the number format is {U,S}{SCALED,INT} */
4563 view->is_integer =
4564 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4565 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4566 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4567 break;
4568 }
4569
4570 view->base_level_info = &surflevel[base_level];
4571 view->base_level = base_level;
4572 view->block_width = util_format_get_blockwidth(pipe_format);
4573 return &view->base;
4574 }
4575
4576 static struct pipe_sampler_view *
4577 si_create_sampler_view(struct pipe_context *ctx,
4578 struct pipe_resource *texture,
4579 const struct pipe_sampler_view *state)
4580 {
4581 return si_create_sampler_view_custom(ctx, texture, state,
4582 texture ? texture->width0 : 0,
4583 texture ? texture->height0 : 0, 0);
4584 }
4585
4586 static void si_sampler_view_destroy(struct pipe_context *ctx,
4587 struct pipe_sampler_view *state)
4588 {
4589 struct si_sampler_view *view = (struct si_sampler_view *)state;
4590
4591 pipe_resource_reference(&state->texture, NULL);
4592 FREE(view);
4593 }
4594
4595 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4596 {
4597 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4598 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4599 (linear_filter &&
4600 (wrap == PIPE_TEX_WRAP_CLAMP ||
4601 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4602 }
4603
4604 static uint32_t si_translate_border_color(struct si_context *sctx,
4605 const struct pipe_sampler_state *state,
4606 const union pipe_color_union *color,
4607 bool is_integer)
4608 {
4609 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4610 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4611
4612 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4613 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4614 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4615 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4616
4617 #define simple_border_types(elt) \
4618 do { \
4619 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4620 color->elt[2] == 0 && color->elt[3] == 0) \
4621 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4622 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4623 color->elt[2] == 0 && color->elt[3] == 1) \
4624 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4625 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4626 color->elt[2] == 1 && color->elt[3] == 1) \
4627 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4628 } while (false)
4629
4630 if (is_integer)
4631 simple_border_types(ui);
4632 else
4633 simple_border_types(f);
4634
4635 #undef simple_border_types
4636
4637 int i;
4638
4639 /* Check if the border has been uploaded already. */
4640 for (i = 0; i < sctx->border_color_count; i++)
4641 if (memcmp(&sctx->border_color_table[i], color,
4642 sizeof(*color)) == 0)
4643 break;
4644
4645 if (i >= SI_MAX_BORDER_COLORS) {
4646 /* Getting 4096 unique border colors is very unlikely. */
4647 fprintf(stderr, "radeonsi: The border color table is full. "
4648 "Any new border colors will be just black. "
4649 "Please file a bug.\n");
4650 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4651 }
4652
4653 if (i == sctx->border_color_count) {
4654 /* Upload a new border color. */
4655 memcpy(&sctx->border_color_table[i], color,
4656 sizeof(*color));
4657 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4658 color, sizeof(*color));
4659 sctx->border_color_count++;
4660 }
4661
4662 return S_008F3C_BORDER_COLOR_PTR(i) |
4663 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4664 }
4665
4666 static inline int S_FIXED(float value, unsigned frac_bits)
4667 {
4668 return value * (1 << frac_bits);
4669 }
4670
4671 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4672 {
4673 if (filter == PIPE_TEX_FILTER_LINEAR)
4674 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4675 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4676 else
4677 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4678 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4679 }
4680
4681 static inline unsigned si_tex_aniso_filter(unsigned filter)
4682 {
4683 if (filter < 2)
4684 return 0;
4685 if (filter < 4)
4686 return 1;
4687 if (filter < 8)
4688 return 2;
4689 if (filter < 16)
4690 return 3;
4691 return 4;
4692 }
4693
4694 static void *si_create_sampler_state(struct pipe_context *ctx,
4695 const struct pipe_sampler_state *state)
4696 {
4697 struct si_context *sctx = (struct si_context *)ctx;
4698 struct si_screen *sscreen = sctx->screen;
4699 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4700 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4701 : state->max_anisotropy;
4702 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4703 union pipe_color_union clamped_border_color;
4704
4705 if (!rstate) {
4706 return NULL;
4707 }
4708
4709 #ifndef NDEBUG
4710 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4711 #endif
4712 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4713 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4714 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4715 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4716 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4717 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4718 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4719 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4720 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4721 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4722 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4723 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4724 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4725 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4726 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4727 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4728 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4729 S_008F38_MIP_POINT_PRECLAMP(0));
4730 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4731
4732 if (sscreen->info.chip_class >= GFX10) {
4733 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4734 } else {
4735 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4736 S_008F38_FILTER_PREC_FIX(1) |
4737 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4738 }
4739
4740 /* Create sampler resource for integer textures. */
4741 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4742 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4743
4744 /* Create sampler resource for upgraded depth textures. */
4745 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4746
4747 for (unsigned i = 0; i < 4; ++i) {
4748 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4749 * when the border color is 1.0. */
4750 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4751 }
4752
4753 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4754 if (sscreen->info.chip_class <= GFX9)
4755 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4756 } else {
4757 rstate->upgraded_depth_val[3] =
4758 si_translate_border_color(sctx, state, &clamped_border_color, false);
4759 }
4760
4761 return rstate;
4762 }
4763
4764 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4765 {
4766 struct si_context *sctx = (struct si_context *)ctx;
4767
4768 if (sctx->sample_mask == (uint16_t)sample_mask)
4769 return;
4770
4771 sctx->sample_mask = sample_mask;
4772 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4773 }
4774
4775 static void si_emit_sample_mask(struct si_context *sctx)
4776 {
4777 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4778 unsigned mask = sctx->sample_mask;
4779
4780 /* Needed for line and polygon smoothing as well as for the Polaris
4781 * small primitive filter. We expect the state tracker to take care of
4782 * this for us.
4783 */
4784 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4785 (mask & 1 && sctx->blitter->running));
4786
4787 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4788 radeon_emit(cs, mask | (mask << 16));
4789 radeon_emit(cs, mask | (mask << 16));
4790 }
4791
4792 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4793 {
4794 #ifndef NDEBUG
4795 struct si_sampler_state *s = state;
4796
4797 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4798 s->magic = 0;
4799 #endif
4800 free(state);
4801 }
4802
4803 /*
4804 * Vertex elements & buffers
4805 */
4806
4807 struct si_fast_udiv_info32
4808 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4809 {
4810 struct util_fast_udiv_info info =
4811 util_compute_fast_udiv_info(D, num_bits, 32);
4812
4813 struct si_fast_udiv_info32 result = {
4814 info.multiplier,
4815 info.pre_shift,
4816 info.post_shift,
4817 info.increment,
4818 };
4819 return result;
4820 }
4821
4822 static void *si_create_vertex_elements(struct pipe_context *ctx,
4823 unsigned count,
4824 const struct pipe_vertex_element *elements)
4825 {
4826 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4827 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4828 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4829 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4830 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4831 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4832 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4833 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4834 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4835 int i;
4836
4837 assert(count <= SI_MAX_ATTRIBS);
4838 if (!v)
4839 return NULL;
4840
4841 v->count = count;
4842 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4843
4844 for (i = 0; i < count; ++i) {
4845 const struct util_format_description *desc;
4846 const struct util_format_channel_description *channel;
4847 int first_non_void;
4848 unsigned vbo_index = elements[i].vertex_buffer_index;
4849
4850 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4851 FREE(v);
4852 return NULL;
4853 }
4854
4855 unsigned instance_divisor = elements[i].instance_divisor;
4856 if (instance_divisor) {
4857 v->uses_instance_divisors = true;
4858
4859 if (instance_divisor == 1) {
4860 v->instance_divisor_is_one |= 1u << i;
4861 } else {
4862 v->instance_divisor_is_fetched |= 1u << i;
4863 divisor_factors[i] =
4864 si_compute_fast_udiv_info32(instance_divisor, 32);
4865 }
4866 }
4867
4868 if (!used[vbo_index]) {
4869 v->first_vb_use_mask |= 1 << i;
4870 used[vbo_index] = true;
4871 }
4872
4873 desc = util_format_description(elements[i].src_format);
4874 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4875 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4876
4877 v->format_size[i] = desc->block.bits / 8;
4878 v->src_offset[i] = elements[i].src_offset;
4879 v->vertex_buffer_index[i] = vbo_index;
4880
4881 bool always_fix = false;
4882 union si_vs_fix_fetch fix_fetch;
4883 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4884
4885 fix_fetch.bits = 0;
4886 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4887
4888 if (channel) {
4889 switch (channel->type) {
4890 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4891 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4892 case UTIL_FORMAT_TYPE_SIGNED: {
4893 if (channel->pure_integer)
4894 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4895 else if (channel->normalized)
4896 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4897 else
4898 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4899 break;
4900 }
4901 case UTIL_FORMAT_TYPE_UNSIGNED: {
4902 if (channel->pure_integer)
4903 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4904 else if (channel->normalized)
4905 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4906 else
4907 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4908 break;
4909 }
4910 default: unreachable("bad format type");
4911 }
4912 } else {
4913 switch (elements[i].src_format) {
4914 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4915 default: unreachable("bad other format");
4916 }
4917 }
4918
4919 if (desc->channel[0].size == 10) {
4920 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4921 log_hw_load_size = 2;
4922
4923 /* The hardware always treats the 2-bit alpha channel as
4924 * unsigned, so a shader workaround is needed. The affected
4925 * chips are GFX8 and older except Stoney (GFX8.1).
4926 */
4927 always_fix = sscreen->info.chip_class <= GFX8 &&
4928 sscreen->info.family != CHIP_STONEY &&
4929 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4930 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4931 fix_fetch.u.log_size = 3; /* special encoding */
4932 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4933 log_hw_load_size = 2;
4934 } else {
4935 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4936 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4937
4938 /* Always fix up:
4939 * - doubles (multiple loads + truncate to float)
4940 * - 32-bit requiring a conversion
4941 */
4942 always_fix =
4943 (fix_fetch.u.log_size == 3) ||
4944 (fix_fetch.u.log_size == 2 &&
4945 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4946 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4947 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4948
4949 /* Also fixup 8_8_8 and 16_16_16. */
4950 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4951 always_fix = true;
4952 log_hw_load_size = fix_fetch.u.log_size;
4953 }
4954 }
4955
4956 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4957 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4958 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4959 fix_fetch.u.reverse = 1;
4960 }
4961
4962 /* Force the workaround for unaligned access here already if the
4963 * offset relative to the vertex buffer base is unaligned.
4964 *
4965 * There is a theoretical case in which this is too conservative:
4966 * if the vertex buffer's offset is also unaligned in just the
4967 * right way, we end up with an aligned address after all.
4968 * However, this case should be extremely rare in practice (it
4969 * won't happen in well-behaved applications), and taking it
4970 * into account would complicate the fast path (where everything
4971 * is nicely aligned).
4972 */
4973 bool check_alignment =
4974 log_hw_load_size >= 1 &&
4975 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
4976 bool opencode = sscreen->options.vs_fetch_always_opencode;
4977
4978 if (check_alignment &&
4979 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4980 opencode = true;
4981
4982 if (always_fix || check_alignment || opencode)
4983 v->fix_fetch[i] = fix_fetch.bits;
4984
4985 if (opencode)
4986 v->fix_fetch_opencode |= 1 << i;
4987 if (opencode || always_fix)
4988 v->fix_fetch_always |= 1 << i;
4989
4990 if (check_alignment && !opencode) {
4991 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4992
4993 v->fix_fetch_unaligned |= 1 << i;
4994 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4995 v->vb_alignment_check_mask |= 1 << vbo_index;
4996 }
4997
4998 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
4999 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5000 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5001 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5002
5003 if (sscreen->info.chip_class >= GFX10) {
5004 const struct gfx10_format *fmt =
5005 &gfx10_format_table[elements[i].src_format];
5006 assert(fmt->img_format != 0 && fmt->img_format < 128);
5007 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5008 S_008F0C_RESOURCE_LEVEL(1);
5009 } else {
5010 unsigned data_format, num_format;
5011 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5012 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5013 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5014 S_008F0C_DATA_FORMAT(data_format);
5015 }
5016 }
5017
5018 if (v->instance_divisor_is_fetched) {
5019 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5020
5021 v->instance_divisor_factor_buffer =
5022 (struct si_resource*)
5023 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5024 num_divisors * sizeof(divisor_factors[0]));
5025 if (!v->instance_divisor_factor_buffer) {
5026 FREE(v);
5027 return NULL;
5028 }
5029 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5030 NULL, PIPE_TRANSFER_WRITE);
5031 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5032 }
5033 return v;
5034 }
5035
5036 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5037 {
5038 struct si_context *sctx = (struct si_context *)ctx;
5039 struct si_vertex_elements *old = sctx->vertex_elements;
5040 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5041
5042 sctx->vertex_elements = v;
5043 sctx->vertex_buffers_dirty = true;
5044
5045 if (v &&
5046 (!old ||
5047 old->count != v->count ||
5048 old->uses_instance_divisors != v->uses_instance_divisors ||
5049 /* we don't check which divisors changed */
5050 v->uses_instance_divisors ||
5051 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5052 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5053 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5054 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5055 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5056 * functions of fix_fetch and the src_offset alignment.
5057 * If they change and fix_fetch doesn't, it must be due to different
5058 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5059 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5060 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5061 sctx->do_update_shaders = true;
5062
5063 if (v && v->instance_divisor_is_fetched) {
5064 struct pipe_constant_buffer cb;
5065
5066 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5067 cb.user_buffer = NULL;
5068 cb.buffer_offset = 0;
5069 cb.buffer_size = 0xffffffff;
5070 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5071 }
5072 }
5073
5074 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5075 {
5076 struct si_context *sctx = (struct si_context *)ctx;
5077 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5078
5079 if (sctx->vertex_elements == state)
5080 sctx->vertex_elements = NULL;
5081 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5082 FREE(state);
5083 }
5084
5085 static void si_set_vertex_buffers(struct pipe_context *ctx,
5086 unsigned start_slot, unsigned count,
5087 const struct pipe_vertex_buffer *buffers)
5088 {
5089 struct si_context *sctx = (struct si_context *)ctx;
5090 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5091 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5092 uint32_t unaligned = orig_unaligned;
5093 int i;
5094
5095 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5096
5097 if (buffers) {
5098 for (i = 0; i < count; i++) {
5099 const struct pipe_vertex_buffer *src = buffers + i;
5100 struct pipe_vertex_buffer *dsti = dst + i;
5101 struct pipe_resource *buf = src->buffer.resource;
5102
5103 pipe_resource_reference(&dsti->buffer.resource, buf);
5104 dsti->buffer_offset = src->buffer_offset;
5105 dsti->stride = src->stride;
5106 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5107 unaligned |= 1 << (start_slot + i);
5108 else
5109 unaligned &= ~(1 << (start_slot + i));
5110
5111 si_context_add_resource_size(sctx, buf);
5112 if (buf)
5113 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5114 }
5115 } else {
5116 for (i = 0; i < count; i++) {
5117 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5118 }
5119 unaligned &= ~u_bit_consecutive(start_slot, count);
5120 }
5121 sctx->vertex_buffers_dirty = true;
5122 sctx->vertex_buffer_unaligned = unaligned;
5123
5124 /* Check whether alignment may have changed in a way that requires
5125 * shader changes. This check is conservative: a vertex buffer can only
5126 * trigger a shader change if the misalignment amount changes (e.g.
5127 * from byte-aligned to short-aligned), but we only keep track of
5128 * whether buffers are at least dword-aligned, since that should always
5129 * be the case in well-behaved applications anyway.
5130 */
5131 if (sctx->vertex_elements &&
5132 (sctx->vertex_elements->vb_alignment_check_mask &
5133 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5134 sctx->do_update_shaders = true;
5135 }
5136
5137 /*
5138 * Misc
5139 */
5140
5141 static void si_set_tess_state(struct pipe_context *ctx,
5142 const float default_outer_level[4],
5143 const float default_inner_level[2])
5144 {
5145 struct si_context *sctx = (struct si_context *)ctx;
5146 struct pipe_constant_buffer cb;
5147 float array[8];
5148
5149 memcpy(array, default_outer_level, sizeof(float) * 4);
5150 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5151
5152 cb.buffer = NULL;
5153 cb.user_buffer = NULL;
5154 cb.buffer_size = sizeof(array);
5155
5156 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5157 (void*)array, sizeof(array),
5158 &cb.buffer_offset);
5159
5160 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5161 pipe_resource_reference(&cb.buffer, NULL);
5162 }
5163
5164 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5165 {
5166 struct si_context *sctx = (struct si_context *)ctx;
5167
5168 si_update_fb_dirtiness_after_rendering(sctx);
5169
5170 /* Multisample surfaces are flushed in si_decompress_textures. */
5171 if (sctx->framebuffer.uncompressed_cb_mask) {
5172 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5173 sctx->framebuffer.CB_has_shader_readable_metadata,
5174 sctx->framebuffer.all_DCC_pipe_aligned);
5175 }
5176 }
5177
5178 /* This only ensures coherency for shader image/buffer stores. */
5179 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5180 {
5181 struct si_context *sctx = (struct si_context *)ctx;
5182
5183 if (!(flags & ~PIPE_BARRIER_UPDATE))
5184 return;
5185
5186 /* Subsequent commands must wait for all shader invocations to
5187 * complete. */
5188 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5189 SI_CONTEXT_CS_PARTIAL_FLUSH;
5190
5191 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5192 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5193 SI_CONTEXT_INV_VCACHE;
5194
5195 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5196 PIPE_BARRIER_SHADER_BUFFER |
5197 PIPE_BARRIER_TEXTURE |
5198 PIPE_BARRIER_IMAGE |
5199 PIPE_BARRIER_STREAMOUT_BUFFER |
5200 PIPE_BARRIER_GLOBAL_BUFFER)) {
5201 /* As far as I can tell, L1 contents are written back to L2
5202 * automatically at end of shader, but the contents of other
5203 * L1 caches might still be stale. */
5204 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5205 }
5206
5207 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5208 /* Indices are read through TC L2 since GFX8.
5209 * L1 isn't used.
5210 */
5211 if (sctx->screen->info.chip_class <= GFX7)
5212 sctx->flags |= SI_CONTEXT_WB_L2;
5213 }
5214
5215 /* MSAA color, any depth and any stencil are flushed in
5216 * si_decompress_textures when needed.
5217 */
5218 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5219 sctx->framebuffer.uncompressed_cb_mask) {
5220 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5221
5222 if (sctx->chip_class <= GFX8)
5223 sctx->flags |= SI_CONTEXT_WB_L2;
5224 }
5225
5226 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5227 if (sctx->screen->info.chip_class <= GFX8 &&
5228 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5229 sctx->flags |= SI_CONTEXT_WB_L2;
5230 }
5231
5232 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5233 {
5234 struct pipe_blend_state blend;
5235
5236 memset(&blend, 0, sizeof(blend));
5237 blend.independent_blend_enable = true;
5238 blend.rt[0].colormask = 0xf;
5239 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5240 }
5241
5242 static void si_init_config(struct si_context *sctx);
5243
5244 void si_init_state_compute_functions(struct si_context *sctx)
5245 {
5246 sctx->b.create_sampler_state = si_create_sampler_state;
5247 sctx->b.delete_sampler_state = si_delete_sampler_state;
5248 sctx->b.create_sampler_view = si_create_sampler_view;
5249 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5250 sctx->b.memory_barrier = si_memory_barrier;
5251 }
5252
5253 void si_init_state_functions(struct si_context *sctx)
5254 {
5255 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5256 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5257 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5258 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5259 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5260 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5261 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5262 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5263 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5264 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5265 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5266
5267 sctx->b.create_blend_state = si_create_blend_state;
5268 sctx->b.bind_blend_state = si_bind_blend_state;
5269 sctx->b.delete_blend_state = si_delete_blend_state;
5270 sctx->b.set_blend_color = si_set_blend_color;
5271
5272 sctx->b.create_rasterizer_state = si_create_rs_state;
5273 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5274 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5275
5276 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5277 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5278 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5279
5280 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5281 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5282 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5283 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5284 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5285
5286 sctx->b.set_clip_state = si_set_clip_state;
5287 sctx->b.set_stencil_ref = si_set_stencil_ref;
5288
5289 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5290
5291 sctx->b.set_sample_mask = si_set_sample_mask;
5292
5293 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5294 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5295 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5296 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5297
5298 sctx->b.texture_barrier = si_texture_barrier;
5299 sctx->b.set_min_samples = si_set_min_samples;
5300 sctx->b.set_tess_state = si_set_tess_state;
5301
5302 sctx->b.set_active_query_state = si_set_active_query_state;
5303
5304 si_init_config(sctx);
5305 }
5306
5307 void si_init_screen_state_functions(struct si_screen *sscreen)
5308 {
5309 sscreen->b.is_format_supported = si_is_format_supported;
5310
5311 if (sscreen->info.chip_class >= GFX10) {
5312 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5313 } else {
5314 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5315 }
5316 }
5317
5318 static void si_set_grbm_gfx_index(struct si_context *sctx,
5319 struct si_pm4_state *pm4, unsigned value)
5320 {
5321 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5322 R_00802C_GRBM_GFX_INDEX;
5323 si_pm4_set_reg(pm4, reg, value);
5324 }
5325
5326 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5327 struct si_pm4_state *pm4, unsigned se)
5328 {
5329 assert(se == ~0 || se < sctx->screen->info.max_se);
5330 si_set_grbm_gfx_index(sctx, pm4,
5331 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5332 S_030800_SE_INDEX(se)) |
5333 S_030800_SH_BROADCAST_WRITES(1) |
5334 S_030800_INSTANCE_BROADCAST_WRITES(1));
5335 }
5336
5337 static void
5338 si_write_harvested_raster_configs(struct si_context *sctx,
5339 struct si_pm4_state *pm4,
5340 unsigned raster_config,
5341 unsigned raster_config_1)
5342 {
5343 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5344 unsigned raster_config_se[4];
5345 unsigned se;
5346
5347 ac_get_harvested_configs(&sctx->screen->info,
5348 raster_config,
5349 &raster_config_1,
5350 raster_config_se);
5351
5352 for (se = 0; se < num_se; se++) {
5353 si_set_grbm_gfx_index_se(sctx, pm4, se);
5354 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5355 }
5356 si_set_grbm_gfx_index(sctx, pm4, ~0);
5357
5358 if (sctx->chip_class >= GFX7) {
5359 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5360 }
5361 }
5362
5363 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5364 {
5365 struct si_screen *sscreen = sctx->screen;
5366 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5367 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5368 unsigned raster_config = sscreen->pa_sc_raster_config;
5369 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5370
5371 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5372 /* Always use the default config when all backends are enabled
5373 * (or when we failed to determine the enabled backends).
5374 */
5375 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5376 raster_config);
5377 if (sctx->chip_class >= GFX7)
5378 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5379 raster_config_1);
5380 } else {
5381 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5382 }
5383 }
5384
5385 static void si_init_config(struct si_context *sctx)
5386 {
5387 struct si_screen *sscreen = sctx->screen;
5388 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5389 bool has_clear_state = sscreen->has_clear_state;
5390 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5391
5392 /* GFX6, radeon kernel disabled CLEAR_STATE. */
5393 assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
5394 !sscreen->info.is_amdgpu);
5395
5396 if (!pm4)
5397 return;
5398
5399 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5400 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5401 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5402 si_pm4_cmd_end(pm4, false);
5403
5404 if (has_clear_state) {
5405 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5406 si_pm4_cmd_add(pm4, 0);
5407 si_pm4_cmd_end(pm4, false);
5408 }
5409
5410 if (sctx->chip_class <= GFX8)
5411 si_set_raster_config(sctx, pm4);
5412
5413 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5414 if (!has_clear_state)
5415 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5416
5417 /* FIXME calculate these values somehow ??? */
5418 if (sctx->chip_class <= GFX8) {
5419 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5420 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5421 }
5422
5423 if (!has_clear_state) {
5424 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5425 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5426 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5427 }
5428
5429 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5430 if (!has_clear_state)
5431 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5432 if (sctx->chip_class < GFX7)
5433 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5434 S_008A14_CLIP_VTX_REORDER_ENA(1));
5435
5436 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5437 * I don't know why. Deduced by trial and error.
5438 */
5439 if (sctx->chip_class <= GFX7) {
5440 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5441 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5442 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5443 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5444 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5445 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5446 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5447 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5448 }
5449
5450 if (!has_clear_state) {
5451 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5452 S_028230_ER_TRI(0xA) |
5453 S_028230_ER_POINT(0xA) |
5454 S_028230_ER_RECT(0xA) |
5455 /* Required by DX10_DIAMOND_TEST_ENA: */
5456 S_028230_ER_LINE_LR(0x1A) |
5457 S_028230_ER_LINE_RL(0x26) |
5458 S_028230_ER_LINE_TB(0xA) |
5459 S_028230_ER_LINE_BT(0xA));
5460 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5461 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5462 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5463 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5464 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5465 }
5466
5467 if (sctx->chip_class >= GFX10) {
5468 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5469 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5470 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5471 } else if (sctx->chip_class >= GFX9) {
5472 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5473 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5474 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5475 } else {
5476 /* These registers, when written, also overwrite the CLEAR_STATE
5477 * context, so we can't rely on CLEAR_STATE setting them.
5478 * It would be an issue if there was another UMD changing them.
5479 */
5480 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5481 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5482 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5483 }
5484
5485 if (sctx->chip_class >= GFX7) {
5486 if (sctx->chip_class >= GFX10) {
5487 /* Logical CUs 16 - 31 */
5488 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5489 S_00B404_CU_EN(0xffff));
5490 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5491 S_00B204_CU_EN(0xffff) |
5492 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
5493 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5494 S_00B104_CU_EN(0xffff));
5495 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5496 S_00B004_CU_EN(0xffff));
5497 }
5498
5499 if (sctx->chip_class >= GFX9) {
5500 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5501 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5502 } else {
5503 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5504 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5505 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5506 S_00B41C_WAVE_LIMIT(0x3F));
5507 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5508 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5509
5510 /* If this is 0, Bonaire can hang even if GS isn't being used.
5511 * Other chips are unaffected. These are suboptimal values,
5512 * but we don't use on-chip GS.
5513 */
5514 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5515 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5516 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5517 }
5518 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5519 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5520
5521 /* Compute LATE_ALLOC_VS.LIMIT. */
5522 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5523 unsigned late_alloc_limit; /* The limit is per SH. */
5524
5525 if (sctx->family == CHIP_KABINI) {
5526 late_alloc_limit = 0; /* Potential hang on Kabini. */
5527 } else if (num_cu_per_sh <= 4) {
5528 /* Too few available compute units per SH. Disallowing
5529 * VS to run on one CU could hurt us more than late VS
5530 * allocation would help.
5531 *
5532 * 2 is the highest safe number that allows us to keep
5533 * all CUs enabled.
5534 */
5535 late_alloc_limit = 2;
5536 } else {
5537 /* This is a good initial value, allowing 1 late_alloc
5538 * wave per SIMD on num_cu - 2.
5539 */
5540 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5541 }
5542
5543 /* VS can't execute on one CU if the limit is > 2. */
5544 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5545 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5546 S_00B118_WAVE_LIMIT(0x3F));
5547 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5548 S_00B11C_LIMIT(late_alloc_limit));
5549
5550 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5551 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5552 }
5553
5554 if (sctx->chip_class >= GFX10) {
5555 /* Break up a pixel wave if it contains deallocs for more than
5556 * half the parameter cache.
5557 *
5558 * To avoid a deadlock where pixel waves aren't launched
5559 * because they're waiting for more pixels while the frontend
5560 * is stuck waiting for PC space, the maximum allowed value is
5561 * the size of the PC minus the largest possible allocation for
5562 * a single primitive shader subgroup.
5563 */
5564 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5565 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5566 si_pm4_set_reg(pm4, R_028838_PA_CL_NGG_CNTL, 0); /* TODO edge flags? */
5567 }
5568
5569 if (sctx->chip_class >= GFX8) {
5570 unsigned vgt_tess_distribution;
5571
5572 vgt_tess_distribution =
5573 S_028B50_ACCUM_ISOLINE(32) |
5574 S_028B50_ACCUM_TRI(11) |
5575 S_028B50_ACCUM_QUAD(11) |
5576 S_028B50_DONUT_SPLIT(16);
5577
5578 /* Testing with Unigine Heaven extreme tesselation yielded best results
5579 * with TRAP_SPLIT = 3.
5580 */
5581 if (sctx->family == CHIP_FIJI ||
5582 sctx->family >= CHIP_POLARIS10)
5583 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5584
5585 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5586 } else if (!has_clear_state) {
5587 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5588 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5589 }
5590
5591 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5592 if (sctx->chip_class >= GFX7) {
5593 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5594 S_028084_ADDRESS(border_color_va >> 40));
5595 }
5596 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5597 RADEON_PRIO_BORDER_COLORS);
5598
5599 if (sctx->chip_class >= GFX9) {
5600 unsigned num_se = sscreen->info.max_se;
5601 unsigned pc_lines = 0;
5602 unsigned max_alloc_count = 0;
5603
5604 switch (sctx->family) {
5605 case CHIP_VEGA10:
5606 case CHIP_VEGA12:
5607 case CHIP_VEGA20:
5608 pc_lines = 2048;
5609 break;
5610 case CHIP_RAVEN:
5611 case CHIP_RAVEN2:
5612 case CHIP_NAVI10:
5613 case CHIP_NAVI12:
5614 pc_lines = 1024;
5615 break;
5616 case CHIP_NAVI14:
5617 pc_lines = 512;
5618 break;
5619 default:
5620 assert(0);
5621 }
5622
5623 if (sctx->chip_class >= GFX10) {
5624 max_alloc_count = pc_lines / 3;
5625 } else {
5626 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
5627 }
5628
5629 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5630 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
5631 S_028C48_MAX_PRIM_PER_BATCH(1023));
5632 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5633 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5634 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5635 }
5636
5637 si_pm4_upload_indirect_buffer(sctx, pm4);
5638 sctx->init_config = pm4;
5639 }