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amd/common: cleanup DATA_FORMAT/NUM_FORMAT field names
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= GFX8) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == GFX8 ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
117
118 radeon_opt_set_context_reg(
119 sctx, R_028424_CB_DCC_CONTROL,
120 SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
125 }
126
127 /* RB+ register settings. */
128 if (sctx->screen->rbplus_allowed) {
129 unsigned spi_shader_col_format =
130 sctx->ps_shader.cso ?
131 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
132 unsigned sx_ps_downconvert = 0;
133 unsigned sx_blend_opt_epsilon = 0;
134 unsigned sx_blend_opt_control = 0;
135
136 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
137 struct si_surface *surf =
138 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
139 unsigned format, swap, spi_format, colormask;
140 bool has_alpha, has_rgb;
141
142 if (!surf)
143 continue;
144
145 format = G_028C70_FORMAT(surf->cb_color_info);
146 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
147 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
149
150 /* Set if RGB and A are present. */
151 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
152
153 if (format == V_028C70_COLOR_8 ||
154 format == V_028C70_COLOR_16 ||
155 format == V_028C70_COLOR_32)
156 has_rgb = !has_alpha;
157 else
158 has_rgb = true;
159
160 /* Check the colormask and export format. */
161 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
162 has_rgb = false;
163 if (!(colormask & PIPE_MASK_A))
164 has_alpha = false;
165
166 if (spi_format == V_028714_SPI_SHADER_ZERO) {
167 has_rgb = false;
168 has_alpha = false;
169 }
170
171 /* Disable value checking for disabled channels. */
172 if (!has_rgb)
173 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
174 if (!has_alpha)
175 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
176
177 /* Enable down-conversion for 32bpp and smaller formats. */
178 switch (format) {
179 case V_028C70_COLOR_8:
180 case V_028C70_COLOR_8_8:
181 case V_028C70_COLOR_8_8_8_8:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_5_6_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_1_5_5_5:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_4_4_4_4:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_32:
213 if (swap == V_028C70_SWAP_STD &&
214 spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV &&
217 spi_format == V_028714_SPI_SHADER_32_AR)
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
219 break;
220
221 case V_028C70_COLOR_16:
222 case V_028C70_COLOR_16_16:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
227 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
228 if (swap == V_028C70_SWAP_STD ||
229 swap == V_028C70_SWAP_STD_REV)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
231 else
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_10_11_11:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
240 }
241 break;
242
243 case V_028C70_COLOR_2_10_10_10:
244 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
246 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
247 }
248 break;
249 }
250 }
251
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
254 SI_TRACKED_SX_PS_DOWNCONVERT,
255 sx_ps_downconvert, sx_blend_opt_epsilon,
256 sx_blend_opt_control);
257 }
258 if (initial_cdw != cs->current.cdw)
259 sctx->context_roll = true;
260 }
261
262 /*
263 * Blender functions
264 */
265
266 static uint32_t si_translate_blend_function(int blend_func)
267 {
268 switch (blend_func) {
269 case PIPE_BLEND_ADD:
270 return V_028780_COMB_DST_PLUS_SRC;
271 case PIPE_BLEND_SUBTRACT:
272 return V_028780_COMB_SRC_MINUS_DST;
273 case PIPE_BLEND_REVERSE_SUBTRACT:
274 return V_028780_COMB_DST_MINUS_SRC;
275 case PIPE_BLEND_MIN:
276 return V_028780_COMB_MIN_DST_SRC;
277 case PIPE_BLEND_MAX:
278 return V_028780_COMB_MAX_DST_SRC;
279 default:
280 PRINT_ERR("Unknown blend function %d\n", blend_func);
281 assert(0);
282 break;
283 }
284 return 0;
285 }
286
287 static uint32_t si_translate_blend_factor(int blend_fact)
288 {
289 switch (blend_fact) {
290 case PIPE_BLENDFACTOR_ONE:
291 return V_028780_BLEND_ONE;
292 case PIPE_BLENDFACTOR_SRC_COLOR:
293 return V_028780_BLEND_SRC_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA:
295 return V_028780_BLEND_SRC_ALPHA;
296 case PIPE_BLENDFACTOR_DST_ALPHA:
297 return V_028780_BLEND_DST_ALPHA;
298 case PIPE_BLENDFACTOR_DST_COLOR:
299 return V_028780_BLEND_DST_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE;
302 case PIPE_BLENDFACTOR_CONST_COLOR:
303 return V_028780_BLEND_CONSTANT_COLOR;
304 case PIPE_BLENDFACTOR_CONST_ALPHA:
305 return V_028780_BLEND_CONSTANT_ALPHA;
306 case PIPE_BLENDFACTOR_ZERO:
307 return V_028780_BLEND_ZERO;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_SRC1_COLOR:
321 return V_028780_BLEND_SRC1_COLOR;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA:
323 return V_028780_BLEND_SRC1_ALPHA;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
325 return V_028780_BLEND_INV_SRC1_COLOR;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
327 return V_028780_BLEND_INV_SRC1_ALPHA;
328 default:
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
330 assert(0);
331 break;
332 }
333 return 0;
334 }
335
336 static uint32_t si_translate_blend_opt_function(int blend_func)
337 {
338 switch (blend_func) {
339 case PIPE_BLEND_ADD:
340 return V_028760_OPT_COMB_ADD;
341 case PIPE_BLEND_SUBTRACT:
342 return V_028760_OPT_COMB_SUBTRACT;
343 case PIPE_BLEND_REVERSE_SUBTRACT:
344 return V_028760_OPT_COMB_REVSUBTRACT;
345 case PIPE_BLEND_MIN:
346 return V_028760_OPT_COMB_MIN;
347 case PIPE_BLEND_MAX:
348 return V_028760_OPT_COMB_MAX;
349 default:
350 return V_028760_OPT_COMB_BLEND_DISABLED;
351 }
352 }
353
354 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
355 {
356 switch (blend_fact) {
357 case PIPE_BLENDFACTOR_ZERO:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
359 case PIPE_BLENDFACTOR_ONE:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
361 case PIPE_BLENDFACTOR_SRC_COLOR:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
365 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
367 case PIPE_BLENDFACTOR_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
372 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
374 default:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
376 }
377 }
378
379 static void si_blend_check_commutativity(struct si_screen *sscreen,
380 struct si_state_blend *blend,
381 enum pipe_blend_func func,
382 enum pipe_blendfactor src,
383 enum pipe_blendfactor dst,
384 unsigned chanmask)
385 {
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed =
388 (1u << PIPE_BLENDFACTOR_ONE) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_ZERO) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
403
404 if (dst == PIPE_BLENDFACTOR_ONE &&
405 (src_allowed & (1u << src))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
408 * rounding.
409 *
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
413 * setting.
414 */
415 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
416 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
417 blend->commutative_4bit |= chanmask;
418 }
419 }
420
421 /**
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
424 */
425 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
426 unsigned *dst_factor, unsigned expected_dst,
427 unsigned replacement_src)
428 {
429 if (*src_factor == expected_dst &&
430 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
431 *src_factor = PIPE_BLENDFACTOR_ZERO;
432 *dst_factor = replacement_src;
433
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func == PIPE_BLEND_SUBTRACT)
436 *func = PIPE_BLEND_REVERSE_SUBTRACT;
437 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
438 *func = PIPE_BLEND_SUBTRACT;
439 }
440 }
441
442 static bool si_blend_factor_uses_dst(unsigned factor)
443 {
444 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
445 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
446 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
447 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
448 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
449 }
450
451 static void *si_create_blend_state_mode(struct pipe_context *ctx,
452 const struct pipe_blend_state *state,
453 unsigned mode)
454 {
455 struct si_context *sctx = (struct si_context*)ctx;
456 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
457 struct si_pm4_state *pm4 = &blend->pm4;
458 uint32_t sx_mrt_blend_opt[8] = {0};
459 uint32_t color_control = 0;
460
461 if (!blend)
462 return NULL;
463
464 blend->alpha_to_coverage = state->alpha_to_coverage;
465 blend->alpha_to_one = state->alpha_to_one;
466 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
467 blend->logicop_enable = state->logicop_enable;
468
469 if (state->logicop_enable) {
470 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
471 } else {
472 color_control |= S_028808_ROP3(0xcc);
473 }
474
475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
481 S_028B70_OFFSET_ROUND(1));
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < 8; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
506
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i >= 1 && blend->dual_src_blend) {
509 /* Vulkan does this for dual source blending. */
510 if (i == 1)
511 blend_cntl |= S_028780_ENABLE(1);
512
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
519 */
520 if (blend->dual_src_blend &&
521 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
522 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* cb_render_state will disable unused ones */
529 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
530 if (state->rt[j].colormask)
531 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
532
533 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
535 continue;
536 }
537
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
540 si_blend_check_commutativity(sctx->screen, blend,
541 eqA, srcA, dstA, 0x8 << (4 * i));
542
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
545 *
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 */
549 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_COLOR,
554 PIPE_BLENDFACTOR_SRC_COLOR);
555 si_blend_remove_dst(&eqA, &srcA, &dstA,
556 PIPE_BLENDFACTOR_DST_ALPHA,
557 PIPE_BLENDFACTOR_SRC_ALPHA);
558
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
561 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
562 srcA_opt = si_translate_blend_opt_factor(srcA, true);
563 dstA_opt = si_translate_blend_opt_factor(dstA, true);
564
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568 if (si_blend_factor_uses_dst(srcA))
569 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
570
571 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
572 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
574 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
576
577 /* Set the final value. */
578 sx_mrt_blend_opt[i] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt) |
583 S_028760_ALPHA_DST_OPT(dstA_opt) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
585
586 /* Set blend state. */
587 blend_cntl |= S_028780_ENABLE(1);
588 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
589 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
590 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
591
592 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
593 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
595 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
596 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
597 }
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599
600 blend->blend_enable_4bit |= 0xfu << (i * 4);
601
602 /* This is only important for formats without alpha. */
603 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
605 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
607 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
608 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
609 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
610 }
611
612 if (blend->cb_target_mask) {
613 color_control |= S_028808_MODE(mode);
614 } else {
615 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
616 }
617
618 if (sctx->screen->rbplus_allowed) {
619 /* Disable RB+ blend optimizations for dual source blending.
620 * Vulkan does this.
621 */
622 if (blend->dual_src_blend) {
623 for (int i = 0; i < 8; i++) {
624 sx_mrt_blend_opt[i] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
627 }
628 }
629
630 for (int i = 0; i < 8; i++)
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
632 sx_mrt_blend_opt[i]);
633
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend->dual_src_blend || state->logicop_enable ||
636 mode == V_028808_CB_RESOLVE)
637 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
638 }
639
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
641 return blend;
642 }
643
644 static void *si_create_blend_state(struct pipe_context *ctx,
645 const struct pipe_blend_state *state)
646 {
647 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
648 }
649
650 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 struct si_state_blend *old_blend = sctx->queued.named.blend;
654 struct si_state_blend *blend = (struct si_state_blend *)state;
655
656 if (!state)
657 return;
658
659 si_pm4_bind_state(sctx, blend, state);
660
661 if (!old_blend ||
662 old_blend->cb_target_mask != blend->cb_target_mask ||
663 old_blend->dual_src_blend != blend->dual_src_blend ||
664 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
665 sctx->framebuffer.nr_samples >= 2 &&
666 sctx->screen->dcc_msaa_allowed))
667 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
668
669 if (!old_blend ||
670 old_blend->cb_target_mask != blend->cb_target_mask ||
671 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
672 old_blend->alpha_to_one != blend->alpha_to_one ||
673 old_blend->dual_src_blend != blend->dual_src_blend ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
676 sctx->do_update_shaders = true;
677
678 if (sctx->screen->dpbb_allowed &&
679 (!old_blend ||
680 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
681 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
682 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
683 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
684
685 if (sctx->screen->has_out_of_order_rast &&
686 (!old_blend ||
687 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
688 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
689 old_blend->commutative_4bit != blend->commutative_4bit ||
690 old_blend->logicop_enable != blend->logicop_enable)))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
692 }
693
694 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
698 }
699
700 static void si_set_blend_color(struct pipe_context *ctx,
701 const struct pipe_blend_color *state)
702 {
703 struct si_context *sctx = (struct si_context *)ctx;
704 static const struct pipe_blend_color zeros;
705
706 sctx->blend_color.state = *state;
707 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
708 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
709 }
710
711 static void si_emit_blend_color(struct si_context *sctx)
712 {
713 struct radeon_cmdbuf *cs = sctx->gfx_cs;
714
715 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
716 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
717 }
718
719 /*
720 * Clipping
721 */
722
723 static void si_set_clip_state(struct pipe_context *ctx,
724 const struct pipe_clip_state *state)
725 {
726 struct si_context *sctx = (struct si_context *)ctx;
727 struct pipe_constant_buffer cb;
728 static const struct pipe_clip_state zeros;
729
730 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
731 return;
732
733 sctx->clip_state.state = *state;
734 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
735 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
736
737 cb.buffer = NULL;
738 cb.user_buffer = state->ucp;
739 cb.buffer_offset = 0;
740 cb.buffer_size = 4*4*8;
741 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
742 pipe_resource_reference(&cb.buffer, NULL);
743 }
744
745 static void si_emit_clip_state(struct si_context *sctx)
746 {
747 struct radeon_cmdbuf *cs = sctx->gfx_cs;
748
749 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
750 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
751 }
752
753 static void si_emit_clip_regs(struct si_context *sctx)
754 {
755 struct si_shader *vs = si_get_vs_state(sctx);
756 struct si_shader_selector *vs_sel = vs->selector;
757 struct tgsi_shader_info *info = &vs_sel->info;
758 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
759 unsigned window_space =
760 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
761 unsigned clipdist_mask = vs_sel->clipdist_mask;
762 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
763 unsigned culldist_mask = vs_sel->culldist_mask;
764 unsigned total_mask;
765
766 if (vs->key.opt.clip_disable) {
767 assert(!info->culldist_writemask);
768 clipdist_mask = 0;
769 culldist_mask = 0;
770 }
771 total_mask = clipdist_mask | culldist_mask;
772
773 /* Clip distances on points have no effect, so need to be implemented
774 * as cull distances. This applies for the clipvertex case as well.
775 *
776 * Setting this for primitives other than points should have no adverse
777 * effects.
778 */
779 clipdist_mask &= rs->clip_plane_enable;
780 culldist_mask |= clipdist_mask;
781
782 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
783 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
784 SI_TRACKED_PA_CL_VS_OUT_CNTL,
785 vs_sel->pa_cl_vs_out_cntl |
786 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
787 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
788 clipdist_mask | (culldist_mask << 8));
789 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
790 SI_TRACKED_PA_CL_CLIP_CNTL,
791 rs->pa_cl_clip_cntl |
792 ucp_mask |
793 S_028810_CLIP_DISABLE(window_space));
794
795 if (initial_cdw != sctx->gfx_cs->current.cdw)
796 sctx->context_roll = true;
797 }
798
799 /*
800 * inferred state between framebuffer and rasterizer
801 */
802 static void si_update_poly_offset_state(struct si_context *sctx)
803 {
804 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
805
806 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
807 si_pm4_bind_state(sctx, poly_offset, NULL);
808 return;
809 }
810
811 /* Use the user format, not db_render_format, so that the polygon
812 * offset behaves as expected by applications.
813 */
814 switch (sctx->framebuffer.state.zsbuf->texture->format) {
815 case PIPE_FORMAT_Z16_UNORM:
816 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
817 break;
818 default: /* 24-bit */
819 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
820 break;
821 case PIPE_FORMAT_Z32_FLOAT:
822 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
823 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
824 break;
825 }
826 }
827
828 /*
829 * Rasterizer
830 */
831
832 static uint32_t si_translate_fill(uint32_t func)
833 {
834 switch(func) {
835 case PIPE_POLYGON_MODE_FILL:
836 return V_028814_X_DRAW_TRIANGLES;
837 case PIPE_POLYGON_MODE_LINE:
838 return V_028814_X_DRAW_LINES;
839 case PIPE_POLYGON_MODE_POINT:
840 return V_028814_X_DRAW_POINTS;
841 default:
842 assert(0);
843 return V_028814_X_DRAW_POINTS;
844 }
845 }
846
847 static void *si_create_rs_state(struct pipe_context *ctx,
848 const struct pipe_rasterizer_state *state)
849 {
850 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
851 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
852 struct si_pm4_state *pm4 = &rs->pm4;
853 unsigned tmp, i;
854 float psize_min, psize_max;
855
856 if (!rs) {
857 return NULL;
858 }
859
860 if (!state->front_ccw) {
861 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
862 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
863 } else {
864 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
865 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
866 }
867 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
868 rs->provoking_vertex_first = state->flatshade_first;
869 rs->scissor_enable = state->scissor;
870 rs->clip_halfz = state->clip_halfz;
871 rs->two_side = state->light_twoside;
872 rs->multisample_enable = state->multisample;
873 rs->force_persample_interp = state->force_persample_interp;
874 rs->clip_plane_enable = state->clip_plane_enable;
875 rs->half_pixel_center = state->half_pixel_center;
876 rs->line_stipple_enable = state->line_stipple_enable;
877 rs->poly_stipple_enable = state->poly_stipple_enable;
878 rs->line_smooth = state->line_smooth;
879 rs->line_width = state->line_width;
880 rs->poly_smooth = state->poly_smooth;
881 rs->uses_poly_offset = state->offset_point || state->offset_line ||
882 state->offset_tri;
883 rs->clamp_fragment_color = state->clamp_fragment_color;
884 rs->clamp_vertex_color = state->clamp_vertex_color;
885 rs->flatshade = state->flatshade;
886 rs->sprite_coord_enable = state->sprite_coord_enable;
887 rs->rasterizer_discard = state->rasterizer_discard;
888 rs->pa_sc_line_stipple = state->line_stipple_enable ?
889 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
890 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
891 rs->pa_cl_clip_cntl =
892 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
893 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
894 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
895 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
896 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
897
898 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
899 S_0286D4_FLAT_SHADE_ENA(1) |
900 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
901 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
902 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
903 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
904 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
905 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
906
907 /* point size 12.4 fixed point */
908 tmp = (unsigned)(state->point_size * 8.0);
909 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
910
911 if (state->point_size_per_vertex) {
912 psize_min = util_get_min_point_size(state);
913 psize_max = SI_MAX_POINT_SIZE;
914 } else {
915 /* Force the point size to be as if the vertex output was disabled. */
916 psize_min = state->point_size;
917 psize_max = state->point_size;
918 }
919 rs->max_point_size = psize_max;
920
921 /* Divide by two, because 0.5 = 1 pixel. */
922 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
923 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
924 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
925
926 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
927 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
928 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
929 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
930 S_028A48_MSAA_ENABLE(state->multisample ||
931 state->poly_smooth ||
932 state->line_smooth) |
933 S_028A48_VPORT_SCISSOR_ENABLE(1) |
934 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
935
936 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
937 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
938 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
939 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
940 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
941 S_028814_FACE(!state->front_ccw) |
942 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
943 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
944 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
945 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
946 state->fill_back != PIPE_POLYGON_MODE_FILL) |
947 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
948 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
949
950 if (!rs->uses_poly_offset)
951 return rs;
952
953 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
954 if (!rs->pm4_poly_offset) {
955 FREE(rs);
956 return NULL;
957 }
958
959 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
960 for (i = 0; i < 3; i++) {
961 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
962 float offset_units = state->offset_units;
963 float offset_scale = state->offset_scale * 16.0f;
964 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
965
966 if (!state->offset_units_unscaled) {
967 switch (i) {
968 case 0: /* 16-bit zbuffer */
969 offset_units *= 4.0f;
970 pa_su_poly_offset_db_fmt_cntl =
971 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
972 break;
973 case 1: /* 24-bit zbuffer */
974 offset_units *= 2.0f;
975 pa_su_poly_offset_db_fmt_cntl =
976 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
977 break;
978 case 2: /* 32-bit zbuffer */
979 offset_units *= 1.0f;
980 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
981 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
982 break;
983 }
984 }
985
986 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
987 fui(offset_scale));
988 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
989 fui(offset_units));
990 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
991 fui(offset_scale));
992 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
993 fui(offset_units));
994 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
995 pa_su_poly_offset_db_fmt_cntl);
996 }
997
998 return rs;
999 }
1000
1001 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1002 {
1003 struct si_context *sctx = (struct si_context *)ctx;
1004 struct si_state_rasterizer *old_rs =
1005 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1006 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1007
1008 if (!state)
1009 return;
1010
1011 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1012 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1013
1014 /* Update the small primitive filter workaround if necessary. */
1015 if (sctx->screen->has_msaa_sample_loc_bug &&
1016 sctx->framebuffer.nr_samples > 1)
1017 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1018 }
1019
1020 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1021 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1022
1023 si_pm4_bind_state(sctx, rasterizer, rs);
1024 si_update_poly_offset_state(sctx);
1025
1026 if (!old_rs ||
1027 old_rs->scissor_enable != rs->scissor_enable)
1028 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1029
1030 if (!old_rs ||
1031 old_rs->line_width != rs->line_width ||
1032 old_rs->max_point_size != rs->max_point_size ||
1033 old_rs->half_pixel_center != rs->half_pixel_center)
1034 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1035
1036 if (!old_rs ||
1037 old_rs->clip_halfz != rs->clip_halfz)
1038 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1039
1040 if (!old_rs ||
1041 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1042 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1043 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1044
1045 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1046 rs->line_stipple_enable;
1047
1048 if (!old_rs ||
1049 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1050 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1051 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1052 old_rs->flatshade != rs->flatshade ||
1053 old_rs->two_side != rs->two_side ||
1054 old_rs->multisample_enable != rs->multisample_enable ||
1055 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1056 old_rs->poly_smooth != rs->poly_smooth ||
1057 old_rs->line_smooth != rs->line_smooth ||
1058 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1059 old_rs->force_persample_interp != rs->force_persample_interp)
1060 sctx->do_update_shaders = true;
1061 }
1062
1063 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1064 {
1065 struct si_context *sctx = (struct si_context *)ctx;
1066 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1067
1068 if (sctx->queued.named.rasterizer == state)
1069 si_pm4_bind_state(sctx, poly_offset, NULL);
1070
1071 FREE(rs->pm4_poly_offset);
1072 si_pm4_delete_state(sctx, rasterizer, rs);
1073 }
1074
1075 /*
1076 * infeered state between dsa and stencil ref
1077 */
1078 static void si_emit_stencil_ref(struct si_context *sctx)
1079 {
1080 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1081 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1082 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1083
1084 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1085 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1086 S_028430_STENCILMASK(dsa->valuemask[0]) |
1087 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1088 S_028430_STENCILOPVAL(1));
1089 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1090 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1091 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1092 S_028434_STENCILOPVAL_BF(1));
1093 }
1094
1095 static void si_set_stencil_ref(struct pipe_context *ctx,
1096 const struct pipe_stencil_ref *state)
1097 {
1098 struct si_context *sctx = (struct si_context *)ctx;
1099
1100 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1101 return;
1102
1103 sctx->stencil_ref.state = *state;
1104 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1105 }
1106
1107
1108 /*
1109 * DSA
1110 */
1111
1112 static uint32_t si_translate_stencil_op(int s_op)
1113 {
1114 switch (s_op) {
1115 case PIPE_STENCIL_OP_KEEP:
1116 return V_02842C_STENCIL_KEEP;
1117 case PIPE_STENCIL_OP_ZERO:
1118 return V_02842C_STENCIL_ZERO;
1119 case PIPE_STENCIL_OP_REPLACE:
1120 return V_02842C_STENCIL_REPLACE_TEST;
1121 case PIPE_STENCIL_OP_INCR:
1122 return V_02842C_STENCIL_ADD_CLAMP;
1123 case PIPE_STENCIL_OP_DECR:
1124 return V_02842C_STENCIL_SUB_CLAMP;
1125 case PIPE_STENCIL_OP_INCR_WRAP:
1126 return V_02842C_STENCIL_ADD_WRAP;
1127 case PIPE_STENCIL_OP_DECR_WRAP:
1128 return V_02842C_STENCIL_SUB_WRAP;
1129 case PIPE_STENCIL_OP_INVERT:
1130 return V_02842C_STENCIL_INVERT;
1131 default:
1132 PRINT_ERR("Unknown stencil op %d", s_op);
1133 assert(0);
1134 break;
1135 }
1136 return 0;
1137 }
1138
1139 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1140 {
1141 return s->enabled && s->writemask &&
1142 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1143 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1144 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1145 }
1146
1147 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1148 {
1149 /* REPLACE is normally order invariant, except when the stencil
1150 * reference value is written by the fragment shader. Tracking this
1151 * interaction does not seem worth the effort, so be conservative. */
1152 return op != PIPE_STENCIL_OP_INCR &&
1153 op != PIPE_STENCIL_OP_DECR &&
1154 op != PIPE_STENCIL_OP_REPLACE;
1155 }
1156
1157 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1158 * invariant in the sense that the set of passing fragments as well as the
1159 * final stencil buffer result does not depend on the order of fragments. */
1160 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1161 {
1162 return !state->enabled || !state->writemask ||
1163 /* The following assumes that Z writes are disabled. */
1164 (state->func == PIPE_FUNC_ALWAYS &&
1165 si_order_invariant_stencil_op(state->zpass_op) &&
1166 si_order_invariant_stencil_op(state->zfail_op)) ||
1167 (state->func == PIPE_FUNC_NEVER &&
1168 si_order_invariant_stencil_op(state->fail_op));
1169 }
1170
1171 static void *si_create_dsa_state(struct pipe_context *ctx,
1172 const struct pipe_depth_stencil_alpha_state *state)
1173 {
1174 struct si_context *sctx = (struct si_context *)ctx;
1175 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1176 struct si_pm4_state *pm4 = &dsa->pm4;
1177 unsigned db_depth_control;
1178 uint32_t db_stencil_control = 0;
1179
1180 if (!dsa) {
1181 return NULL;
1182 }
1183
1184 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1185 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1186 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1187 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1188
1189 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1190 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1191 S_028800_ZFUNC(state->depth.func) |
1192 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1193
1194 /* stencil */
1195 if (state->stencil[0].enabled) {
1196 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1197 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1198 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1199 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1200 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1201
1202 if (state->stencil[1].enabled) {
1203 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1204 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1205 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1206 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1207 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1208 }
1209 }
1210
1211 /* alpha */
1212 if (state->alpha.enabled) {
1213 dsa->alpha_func = state->alpha.func;
1214
1215 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1216 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1217 } else {
1218 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1219 }
1220
1221 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1222 if (state->stencil[0].enabled)
1223 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1224 if (state->depth.bounds_test) {
1225 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1226 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1227 }
1228
1229 dsa->depth_enabled = state->depth.enabled;
1230 dsa->depth_write_enabled = state->depth.enabled &&
1231 state->depth.writemask;
1232 dsa->stencil_enabled = state->stencil[0].enabled;
1233 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1234 (si_dsa_writes_stencil(&state->stencil[0]) ||
1235 si_dsa_writes_stencil(&state->stencil[1]));
1236 dsa->db_can_write = dsa->depth_write_enabled ||
1237 dsa->stencil_write_enabled;
1238
1239 bool zfunc_is_ordered =
1240 state->depth.func == PIPE_FUNC_NEVER ||
1241 state->depth.func == PIPE_FUNC_LESS ||
1242 state->depth.func == PIPE_FUNC_LEQUAL ||
1243 state->depth.func == PIPE_FUNC_GREATER ||
1244 state->depth.func == PIPE_FUNC_GEQUAL;
1245
1246 bool nozwrite_and_order_invariant_stencil =
1247 !dsa->db_can_write ||
1248 (!dsa->depth_write_enabled &&
1249 si_order_invariant_stencil_state(&state->stencil[0]) &&
1250 si_order_invariant_stencil_state(&state->stencil[1]));
1251
1252 dsa->order_invariance[1].zs =
1253 nozwrite_and_order_invariant_stencil ||
1254 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1255 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1256
1257 dsa->order_invariance[1].pass_set =
1258 nozwrite_and_order_invariant_stencil ||
1259 (!dsa->stencil_write_enabled &&
1260 (state->depth.func == PIPE_FUNC_ALWAYS ||
1261 state->depth.func == PIPE_FUNC_NEVER));
1262 dsa->order_invariance[0].pass_set =
1263 !dsa->depth_write_enabled ||
1264 (state->depth.func == PIPE_FUNC_ALWAYS ||
1265 state->depth.func == PIPE_FUNC_NEVER);
1266
1267 dsa->order_invariance[1].pass_last =
1268 sctx->screen->assume_no_z_fights &&
1269 !dsa->stencil_write_enabled &&
1270 dsa->depth_write_enabled && zfunc_is_ordered;
1271 dsa->order_invariance[0].pass_last =
1272 sctx->screen->assume_no_z_fights &&
1273 dsa->depth_write_enabled && zfunc_is_ordered;
1274
1275 return dsa;
1276 }
1277
1278 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1279 {
1280 struct si_context *sctx = (struct si_context *)ctx;
1281 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1282 struct si_state_dsa *dsa = state;
1283
1284 if (!state)
1285 return;
1286
1287 si_pm4_bind_state(sctx, dsa, dsa);
1288
1289 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1290 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1291 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1292 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1293 }
1294
1295 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1296 sctx->do_update_shaders = true;
1297
1298 if (sctx->screen->dpbb_allowed &&
1299 (!old_dsa ||
1300 (old_dsa->depth_enabled != dsa->depth_enabled ||
1301 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1302 old_dsa->db_can_write != dsa->db_can_write)))
1303 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1304
1305 if (sctx->screen->has_out_of_order_rast &&
1306 (!old_dsa ||
1307 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1308 sizeof(old_dsa->order_invariance))))
1309 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1310 }
1311
1312 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1313 {
1314 struct si_context *sctx = (struct si_context *)ctx;
1315 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1316 }
1317
1318 static void *si_create_db_flush_dsa(struct si_context *sctx)
1319 {
1320 struct pipe_depth_stencil_alpha_state dsa = {};
1321
1322 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1323 }
1324
1325 /* DB RENDER STATE */
1326
1327 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1328 {
1329 struct si_context *sctx = (struct si_context*)ctx;
1330
1331 /* Pipeline stat & streamout queries. */
1332 if (enable) {
1333 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1334 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1335 } else {
1336 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1337 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1338 }
1339
1340 /* Occlusion queries. */
1341 if (sctx->occlusion_queries_disabled != !enable) {
1342 sctx->occlusion_queries_disabled = !enable;
1343 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1344 }
1345 }
1346
1347 void si_set_occlusion_query_state(struct si_context *sctx,
1348 bool old_perfect_enable)
1349 {
1350 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1351
1352 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1353
1354 if (perfect_enable != old_perfect_enable)
1355 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1356 }
1357
1358 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1359 {
1360 st->saved_compute = sctx->cs_shader_state.program;
1361
1362 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1363 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1364
1365 st->saved_ssbo_writable_mask = 0;
1366
1367 for (unsigned i = 0; i < 3; i++) {
1368 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1369 (1u << si_get_shaderbuf_slot(i)))
1370 st->saved_ssbo_writable_mask |= 1 << i;
1371 }
1372 }
1373
1374 static void si_emit_db_render_state(struct si_context *sctx)
1375 {
1376 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1377 unsigned db_shader_control, db_render_control, db_count_control;
1378 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1379
1380 /* DB_RENDER_CONTROL */
1381 if (sctx->dbcb_depth_copy_enabled ||
1382 sctx->dbcb_stencil_copy_enabled) {
1383 db_render_control =
1384 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1385 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1386 S_028000_COPY_CENTROID(1) |
1387 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1388 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1389 db_render_control =
1390 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1391 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1392 } else {
1393 db_render_control =
1394 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1395 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1396 }
1397
1398 /* DB_COUNT_CONTROL (occlusion queries) */
1399 if (sctx->num_occlusion_queries > 0 &&
1400 !sctx->occlusion_queries_disabled) {
1401 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1402
1403 if (sctx->chip_class >= GFX7) {
1404 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1405
1406 /* Stoney doesn't increment occlusion query counters
1407 * if the sample rate is 16x. Use 8x sample rate instead.
1408 */
1409 if (sctx->family == CHIP_STONEY)
1410 log_sample_rate = MIN2(log_sample_rate, 3);
1411
1412 db_count_control =
1413 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1414 S_028004_SAMPLE_RATE(log_sample_rate) |
1415 S_028004_ZPASS_ENABLE(1) |
1416 S_028004_SLICE_EVEN_ENABLE(1) |
1417 S_028004_SLICE_ODD_ENABLE(1);
1418 } else {
1419 db_count_control =
1420 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1421 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1422 }
1423 } else {
1424 /* Disable occlusion queries. */
1425 if (sctx->chip_class >= GFX7) {
1426 db_count_control = 0;
1427 } else {
1428 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1429 }
1430 }
1431
1432 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1433 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1434 db_count_control);
1435
1436 /* DB_RENDER_OVERRIDE2 */
1437 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1438 SI_TRACKED_DB_RENDER_OVERRIDE2,
1439 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1440 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1441 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1442
1443 db_shader_control = sctx->ps_db_shader_control;
1444
1445 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1446 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1447 db_shader_control &= C_02880C_Z_ORDER;
1448 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1449 }
1450
1451 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1452 if (!rs->multisample_enable)
1453 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1454
1455 if (sctx->screen->has_rbplus &&
1456 !sctx->screen->rbplus_allowed)
1457 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1458
1459 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1460 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1461
1462 if (initial_cdw != sctx->gfx_cs->current.cdw)
1463 sctx->context_roll = true;
1464 }
1465
1466 /*
1467 * format translation
1468 */
1469 static uint32_t si_translate_colorformat(enum pipe_format format)
1470 {
1471 const struct util_format_description *desc = util_format_description(format);
1472 if (!desc)
1473 return V_028C70_COLOR_INVALID;
1474
1475 #define HAS_SIZE(x,y,z,w) \
1476 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1477 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1478
1479 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1480 return V_028C70_COLOR_10_11_11;
1481
1482 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1483 return V_028C70_COLOR_INVALID;
1484
1485 /* hw cannot support mixed formats (except depth/stencil, since
1486 * stencil is not written to). */
1487 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1488 return V_028C70_COLOR_INVALID;
1489
1490 switch (desc->nr_channels) {
1491 case 1:
1492 switch (desc->channel[0].size) {
1493 case 8:
1494 return V_028C70_COLOR_8;
1495 case 16:
1496 return V_028C70_COLOR_16;
1497 case 32:
1498 return V_028C70_COLOR_32;
1499 }
1500 break;
1501 case 2:
1502 if (desc->channel[0].size == desc->channel[1].size) {
1503 switch (desc->channel[0].size) {
1504 case 8:
1505 return V_028C70_COLOR_8_8;
1506 case 16:
1507 return V_028C70_COLOR_16_16;
1508 case 32:
1509 return V_028C70_COLOR_32_32;
1510 }
1511 } else if (HAS_SIZE(8,24,0,0)) {
1512 return V_028C70_COLOR_24_8;
1513 } else if (HAS_SIZE(24,8,0,0)) {
1514 return V_028C70_COLOR_8_24;
1515 }
1516 break;
1517 case 3:
1518 if (HAS_SIZE(5,6,5,0)) {
1519 return V_028C70_COLOR_5_6_5;
1520 } else if (HAS_SIZE(32,8,24,0)) {
1521 return V_028C70_COLOR_X24_8_32_FLOAT;
1522 }
1523 break;
1524 case 4:
1525 if (desc->channel[0].size == desc->channel[1].size &&
1526 desc->channel[0].size == desc->channel[2].size &&
1527 desc->channel[0].size == desc->channel[3].size) {
1528 switch (desc->channel[0].size) {
1529 case 4:
1530 return V_028C70_COLOR_4_4_4_4;
1531 case 8:
1532 return V_028C70_COLOR_8_8_8_8;
1533 case 16:
1534 return V_028C70_COLOR_16_16_16_16;
1535 case 32:
1536 return V_028C70_COLOR_32_32_32_32;
1537 }
1538 } else if (HAS_SIZE(5,5,5,1)) {
1539 return V_028C70_COLOR_1_5_5_5;
1540 } else if (HAS_SIZE(1,5,5,5)) {
1541 return V_028C70_COLOR_5_5_5_1;
1542 } else if (HAS_SIZE(10,10,10,2)) {
1543 return V_028C70_COLOR_2_10_10_10;
1544 }
1545 break;
1546 }
1547 return V_028C70_COLOR_INVALID;
1548 }
1549
1550 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1551 {
1552 if (SI_BIG_ENDIAN) {
1553 switch(colorformat) {
1554 /* 8-bit buffers. */
1555 case V_028C70_COLOR_8:
1556 return V_028C70_ENDIAN_NONE;
1557
1558 /* 16-bit buffers. */
1559 case V_028C70_COLOR_5_6_5:
1560 case V_028C70_COLOR_1_5_5_5:
1561 case V_028C70_COLOR_4_4_4_4:
1562 case V_028C70_COLOR_16:
1563 case V_028C70_COLOR_8_8:
1564 return V_028C70_ENDIAN_8IN16;
1565
1566 /* 32-bit buffers. */
1567 case V_028C70_COLOR_8_8_8_8:
1568 case V_028C70_COLOR_2_10_10_10:
1569 case V_028C70_COLOR_8_24:
1570 case V_028C70_COLOR_24_8:
1571 case V_028C70_COLOR_16_16:
1572 return V_028C70_ENDIAN_8IN32;
1573
1574 /* 64-bit buffers. */
1575 case V_028C70_COLOR_16_16_16_16:
1576 return V_028C70_ENDIAN_8IN16;
1577
1578 case V_028C70_COLOR_32_32:
1579 return V_028C70_ENDIAN_8IN32;
1580
1581 /* 128-bit buffers. */
1582 case V_028C70_COLOR_32_32_32_32:
1583 return V_028C70_ENDIAN_8IN32;
1584 default:
1585 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1586 }
1587 } else {
1588 return V_028C70_ENDIAN_NONE;
1589 }
1590 }
1591
1592 static uint32_t si_translate_dbformat(enum pipe_format format)
1593 {
1594 switch (format) {
1595 case PIPE_FORMAT_Z16_UNORM:
1596 return V_028040_Z_16;
1597 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1598 case PIPE_FORMAT_X8Z24_UNORM:
1599 case PIPE_FORMAT_Z24X8_UNORM:
1600 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1601 return V_028040_Z_24; /* deprecated on AMD GCN */
1602 case PIPE_FORMAT_Z32_FLOAT:
1603 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1604 return V_028040_Z_32_FLOAT;
1605 default:
1606 return V_028040_Z_INVALID;
1607 }
1608 }
1609
1610 /*
1611 * Texture translation
1612 */
1613
1614 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1615 enum pipe_format format,
1616 const struct util_format_description *desc,
1617 int first_non_void)
1618 {
1619 struct si_screen *sscreen = (struct si_screen*)screen;
1620 bool uniform = true;
1621 int i;
1622
1623 /* Colorspace (return non-RGB formats directly). */
1624 switch (desc->colorspace) {
1625 /* Depth stencil formats */
1626 case UTIL_FORMAT_COLORSPACE_ZS:
1627 switch (format) {
1628 case PIPE_FORMAT_Z16_UNORM:
1629 return V_008F14_IMG_DATA_FORMAT_16;
1630 case PIPE_FORMAT_X24S8_UINT:
1631 case PIPE_FORMAT_S8X24_UINT:
1632 /*
1633 * Implemented as an 8_8_8_8 data format to fix texture
1634 * gathers in stencil sampling. This affects at least
1635 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1636 */
1637 if (sscreen->info.chip_class <= GFX8)
1638 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1639
1640 if (format == PIPE_FORMAT_X24S8_UINT)
1641 return V_008F14_IMG_DATA_FORMAT_8_24;
1642 else
1643 return V_008F14_IMG_DATA_FORMAT_24_8;
1644 case PIPE_FORMAT_Z24X8_UNORM:
1645 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1646 return V_008F14_IMG_DATA_FORMAT_8_24;
1647 case PIPE_FORMAT_X8Z24_UNORM:
1648 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1649 return V_008F14_IMG_DATA_FORMAT_24_8;
1650 case PIPE_FORMAT_S8_UINT:
1651 return V_008F14_IMG_DATA_FORMAT_8;
1652 case PIPE_FORMAT_Z32_FLOAT:
1653 return V_008F14_IMG_DATA_FORMAT_32;
1654 case PIPE_FORMAT_X32_S8X24_UINT:
1655 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1656 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1657 default:
1658 goto out_unknown;
1659 }
1660
1661 case UTIL_FORMAT_COLORSPACE_YUV:
1662 goto out_unknown; /* TODO */
1663
1664 case UTIL_FORMAT_COLORSPACE_SRGB:
1665 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1666 goto out_unknown;
1667 break;
1668
1669 default:
1670 break;
1671 }
1672
1673 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1674 if (!sscreen->info.has_format_bc1_through_bc7)
1675 goto out_unknown;
1676
1677 switch (format) {
1678 case PIPE_FORMAT_RGTC1_SNORM:
1679 case PIPE_FORMAT_LATC1_SNORM:
1680 case PIPE_FORMAT_RGTC1_UNORM:
1681 case PIPE_FORMAT_LATC1_UNORM:
1682 return V_008F14_IMG_DATA_FORMAT_BC4;
1683 case PIPE_FORMAT_RGTC2_SNORM:
1684 case PIPE_FORMAT_LATC2_SNORM:
1685 case PIPE_FORMAT_RGTC2_UNORM:
1686 case PIPE_FORMAT_LATC2_UNORM:
1687 return V_008F14_IMG_DATA_FORMAT_BC5;
1688 default:
1689 goto out_unknown;
1690 }
1691 }
1692
1693 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1694 (sscreen->info.family == CHIP_STONEY ||
1695 sscreen->info.family == CHIP_VEGA10 ||
1696 sscreen->info.family == CHIP_RAVEN)) {
1697 switch (format) {
1698 case PIPE_FORMAT_ETC1_RGB8:
1699 case PIPE_FORMAT_ETC2_RGB8:
1700 case PIPE_FORMAT_ETC2_SRGB8:
1701 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1702 case PIPE_FORMAT_ETC2_RGB8A1:
1703 case PIPE_FORMAT_ETC2_SRGB8A1:
1704 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1705 case PIPE_FORMAT_ETC2_RGBA8:
1706 case PIPE_FORMAT_ETC2_SRGBA8:
1707 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1708 case PIPE_FORMAT_ETC2_R11_UNORM:
1709 case PIPE_FORMAT_ETC2_R11_SNORM:
1710 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1711 case PIPE_FORMAT_ETC2_RG11_UNORM:
1712 case PIPE_FORMAT_ETC2_RG11_SNORM:
1713 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1714 default:
1715 goto out_unknown;
1716 }
1717 }
1718
1719 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1720 if (!sscreen->info.has_format_bc1_through_bc7)
1721 goto out_unknown;
1722
1723 switch (format) {
1724 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1725 case PIPE_FORMAT_BPTC_SRGBA:
1726 return V_008F14_IMG_DATA_FORMAT_BC7;
1727 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1728 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1729 return V_008F14_IMG_DATA_FORMAT_BC6;
1730 default:
1731 goto out_unknown;
1732 }
1733 }
1734
1735 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1736 switch (format) {
1737 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1738 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1739 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1740 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1741 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1742 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1743 default:
1744 goto out_unknown;
1745 }
1746 }
1747
1748 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1749 if (!sscreen->info.has_format_bc1_through_bc7)
1750 goto out_unknown;
1751
1752 switch (format) {
1753 case PIPE_FORMAT_DXT1_RGB:
1754 case PIPE_FORMAT_DXT1_RGBA:
1755 case PIPE_FORMAT_DXT1_SRGB:
1756 case PIPE_FORMAT_DXT1_SRGBA:
1757 return V_008F14_IMG_DATA_FORMAT_BC1;
1758 case PIPE_FORMAT_DXT3_RGBA:
1759 case PIPE_FORMAT_DXT3_SRGBA:
1760 return V_008F14_IMG_DATA_FORMAT_BC2;
1761 case PIPE_FORMAT_DXT5_RGBA:
1762 case PIPE_FORMAT_DXT5_SRGBA:
1763 return V_008F14_IMG_DATA_FORMAT_BC3;
1764 default:
1765 goto out_unknown;
1766 }
1767 }
1768
1769 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1770 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1771 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1772 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1773 }
1774
1775 /* R8G8Bx_SNORM - TODO CxV8U8 */
1776
1777 /* hw cannot support mixed formats (except depth/stencil, since only
1778 * depth is read).*/
1779 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1780 goto out_unknown;
1781
1782 /* See whether the components are of the same size. */
1783 for (i = 1; i < desc->nr_channels; i++) {
1784 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1785 }
1786
1787 /* Non-uniform formats. */
1788 if (!uniform) {
1789 switch(desc->nr_channels) {
1790 case 3:
1791 if (desc->channel[0].size == 5 &&
1792 desc->channel[1].size == 6 &&
1793 desc->channel[2].size == 5) {
1794 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1795 }
1796 goto out_unknown;
1797 case 4:
1798 if (desc->channel[0].size == 5 &&
1799 desc->channel[1].size == 5 &&
1800 desc->channel[2].size == 5 &&
1801 desc->channel[3].size == 1) {
1802 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1803 }
1804 if (desc->channel[0].size == 1 &&
1805 desc->channel[1].size == 5 &&
1806 desc->channel[2].size == 5 &&
1807 desc->channel[3].size == 5) {
1808 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1809 }
1810 if (desc->channel[0].size == 10 &&
1811 desc->channel[1].size == 10 &&
1812 desc->channel[2].size == 10 &&
1813 desc->channel[3].size == 2) {
1814 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1815 }
1816 goto out_unknown;
1817 }
1818 goto out_unknown;
1819 }
1820
1821 if (first_non_void < 0 || first_non_void > 3)
1822 goto out_unknown;
1823
1824 /* uniform formats */
1825 switch (desc->channel[first_non_void].size) {
1826 case 4:
1827 switch (desc->nr_channels) {
1828 #if 0 /* Not supported for render targets */
1829 case 2:
1830 return V_008F14_IMG_DATA_FORMAT_4_4;
1831 #endif
1832 case 4:
1833 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1834 }
1835 break;
1836 case 8:
1837 switch (desc->nr_channels) {
1838 case 1:
1839 return V_008F14_IMG_DATA_FORMAT_8;
1840 case 2:
1841 return V_008F14_IMG_DATA_FORMAT_8_8;
1842 case 4:
1843 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1844 }
1845 break;
1846 case 16:
1847 switch (desc->nr_channels) {
1848 case 1:
1849 return V_008F14_IMG_DATA_FORMAT_16;
1850 case 2:
1851 return V_008F14_IMG_DATA_FORMAT_16_16;
1852 case 4:
1853 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1854 }
1855 break;
1856 case 32:
1857 switch (desc->nr_channels) {
1858 case 1:
1859 return V_008F14_IMG_DATA_FORMAT_32;
1860 case 2:
1861 return V_008F14_IMG_DATA_FORMAT_32_32;
1862 #if 0 /* Not supported for render targets */
1863 case 3:
1864 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1865 #endif
1866 case 4:
1867 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1868 }
1869 }
1870
1871 out_unknown:
1872 return ~0;
1873 }
1874
1875 static unsigned si_tex_wrap(unsigned wrap)
1876 {
1877 switch (wrap) {
1878 default:
1879 case PIPE_TEX_WRAP_REPEAT:
1880 return V_008F30_SQ_TEX_WRAP;
1881 case PIPE_TEX_WRAP_CLAMP:
1882 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1883 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1884 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1885 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1886 return V_008F30_SQ_TEX_CLAMP_BORDER;
1887 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1888 return V_008F30_SQ_TEX_MIRROR;
1889 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1890 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1891 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1892 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1893 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1894 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1895 }
1896 }
1897
1898 static unsigned si_tex_mipfilter(unsigned filter)
1899 {
1900 switch (filter) {
1901 case PIPE_TEX_MIPFILTER_NEAREST:
1902 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1903 case PIPE_TEX_MIPFILTER_LINEAR:
1904 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1905 default:
1906 case PIPE_TEX_MIPFILTER_NONE:
1907 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1908 }
1909 }
1910
1911 static unsigned si_tex_compare(unsigned compare)
1912 {
1913 switch (compare) {
1914 default:
1915 case PIPE_FUNC_NEVER:
1916 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1917 case PIPE_FUNC_LESS:
1918 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1919 case PIPE_FUNC_EQUAL:
1920 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1921 case PIPE_FUNC_LEQUAL:
1922 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1923 case PIPE_FUNC_GREATER:
1924 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1925 case PIPE_FUNC_NOTEQUAL:
1926 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1927 case PIPE_FUNC_GEQUAL:
1928 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1929 case PIPE_FUNC_ALWAYS:
1930 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1931 }
1932 }
1933
1934 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1935 unsigned view_target, unsigned nr_samples)
1936 {
1937 unsigned res_target = tex->buffer.b.b.target;
1938
1939 if (view_target == PIPE_TEXTURE_CUBE ||
1940 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1941 res_target = view_target;
1942 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1943 else if (res_target == PIPE_TEXTURE_CUBE ||
1944 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1945 res_target = PIPE_TEXTURE_2D_ARRAY;
1946
1947 /* GFX9 allocates 1D textures as 2D. */
1948 if ((res_target == PIPE_TEXTURE_1D ||
1949 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1950 sscreen->info.chip_class >= GFX9 &&
1951 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1952 if (res_target == PIPE_TEXTURE_1D)
1953 res_target = PIPE_TEXTURE_2D;
1954 else
1955 res_target = PIPE_TEXTURE_2D_ARRAY;
1956 }
1957
1958 switch (res_target) {
1959 default:
1960 case PIPE_TEXTURE_1D:
1961 return V_008F1C_SQ_RSRC_IMG_1D;
1962 case PIPE_TEXTURE_1D_ARRAY:
1963 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1964 case PIPE_TEXTURE_2D:
1965 case PIPE_TEXTURE_RECT:
1966 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1967 V_008F1C_SQ_RSRC_IMG_2D;
1968 case PIPE_TEXTURE_2D_ARRAY:
1969 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1970 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1971 case PIPE_TEXTURE_3D:
1972 return V_008F1C_SQ_RSRC_IMG_3D;
1973 case PIPE_TEXTURE_CUBE:
1974 case PIPE_TEXTURE_CUBE_ARRAY:
1975 return V_008F1C_SQ_RSRC_IMG_CUBE;
1976 }
1977 }
1978
1979 /*
1980 * Format support testing
1981 */
1982
1983 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1984 {
1985 const struct util_format_description *desc = util_format_description(format);
1986 if (!desc)
1987 return false;
1988
1989 return si_translate_texformat(screen, format, desc,
1990 util_format_get_first_non_void_channel(format)) != ~0U;
1991 }
1992
1993 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1994 const struct util_format_description *desc,
1995 int first_non_void)
1996 {
1997 int i;
1998
1999 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2000 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2001
2002 assert(first_non_void >= 0);
2003
2004 if (desc->nr_channels == 4 &&
2005 desc->channel[0].size == 10 &&
2006 desc->channel[1].size == 10 &&
2007 desc->channel[2].size == 10 &&
2008 desc->channel[3].size == 2)
2009 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2010
2011 /* See whether the components are of the same size. */
2012 for (i = 0; i < desc->nr_channels; i++) {
2013 if (desc->channel[first_non_void].size != desc->channel[i].size)
2014 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2015 }
2016
2017 switch (desc->channel[first_non_void].size) {
2018 case 8:
2019 switch (desc->nr_channels) {
2020 case 1:
2021 case 3: /* 3 loads */
2022 return V_008F0C_BUF_DATA_FORMAT_8;
2023 case 2:
2024 return V_008F0C_BUF_DATA_FORMAT_8_8;
2025 case 4:
2026 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2027 }
2028 break;
2029 case 16:
2030 switch (desc->nr_channels) {
2031 case 1:
2032 case 3: /* 3 loads */
2033 return V_008F0C_BUF_DATA_FORMAT_16;
2034 case 2:
2035 return V_008F0C_BUF_DATA_FORMAT_16_16;
2036 case 4:
2037 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2038 }
2039 break;
2040 case 32:
2041 switch (desc->nr_channels) {
2042 case 1:
2043 return V_008F0C_BUF_DATA_FORMAT_32;
2044 case 2:
2045 return V_008F0C_BUF_DATA_FORMAT_32_32;
2046 case 3:
2047 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2048 case 4:
2049 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2050 }
2051 break;
2052 case 64:
2053 /* Legacy double formats. */
2054 switch (desc->nr_channels) {
2055 case 1: /* 1 load */
2056 return V_008F0C_BUF_DATA_FORMAT_32_32;
2057 case 2: /* 1 load */
2058 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2059 case 3: /* 3 loads */
2060 return V_008F0C_BUF_DATA_FORMAT_32_32;
2061 case 4: /* 2 loads */
2062 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2063 }
2064 break;
2065 }
2066
2067 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2068 }
2069
2070 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2071 const struct util_format_description *desc,
2072 int first_non_void)
2073 {
2074 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2075 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2076
2077 assert(first_non_void >= 0);
2078
2079 switch (desc->channel[first_non_void].type) {
2080 case UTIL_FORMAT_TYPE_SIGNED:
2081 case UTIL_FORMAT_TYPE_FIXED:
2082 if (desc->channel[first_non_void].size >= 32 ||
2083 desc->channel[first_non_void].pure_integer)
2084 return V_008F0C_BUF_NUM_FORMAT_SINT;
2085 else if (desc->channel[first_non_void].normalized)
2086 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2087 else
2088 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2089 break;
2090 case UTIL_FORMAT_TYPE_UNSIGNED:
2091 if (desc->channel[first_non_void].size >= 32 ||
2092 desc->channel[first_non_void].pure_integer)
2093 return V_008F0C_BUF_NUM_FORMAT_UINT;
2094 else if (desc->channel[first_non_void].normalized)
2095 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2096 else
2097 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2098 break;
2099 case UTIL_FORMAT_TYPE_FLOAT:
2100 default:
2101 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2102 }
2103 }
2104
2105 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2106 enum pipe_format format,
2107 unsigned usage)
2108 {
2109 const struct util_format_description *desc;
2110 int first_non_void;
2111 unsigned data_format;
2112
2113 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2114 PIPE_BIND_SAMPLER_VIEW |
2115 PIPE_BIND_VERTEX_BUFFER)) == 0);
2116
2117 desc = util_format_description(format);
2118 if (!desc)
2119 return 0;
2120
2121 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2122 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2123 * for read-only access (with caveats surrounding bounds checks), but
2124 * obviously fails for write access which we have to implement for
2125 * shader images. Luckily, OpenGL doesn't expect this to be supported
2126 * anyway, and so the only impact is on PBO uploads / downloads, which
2127 * shouldn't be expected to be fast for GL_RGB anyway.
2128 */
2129 if (desc->block.bits == 3 * 8 ||
2130 desc->block.bits == 3 * 16) {
2131 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2132 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2133 if (!usage)
2134 return 0;
2135 }
2136 }
2137
2138 first_non_void = util_format_get_first_non_void_channel(format);
2139 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2140 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2141 return 0;
2142
2143 return usage;
2144 }
2145
2146 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2147 {
2148 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2149 si_translate_colorswap(format, false) != ~0U;
2150 }
2151
2152 static bool si_is_zs_format_supported(enum pipe_format format)
2153 {
2154 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2155 }
2156
2157 static boolean si_is_format_supported(struct pipe_screen *screen,
2158 enum pipe_format format,
2159 enum pipe_texture_target target,
2160 unsigned sample_count,
2161 unsigned storage_sample_count,
2162 unsigned usage)
2163 {
2164 struct si_screen *sscreen = (struct si_screen *)screen;
2165 unsigned retval = 0;
2166
2167 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2168 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2169 return false;
2170 }
2171
2172 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2173 return false;
2174
2175 if (sample_count > 1) {
2176 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2177 return false;
2178
2179 if (usage & PIPE_BIND_SHADER_IMAGE)
2180 return false;
2181
2182 /* Only power-of-two sample counts are supported. */
2183 if (!util_is_power_of_two_or_zero(sample_count) ||
2184 !util_is_power_of_two_or_zero(storage_sample_count))
2185 return false;
2186
2187 /* MSAA support without framebuffer attachments. */
2188 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2189 return true;
2190
2191 if (!sscreen->info.has_eqaa_surface_allocator ||
2192 util_format_is_depth_or_stencil(format)) {
2193 /* Color without EQAA or depth/stencil. */
2194 if (sample_count > 8 ||
2195 sample_count != storage_sample_count)
2196 return false;
2197 } else {
2198 /* Color with EQAA. */
2199 if (sample_count > 16 ||
2200 storage_sample_count > 8)
2201 return false;
2202 }
2203 }
2204
2205 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2206 PIPE_BIND_SHADER_IMAGE)) {
2207 if (target == PIPE_BUFFER) {
2208 retval |= si_is_vertex_format_supported(
2209 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2210 PIPE_BIND_SHADER_IMAGE));
2211 } else {
2212 if (si_is_sampler_format_supported(screen, format))
2213 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2214 PIPE_BIND_SHADER_IMAGE);
2215 }
2216 }
2217
2218 if ((usage & (PIPE_BIND_RENDER_TARGET |
2219 PIPE_BIND_DISPLAY_TARGET |
2220 PIPE_BIND_SCANOUT |
2221 PIPE_BIND_SHARED |
2222 PIPE_BIND_BLENDABLE)) &&
2223 si_is_colorbuffer_format_supported(format)) {
2224 retval |= usage &
2225 (PIPE_BIND_RENDER_TARGET |
2226 PIPE_BIND_DISPLAY_TARGET |
2227 PIPE_BIND_SCANOUT |
2228 PIPE_BIND_SHARED);
2229 if (!util_format_is_pure_integer(format) &&
2230 !util_format_is_depth_or_stencil(format))
2231 retval |= usage & PIPE_BIND_BLENDABLE;
2232 }
2233
2234 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2235 si_is_zs_format_supported(format)) {
2236 retval |= PIPE_BIND_DEPTH_STENCIL;
2237 }
2238
2239 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2240 retval |= si_is_vertex_format_supported(screen, format,
2241 PIPE_BIND_VERTEX_BUFFER);
2242 }
2243
2244 if ((usage & PIPE_BIND_LINEAR) &&
2245 !util_format_is_compressed(format) &&
2246 !(usage & PIPE_BIND_DEPTH_STENCIL))
2247 retval |= PIPE_BIND_LINEAR;
2248
2249 return retval == usage;
2250 }
2251
2252 /*
2253 * framebuffer handling
2254 */
2255
2256 static void si_choose_spi_color_formats(struct si_surface *surf,
2257 unsigned format, unsigned swap,
2258 unsigned ntype, bool is_depth)
2259 {
2260 /* Alpha is needed for alpha-to-coverage.
2261 * Blending may be with or without alpha.
2262 */
2263 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2264 unsigned alpha = 0; /* exports alpha, but may not support blending */
2265 unsigned blend = 0; /* supports blending, but may not export alpha */
2266 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2267
2268 /* Choose the SPI color formats. These are required values for RB+.
2269 * Other chips have multiple choices, though they are not necessarily better.
2270 */
2271 switch (format) {
2272 case V_028C70_COLOR_5_6_5:
2273 case V_028C70_COLOR_1_5_5_5:
2274 case V_028C70_COLOR_5_5_5_1:
2275 case V_028C70_COLOR_4_4_4_4:
2276 case V_028C70_COLOR_10_11_11:
2277 case V_028C70_COLOR_11_11_10:
2278 case V_028C70_COLOR_8:
2279 case V_028C70_COLOR_8_8:
2280 case V_028C70_COLOR_8_8_8_8:
2281 case V_028C70_COLOR_10_10_10_2:
2282 case V_028C70_COLOR_2_10_10_10:
2283 if (ntype == V_028C70_NUMBER_UINT)
2284 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2285 else if (ntype == V_028C70_NUMBER_SINT)
2286 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2287 else
2288 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2289 break;
2290
2291 case V_028C70_COLOR_16:
2292 case V_028C70_COLOR_16_16:
2293 case V_028C70_COLOR_16_16_16_16:
2294 if (ntype == V_028C70_NUMBER_UNORM ||
2295 ntype == V_028C70_NUMBER_SNORM) {
2296 /* UNORM16 and SNORM16 don't support blending */
2297 if (ntype == V_028C70_NUMBER_UNORM)
2298 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2299 else
2300 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2301
2302 /* Use 32 bits per channel for blending. */
2303 if (format == V_028C70_COLOR_16) {
2304 if (swap == V_028C70_SWAP_STD) { /* R */
2305 blend = V_028714_SPI_SHADER_32_R;
2306 blend_alpha = V_028714_SPI_SHADER_32_AR;
2307 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2308 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2309 else
2310 assert(0);
2311 } else if (format == V_028C70_COLOR_16_16) {
2312 if (swap == V_028C70_SWAP_STD) { /* RG */
2313 blend = V_028714_SPI_SHADER_32_GR;
2314 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2315 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2316 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2317 else
2318 assert(0);
2319 } else /* 16_16_16_16 */
2320 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2321 } else if (ntype == V_028C70_NUMBER_UINT)
2322 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2323 else if (ntype == V_028C70_NUMBER_SINT)
2324 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2325 else if (ntype == V_028C70_NUMBER_FLOAT)
2326 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2327 else
2328 assert(0);
2329 break;
2330
2331 case V_028C70_COLOR_32:
2332 if (swap == V_028C70_SWAP_STD) { /* R */
2333 blend = normal = V_028714_SPI_SHADER_32_R;
2334 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2335 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2336 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2337 else
2338 assert(0);
2339 break;
2340
2341 case V_028C70_COLOR_32_32:
2342 if (swap == V_028C70_SWAP_STD) { /* RG */
2343 blend = normal = V_028714_SPI_SHADER_32_GR;
2344 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2345 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2346 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2347 else
2348 assert(0);
2349 break;
2350
2351 case V_028C70_COLOR_32_32_32_32:
2352 case V_028C70_COLOR_8_24:
2353 case V_028C70_COLOR_24_8:
2354 case V_028C70_COLOR_X24_8_32_FLOAT:
2355 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2356 break;
2357
2358 default:
2359 assert(0);
2360 return;
2361 }
2362
2363 /* The DB->CB copy needs 32_ABGR. */
2364 if (is_depth)
2365 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2366
2367 surf->spi_shader_col_format = normal;
2368 surf->spi_shader_col_format_alpha = alpha;
2369 surf->spi_shader_col_format_blend = blend;
2370 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2371 }
2372
2373 static void si_initialize_color_surface(struct si_context *sctx,
2374 struct si_surface *surf)
2375 {
2376 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2377 unsigned color_info, color_attrib;
2378 unsigned format, swap, ntype, endian;
2379 const struct util_format_description *desc;
2380 int firstchan;
2381 unsigned blend_clamp = 0, blend_bypass = 0;
2382
2383 desc = util_format_description(surf->base.format);
2384 for (firstchan = 0; firstchan < 4; firstchan++) {
2385 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2386 break;
2387 }
2388 }
2389 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2390 ntype = V_028C70_NUMBER_FLOAT;
2391 } else {
2392 ntype = V_028C70_NUMBER_UNORM;
2393 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2394 ntype = V_028C70_NUMBER_SRGB;
2395 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2396 if (desc->channel[firstchan].pure_integer) {
2397 ntype = V_028C70_NUMBER_SINT;
2398 } else {
2399 assert(desc->channel[firstchan].normalized);
2400 ntype = V_028C70_NUMBER_SNORM;
2401 }
2402 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2403 if (desc->channel[firstchan].pure_integer) {
2404 ntype = V_028C70_NUMBER_UINT;
2405 } else {
2406 assert(desc->channel[firstchan].normalized);
2407 ntype = V_028C70_NUMBER_UNORM;
2408 }
2409 }
2410 }
2411
2412 format = si_translate_colorformat(surf->base.format);
2413 if (format == V_028C70_COLOR_INVALID) {
2414 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2415 }
2416 assert(format != V_028C70_COLOR_INVALID);
2417 swap = si_translate_colorswap(surf->base.format, false);
2418 endian = si_colorformat_endian_swap(format);
2419
2420 /* blend clamp should be set for all NORM/SRGB types */
2421 if (ntype == V_028C70_NUMBER_UNORM ||
2422 ntype == V_028C70_NUMBER_SNORM ||
2423 ntype == V_028C70_NUMBER_SRGB)
2424 blend_clamp = 1;
2425
2426 /* set blend bypass according to docs if SINT/UINT or
2427 8/24 COLOR variants */
2428 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2429 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2430 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2431 blend_clamp = 0;
2432 blend_bypass = 1;
2433 }
2434
2435 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2436 if (format == V_028C70_COLOR_8 ||
2437 format == V_028C70_COLOR_8_8 ||
2438 format == V_028C70_COLOR_8_8_8_8)
2439 surf->color_is_int8 = true;
2440 else if (format == V_028C70_COLOR_10_10_10_2 ||
2441 format == V_028C70_COLOR_2_10_10_10)
2442 surf->color_is_int10 = true;
2443 }
2444
2445 color_info = S_028C70_FORMAT(format) |
2446 S_028C70_COMP_SWAP(swap) |
2447 S_028C70_BLEND_CLAMP(blend_clamp) |
2448 S_028C70_BLEND_BYPASS(blend_bypass) |
2449 S_028C70_SIMPLE_FLOAT(1) |
2450 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2451 ntype != V_028C70_NUMBER_SNORM &&
2452 ntype != V_028C70_NUMBER_SRGB &&
2453 format != V_028C70_COLOR_8_24 &&
2454 format != V_028C70_COLOR_24_8) |
2455 S_028C70_NUMBER_TYPE(ntype) |
2456 S_028C70_ENDIAN(endian);
2457
2458 /* Intensity is implemented as Red, so treat it that way. */
2459 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2460 util_format_is_intensity(surf->base.format));
2461
2462 if (tex->buffer.b.b.nr_samples > 1) {
2463 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2464 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2465
2466 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2467 S_028C74_NUM_FRAGMENTS(log_fragments);
2468
2469 if (tex->surface.fmask_size) {
2470 color_info |= S_028C70_COMPRESSION(1);
2471 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2472
2473 if (sctx->chip_class == GFX6) {
2474 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2475 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2476 }
2477 }
2478 }
2479
2480 if (sctx->chip_class >= GFX8) {
2481 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2482 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2483
2484 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2485 64 for APU because all of our APUs to date use DIMMs which have
2486 a request granularity size of 64B while all other chips have a
2487 32B request size */
2488 if (!sctx->screen->info.has_dedicated_vram)
2489 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2490
2491 if (tex->buffer.b.b.nr_storage_samples > 1) {
2492 if (tex->surface.bpe == 1)
2493 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2494 else if (tex->surface.bpe == 2)
2495 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2496 }
2497
2498 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2499 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2500 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2501 }
2502
2503 /* This must be set for fast clear to work without FMASK. */
2504 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2505 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2506 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2507 }
2508
2509 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2510 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2511
2512 if (sctx->chip_class >= GFX9) {
2513 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2514
2515 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2516 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2517 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2518 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2519 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2520 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2521 }
2522
2523 surf->cb_color_view = color_view;
2524 surf->cb_color_info = color_info;
2525 surf->cb_color_attrib = color_attrib;
2526
2527 /* Determine pixel shader export format */
2528 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2529
2530 surf->color_initialized = true;
2531 }
2532
2533 static void si_init_depth_surface(struct si_context *sctx,
2534 struct si_surface *surf)
2535 {
2536 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2537 unsigned level = surf->base.u.tex.level;
2538 unsigned format, stencil_format;
2539 uint32_t z_info, s_info;
2540
2541 format = si_translate_dbformat(tex->db_render_format);
2542 stencil_format = tex->surface.has_stencil ?
2543 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2544
2545 assert(format != V_028040_Z_INVALID);
2546 if (format == V_028040_Z_INVALID)
2547 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2548
2549 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2550 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2551 surf->db_htile_data_base = 0;
2552 surf->db_htile_surface = 0;
2553
2554 if (sctx->chip_class >= GFX9) {
2555 assert(tex->surface.u.gfx9.surf_offset == 0);
2556 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2557 surf->db_stencil_base = (tex->buffer.gpu_address +
2558 tex->surface.u.gfx9.stencil_offset) >> 8;
2559 z_info = S_028038_FORMAT(format) |
2560 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2561 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2562 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2563 s_info = S_02803C_FORMAT(stencil_format) |
2564 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2565 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2566 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2567 surf->db_depth_view |= S_028008_MIPID(level);
2568 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2569 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2570
2571 if (si_htile_enabled(tex, level)) {
2572 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2573 S_028038_ALLOW_EXPCLEAR(1);
2574
2575 if (tex->tc_compatible_htile) {
2576 unsigned max_zplanes = 4;
2577
2578 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2579 tex->buffer.b.b.nr_samples > 1)
2580 max_zplanes = 2;
2581
2582 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2583 S_028038_ITERATE_FLUSH(1);
2584 s_info |= S_02803C_ITERATE_FLUSH(1);
2585 }
2586
2587 if (tex->surface.has_stencil) {
2588 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2589 * See that for explanation.
2590 */
2591 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2592 } else {
2593 /* Use all HTILE for depth if there's no stencil. */
2594 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2595 }
2596
2597 surf->db_htile_data_base = (tex->buffer.gpu_address +
2598 tex->htile_offset) >> 8;
2599 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2600 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2601 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2602 }
2603 } else {
2604 /* GFX6-GFX8 */
2605 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2606
2607 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2608
2609 surf->db_depth_base = (tex->buffer.gpu_address +
2610 tex->surface.u.legacy.level[level].offset) >> 8;
2611 surf->db_stencil_base = (tex->buffer.gpu_address +
2612 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2613
2614 z_info = S_028040_FORMAT(format) |
2615 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2616 s_info = S_028044_FORMAT(stencil_format);
2617 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2618
2619 if (sctx->chip_class >= GFX7) {
2620 struct radeon_info *info = &sctx->screen->info;
2621 unsigned index = tex->surface.u.legacy.tiling_index[level];
2622 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2623 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2624 unsigned tile_mode = info->si_tile_mode_array[index];
2625 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2626 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2627
2628 surf->db_depth_info |=
2629 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2630 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2631 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2632 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2633 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2634 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2635 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2636 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2637 } else {
2638 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2639 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2640 tile_mode_index = si_tile_mode_index(tex, level, true);
2641 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2642 }
2643
2644 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2645 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2646 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2647 levelinfo->nblk_y) / 64 - 1);
2648
2649 if (si_htile_enabled(tex, level)) {
2650 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2651 S_028040_ALLOW_EXPCLEAR(1);
2652
2653 if (tex->surface.has_stencil) {
2654 /* Workaround: For a not yet understood reason, the
2655 * combination of MSAA, fast stencil clear and stencil
2656 * decompress messes with subsequent stencil buffer
2657 * uses. Problem was reproduced on Verde, Bonaire,
2658 * Tonga, and Carrizo.
2659 *
2660 * Disabling EXPCLEAR works around the problem.
2661 *
2662 * Check piglit's arb_texture_multisample-stencil-clear
2663 * test if you want to try changing this.
2664 */
2665 if (tex->buffer.b.b.nr_samples <= 1)
2666 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2667 } else if (!tex->tc_compatible_htile) {
2668 /* Use all of the htile_buffer for depth if there's no stencil.
2669 * This must not be set when TC-compatible HTILE is enabled
2670 * due to a hw bug.
2671 */
2672 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2673 }
2674
2675 surf->db_htile_data_base = (tex->buffer.gpu_address +
2676 tex->htile_offset) >> 8;
2677 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2678
2679 if (tex->tc_compatible_htile) {
2680 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2681
2682 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2683 if (tex->buffer.b.b.nr_samples <= 1)
2684 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2685 else if (tex->buffer.b.b.nr_samples <= 4)
2686 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2687 else
2688 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2689 }
2690 }
2691 }
2692
2693 surf->db_z_info = z_info;
2694 surf->db_stencil_info = s_info;
2695
2696 surf->depth_initialized = true;
2697 }
2698
2699 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2700 {
2701 if (sctx->decompression_enabled)
2702 return;
2703
2704 if (sctx->framebuffer.state.zsbuf) {
2705 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2706 struct si_texture *tex = (struct si_texture *)surf->texture;
2707
2708 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2709
2710 if (tex->surface.has_stencil)
2711 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2712 }
2713
2714 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2715 while (compressed_cb_mask) {
2716 unsigned i = u_bit_scan(&compressed_cb_mask);
2717 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2718 struct si_texture *tex = (struct si_texture*)surf->texture;
2719
2720 if (tex->surface.fmask_size)
2721 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2722 if (tex->dcc_gather_statistics)
2723 tex->separate_dcc_dirty = true;
2724 }
2725 }
2726
2727 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2728 {
2729 for (int i = 0; i < state->nr_cbufs; ++i) {
2730 struct si_surface *surf = NULL;
2731 struct si_texture *tex;
2732
2733 if (!state->cbufs[i])
2734 continue;
2735 surf = (struct si_surface*)state->cbufs[i];
2736 tex = (struct si_texture*)surf->base.texture;
2737
2738 p_atomic_dec(&tex->framebuffers_bound);
2739 }
2740 }
2741
2742 static void si_set_framebuffer_state(struct pipe_context *ctx,
2743 const struct pipe_framebuffer_state *state)
2744 {
2745 struct si_context *sctx = (struct si_context *)ctx;
2746 struct si_surface *surf = NULL;
2747 struct si_texture *tex;
2748 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2749 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2750 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2751 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2752 bool old_has_stencil =
2753 old_has_zsbuf &&
2754 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2755 bool unbound = false;
2756 int i;
2757
2758 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2759 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2760 * We could implement the full workaround here, but it's a useless case.
2761 */
2762 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2763 unreachable("the framebuffer shouldn't have zero area");
2764 return;
2765 }
2766
2767 si_update_fb_dirtiness_after_rendering(sctx);
2768
2769 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2770 if (!sctx->framebuffer.state.cbufs[i])
2771 continue;
2772
2773 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2774 if (tex->dcc_gather_statistics)
2775 vi_separate_dcc_stop_query(sctx, tex);
2776 }
2777
2778 /* Disable DCC if the formats are incompatible. */
2779 for (i = 0; i < state->nr_cbufs; i++) {
2780 if (!state->cbufs[i])
2781 continue;
2782
2783 surf = (struct si_surface*)state->cbufs[i];
2784 tex = (struct si_texture*)surf->base.texture;
2785
2786 if (!surf->dcc_incompatible)
2787 continue;
2788
2789 /* Since the DCC decompression calls back into set_framebuffer-
2790 * _state, we need to unbind the framebuffer, so that
2791 * vi_separate_dcc_stop_query isn't called twice with the same
2792 * color buffer.
2793 */
2794 if (!unbound) {
2795 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2796 unbound = true;
2797 }
2798
2799 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2800 if (!si_texture_disable_dcc(sctx, tex))
2801 si_decompress_dcc(sctx, tex);
2802
2803 surf->dcc_incompatible = false;
2804 }
2805
2806 /* Only flush TC when changing the framebuffer state, because
2807 * the only client not using TC that can change textures is
2808 * the framebuffer.
2809 *
2810 * Wait for compute shaders because of possible transitions:
2811 * - FB write -> shader read
2812 * - shader write -> FB read
2813 *
2814 * DB caches are flushed on demand (using si_decompress_textures).
2815 *
2816 * When MSAA is enabled, CB and TC caches are flushed on demand
2817 * (after FMASK decompression). Shader write -> FB read transitions
2818 * cannot happen for MSAA textures, because MSAA shader images are
2819 * not supported.
2820 *
2821 * Only flush and wait for CB if there is actually a bound color buffer.
2822 */
2823 if (sctx->framebuffer.uncompressed_cb_mask) {
2824 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2825 sctx->framebuffer.CB_has_shader_readable_metadata,
2826 sctx->framebuffer.all_DCC_pipe_aligned);
2827 }
2828
2829 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2830
2831 /* u_blitter doesn't invoke depth decompression when it does multiple
2832 * blits in a row, but the only case when it matters for DB is when
2833 * doing generate_mipmap. So here we flush DB manually between
2834 * individual generate_mipmap blits.
2835 * Note that lower mipmap levels aren't compressed.
2836 */
2837 if (sctx->generate_mipmap_for_depth) {
2838 si_make_DB_shader_coherent(sctx, 1, false,
2839 sctx->framebuffer.DB_has_shader_readable_metadata);
2840 } else if (sctx->chip_class == GFX9) {
2841 /* It appears that DB metadata "leaks" in a sequence of:
2842 * - depth clear
2843 * - DCC decompress for shader image writes (with DB disabled)
2844 * - render with DEPTH_BEFORE_SHADER=1
2845 * Flushing DB metadata works around the problem.
2846 */
2847 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2848 }
2849
2850 /* Take the maximum of the old and new count. If the new count is lower,
2851 * dirtying is needed to disable the unbound colorbuffers.
2852 */
2853 sctx->framebuffer.dirty_cbufs |=
2854 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2855 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2856
2857 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2858 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2859
2860 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2861 sctx->framebuffer.spi_shader_col_format = 0;
2862 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2863 sctx->framebuffer.spi_shader_col_format_blend = 0;
2864 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2865 sctx->framebuffer.color_is_int8 = 0;
2866 sctx->framebuffer.color_is_int10 = 0;
2867
2868 sctx->framebuffer.compressed_cb_mask = 0;
2869 sctx->framebuffer.uncompressed_cb_mask = 0;
2870 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2871 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2872 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2873 sctx->framebuffer.any_dst_linear = false;
2874 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2875 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2876 sctx->framebuffer.all_DCC_pipe_aligned = true;
2877 unsigned num_bpp64_colorbufs = 0;
2878
2879 for (i = 0; i < state->nr_cbufs; i++) {
2880 if (!state->cbufs[i])
2881 continue;
2882
2883 surf = (struct si_surface*)state->cbufs[i];
2884 tex = (struct si_texture*)surf->base.texture;
2885
2886 if (!surf->color_initialized) {
2887 si_initialize_color_surface(sctx, surf);
2888 }
2889
2890 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2891 sctx->framebuffer.spi_shader_col_format |=
2892 surf->spi_shader_col_format << (i * 4);
2893 sctx->framebuffer.spi_shader_col_format_alpha |=
2894 surf->spi_shader_col_format_alpha << (i * 4);
2895 sctx->framebuffer.spi_shader_col_format_blend |=
2896 surf->spi_shader_col_format_blend << (i * 4);
2897 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2898 surf->spi_shader_col_format_blend_alpha << (i * 4);
2899
2900 if (surf->color_is_int8)
2901 sctx->framebuffer.color_is_int8 |= 1 << i;
2902 if (surf->color_is_int10)
2903 sctx->framebuffer.color_is_int10 |= 1 << i;
2904
2905 if (tex->surface.fmask_size)
2906 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2907 else
2908 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2909
2910 /* Don't update nr_color_samples for non-AA buffers.
2911 * (e.g. destination of MSAA resolve)
2912 */
2913 if (tex->buffer.b.b.nr_samples >= 2 &&
2914 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2915 sctx->framebuffer.nr_color_samples =
2916 MIN2(sctx->framebuffer.nr_color_samples,
2917 tex->buffer.b.b.nr_storage_samples);
2918 sctx->framebuffer.nr_color_samples =
2919 MAX2(1, sctx->framebuffer.nr_color_samples);
2920 }
2921
2922 if (tex->surface.is_linear)
2923 sctx->framebuffer.any_dst_linear = true;
2924 if (tex->surface.bpe >= 8)
2925 num_bpp64_colorbufs++;
2926
2927 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2928 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2929
2930 if (sctx->chip_class >= GFX9 &&
2931 !tex->surface.u.gfx9.dcc.pipe_aligned)
2932 sctx->framebuffer.all_DCC_pipe_aligned = false;
2933 }
2934
2935 si_context_add_resource_size(sctx, surf->base.texture);
2936
2937 p_atomic_inc(&tex->framebuffers_bound);
2938
2939 if (tex->dcc_gather_statistics) {
2940 /* Dirty tracking must be enabled for DCC usage analysis. */
2941 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2942 vi_separate_dcc_start_query(sctx, tex);
2943 }
2944 }
2945
2946 /* For optimal DCC performance. */
2947 if (sctx->chip_class == GFX8)
2948 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2949 else if (num_bpp64_colorbufs >= 5)
2950 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2951 else
2952 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2953
2954 struct si_texture *zstex = NULL;
2955
2956 if (state->zsbuf) {
2957 surf = (struct si_surface*)state->zsbuf;
2958 zstex = (struct si_texture*)surf->base.texture;
2959
2960 if (!surf->depth_initialized) {
2961 si_init_depth_surface(sctx, surf);
2962 }
2963
2964 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2965 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2966
2967 si_context_add_resource_size(sctx, surf->base.texture);
2968 }
2969
2970 si_update_ps_colorbuf0_slot(sctx);
2971 si_update_poly_offset_state(sctx);
2972 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2973 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2974
2975 if (sctx->screen->dpbb_allowed)
2976 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2977
2978 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2979 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2980
2981 if (sctx->screen->has_out_of_order_rast &&
2982 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2983 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2984 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2985 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2986
2987 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2988 struct pipe_constant_buffer constbuf = {0};
2989
2990 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2991 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2992
2993 constbuf.buffer = sctx->sample_pos_buffer;
2994
2995 /* Set sample locations as fragment shader constants. */
2996 switch (sctx->framebuffer.nr_samples) {
2997 case 1:
2998 constbuf.buffer_offset = 0;
2999 break;
3000 case 2:
3001 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3002 (ubyte*)sctx->sample_positions.x1;
3003 break;
3004 case 4:
3005 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3006 (ubyte*)sctx->sample_positions.x1;
3007 break;
3008 case 8:
3009 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3010 (ubyte*)sctx->sample_positions.x1;
3011 break;
3012 case 16:
3013 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3014 (ubyte*)sctx->sample_positions.x1;
3015 break;
3016 default:
3017 PRINT_ERR("Requested an invalid number of samples %i.\n",
3018 sctx->framebuffer.nr_samples);
3019 assert(0);
3020 }
3021 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3022 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3023
3024 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3025 }
3026
3027 sctx->do_update_shaders = true;
3028
3029 if (!sctx->decompression_enabled) {
3030 /* Prevent textures decompression when the framebuffer state
3031 * changes come from the decompression passes themselves.
3032 */
3033 sctx->need_check_render_feedback = true;
3034 }
3035 }
3036
3037 static void si_emit_framebuffer_state(struct si_context *sctx)
3038 {
3039 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3040 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3041 unsigned i, nr_cbufs = state->nr_cbufs;
3042 struct si_texture *tex = NULL;
3043 struct si_surface *cb = NULL;
3044 unsigned cb_color_info = 0;
3045
3046 /* Colorbuffers. */
3047 for (i = 0; i < nr_cbufs; i++) {
3048 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3049 unsigned cb_color_attrib;
3050
3051 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3052 continue;
3053
3054 cb = (struct si_surface*)state->cbufs[i];
3055 if (!cb) {
3056 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3057 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3058 continue;
3059 }
3060
3061 tex = (struct si_texture *)cb->base.texture;
3062 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3063 &tex->buffer, RADEON_USAGE_READWRITE,
3064 tex->buffer.b.b.nr_samples > 1 ?
3065 RADEON_PRIO_COLOR_BUFFER_MSAA :
3066 RADEON_PRIO_COLOR_BUFFER);
3067
3068 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3069 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3070 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3071 RADEON_PRIO_SEPARATE_META);
3072 }
3073
3074 if (tex->dcc_separate_buffer)
3075 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3076 tex->dcc_separate_buffer,
3077 RADEON_USAGE_READWRITE,
3078 RADEON_PRIO_SEPARATE_META);
3079
3080 /* Compute mutable surface parameters. */
3081 cb_color_base = tex->buffer.gpu_address >> 8;
3082 cb_color_fmask = 0;
3083 cb_color_cmask = tex->cmask_base_address_reg;
3084 cb_dcc_base = 0;
3085 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3086 cb_color_attrib = cb->cb_color_attrib;
3087
3088 if (cb->base.u.tex.level > 0)
3089 cb_color_info &= C_028C70_FAST_CLEAR;
3090
3091 if (tex->surface.fmask_size) {
3092 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3093 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3094 }
3095
3096 /* Set up DCC. */
3097 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3098 bool is_msaa_resolve_dst = state->cbufs[0] &&
3099 state->cbufs[0]->texture->nr_samples > 1 &&
3100 state->cbufs[1] == &cb->base &&
3101 state->cbufs[1]->texture->nr_samples <= 1;
3102
3103 if (!is_msaa_resolve_dst)
3104 cb_color_info |= S_028C70_DCC_ENABLE(1);
3105
3106 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3107 tex->dcc_offset) >> 8;
3108 cb_dcc_base |= tex->surface.tile_swizzle;
3109 }
3110
3111 if (sctx->chip_class >= GFX9) {
3112 struct gfx9_surf_meta_flags meta;
3113
3114 if (tex->dcc_offset)
3115 meta = tex->surface.u.gfx9.dcc;
3116 else
3117 meta = tex->surface.u.gfx9.cmask;
3118
3119 /* Set mutable surface parameters. */
3120 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3121 cb_color_base |= tex->surface.tile_swizzle;
3122 if (!tex->surface.fmask_size)
3123 cb_color_fmask = cb_color_base;
3124 if (cb->base.u.tex.level > 0)
3125 cb_color_cmask = cb_color_base;
3126 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3127 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3128 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3129 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3130
3131 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3132 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3133 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3134 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3135 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3136 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3137 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3138 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3139 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3140 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3141 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3142 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3143 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3144 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3145 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3146 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3147
3148 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3149 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3150 } else {
3151 /* Compute mutable surface parameters (GFX6-GFX8). */
3152 const struct legacy_surf_level *level_info =
3153 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3154 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3155 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3156
3157 cb_color_base += level_info->offset >> 8;
3158 /* Only macrotiled modes can set tile swizzle. */
3159 if (level_info->mode == RADEON_SURF_MODE_2D)
3160 cb_color_base |= tex->surface.tile_swizzle;
3161
3162 if (!tex->surface.fmask_size)
3163 cb_color_fmask = cb_color_base;
3164 if (cb->base.u.tex.level > 0)
3165 cb_color_cmask = cb_color_base;
3166 if (cb_dcc_base)
3167 cb_dcc_base += level_info->dcc_offset >> 8;
3168
3169 pitch_tile_max = level_info->nblk_x / 8 - 1;
3170 slice_tile_max = level_info->nblk_x *
3171 level_info->nblk_y / 64 - 1;
3172 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3173
3174 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3175 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3176 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3177
3178 if (tex->surface.fmask_size) {
3179 if (sctx->chip_class >= GFX7)
3180 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3181 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3182 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3183 } else {
3184 /* This must be set for fast clear to work without FMASK. */
3185 if (sctx->chip_class >= GFX7)
3186 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3187 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3188 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3189 }
3190
3191 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3192 sctx->chip_class >= GFX8 ? 14 : 13);
3193 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3194 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3195 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3196 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3197 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3198 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3199 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3200 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3201 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3202 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3203 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3204 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3205 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3206
3207 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3208 radeon_emit(cs, cb_dcc_base);
3209 }
3210 }
3211 for (; i < 8 ; i++)
3212 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3213 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3214
3215 /* ZS buffer. */
3216 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3217 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3218 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3219
3220 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3221 &tex->buffer, RADEON_USAGE_READWRITE,
3222 zb->base.texture->nr_samples > 1 ?
3223 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3224 RADEON_PRIO_DEPTH_BUFFER);
3225
3226 if (sctx->chip_class >= GFX9) {
3227 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3228 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3229 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3230 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3231
3232 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3233 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3234 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3235 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3236 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3237 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3238 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3239 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3240 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3241 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3242 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3243 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3244
3245 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3246 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3247 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3248 } else {
3249 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3250
3251 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3252 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3253 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3254 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3255 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3256 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3257 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3258 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3259 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3260 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3261 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3262 }
3263
3264 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3265 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3266 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3267
3268 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3269 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3270 } else if (sctx->framebuffer.dirty_zsbuf) {
3271 if (sctx->chip_class >= GFX9)
3272 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3273 else
3274 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3275
3276 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3277 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3278 }
3279
3280 /* Framebuffer dimensions. */
3281 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3282 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3283 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3284
3285 if (sctx->screen->dfsm_allowed) {
3286 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3287 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3288 }
3289
3290 sctx->framebuffer.dirty_cbufs = 0;
3291 sctx->framebuffer.dirty_zsbuf = false;
3292 }
3293
3294 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3295 {
3296 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3297 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3298 unsigned nr_samples = sctx->framebuffer.nr_samples;
3299 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3300
3301 /* Smoothing (only possible with nr_samples == 1) uses the same
3302 * sample locations as the MSAA it simulates.
3303 */
3304 if (nr_samples <= 1 && sctx->smoothing_enabled)
3305 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3306
3307 /* On Polaris, the small primitive filter uses the sample locations
3308 * even when MSAA is off, so we need to make sure they're set to 0.
3309 */
3310 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3311 nr_samples != sctx->sample_locs_num_samples) {
3312 sctx->sample_locs_num_samples = nr_samples;
3313 si_emit_sample_locations(cs, nr_samples);
3314 }
3315
3316 if (sctx->family >= CHIP_POLARIS10) {
3317 unsigned small_prim_filter_cntl =
3318 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3319 /* line bug */
3320 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3321
3322 /* The alternative of setting sample locations to 0 would
3323 * require a DB flush to avoid Z errors, see
3324 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3325 */
3326 if (has_msaa_sample_loc_bug &&
3327 sctx->framebuffer.nr_samples > 1 &&
3328 !rs->multisample_enable)
3329 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3330
3331 radeon_opt_set_context_reg(sctx,
3332 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3333 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3334 small_prim_filter_cntl);
3335 }
3336
3337 /* The exclusion bits can be set to improve rasterization efficiency
3338 * if no sample lies on the pixel boundary (-8 sample offset).
3339 */
3340 bool exclusion = sctx->chip_class >= GFX7 &&
3341 (!rs->multisample_enable || nr_samples != 16);
3342 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3343 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3344 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3345 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3346 }
3347
3348 static bool si_out_of_order_rasterization(struct si_context *sctx)
3349 {
3350 struct si_state_blend *blend = sctx->queued.named.blend;
3351 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3352
3353 if (!sctx->screen->has_out_of_order_rast)
3354 return false;
3355
3356 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3357
3358 if (blend) {
3359 colormask &= blend->cb_target_enabled_4bit;
3360 } else {
3361 colormask = 0;
3362 }
3363
3364 /* Conservative: No logic op. */
3365 if (colormask && blend->logicop_enable)
3366 return false;
3367
3368 struct si_dsa_order_invariance dsa_order_invariant = {
3369 .zs = true, .pass_set = true, .pass_last = false
3370 };
3371
3372 if (sctx->framebuffer.state.zsbuf) {
3373 struct si_texture *zstex =
3374 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3375 bool has_stencil = zstex->surface.has_stencil;
3376 dsa_order_invariant = dsa->order_invariance[has_stencil];
3377 if (!dsa_order_invariant.zs)
3378 return false;
3379
3380 /* The set of PS invocations is always order invariant,
3381 * except when early Z/S tests are requested. */
3382 if (sctx->ps_shader.cso &&
3383 sctx->ps_shader.cso->info.writes_memory &&
3384 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3385 !dsa_order_invariant.pass_set)
3386 return false;
3387
3388 if (sctx->num_perfect_occlusion_queries != 0 &&
3389 !dsa_order_invariant.pass_set)
3390 return false;
3391 }
3392
3393 if (!colormask)
3394 return true;
3395
3396 unsigned blendmask = colormask & blend->blend_enable_4bit;
3397
3398 if (blendmask) {
3399 /* Only commutative blending. */
3400 if (blendmask & ~blend->commutative_4bit)
3401 return false;
3402
3403 if (!dsa_order_invariant.pass_set)
3404 return false;
3405 }
3406
3407 if (colormask & ~blendmask) {
3408 if (!dsa_order_invariant.pass_last)
3409 return false;
3410 }
3411
3412 return true;
3413 }
3414
3415 static void si_emit_msaa_config(struct si_context *sctx)
3416 {
3417 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3418 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3419 /* 33% faster rendering to linear color buffers */
3420 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3421 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3422 unsigned sc_mode_cntl_1 =
3423 S_028A4C_WALK_SIZE(dst_is_linear) |
3424 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3425 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3426 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3427 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3428 /* always 1: */
3429 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3430 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3431 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3432 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3433 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3434 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3435 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3436 S_028804_INCOHERENT_EQAA_READS(1) |
3437 S_028804_INTERPOLATE_COMP_Z(1) |
3438 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3439 unsigned coverage_samples, color_samples, z_samples;
3440
3441 /* S: Coverage samples (up to 16x):
3442 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3443 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3444 *
3445 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3446 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3447 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3448 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3449 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3450 * # Z samples).
3451 *
3452 * F: Color samples (up to 8x, must be <= coverage samples):
3453 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3454 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3455 *
3456 * Can be anything between coverage and color samples:
3457 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3458 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3459 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3460 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3461 * # All are currently set the same as coverage samples.
3462 *
3463 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3464 * flag for undefined color samples. A shader-based resolve must handle unknowns
3465 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3466 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3467 * useful. The CB resolve always drops unknowns.
3468 *
3469 * Sensible AA configurations:
3470 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3471 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3472 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3473 * EQAA 8s 8z 8f = 8x MSAA
3474 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3475 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3476 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3477 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3478 * EQAA 4s 4z 4f = 4x MSAA
3479 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3480 * EQAA 2s 2z 2f = 2x MSAA
3481 */
3482 if (sctx->framebuffer.nr_samples > 1) {
3483 coverage_samples = sctx->framebuffer.nr_samples;
3484 color_samples = sctx->framebuffer.nr_color_samples;
3485
3486 if (sctx->framebuffer.state.zsbuf) {
3487 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3488 z_samples = MAX2(1, z_samples);
3489 } else {
3490 z_samples = coverage_samples;
3491 }
3492 } else if (sctx->smoothing_enabled) {
3493 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3494 } else {
3495 coverage_samples = color_samples = z_samples = 1;
3496 }
3497
3498 /* Required by OpenGL line rasterization.
3499 *
3500 * TODO: We should also enable perpendicular endcaps for AA lines,
3501 * but that requires implementing line stippling in the pixel
3502 * shader. SC can only do line stippling with axis-aligned
3503 * endcaps.
3504 */
3505 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3506 unsigned sc_aa_config = 0;
3507
3508 if (coverage_samples > 1) {
3509 /* distance from the pixel center, indexed by log2(nr_samples) */
3510 static unsigned max_dist[] = {
3511 0, /* unused */
3512 4, /* 2x MSAA */
3513 6, /* 4x MSAA */
3514 7, /* 8x MSAA */
3515 8, /* 16x MSAA */
3516 };
3517 unsigned log_samples = util_logbase2(coverage_samples);
3518 unsigned log_z_samples = util_logbase2(z_samples);
3519 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3520 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3521
3522 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3523 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3524 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3525 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3526
3527 if (sctx->framebuffer.nr_samples > 1) {
3528 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3529 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3530 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3531 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3532 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3533 } else if (sctx->smoothing_enabled) {
3534 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3535 }
3536 }
3537
3538 unsigned initial_cdw = cs->current.cdw;
3539
3540 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3541 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3542 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3543 sc_aa_config);
3544 /* R_028804_DB_EQAA */
3545 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3546 db_eqaa);
3547 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3548 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3549 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3550
3551 if (initial_cdw != cs->current.cdw) {
3552 sctx->context_roll = true;
3553
3554 /* GFX9: Flush DFSM when the AA mode changes. */
3555 if (sctx->screen->dfsm_allowed) {
3556 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3557 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3558 }
3559 }
3560 }
3561
3562 void si_update_ps_iter_samples(struct si_context *sctx)
3563 {
3564 if (sctx->framebuffer.nr_samples > 1)
3565 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3566 if (sctx->screen->dpbb_allowed)
3567 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3568 }
3569
3570 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3571 {
3572 struct si_context *sctx = (struct si_context *)ctx;
3573
3574 /* The hardware can only do sample shading with 2^n samples. */
3575 min_samples = util_next_power_of_two(min_samples);
3576
3577 if (sctx->ps_iter_samples == min_samples)
3578 return;
3579
3580 sctx->ps_iter_samples = min_samples;
3581 sctx->do_update_shaders = true;
3582
3583 si_update_ps_iter_samples(sctx);
3584 }
3585
3586 /*
3587 * Samplers
3588 */
3589
3590 /**
3591 * Build the sampler view descriptor for a buffer texture.
3592 * @param state 256-bit descriptor; only the high 128 bits are filled in
3593 */
3594 void
3595 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3596 enum pipe_format format,
3597 unsigned offset, unsigned size,
3598 uint32_t *state)
3599 {
3600 const struct util_format_description *desc;
3601 int first_non_void;
3602 unsigned stride;
3603 unsigned num_records;
3604 unsigned num_format, data_format;
3605
3606 desc = util_format_description(format);
3607 first_non_void = util_format_get_first_non_void_channel(format);
3608 stride = desc->block.bits / 8;
3609 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3610 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3611
3612 num_records = size / stride;
3613 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3614
3615 /* The NUM_RECORDS field has a different meaning depending on the chip,
3616 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3617 *
3618 * GFX6-GFX7:
3619 * - If STRIDE == 0, it's in byte units.
3620 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3621 *
3622 * GFX8:
3623 * - For SMEM and STRIDE == 0, it's in byte units.
3624 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3625 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3626 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3627 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3628 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3629 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3630 * That way the same descriptor can be used by both SMEM and VMEM.
3631 *
3632 * GFX9:
3633 * - For SMEM and STRIDE == 0, it's in byte units.
3634 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3635 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3636 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3637 */
3638 if (screen->info.chip_class >= GFX9 && HAVE_LLVM < 0x0800)
3639 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3640 * from STRIDE to bytes. This works around it by setting
3641 * NUM_RECORDS to at least the size of one element, so that
3642 * the first element is readable when IDXEN == 0.
3643 */
3644 num_records = num_records ? MAX2(num_records, stride) : 0;
3645 else if (screen->info.chip_class == GFX8)
3646 num_records *= stride;
3647
3648 state[4] = 0;
3649 state[5] = S_008F04_STRIDE(stride);
3650 state[6] = num_records;
3651 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3652 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3653 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3654 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3655 S_008F0C_NUM_FORMAT(num_format) |
3656 S_008F0C_DATA_FORMAT(data_format);
3657 }
3658
3659 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3660 {
3661 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3662
3663 if (swizzle[3] == PIPE_SWIZZLE_X) {
3664 /* For the pre-defined border color values (white, opaque
3665 * black, transparent black), the only thing that matters is
3666 * that the alpha channel winds up in the correct place
3667 * (because the RGB channels are all the same) so either of
3668 * these enumerations will work.
3669 */
3670 if (swizzle[2] == PIPE_SWIZZLE_Y)
3671 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3672 else
3673 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3674 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3675 if (swizzle[1] == PIPE_SWIZZLE_Y)
3676 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3677 else
3678 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3679 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3680 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3681 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3682 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3683 }
3684
3685 return bc_swizzle;
3686 }
3687
3688 /**
3689 * Build the sampler view descriptor for a texture.
3690 */
3691 void
3692 si_make_texture_descriptor(struct si_screen *screen,
3693 struct si_texture *tex,
3694 bool sampler,
3695 enum pipe_texture_target target,
3696 enum pipe_format pipe_format,
3697 const unsigned char state_swizzle[4],
3698 unsigned first_level, unsigned last_level,
3699 unsigned first_layer, unsigned last_layer,
3700 unsigned width, unsigned height, unsigned depth,
3701 uint32_t *state,
3702 uint32_t *fmask_state)
3703 {
3704 struct pipe_resource *res = &tex->buffer.b.b;
3705 const struct util_format_description *desc;
3706 unsigned char swizzle[4];
3707 int first_non_void;
3708 unsigned num_format, data_format, type, num_samples;
3709 uint64_t va;
3710
3711 desc = util_format_description(pipe_format);
3712
3713 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3714 MAX2(1, res->nr_samples) :
3715 MAX2(1, res->nr_storage_samples);
3716
3717 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3718 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3719 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3720 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3721
3722 switch (pipe_format) {
3723 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3724 case PIPE_FORMAT_X32_S8X24_UINT:
3725 case PIPE_FORMAT_X8Z24_UNORM:
3726 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3727 break;
3728 case PIPE_FORMAT_X24S8_UINT:
3729 /*
3730 * X24S8 is implemented as an 8_8_8_8 data format, to
3731 * fix texture gathers. This affects at least
3732 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3733 */
3734 if (screen->info.chip_class <= GFX8)
3735 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3736 else
3737 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3738 break;
3739 default:
3740 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3741 }
3742 } else {
3743 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3744 }
3745
3746 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3747
3748 switch (pipe_format) {
3749 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3750 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3751 break;
3752 default:
3753 if (first_non_void < 0) {
3754 if (util_format_is_compressed(pipe_format)) {
3755 switch (pipe_format) {
3756 case PIPE_FORMAT_DXT1_SRGB:
3757 case PIPE_FORMAT_DXT1_SRGBA:
3758 case PIPE_FORMAT_DXT3_SRGBA:
3759 case PIPE_FORMAT_DXT5_SRGBA:
3760 case PIPE_FORMAT_BPTC_SRGBA:
3761 case PIPE_FORMAT_ETC2_SRGB8:
3762 case PIPE_FORMAT_ETC2_SRGB8A1:
3763 case PIPE_FORMAT_ETC2_SRGBA8:
3764 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3765 break;
3766 case PIPE_FORMAT_RGTC1_SNORM:
3767 case PIPE_FORMAT_LATC1_SNORM:
3768 case PIPE_FORMAT_RGTC2_SNORM:
3769 case PIPE_FORMAT_LATC2_SNORM:
3770 case PIPE_FORMAT_ETC2_R11_SNORM:
3771 case PIPE_FORMAT_ETC2_RG11_SNORM:
3772 /* implies float, so use SNORM/UNORM to determine
3773 whether data is signed or not */
3774 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3775 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3776 break;
3777 default:
3778 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3779 break;
3780 }
3781 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3782 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3783 } else {
3784 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3785 }
3786 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3787 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3788 } else {
3789 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3790
3791 switch (desc->channel[first_non_void].type) {
3792 case UTIL_FORMAT_TYPE_FLOAT:
3793 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3794 break;
3795 case UTIL_FORMAT_TYPE_SIGNED:
3796 if (desc->channel[first_non_void].normalized)
3797 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3798 else if (desc->channel[first_non_void].pure_integer)
3799 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3800 else
3801 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3802 break;
3803 case UTIL_FORMAT_TYPE_UNSIGNED:
3804 if (desc->channel[first_non_void].normalized)
3805 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3806 else if (desc->channel[first_non_void].pure_integer)
3807 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3808 else
3809 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3810 }
3811 }
3812 }
3813
3814 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3815 if (data_format == ~0) {
3816 data_format = 0;
3817 }
3818
3819 /* S8 with Z32 HTILE needs a special format. */
3820 if (screen->info.chip_class >= GFX9 &&
3821 pipe_format == PIPE_FORMAT_S8_UINT &&
3822 tex->tc_compatible_htile)
3823 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3824
3825 if (!sampler &&
3826 (res->target == PIPE_TEXTURE_CUBE ||
3827 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3828 (screen->info.chip_class <= GFX8 &&
3829 res->target == PIPE_TEXTURE_3D))) {
3830 /* For the purpose of shader images, treat cube maps and 3D
3831 * textures as 2D arrays. For 3D textures, the address
3832 * calculations for mipmaps are different, so we rely on the
3833 * caller to effectively disable mipmaps.
3834 */
3835 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3836
3837 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3838 } else {
3839 type = si_tex_dim(screen, tex, target, num_samples);
3840 }
3841
3842 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3843 height = 1;
3844 depth = res->array_size;
3845 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3846 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3847 if (sampler || res->target != PIPE_TEXTURE_3D)
3848 depth = res->array_size;
3849 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3850 depth = res->array_size / 6;
3851
3852 state[0] = 0;
3853 state[1] = (S_008F14_DATA_FORMAT(data_format) |
3854 S_008F14_NUM_FORMAT(num_format));
3855 state[2] = (S_008F18_WIDTH(width - 1) |
3856 S_008F18_HEIGHT(height - 1) |
3857 S_008F18_PERF_MOD(4));
3858 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3859 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3860 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3861 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3862 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3863 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3864 util_logbase2(num_samples) :
3865 last_level) |
3866 S_008F1C_TYPE(type));
3867 state[4] = 0;
3868 state[5] = S_008F24_BASE_ARRAY(first_layer);
3869 state[6] = 0;
3870 state[7] = 0;
3871
3872 if (screen->info.chip_class >= GFX9) {
3873 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3874
3875 /* Depth is the the last accessible layer on Gfx9.
3876 * The hw doesn't need to know the total number of layers.
3877 */
3878 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3879 state[4] |= S_008F20_DEPTH(depth - 1);
3880 else
3881 state[4] |= S_008F20_DEPTH(last_layer);
3882
3883 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3884 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3885 util_logbase2(num_samples) :
3886 tex->buffer.b.b.last_level);
3887 } else {
3888 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3889 state[4] |= S_008F20_DEPTH(depth - 1);
3890 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3891 }
3892
3893 if (tex->dcc_offset) {
3894 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3895 } else {
3896 /* The last dword is unused by hw. The shader uses it to clear
3897 * bits in the first dword of sampler state.
3898 */
3899 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
3900 if (first_level == last_level)
3901 state[7] = C_008F30_MAX_ANISO_RATIO;
3902 else
3903 state[7] = 0xffffffff;
3904 }
3905 }
3906
3907 /* Initialize the sampler view for FMASK. */
3908 if (tex->surface.fmask_size) {
3909 uint32_t data_format, num_format;
3910
3911 va = tex->buffer.gpu_address + tex->fmask_offset;
3912
3913 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3914 if (screen->info.chip_class >= GFX9) {
3915 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3916 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3917 case FMASK(2,1):
3918 num_format = V_008F14_IMG_FMASK_8_2_1;
3919 break;
3920 case FMASK(2,2):
3921 num_format = V_008F14_IMG_FMASK_8_2_2;
3922 break;
3923 case FMASK(4,1):
3924 num_format = V_008F14_IMG_FMASK_8_4_1;
3925 break;
3926 case FMASK(4,2):
3927 num_format = V_008F14_IMG_FMASK_8_4_2;
3928 break;
3929 case FMASK(4,4):
3930 num_format = V_008F14_IMG_FMASK_8_4_4;
3931 break;
3932 case FMASK(8,1):
3933 num_format = V_008F14_IMG_FMASK_8_8_1;
3934 break;
3935 case FMASK(8,2):
3936 num_format = V_008F14_IMG_FMASK_16_8_2;
3937 break;
3938 case FMASK(8,4):
3939 num_format = V_008F14_IMG_FMASK_32_8_4;
3940 break;
3941 case FMASK(8,8):
3942 num_format = V_008F14_IMG_FMASK_32_8_8;
3943 break;
3944 case FMASK(16,1):
3945 num_format = V_008F14_IMG_FMASK_16_16_1;
3946 break;
3947 case FMASK(16,2):
3948 num_format = V_008F14_IMG_FMASK_32_16_2;
3949 break;
3950 case FMASK(16,4):
3951 num_format = V_008F14_IMG_FMASK_64_16_4;
3952 break;
3953 case FMASK(16,8):
3954 num_format = V_008F14_IMG_FMASK_64_16_8;
3955 break;
3956 default:
3957 unreachable("invalid nr_samples");
3958 }
3959 } else {
3960 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3961 case FMASK(2,1):
3962 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3963 break;
3964 case FMASK(2,2):
3965 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3966 break;
3967 case FMASK(4,1):
3968 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3969 break;
3970 case FMASK(4,2):
3971 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3972 break;
3973 case FMASK(4,4):
3974 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3975 break;
3976 case FMASK(8,1):
3977 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3978 break;
3979 case FMASK(8,2):
3980 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3981 break;
3982 case FMASK(8,4):
3983 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3984 break;
3985 case FMASK(8,8):
3986 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3987 break;
3988 case FMASK(16,1):
3989 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3990 break;
3991 case FMASK(16,2):
3992 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3993 break;
3994 case FMASK(16,4):
3995 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3996 break;
3997 case FMASK(16,8):
3998 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3999 break;
4000 default:
4001 unreachable("invalid nr_samples");
4002 }
4003 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4004 }
4005 #undef FMASK
4006
4007 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4008 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4009 S_008F14_DATA_FORMAT(data_format) |
4010 S_008F14_NUM_FORMAT(num_format);
4011 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4012 S_008F18_HEIGHT(height - 1);
4013 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4014 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4015 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4016 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4017 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4018 fmask_state[4] = 0;
4019 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4020 fmask_state[6] = 0;
4021 fmask_state[7] = 0;
4022
4023 if (screen->info.chip_class >= GFX9) {
4024 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4025 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4026 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
4027 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4028 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4029 } else {
4030 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4031 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4032 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4033 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4034 }
4035 }
4036 }
4037
4038 /**
4039 * Create a sampler view.
4040 *
4041 * @param ctx context
4042 * @param texture texture
4043 * @param state sampler view template
4044 * @param width0 width0 override (for compressed textures as int)
4045 * @param height0 height0 override (for compressed textures as int)
4046 * @param force_level set the base address to the level (for compressed textures)
4047 */
4048 struct pipe_sampler_view *
4049 si_create_sampler_view_custom(struct pipe_context *ctx,
4050 struct pipe_resource *texture,
4051 const struct pipe_sampler_view *state,
4052 unsigned width0, unsigned height0,
4053 unsigned force_level)
4054 {
4055 struct si_context *sctx = (struct si_context*)ctx;
4056 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4057 struct si_texture *tex = (struct si_texture*)texture;
4058 unsigned base_level, first_level, last_level;
4059 unsigned char state_swizzle[4];
4060 unsigned height, depth, width;
4061 unsigned last_layer = state->u.tex.last_layer;
4062 enum pipe_format pipe_format;
4063 const struct legacy_surf_level *surflevel;
4064
4065 if (!view)
4066 return NULL;
4067
4068 /* initialize base object */
4069 view->base = *state;
4070 view->base.texture = NULL;
4071 view->base.reference.count = 1;
4072 view->base.context = ctx;
4073
4074 assert(texture);
4075 pipe_resource_reference(&view->base.texture, texture);
4076
4077 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4078 state->format == PIPE_FORMAT_S8X24_UINT ||
4079 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4080 state->format == PIPE_FORMAT_S8_UINT)
4081 view->is_stencil_sampler = true;
4082
4083 /* Buffer resource. */
4084 if (texture->target == PIPE_BUFFER) {
4085 si_make_buffer_descriptor(sctx->screen,
4086 si_resource(texture),
4087 state->format,
4088 state->u.buf.offset,
4089 state->u.buf.size,
4090 view->state);
4091 return &view->base;
4092 }
4093
4094 state_swizzle[0] = state->swizzle_r;
4095 state_swizzle[1] = state->swizzle_g;
4096 state_swizzle[2] = state->swizzle_b;
4097 state_swizzle[3] = state->swizzle_a;
4098
4099 base_level = 0;
4100 first_level = state->u.tex.first_level;
4101 last_level = state->u.tex.last_level;
4102 width = width0;
4103 height = height0;
4104 depth = texture->depth0;
4105
4106 if (sctx->chip_class <= GFX8 && force_level) {
4107 assert(force_level == first_level &&
4108 force_level == last_level);
4109 base_level = force_level;
4110 first_level = 0;
4111 last_level = 0;
4112 width = u_minify(width, force_level);
4113 height = u_minify(height, force_level);
4114 depth = u_minify(depth, force_level);
4115 }
4116
4117 /* This is not needed if state trackers set last_layer correctly. */
4118 if (state->target == PIPE_TEXTURE_1D ||
4119 state->target == PIPE_TEXTURE_2D ||
4120 state->target == PIPE_TEXTURE_RECT ||
4121 state->target == PIPE_TEXTURE_CUBE)
4122 last_layer = state->u.tex.first_layer;
4123
4124 /* Texturing with separate depth and stencil. */
4125 pipe_format = state->format;
4126
4127 /* Depth/stencil texturing sometimes needs separate texture. */
4128 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4129 if (!tex->flushed_depth_texture &&
4130 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4131 pipe_resource_reference(&view->base.texture, NULL);
4132 FREE(view);
4133 return NULL;
4134 }
4135
4136 assert(tex->flushed_depth_texture);
4137
4138 /* Override format for the case where the flushed texture
4139 * contains only Z or only S.
4140 */
4141 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4142 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4143
4144 tex = tex->flushed_depth_texture;
4145 }
4146
4147 surflevel = tex->surface.u.legacy.level;
4148
4149 if (tex->db_compatible) {
4150 if (!view->is_stencil_sampler)
4151 pipe_format = tex->db_render_format;
4152
4153 switch (pipe_format) {
4154 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4155 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4156 break;
4157 case PIPE_FORMAT_X8Z24_UNORM:
4158 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4159 /* Z24 is always stored like this for DB
4160 * compatibility.
4161 */
4162 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4163 break;
4164 case PIPE_FORMAT_X24S8_UINT:
4165 case PIPE_FORMAT_S8X24_UINT:
4166 case PIPE_FORMAT_X32_S8X24_UINT:
4167 pipe_format = PIPE_FORMAT_S8_UINT;
4168 surflevel = tex->surface.u.legacy.stencil_level;
4169 break;
4170 default:;
4171 }
4172 }
4173
4174 view->dcc_incompatible =
4175 vi_dcc_formats_are_incompatible(texture,
4176 state->u.tex.first_level,
4177 state->format);
4178
4179 si_make_texture_descriptor(sctx->screen, tex, true,
4180 state->target, pipe_format, state_swizzle,
4181 first_level, last_level,
4182 state->u.tex.first_layer, last_layer,
4183 width, height, depth,
4184 view->state, view->fmask_state);
4185
4186 unsigned num_format = G_008F14_NUM_FORMAT(view->state[1]);
4187 view->is_integer =
4188 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4189 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4190 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4191 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4192 view->base_level_info = &surflevel[base_level];
4193 view->base_level = base_level;
4194 view->block_width = util_format_get_blockwidth(pipe_format);
4195 return &view->base;
4196 }
4197
4198 static struct pipe_sampler_view *
4199 si_create_sampler_view(struct pipe_context *ctx,
4200 struct pipe_resource *texture,
4201 const struct pipe_sampler_view *state)
4202 {
4203 return si_create_sampler_view_custom(ctx, texture, state,
4204 texture ? texture->width0 : 0,
4205 texture ? texture->height0 : 0, 0);
4206 }
4207
4208 static void si_sampler_view_destroy(struct pipe_context *ctx,
4209 struct pipe_sampler_view *state)
4210 {
4211 struct si_sampler_view *view = (struct si_sampler_view *)state;
4212
4213 pipe_resource_reference(&state->texture, NULL);
4214 FREE(view);
4215 }
4216
4217 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4218 {
4219 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4220 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4221 (linear_filter &&
4222 (wrap == PIPE_TEX_WRAP_CLAMP ||
4223 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4224 }
4225
4226 static uint32_t si_translate_border_color(struct si_context *sctx,
4227 const struct pipe_sampler_state *state,
4228 const union pipe_color_union *color,
4229 bool is_integer)
4230 {
4231 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4232 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4233
4234 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4235 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4236 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4237 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4238
4239 #define simple_border_types(elt) \
4240 do { \
4241 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4242 color->elt[2] == 0 && color->elt[3] == 0) \
4243 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4244 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4245 color->elt[2] == 0 && color->elt[3] == 1) \
4246 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4247 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4248 color->elt[2] == 1 && color->elt[3] == 1) \
4249 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4250 } while (false)
4251
4252 if (is_integer)
4253 simple_border_types(ui);
4254 else
4255 simple_border_types(f);
4256
4257 #undef simple_border_types
4258
4259 int i;
4260
4261 /* Check if the border has been uploaded already. */
4262 for (i = 0; i < sctx->border_color_count; i++)
4263 if (memcmp(&sctx->border_color_table[i], color,
4264 sizeof(*color)) == 0)
4265 break;
4266
4267 if (i >= SI_MAX_BORDER_COLORS) {
4268 /* Getting 4096 unique border colors is very unlikely. */
4269 fprintf(stderr, "radeonsi: The border color table is full. "
4270 "Any new border colors will be just black. "
4271 "Please file a bug.\n");
4272 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4273 }
4274
4275 if (i == sctx->border_color_count) {
4276 /* Upload a new border color. */
4277 memcpy(&sctx->border_color_table[i], color,
4278 sizeof(*color));
4279 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4280 color, sizeof(*color));
4281 sctx->border_color_count++;
4282 }
4283
4284 return S_008F3C_BORDER_COLOR_PTR(i) |
4285 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4286 }
4287
4288 static inline int S_FIXED(float value, unsigned frac_bits)
4289 {
4290 return value * (1 << frac_bits);
4291 }
4292
4293 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4294 {
4295 if (filter == PIPE_TEX_FILTER_LINEAR)
4296 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4297 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4298 else
4299 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4300 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4301 }
4302
4303 static inline unsigned si_tex_aniso_filter(unsigned filter)
4304 {
4305 if (filter < 2)
4306 return 0;
4307 if (filter < 4)
4308 return 1;
4309 if (filter < 8)
4310 return 2;
4311 if (filter < 16)
4312 return 3;
4313 return 4;
4314 }
4315
4316 static void *si_create_sampler_state(struct pipe_context *ctx,
4317 const struct pipe_sampler_state *state)
4318 {
4319 struct si_context *sctx = (struct si_context *)ctx;
4320 struct si_screen *sscreen = sctx->screen;
4321 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4322 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4323 : state->max_anisotropy;
4324 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4325 union pipe_color_union clamped_border_color;
4326
4327 if (!rstate) {
4328 return NULL;
4329 }
4330
4331 #ifndef NDEBUG
4332 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4333 #endif
4334 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4335 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4336 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4337 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4338 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4339 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4340 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4341 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4342 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4343 S_008F30_COMPAT_MODE(sctx->chip_class >= GFX8));
4344 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4345 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4346 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4347 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4348 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4349 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4350 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4351 S_008F38_MIP_POINT_PRECLAMP(0) |
4352 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4353 S_008F38_FILTER_PREC_FIX(1) |
4354 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= GFX8));
4355 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4356
4357 /* Create sampler resource for integer textures. */
4358 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4359 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4360
4361 /* Create sampler resource for upgraded depth textures. */
4362 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4363
4364 for (unsigned i = 0; i < 4; ++i) {
4365 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4366 * when the border color is 1.0. */
4367 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4368 }
4369
4370 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4371 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4372 else
4373 rstate->upgraded_depth_val[3] =
4374 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4375 S_008F3C_UPGRADED_DEPTH(1);
4376
4377 return rstate;
4378 }
4379
4380 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4381 {
4382 struct si_context *sctx = (struct si_context *)ctx;
4383
4384 if (sctx->sample_mask == (uint16_t)sample_mask)
4385 return;
4386
4387 sctx->sample_mask = sample_mask;
4388 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4389 }
4390
4391 static void si_emit_sample_mask(struct si_context *sctx)
4392 {
4393 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4394 unsigned mask = sctx->sample_mask;
4395
4396 /* Needed for line and polygon smoothing as well as for the Polaris
4397 * small primitive filter. We expect the state tracker to take care of
4398 * this for us.
4399 */
4400 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4401 (mask & 1 && sctx->blitter->running));
4402
4403 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4404 radeon_emit(cs, mask | (mask << 16));
4405 radeon_emit(cs, mask | (mask << 16));
4406 }
4407
4408 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4409 {
4410 #ifndef NDEBUG
4411 struct si_sampler_state *s = state;
4412
4413 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4414 s->magic = 0;
4415 #endif
4416 free(state);
4417 }
4418
4419 /*
4420 * Vertex elements & buffers
4421 */
4422
4423 struct si_fast_udiv_info32
4424 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4425 {
4426 struct util_fast_udiv_info info =
4427 util_compute_fast_udiv_info(D, num_bits, 32);
4428
4429 struct si_fast_udiv_info32 result = {
4430 info.multiplier,
4431 info.pre_shift,
4432 info.post_shift,
4433 info.increment,
4434 };
4435 return result;
4436 }
4437
4438 static void *si_create_vertex_elements(struct pipe_context *ctx,
4439 unsigned count,
4440 const struct pipe_vertex_element *elements)
4441 {
4442 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4443 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4444 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4445 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4446 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4447 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4448 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4449 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4450 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4451 int i;
4452
4453 assert(count <= SI_MAX_ATTRIBS);
4454 if (!v)
4455 return NULL;
4456
4457 v->count = count;
4458 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4459
4460 for (i = 0; i < count; ++i) {
4461 const struct util_format_description *desc;
4462 const struct util_format_channel_description *channel;
4463 int first_non_void;
4464 unsigned vbo_index = elements[i].vertex_buffer_index;
4465
4466 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4467 FREE(v);
4468 return NULL;
4469 }
4470
4471 unsigned instance_divisor = elements[i].instance_divisor;
4472 if (instance_divisor) {
4473 v->uses_instance_divisors = true;
4474
4475 if (instance_divisor == 1) {
4476 v->instance_divisor_is_one |= 1u << i;
4477 } else {
4478 v->instance_divisor_is_fetched |= 1u << i;
4479 divisor_factors[i] =
4480 si_compute_fast_udiv_info32(instance_divisor, 32);
4481 }
4482 }
4483
4484 if (!used[vbo_index]) {
4485 v->first_vb_use_mask |= 1 << i;
4486 used[vbo_index] = true;
4487 }
4488
4489 desc = util_format_description(elements[i].src_format);
4490 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4491 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4492
4493 v->format_size[i] = desc->block.bits / 8;
4494 v->src_offset[i] = elements[i].src_offset;
4495 v->vertex_buffer_index[i] = vbo_index;
4496
4497 bool always_fix = false;
4498 union si_vs_fix_fetch fix_fetch;
4499 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4500
4501 fix_fetch.bits = 0;
4502 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4503
4504 if (channel) {
4505 switch (channel->type) {
4506 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4507 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4508 case UTIL_FORMAT_TYPE_SIGNED: {
4509 if (channel->pure_integer)
4510 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4511 else if (channel->normalized)
4512 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4513 else
4514 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4515 break;
4516 }
4517 case UTIL_FORMAT_TYPE_UNSIGNED: {
4518 if (channel->pure_integer)
4519 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4520 else if (channel->normalized)
4521 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4522 else
4523 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4524 break;
4525 }
4526 default: unreachable("bad format type");
4527 }
4528 } else {
4529 switch (elements[i].src_format) {
4530 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4531 default: unreachable("bad other format");
4532 }
4533 }
4534
4535 if (desc->channel[0].size == 10) {
4536 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4537 log_hw_load_size = 2;
4538
4539 /* The hardware always treats the 2-bit alpha channel as
4540 * unsigned, so a shader workaround is needed. The affected
4541 * chips are GFX8 and older except Stoney (GFX8.1).
4542 */
4543 always_fix = sscreen->info.chip_class <= GFX8 &&
4544 sscreen->info.family != CHIP_STONEY &&
4545 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4546 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4547 fix_fetch.u.log_size = 3; /* special encoding */
4548 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4549 log_hw_load_size = 2;
4550 } else {
4551 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4552 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4553
4554 /* Always fix up:
4555 * - doubles (multiple loads + truncate to float)
4556 * - 32-bit requiring a conversion
4557 */
4558 always_fix =
4559 (fix_fetch.u.log_size == 3) ||
4560 (fix_fetch.u.log_size == 2 &&
4561 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4562 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4563 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4564
4565 /* Also fixup 8_8_8 and 16_16_16. */
4566 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4567 always_fix = true;
4568 log_hw_load_size = fix_fetch.u.log_size;
4569 }
4570 }
4571
4572 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4573 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4574 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4575 fix_fetch.u.reverse = 1;
4576 }
4577
4578 /* Force the workaround for unaligned access here already if the
4579 * offset relative to the vertex buffer base is unaligned.
4580 *
4581 * There is a theoretical case in which this is too conservative:
4582 * if the vertex buffer's offset is also unaligned in just the
4583 * right way, we end up with an aligned address after all.
4584 * However, this case should be extremely rare in practice (it
4585 * won't happen in well-behaved applications), and taking it
4586 * into account would complicate the fast path (where everything
4587 * is nicely aligned).
4588 */
4589 bool check_alignment = log_hw_load_size >= 1 && sscreen->info.chip_class == GFX6;
4590 bool opencode = sscreen->options.vs_fetch_always_opencode;
4591
4592 if (check_alignment &&
4593 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4594 opencode = true;
4595
4596 if (always_fix || check_alignment || opencode)
4597 v->fix_fetch[i] = fix_fetch.bits;
4598
4599 if (opencode)
4600 v->fix_fetch_opencode |= 1 << i;
4601 if (opencode || always_fix)
4602 v->fix_fetch_always |= 1 << i;
4603
4604 if (check_alignment && !opencode) {
4605 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4606
4607 v->fix_fetch_unaligned |= 1 << i;
4608 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4609 v->vb_alignment_check_mask |= 1 << vbo_index;
4610 }
4611
4612 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
4613 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
4614 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
4615 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
4616
4617 unsigned data_format, num_format;
4618 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4619 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4620 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
4621 S_008F0C_DATA_FORMAT(data_format);
4622 }
4623
4624 if (v->instance_divisor_is_fetched) {
4625 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4626
4627 v->instance_divisor_factor_buffer =
4628 (struct si_resource*)
4629 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4630 num_divisors * sizeof(divisor_factors[0]));
4631 if (!v->instance_divisor_factor_buffer) {
4632 FREE(v);
4633 return NULL;
4634 }
4635 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4636 NULL, PIPE_TRANSFER_WRITE);
4637 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4638 }
4639 return v;
4640 }
4641
4642 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4643 {
4644 struct si_context *sctx = (struct si_context *)ctx;
4645 struct si_vertex_elements *old = sctx->vertex_elements;
4646 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4647
4648 sctx->vertex_elements = v;
4649 sctx->vertex_buffers_dirty = true;
4650
4651 if (v &&
4652 (!old ||
4653 old->count != v->count ||
4654 old->uses_instance_divisors != v->uses_instance_divisors ||
4655 /* we don't check which divisors changed */
4656 v->uses_instance_divisors ||
4657 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
4658 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4659 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4660 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
4661 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4662 * functions of fix_fetch and the src_offset alignment.
4663 * If they change and fix_fetch doesn't, it must be due to different
4664 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4665 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4666 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4667 sctx->do_update_shaders = true;
4668
4669 if (v && v->instance_divisor_is_fetched) {
4670 struct pipe_constant_buffer cb;
4671
4672 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4673 cb.user_buffer = NULL;
4674 cb.buffer_offset = 0;
4675 cb.buffer_size = 0xffffffff;
4676 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4677 }
4678 }
4679
4680 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4681 {
4682 struct si_context *sctx = (struct si_context *)ctx;
4683 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4684
4685 if (sctx->vertex_elements == state)
4686 sctx->vertex_elements = NULL;
4687 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4688 FREE(state);
4689 }
4690
4691 static void si_set_vertex_buffers(struct pipe_context *ctx,
4692 unsigned start_slot, unsigned count,
4693 const struct pipe_vertex_buffer *buffers)
4694 {
4695 struct si_context *sctx = (struct si_context *)ctx;
4696 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4697 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
4698 uint32_t unaligned = orig_unaligned;
4699 int i;
4700
4701 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4702
4703 if (buffers) {
4704 for (i = 0; i < count; i++) {
4705 const struct pipe_vertex_buffer *src = buffers + i;
4706 struct pipe_vertex_buffer *dsti = dst + i;
4707 struct pipe_resource *buf = src->buffer.resource;
4708
4709 pipe_resource_reference(&dsti->buffer.resource, buf);
4710 dsti->buffer_offset = src->buffer_offset;
4711 dsti->stride = src->stride;
4712 if (dsti->buffer_offset & 3 || dsti->stride & 3)
4713 unaligned |= 1 << (start_slot + i);
4714 else
4715 unaligned &= ~(1 << (start_slot + i));
4716
4717 si_context_add_resource_size(sctx, buf);
4718 if (buf)
4719 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4720 }
4721 } else {
4722 for (i = 0; i < count; i++) {
4723 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4724 }
4725 unaligned &= ~u_bit_consecutive(start_slot, count);
4726 }
4727 sctx->vertex_buffers_dirty = true;
4728 sctx->vertex_buffer_unaligned = unaligned;
4729
4730 /* Check whether alignment may have changed in a way that requires
4731 * shader changes. This check is conservative: a vertex buffer can only
4732 * trigger a shader change if the misalignment amount changes (e.g.
4733 * from byte-aligned to short-aligned), but we only keep track of
4734 * whether buffers are at least dword-aligned, since that should always
4735 * be the case in well-behaved applications anyway.
4736 */
4737 if (sctx->vertex_elements &&
4738 (sctx->vertex_elements->vb_alignment_check_mask &
4739 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
4740 sctx->do_update_shaders = true;
4741 }
4742
4743 /*
4744 * Misc
4745 */
4746
4747 static void si_set_tess_state(struct pipe_context *ctx,
4748 const float default_outer_level[4],
4749 const float default_inner_level[2])
4750 {
4751 struct si_context *sctx = (struct si_context *)ctx;
4752 struct pipe_constant_buffer cb;
4753 float array[8];
4754
4755 memcpy(array, default_outer_level, sizeof(float) * 4);
4756 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4757
4758 cb.buffer = NULL;
4759 cb.user_buffer = NULL;
4760 cb.buffer_size = sizeof(array);
4761
4762 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
4763 (void*)array, sizeof(array),
4764 &cb.buffer_offset);
4765
4766 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4767 pipe_resource_reference(&cb.buffer, NULL);
4768 }
4769
4770 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4771 {
4772 struct si_context *sctx = (struct si_context *)ctx;
4773
4774 si_update_fb_dirtiness_after_rendering(sctx);
4775
4776 /* Multisample surfaces are flushed in si_decompress_textures. */
4777 if (sctx->framebuffer.uncompressed_cb_mask) {
4778 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4779 sctx->framebuffer.CB_has_shader_readable_metadata,
4780 sctx->framebuffer.all_DCC_pipe_aligned);
4781 }
4782 }
4783
4784 /* This only ensures coherency for shader image/buffer stores. */
4785 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4786 {
4787 struct si_context *sctx = (struct si_context *)ctx;
4788
4789 if (!(flags & ~PIPE_BARRIER_UPDATE))
4790 return;
4791
4792 /* Subsequent commands must wait for all shader invocations to
4793 * complete. */
4794 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4795 SI_CONTEXT_CS_PARTIAL_FLUSH;
4796
4797 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4798 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4799 SI_CONTEXT_INV_VMEM_L1;
4800
4801 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4802 PIPE_BARRIER_SHADER_BUFFER |
4803 PIPE_BARRIER_TEXTURE |
4804 PIPE_BARRIER_IMAGE |
4805 PIPE_BARRIER_STREAMOUT_BUFFER |
4806 PIPE_BARRIER_GLOBAL_BUFFER)) {
4807 /* As far as I can tell, L1 contents are written back to L2
4808 * automatically at end of shader, but the contents of other
4809 * L1 caches might still be stale. */
4810 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4811 }
4812
4813 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4814 /* Indices are read through TC L2 since GFX8.
4815 * L1 isn't used.
4816 */
4817 if (sctx->screen->info.chip_class <= GFX7)
4818 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4819 }
4820
4821 /* MSAA color, any depth and any stencil are flushed in
4822 * si_decompress_textures when needed.
4823 */
4824 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4825 sctx->framebuffer.uncompressed_cb_mask) {
4826 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4827
4828 if (sctx->chip_class <= GFX8)
4829 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4830 }
4831
4832 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4833 if (sctx->screen->info.chip_class <= GFX8 &&
4834 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4835 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4836 }
4837
4838 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4839 {
4840 struct pipe_blend_state blend;
4841
4842 memset(&blend, 0, sizeof(blend));
4843 blend.independent_blend_enable = true;
4844 blend.rt[0].colormask = 0xf;
4845 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4846 }
4847
4848 static void si_init_config(struct si_context *sctx);
4849
4850 void si_init_state_compute_functions(struct si_context *sctx)
4851 {
4852 sctx->b.create_sampler_state = si_create_sampler_state;
4853 sctx->b.delete_sampler_state = si_delete_sampler_state;
4854 sctx->b.create_sampler_view = si_create_sampler_view;
4855 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4856 sctx->b.memory_barrier = si_memory_barrier;
4857 }
4858
4859 void si_init_state_functions(struct si_context *sctx)
4860 {
4861 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4862 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4863 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4864 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4865 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4866 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4867 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4868 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4869 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4870 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4871 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4872
4873 sctx->b.create_blend_state = si_create_blend_state;
4874 sctx->b.bind_blend_state = si_bind_blend_state;
4875 sctx->b.delete_blend_state = si_delete_blend_state;
4876 sctx->b.set_blend_color = si_set_blend_color;
4877
4878 sctx->b.create_rasterizer_state = si_create_rs_state;
4879 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4880 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4881
4882 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4883 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4884 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4885
4886 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4887 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4888 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4889 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4890 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4891
4892 sctx->b.set_clip_state = si_set_clip_state;
4893 sctx->b.set_stencil_ref = si_set_stencil_ref;
4894
4895 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4896
4897 sctx->b.set_sample_mask = si_set_sample_mask;
4898
4899 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4900 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4901 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4902 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4903
4904 sctx->b.texture_barrier = si_texture_barrier;
4905 sctx->b.set_min_samples = si_set_min_samples;
4906 sctx->b.set_tess_state = si_set_tess_state;
4907
4908 sctx->b.set_active_query_state = si_set_active_query_state;
4909
4910 si_init_config(sctx);
4911 }
4912
4913 void si_init_screen_state_functions(struct si_screen *sscreen)
4914 {
4915 sscreen->b.is_format_supported = si_is_format_supported;
4916 }
4917
4918 static void si_set_grbm_gfx_index(struct si_context *sctx,
4919 struct si_pm4_state *pm4, unsigned value)
4920 {
4921 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
4922 R_00802C_GRBM_GFX_INDEX;
4923 si_pm4_set_reg(pm4, reg, value);
4924 }
4925
4926 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4927 struct si_pm4_state *pm4, unsigned se)
4928 {
4929 assert(se == ~0 || se < sctx->screen->info.max_se);
4930 si_set_grbm_gfx_index(sctx, pm4,
4931 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4932 S_030800_SE_INDEX(se)) |
4933 S_030800_SH_BROADCAST_WRITES(1) |
4934 S_030800_INSTANCE_BROADCAST_WRITES(1));
4935 }
4936
4937 static void
4938 si_write_harvested_raster_configs(struct si_context *sctx,
4939 struct si_pm4_state *pm4,
4940 unsigned raster_config,
4941 unsigned raster_config_1)
4942 {
4943 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4944 unsigned raster_config_se[4];
4945 unsigned se;
4946
4947 ac_get_harvested_configs(&sctx->screen->info,
4948 raster_config,
4949 &raster_config_1,
4950 raster_config_se);
4951
4952 for (se = 0; se < num_se; se++) {
4953 si_set_grbm_gfx_index_se(sctx, pm4, se);
4954 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4955 }
4956 si_set_grbm_gfx_index(sctx, pm4, ~0);
4957
4958 if (sctx->chip_class >= GFX7) {
4959 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4960 }
4961 }
4962
4963 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4964 {
4965 struct si_screen *sscreen = sctx->screen;
4966 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4967 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4968 unsigned raster_config = sscreen->pa_sc_raster_config;
4969 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4970
4971 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4972 /* Always use the default config when all backends are enabled
4973 * (or when we failed to determine the enabled backends).
4974 */
4975 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4976 raster_config);
4977 if (sctx->chip_class >= GFX7)
4978 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4979 raster_config_1);
4980 } else {
4981 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4982 }
4983 }
4984
4985 static void si_init_config(struct si_context *sctx)
4986 {
4987 struct si_screen *sscreen = sctx->screen;
4988 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4989 bool has_clear_state = sscreen->has_clear_state;
4990 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4991
4992 /* GFX6, radeon kernel disabled CLEAR_STATE. */
4993 assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
4994 sscreen->info.drm_major != 3);
4995
4996 if (!pm4)
4997 return;
4998
4999 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5000 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5001 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5002 si_pm4_cmd_end(pm4, false);
5003
5004 if (has_clear_state) {
5005 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5006 si_pm4_cmd_add(pm4, 0);
5007 si_pm4_cmd_end(pm4, false);
5008 }
5009
5010 if (sctx->chip_class <= GFX8)
5011 si_set_raster_config(sctx, pm4);
5012
5013 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5014 if (!has_clear_state)
5015 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5016
5017 /* FIXME calculate these values somehow ??? */
5018 if (sctx->chip_class <= GFX8) {
5019 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5020 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5021 }
5022
5023 if (!has_clear_state) {
5024 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5025 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5026 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5027 }
5028
5029 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5030 if (!has_clear_state)
5031 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5032 if (sctx->chip_class < GFX7)
5033 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5034 S_008A14_CLIP_VTX_REORDER_ENA(1));
5035
5036 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5037 * I don't know why. Deduced by trial and error.
5038 */
5039 if (sctx->chip_class <= GFX7) {
5040 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5041 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5042 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5043 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5044 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5045 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5046 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5047 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5048 }
5049
5050 if (!has_clear_state) {
5051 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5052 S_028230_ER_TRI(0xA) |
5053 S_028230_ER_POINT(0xA) |
5054 S_028230_ER_RECT(0xA) |
5055 /* Required by DX10_DIAMOND_TEST_ENA: */
5056 S_028230_ER_LINE_LR(0x1A) |
5057 S_028230_ER_LINE_RL(0x26) |
5058 S_028230_ER_LINE_TB(0xA) |
5059 S_028230_ER_LINE_BT(0xA));
5060 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5061 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5062 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5063 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5064 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5065 }
5066
5067 if (sctx->chip_class >= GFX9) {
5068 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5069 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5070 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5071 } else {
5072 /* These registers, when written, also overwrite the CLEAR_STATE
5073 * context, so we can't rely on CLEAR_STATE setting them.
5074 * It would be an issue if there was another UMD changing them.
5075 */
5076 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5077 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5078 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5079 }
5080
5081 if (sctx->chip_class >= GFX7) {
5082 if (sctx->chip_class >= GFX9) {
5083 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5084 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5085 } else {
5086 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5087 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5088 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5089 S_00B41C_WAVE_LIMIT(0x3F));
5090 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5091 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5092
5093 /* If this is 0, Bonaire can hang even if GS isn't being used.
5094 * Other chips are unaffected. These are suboptimal values,
5095 * but we don't use on-chip GS.
5096 */
5097 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5098 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5099 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5100 }
5101 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5102 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5103
5104 /* Compute LATE_ALLOC_VS.LIMIT. */
5105 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5106 unsigned late_alloc_limit; /* The limit is per SH. */
5107
5108 if (sctx->family == CHIP_KABINI) {
5109 late_alloc_limit = 0; /* Potential hang on Kabini. */
5110 } else if (num_cu_per_sh <= 4) {
5111 /* Too few available compute units per SH. Disallowing
5112 * VS to run on one CU could hurt us more than late VS
5113 * allocation would help.
5114 *
5115 * 2 is the highest safe number that allows us to keep
5116 * all CUs enabled.
5117 */
5118 late_alloc_limit = 2;
5119 } else {
5120 /* This is a good initial value, allowing 1 late_alloc
5121 * wave per SIMD on num_cu - 2.
5122 */
5123 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5124
5125 /* The limit is 0-based, so 0 means 1. */
5126 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5127 late_alloc_limit -= 1;
5128 }
5129
5130 /* VS can't execute on one CU if the limit is > 2. */
5131 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5132 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5133 S_00B118_WAVE_LIMIT(0x3F));
5134 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5135 S_00B11C_LIMIT(late_alloc_limit));
5136 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5137 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5138 }
5139
5140 if (sctx->chip_class >= GFX8) {
5141 unsigned vgt_tess_distribution;
5142
5143 vgt_tess_distribution =
5144 S_028B50_ACCUM_ISOLINE(32) |
5145 S_028B50_ACCUM_TRI(11) |
5146 S_028B50_ACCUM_QUAD(11) |
5147 S_028B50_DONUT_SPLIT(16);
5148
5149 /* Testing with Unigine Heaven extreme tesselation yielded best results
5150 * with TRAP_SPLIT = 3.
5151 */
5152 if (sctx->family == CHIP_FIJI ||
5153 sctx->family >= CHIP_POLARIS10)
5154 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5155
5156 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5157 } else if (!has_clear_state) {
5158 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5159 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5160 }
5161
5162 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5163 if (sctx->chip_class >= GFX7) {
5164 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5165 S_028084_ADDRESS(border_color_va >> 40));
5166 }
5167 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5168 RADEON_PRIO_BORDER_COLORS);
5169
5170 if (sctx->chip_class >= GFX9) {
5171 unsigned num_se = sscreen->info.max_se;
5172 unsigned pc_lines = 0;
5173
5174 switch (sctx->family) {
5175 case CHIP_VEGA10:
5176 case CHIP_VEGA12:
5177 case CHIP_VEGA20:
5178 pc_lines = 4096;
5179 break;
5180 case CHIP_RAVEN:
5181 case CHIP_RAVEN2:
5182 pc_lines = 1024;
5183 break;
5184 default:
5185 assert(0);
5186 }
5187
5188 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5189 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5190 S_028C48_MAX_PRIM_PER_BATCH(1023));
5191 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5192 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5193 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5194 }
5195
5196 si_pm4_upload_indirect_buffer(sctx, pm4);
5197 sctx->init_config = pm4;
5198 }