src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "radeonsi_pm4.h"
  31 #include "../radeon/r600_pipe_common.h"
  32
  33 struct si_state_blend {
  34         struct si_pm4_state     pm4;
  35         uint32_t                cb_target_mask;
  36         bool                    alpha_to_one;
  37 };
  38
  39 struct si_state_viewport {
  40         struct si_pm4_state             pm4;
  41         struct pipe_viewport_state      viewport;
  42 };
  43
  44 struct si_state_rasterizer {
  45         struct si_pm4_state     pm4;
  46         bool                    flatshade;
  47         bool                    two_side;
  48         bool                    multisample_enable;
  49         bool                    line_stipple_enable;
  50         unsigned                sprite_coord_enable;
  51         unsigned                pa_sc_line_stipple;
  52         unsigned                pa_su_sc_mode_cntl;
  53         unsigned                pa_cl_clip_cntl;
  54         unsigned                pa_cl_vs_out_cntl;
  55         unsigned                clip_plane_enable;
  56         float                   offset_units;
  57         float                   offset_scale;
  58 };
  59
  60 struct si_state_dsa {
  61         struct si_pm4_state     pm4;
  62         float                   alpha_ref;
  63         unsigned                alpha_func;
  64         unsigned                db_render_control;
  65         uint8_t                 valuemask[2];
  66         uint8_t                 writemask[2];
  67 };
  68
  69 struct si_vertex_element
  70 {
  71         unsigned                        count;
  72         uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
  73         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
  74 };
  75
  76 union si_state {
  77         struct {
  78                 struct si_pm4_state             *init;
  79                 struct si_state_blend           *blend;
  80                 struct si_pm4_state             *blend_color;
  81                 struct si_pm4_state             *clip;
  82                 struct si_pm4_state             *sample_mask;
  83                 struct si_pm4_state             *scissor;
  84                 struct si_state_viewport        *viewport;
  85                 struct si_pm4_state             *framebuffer;
  86                 struct si_state_rasterizer      *rasterizer;
  87                 struct si_state_dsa             *dsa;
  88                 struct si_pm4_state             *fb_rs;
  89                 struct si_pm4_state             *fb_blend;
  90                 struct si_pm4_state             *dsa_stencil_ref;
  91                 struct si_pm4_state             *vs;
  92                 struct si_pm4_state             *vs_sampler;
  93                 struct si_pm4_state             *ps;
  94                 struct si_pm4_state             *ps_sampler;
  95                 struct si_pm4_state             *spi;
  96                 struct si_pm4_state             *vertex_buffers;
  97                 struct si_pm4_state             *draw_info;
  98                 struct si_pm4_state             *draw;
  99         } named;
 100         struct si_pm4_state     *array[0];
 101 };
 102
 103 #define NUM_TEX_UNITS 16
 104
 105 /* User sampler views:   0..15
 106  * FMASK sampler views: 16..31 (no sampler states)
 107  */
 108 #define FMASK_TEX_OFFSET        NUM_TEX_UNITS
 109 #define NUM_SAMPLER_VIEWS       (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
 110 #define NUM_SAMPLER_STATES      NUM_TEX_UNITS
 111
 112 #define NUM_PIPE_CONST_BUFFERS 16
 113 #define NUM_CONST_BUFFERS 17
 114
 115 /* This represents resource descriptors in memory, such as buffer resources,
 116  * image resources, and sampler states.
 117  */
 118 struct si_descriptors {
 119         struct r600_atom atom;
 120
 121         /* The size of one resource descriptor. */
 122         unsigned element_dw_size;
 123         /* The maximum number of resource descriptors. */
 124         unsigned num_elements;
 125
 126         /* The buffer where resource descriptors are stored. */
 127         struct r600_resource *buffer;
 128
 129         /* The i-th bit is set if that element is dirty (changed but not emitted). */
 130         unsigned dirty_mask;
 131         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 132         unsigned enabled_mask;
 133
 134         /* We can't update descriptors directly because the GPU might be
 135          * reading them at the same time, so we have to update them
 136          * in a copy-on-write manner. Each such copy is called a context,
 137          * which is just another array descriptors in the same buffer. */
 138         unsigned current_context_id;
 139         /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
 140         unsigned context_size;
 141
 142         /* The shader userdata register where the 64-bit pointer to the descriptor
 143          * array will be stored. */
 144         unsigned shader_userdata_reg;
 145 };
 146
 147 struct si_sampler_views {
 148         struct si_descriptors           desc;
 149         struct pipe_sampler_view        *views[NUM_SAMPLER_VIEWS];
 150         uint32_t                        *desc_data[NUM_SAMPLER_VIEWS];
 151 };
 152
 153 struct si_buffer_resources {
 154         struct si_descriptors           desc;
 155         unsigned                        num_buffers;
 156         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 157         struct pipe_resource            **buffers; /* this has num_buffers elements */
 158         uint32_t                        *desc_storage; /* this has num_buffers*4 elements */
 159         uint32_t                        **desc_data; /* an array of pointers pointing to desc_storage */
 160 };
 161
 162 #define si_pm4_block_idx(member) \
 163         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 164
 165 #define si_pm4_state_changed(rctx, member) \
 166         ((rctx)->queued.named.member != (rctx)->emitted.named.member)
 167
 168 #define si_pm4_bind_state(rctx, member, value) \
 169         do { \
 170                 (rctx)->queued.named.member = (value); \
 171         } while(0)
 172
 173 #define si_pm4_delete_state(rctx, member, value) \
 174         do { \
 175                 if ((rctx)->queued.named.member == (value)) { \
 176                         (rctx)->queued.named.member = NULL; \
 177                 } \
 178                 si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \
 179                                   si_pm4_block_idx(member)); \
 180         } while(0)
 181
 182 #define si_pm4_set_state(rctx, member, value) \
 183         do { \
 184                 if ((rctx)->queued.named.member != (value)) { \
 185                         si_pm4_free_state(rctx, \
 186                                 (struct si_pm4_state *)(rctx)->queued.named.member, \
 187                                 si_pm4_block_idx(member)); \
 188                         (rctx)->queued.named.member = (value); \
 189                 } \
 190         } while(0)
 191
 192 /* si_descriptors.c */
 193 void si_set_sampler_view(struct r600_context *rctx, unsigned shader,
 194                          unsigned slot, struct pipe_sampler_view *view,
 195                          unsigned *view_desc);
 196 void si_init_all_descriptors(struct r600_context *rctx);
 197 void si_release_all_descriptors(struct r600_context *rctx);
 198 void si_all_descriptors_begin_new_cs(struct r600_context *rctx);
 199 void si_copy_buffer(struct r600_context *rctx,
 200                     struct pipe_resource *dst, struct pipe_resource *src,
 201                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 202
 203 /* si_state.c */
 204 struct si_pipe_shader_selector;
 205 struct r600_surface;
 206
 207 boolean si_is_format_supported(struct pipe_screen *screen,
 208                                enum pipe_format format,
 209                                enum pipe_texture_target target,
 210                                unsigned sample_count,
 211                                unsigned usage);
 212 int si_shader_select(struct pipe_context *ctx,
 213                      struct si_pipe_shader_selector *sel,
 214                      unsigned *dirty);
 215 void si_init_state_functions(struct r600_context *rctx);
 216 void si_init_config(struct r600_context *rctx);
 217
 218 /* si_state_draw.c */
 219 extern const struct r600_atom si_atom_cache_flush;
 220 void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *atom);
 221 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 222
 223 /* si_commands.c */
 224 void si_cmd_context_control(struct si_pm4_state *pm4);
 225 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
 226                          uint64_t index_base, uint32_t index_count,
 227                          uint32_t initiator, bool predicate);
 228 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
 229                             uint32_t initiator, bool predicate);
 230 void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
 231
 232 #endif