2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "pipebuffer/pb_slab.h"
31 #include "util/u_blitter.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
36 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
37 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
38 #define SI_NUM_CONST_BUFFERS 16
39 #define SI_NUM_IMAGES 16
40 #define SI_NUM_IMAGE_SLOTS (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
41 #define SI_NUM_SHADER_BUFFERS 16
45 struct si_shader_ctx_state
;
46 struct si_shader_selector
;
50 struct si_state_blend
{
51 struct si_pm4_state pm4
;
52 uint32_t cb_target_mask
;
53 /* Set 0xf or 0x0 (4 bits) per render target if the following is
54 * true. ANDed with spi_shader_col_format.
56 unsigned cb_target_enabled_4bit
;
57 unsigned blend_enable_4bit
;
58 unsigned need_src_alpha_4bit
;
59 unsigned commutative_4bit
;
60 unsigned dcc_msaa_corruption_4bit
;
61 bool alpha_to_coverage
:1;
63 bool dual_src_blend
:1;
64 bool logicop_enable
:1;
67 struct si_state_rasterizer
{
68 struct si_pm4_state pm4
;
69 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
70 struct si_pm4_state
*pm4_poly_offset
;
71 unsigned pa_sc_line_stipple
;
72 unsigned pa_cl_clip_cntl
;
75 unsigned sprite_coord_enable
:8;
76 unsigned clip_plane_enable
:8;
77 unsigned half_pixel_center
:1;
79 unsigned flatshade_first
:1;
81 unsigned multisample_enable
:1;
82 unsigned force_persample_interp
:1;
83 unsigned line_stipple_enable
:1;
84 unsigned poly_stipple_enable
:1;
85 unsigned line_smooth
:1;
86 unsigned poly_smooth
:1;
87 unsigned uses_poly_offset
:1;
88 unsigned clamp_fragment_color
:1;
89 unsigned clamp_vertex_color
:1;
90 unsigned rasterizer_discard
:1;
91 unsigned scissor_enable
:1;
92 unsigned clip_halfz
:1;
93 unsigned cull_front
:1;
95 unsigned depth_clamp_any
:1;
96 unsigned provoking_vertex_first
:1;
99 struct si_dsa_stencil_ref_part
{
100 uint8_t valuemask
[2];
101 uint8_t writemask
[2];
104 struct si_dsa_order_invariance
{
105 /** Whether the final result in Z/S buffers is guaranteed to be
106 * invariant under changes to the order in which fragments arrive. */
109 /** Whether the set of fragments that pass the combined Z/S test is
110 * guaranteed to be invariant under changes to the order in which
111 * fragments arrive. */
114 /** Whether the last fragment that passes the combined Z/S test at each
115 * sample is guaranteed to be invariant under changes to the order in
116 * which fragments arrive. */
120 struct si_state_dsa
{
121 struct si_pm4_state pm4
;
122 struct si_dsa_stencil_ref_part stencil_ref
;
124 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
125 struct si_dsa_order_invariance order_invariance
[2];
128 bool depth_enabled
:1;
129 bool depth_write_enabled
:1;
130 bool stencil_enabled
:1;
131 bool stencil_write_enabled
:1;
136 struct si_stencil_ref
{
137 struct pipe_stencil_ref state
;
138 struct si_dsa_stencil_ref_part dsa_part
;
141 struct si_vertex_elements
143 struct si_resource
*instance_divisor_factor_buffer
;
144 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
145 uint16_t src_offset
[SI_MAX_ATTRIBS
];
146 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
147 uint8_t format_size
[SI_MAX_ATTRIBS
];
148 uint8_t vertex_buffer_index
[SI_MAX_ATTRIBS
];
150 /* Bitmask of elements that always need a fixup to be applied. */
151 uint16_t fix_fetch_always
;
153 /* Bitmask of elements whose fetch should always be opencoded. */
154 uint16_t fix_fetch_opencode
;
156 /* Bitmask of elements which need to be opencoded if the vertex buffer
158 uint16_t fix_fetch_unaligned
;
160 /* For elements in fix_fetch_unaligned: whether the effective
161 * element load size as seen by the hardware is a dword (as opposed
164 uint16_t hw_load_is_dword
;
166 /* Bitmask of vertex buffers requiring alignment check */
167 uint16_t vb_alignment_check_mask
;
170 bool uses_instance_divisors
;
172 uint16_t first_vb_use_mask
;
173 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
174 uint16_t desc_list_byte_size
;
175 uint16_t instance_divisor_is_one
; /* bitmask of inputs */
176 uint16_t instance_divisor_is_fetched
; /* bitmask of inputs */
181 struct si_state_blend
*blend
;
182 struct si_state_rasterizer
*rasterizer
;
183 struct si_state_dsa
*dsa
;
184 struct si_pm4_state
*poly_offset
;
185 struct si_pm4_state
*ls
;
186 struct si_pm4_state
*hs
;
187 struct si_pm4_state
*es
;
188 struct si_pm4_state
*gs
;
189 struct si_pm4_state
*vgt_shader_config
;
190 struct si_pm4_state
*vs
;
191 struct si_pm4_state
*ps
;
193 struct si_pm4_state
*array
[0];
196 #define SI_STATE_IDX(name) \
197 (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
198 #define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
199 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
201 static inline unsigned si_states_that_always_roll_context(void)
203 return (SI_STATE_BIT(blend
) |
204 SI_STATE_BIT(rasterizer
) |
206 SI_STATE_BIT(poly_offset
) |
207 SI_STATE_BIT(vgt_shader_config
));
210 union si_state_atoms
{
212 /* The order matters. */
213 struct si_atom render_cond
;
214 struct si_atom streamout_begin
;
215 struct si_atom streamout_enable
; /* must be after streamout_begin */
216 struct si_atom framebuffer
;
217 struct si_atom msaa_sample_locs
;
218 struct si_atom db_render_state
;
219 struct si_atom dpbb_state
;
220 struct si_atom msaa_config
;
221 struct si_atom sample_mask
;
222 struct si_atom cb_render_state
;
223 struct si_atom blend_color
;
224 struct si_atom clip_regs
;
225 struct si_atom clip_state
;
226 struct si_atom shader_pointers
;
227 struct si_atom guardband
;
228 struct si_atom scissors
;
229 struct si_atom viewports
;
230 struct si_atom stencil_ref
;
231 struct si_atom spi_map
;
232 struct si_atom scratch_state
;
233 struct si_atom window_rectangles
;
234 struct si_atom shader_query
;
236 struct si_atom array
[0];
239 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / \
240 sizeof(struct si_atom)))
241 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
243 static inline unsigned si_atoms_that_always_roll_context(void)
245 return (SI_ATOM_BIT(streamout_begin
) |
246 SI_ATOM_BIT(streamout_enable
) |
247 SI_ATOM_BIT(framebuffer
) |
248 SI_ATOM_BIT(msaa_sample_locs
) |
249 SI_ATOM_BIT(sample_mask
) |
250 SI_ATOM_BIT(blend_color
) |
251 SI_ATOM_BIT(clip_state
) |
252 SI_ATOM_BIT(scissors
) |
253 SI_ATOM_BIT(viewports
) |
254 SI_ATOM_BIT(stencil_ref
) |
255 SI_ATOM_BIT(scratch_state
) |
256 SI_ATOM_BIT(window_rectangles
));
259 struct si_shader_data
{
260 uint32_t sh_base
[SI_NUM_SHADERS
];
263 #define SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK \
264 (S_02881C_USE_VTX_POINT_SIZE(1) | \
265 S_02881C_USE_VTX_EDGE_FLAG(1) | \
266 S_02881C_USE_VTX_RENDER_TARGET_INDX(1) | \
267 S_02881C_USE_VTX_VIEWPORT_INDX(1) | \
268 S_02881C_VS_OUT_MISC_VEC_ENA(1) | \
269 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1))
271 /* The list of registers whose emitted values are remembered by si_context. */
272 enum si_tracked_reg
{
273 SI_TRACKED_DB_RENDER_CONTROL
, /* 2 consecutive registers */
274 SI_TRACKED_DB_COUNT_CONTROL
,
276 SI_TRACKED_DB_RENDER_OVERRIDE2
,
277 SI_TRACKED_DB_SHADER_CONTROL
,
279 SI_TRACKED_CB_TARGET_MASK
,
280 SI_TRACKED_CB_DCC_CONTROL
,
282 SI_TRACKED_SX_PS_DOWNCONVERT
, /* 3 consecutive registers */
283 SI_TRACKED_SX_BLEND_OPT_EPSILON
,
284 SI_TRACKED_SX_BLEND_OPT_CONTROL
,
286 SI_TRACKED_PA_SC_LINE_CNTL
, /* 2 consecutive registers */
287 SI_TRACKED_PA_SC_AA_CONFIG
,
290 SI_TRACKED_PA_SC_MODE_CNTL_1
,
292 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
293 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
295 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
, /* set with SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK*/
296 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
, /* set with ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK */
297 SI_TRACKED_PA_CL_CLIP_CNTL
,
299 SI_TRACKED_PA_SC_BINNER_CNTL_0
,
300 SI_TRACKED_DB_DFSM_CONTROL
,
302 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ
, /* 4 consecutive registers */
303 SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ
,
304 SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ
,
305 SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ
,
307 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET
,
308 SI_TRACKED_PA_SU_VTX_CNTL
,
310 SI_TRACKED_PA_SC_CLIPRECT_RULE
,
312 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
314 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
, /* 3 consecutive registers */
315 SI_TRACKED_VGT_GSVS_RING_OFFSET_2
,
316 SI_TRACKED_VGT_GSVS_RING_OFFSET_3
,
318 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
319 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
321 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
, /* 4 consecutive registers */
322 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1
,
323 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2
,
324 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3
,
326 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
327 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
328 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
329 SI_TRACKED_VGT_GS_MODE
,
330 SI_TRACKED_VGT_PRIMITIVEID_EN
,
331 SI_TRACKED_VGT_REUSE_OFF
,
332 SI_TRACKED_SPI_VS_OUT_CONFIG
,
333 SI_TRACKED_PA_CL_VTE_CNTL
,
334 SI_TRACKED_PA_CL_NGG_CNTL
,
335 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
336 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
338 SI_TRACKED_SPI_SHADER_IDX_FORMAT
, /* 2 consecutive registers */
339 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
341 SI_TRACKED_SPI_PS_INPUT_ENA
, /* 2 consecutive registers */
342 SI_TRACKED_SPI_PS_INPUT_ADDR
,
344 SI_TRACKED_SPI_BARYC_CNTL
,
345 SI_TRACKED_SPI_PS_IN_CONTROL
,
347 SI_TRACKED_SPI_SHADER_Z_FORMAT
, /* 2 consecutive registers */
348 SI_TRACKED_SPI_SHADER_COL_FORMAT
,
350 SI_TRACKED_CB_SHADER_MASK
,
351 SI_TRACKED_VGT_TF_PARAM
,
352 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
357 struct si_tracked_regs
{
359 uint32_t reg_value
[SI_NUM_TRACKED_REGS
];
360 uint32_t spi_ps_input_cntl
[32];
363 /* Private read-write buffer slots. */
370 SI_VS_STREAMOUT_BUF0
,
371 SI_VS_STREAMOUT_BUF1
,
372 SI_VS_STREAMOUT_BUF2
,
373 SI_VS_STREAMOUT_BUF3
,
375 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
376 SI_VS_CONST_INSTANCE_DIVISORS
,
377 SI_VS_CONST_CLIP_PLANES
,
378 SI_PS_CONST_POLY_STIPPLE
,
379 SI_PS_CONST_SAMPLE_POSITIONS
,
381 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
382 SI_PS_IMAGE_COLORBUF0
,
383 SI_PS_IMAGE_COLORBUF0_HI
,
384 SI_PS_IMAGE_COLORBUF0_FMASK
,
385 SI_PS_IMAGE_COLORBUF0_FMASK_HI
,
392 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
396 * 1 - vertex const and shader buffers
397 * 2 - vertex samplers and images
398 * 3 - fragment const and shader buffer
400 * 11 - compute const and shader buffers
401 * 12 - compute samplers and images
404 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
405 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
409 #define SI_DESCS_RW_BUFFERS 0
410 #define SI_DESCS_FIRST_SHADER 1
411 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
412 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
413 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
414 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
416 #define SI_DESCS_SHADER_MASK(name) \
417 u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
418 PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
421 static inline unsigned
422 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
424 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
425 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
428 static inline unsigned
429 si_sampler_and_image_descriptors_idx(unsigned shader
)
431 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
432 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
435 /* This represents descriptors in memory, such as buffer resources,
436 * image resources, and sampler states.
438 struct si_descriptors
{
439 /* The list of descriptors in malloc'd memory. */
441 /* The list in mapped GPU memory. */
444 /* The buffer where the descriptors have been uploaded. */
445 struct si_resource
*buffer
;
446 uint64_t gpu_address
;
448 /* The maximum number of descriptors. */
449 uint32_t num_elements
;
451 /* Slots that are used by currently-bound shaders.
452 * It determines which slots are uploaded.
454 uint32_t first_active_slot
;
455 uint32_t num_active_slots
;
457 /* The SH register offset relative to USER_DATA*_0 where the pointer
458 * to the descriptor array will be stored. */
459 short shader_userdata_offset
;
460 /* The size of one descriptor. */
461 ubyte element_dw_size
;
462 /* If there is only one slot enabled, bind it directly instead of
463 * uploading descriptors. -1 if disabled. */
464 signed char slot_index_to_bind_directly
;
467 struct si_buffer_resources
{
468 struct pipe_resource
**buffers
; /* this has num_buffers elements */
469 unsigned *offsets
; /* this has num_buffers elements */
471 enum radeon_bo_priority priority
:6;
472 enum radeon_bo_priority priority_constbuf
:6;
474 /* The i-th bit is set if that element is enabled (non-NULL resource). */
475 unsigned enabled_mask
;
476 unsigned writable_mask
;
479 #define si_pm4_state_changed(sctx, member) \
480 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
482 #define si_pm4_state_enabled_and_changed(sctx, member) \
483 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
485 #define si_pm4_bind_state(sctx, member, value) \
487 (sctx)->queued.named.member = (value); \
488 (sctx)->dirty_states |= SI_STATE_BIT(member); \
491 #define si_pm4_delete_state(sctx, member, value) \
493 if ((sctx)->queued.named.member == (value)) { \
494 (sctx)->queued.named.member = NULL; \
496 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
497 SI_STATE_IDX(member)); \
500 /* si_descriptors.c */
501 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
502 struct si_texture
*tex
,
503 const struct legacy_surf_level
*base_level_info
,
504 unsigned base_level
, unsigned first_level
,
505 unsigned block_width
, bool is_stencil
,
507 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
);
508 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
509 uint slot
, struct pipe_constant_buffer
*cbuf
);
510 void si_get_shader_buffers(struct si_context
*sctx
,
511 enum pipe_shader_type shader
,
512 uint start_slot
, uint count
,
513 struct pipe_shader_buffer
*sbuf
);
514 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
515 struct pipe_resource
*buffer
,
516 unsigned stride
, unsigned num_records
,
517 bool add_tid
, bool swizzle
,
518 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
519 void si_init_all_descriptors(struct si_context
*sctx
);
520 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
521 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
522 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
523 void si_release_all_descriptors(struct si_context
*sctx
);
524 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
);
525 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
);
526 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
527 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
528 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
529 void si_update_all_texture_descriptors(struct si_context
*sctx
);
530 void si_shader_change_notify(struct si_context
*sctx
);
531 void si_update_needs_color_decompress_masks(struct si_context
*sctx
);
532 void si_emit_graphics_shader_pointers(struct si_context
*sctx
);
533 void si_emit_compute_shader_pointers(struct si_context
*sctx
);
534 void si_set_rw_buffer(struct si_context
*sctx
,
535 uint slot
, const struct pipe_constant_buffer
*input
);
536 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
537 const struct pipe_shader_buffer
*sbuffer
);
538 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
539 uint64_t new_active_mask
);
540 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
541 struct si_shader_selector
*sel
);
542 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
543 struct pb_slab_entry
*entry
);
544 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
546 unsigned group_index
);
547 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
);
548 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
);
550 void si_init_state_compute_functions(struct si_context
*sctx
);
551 void si_init_state_functions(struct si_context
*sctx
);
552 void si_init_screen_state_functions(struct si_screen
*sscreen
);
554 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
555 enum pipe_format format
,
556 unsigned offset
, unsigned size
,
558 struct pipe_sampler_view
*
559 si_create_sampler_view_custom(struct pipe_context
*ctx
,
560 struct pipe_resource
*texture
,
561 const struct pipe_sampler_view
*state
,
562 unsigned width0
, unsigned height0
,
563 unsigned force_level
);
564 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
);
565 void si_update_ps_iter_samples(struct si_context
*sctx
);
566 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
);
567 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
);
568 void si_set_occlusion_query_state(struct si_context
*sctx
,
569 bool old_perfect_enable
);
571 struct si_fast_udiv_info32
{
572 unsigned multiplier
; /* the "magic number" multiplier */
573 unsigned pre_shift
; /* shift for the dividend before multiplying */
574 unsigned post_shift
; /* shift for the dividend after multiplying */
575 int increment
; /* 0 or 1; if set then increment the numerator, using one of
576 the two strategies */
579 struct si_fast_udiv_info32
580 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
);
582 /* si_state_binning.c */
583 void si_emit_dpbb_state(struct si_context
*sctx
);
585 /* si_state_shaders.c */
586 void *si_get_ir_binary(struct si_shader_selector
*sel
, bool ngg
, bool es
);
587 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
588 struct si_shader
*shader
);
589 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
590 struct si_shader
*shader
,
591 bool insert_into_disk_cache
);
592 bool si_update_shaders(struct si_context
*sctx
);
593 void si_init_shader_functions(struct si_context
*sctx
);
594 bool si_init_shader_cache(struct si_screen
*sscreen
);
595 void si_destroy_shader_cache(struct si_screen
*sscreen
);
596 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
597 struct util_queue_fence
*ready_fence
,
598 struct si_compiler_ctx_state
*compiler_ctx_state
,
599 void *job
, util_queue_execute_func execute
);
600 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
601 uint32_t *const_and_shader_buffers
,
602 uint64_t *samplers_and_images
);
603 int si_shader_select_with_key(struct si_screen
*sscreen
,
604 struct si_shader_ctx_state
*state
,
605 struct si_compiler_ctx_state
*compiler_state
,
606 struct si_shader_key
*key
,
608 bool optimized_or_none
);
609 void si_shader_selector_key_vs(struct si_context
*sctx
,
610 struct si_shader_selector
*vs
,
611 struct si_shader_key
*key
,
612 struct si_vs_prolog_bits
*prolog_key
);
613 unsigned si_get_input_prim(const struct si_shader_selector
*gs
);
614 bool si_update_ngg(struct si_context
*sctx
);
616 /* si_state_draw.c */
617 void si_emit_surface_sync(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
618 unsigned cp_coher_cntl
);
619 void si_prim_discard_signal_next_compute_ib_start(struct si_context
*sctx
);
620 void gfx10_emit_cache_flush(struct si_context
*sctx
);
621 void si_emit_cache_flush(struct si_context
*sctx
);
622 void si_trace_emit(struct si_context
*sctx
);
623 void si_init_draw_functions(struct si_context
*sctx
);
625 /* si_state_msaa.c */
626 void si_init_msaa_functions(struct si_context
*sctx
);
627 void si_emit_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
629 /* si_state_streamout.c */
630 void si_streamout_buffers_dirty(struct si_context
*sctx
);
631 void si_emit_streamout_end(struct si_context
*sctx
);
632 void si_update_prims_generated_query_state(struct si_context
*sctx
,
633 unsigned type
, int diff
);
634 void si_init_streamout_functions(struct si_context
*sctx
);
637 static inline unsigned si_get_constbuf_slot(unsigned slot
)
639 /* Constant buffers are in slots [16..31], ascending */
640 return SI_NUM_SHADER_BUFFERS
+ slot
;
643 static inline unsigned si_get_shaderbuf_slot(unsigned slot
)
645 /* shader buffers are in slots [15..0], descending */
646 return SI_NUM_SHADER_BUFFERS
- 1 - slot
;
649 static inline unsigned si_get_sampler_slot(unsigned slot
)
651 /* 32 samplers are in sampler slots [16..47], 16 dw per slot, ascending */
652 /* those are equivalent to image slots [32..95], 8 dw per slot, ascending */
653 return SI_NUM_IMAGE_SLOTS
/ 2 + slot
;
656 static inline unsigned si_get_image_slot(unsigned slot
)
658 /* image slots are in [31..0] (sampler slots [15..0]), descending */
659 /* images are in slots [31..16], while FMASKs are in slots [15..0] */
660 return SI_NUM_IMAGE_SLOTS
- 1 - slot
;