src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_MAX_ATTRIBS 16
  35
  36 struct si_screen;
  37 struct si_shader;
  38
  39 struct si_state_blend {
  40         struct si_pm4_state     pm4;
  41         uint32_t                cb_target_mask;
  42         bool                    alpha_to_coverage;
  43         bool                    alpha_to_one;
  44         bool                    dual_src_blend;
  45         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  46          * true. ANDed with spi_shader_col_format.
  47          */
  48         unsigned                blend_enable_4bit;
  49         unsigned                need_src_alpha_4bit;
  50 };
  51
  52 struct si_state_rasterizer {
  53         struct si_pm4_state     pm4;
  54         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  55         struct si_pm4_state     pm4_poly_offset[3];
  56         bool                    flatshade;
  57         bool                    two_side;
  58         bool                    multisample_enable;
  59         bool                    force_persample_interp;
  60         bool                    line_stipple_enable;
  61         unsigned                sprite_coord_enable;
  62         unsigned                pa_sc_line_stipple;
  63         unsigned                pa_cl_clip_cntl;
  64         unsigned                clip_plane_enable;
  65         bool                    poly_stipple_enable;
  66         bool                    line_smooth;
  67         bool                    poly_smooth;
  68         bool                    uses_poly_offset;
  69         bool                    clamp_fragment_color;
  70         bool                    rasterizer_discard;
  71 };
  72
  73 struct si_dsa_stencil_ref_part {
  74         uint8_t                 valuemask[2];
  75         uint8_t                 writemask[2];
  76 };
  77
  78 struct si_state_dsa {
  79         struct si_pm4_state             pm4;
  80         unsigned                        alpha_func;
  81         struct si_dsa_stencil_ref_part  stencil_ref;
  82 };
  83
  84 struct si_stencil_ref {
  85         struct r600_atom                atom;
  86         struct pipe_stencil_ref         state;
  87         struct si_dsa_stencil_ref_part  dsa_part;
  88 };
  89
  90 struct si_vertex_element
  91 {
  92         unsigned                        count;
  93         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
  94         uint32_t                        format_size[SI_MAX_ATTRIBS];
  95         struct pipe_vertex_element      elements[SI_MAX_ATTRIBS];
  96 };
  97
  98 union si_state {
  99         struct {
 100                 struct si_state_blend           *blend;
 101                 struct si_state_rasterizer      *rasterizer;
 102                 struct si_state_dsa             *dsa;
 103                 struct si_pm4_state             *poly_offset;
 104                 struct si_pm4_state             *ls;
 105                 struct si_pm4_state             *hs;
 106                 struct si_pm4_state             *es;
 107                 struct si_pm4_state             *gs;
 108                 struct si_pm4_state             *vgt_shader_config;
 109                 struct si_pm4_state             *vs;
 110                 struct si_pm4_state             *ps;
 111         } named;
 112         struct si_pm4_state     *array[0];
 113 };
 114
 115 union si_state_atoms {
 116         struct {
 117                 /* The order matters. */
 118                 struct r600_atom *cache_flush;
 119                 struct r600_atom *render_cond;
 120                 struct r600_atom *streamout_begin;
 121                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 122                 struct r600_atom *framebuffer;
 123                 struct r600_atom *msaa_sample_locs;
 124                 struct r600_atom *db_render_state;
 125                 struct r600_atom *msaa_config;
 126                 struct r600_atom *sample_mask;
 127                 struct r600_atom *cb_target_mask;
 128                 struct r600_atom *blend_color;
 129                 struct r600_atom *clip_regs;
 130                 struct r600_atom *clip_state;
 131                 struct r600_atom *shader_userdata;
 132                 struct r600_atom *scissors;
 133                 struct r600_atom *viewports;
 134                 struct r600_atom *stencil_ref;
 135                 struct r600_atom *spi_map;
 136                 struct r600_atom *spi_ps_input;
 137         } s;
 138         struct r600_atom *array[0];
 139 };
 140
 141 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 142
 143 struct si_shader_data {
 144         struct r600_atom        atom;
 145         uint32_t                sh_base[SI_NUM_SHADERS];
 146 };
 147
 148 #define SI_NUM_USER_SAMPLERS            16 /* AKA OpenGL textures units per shader */
 149 #define SI_POLY_STIPPLE_SAMPLER         SI_NUM_USER_SAMPLERS
 150 #define SI_NUM_SAMPLERS                 (SI_POLY_STIPPLE_SAMPLER + 1)
 151
 152 /* User sampler views:   0..15
 153  * Polygon stipple tex:  16
 154  * FMASK sampler views:  17..33 (no sampler states)
 155  */
 156 #define SI_FMASK_TEX_OFFSET             SI_NUM_SAMPLERS
 157 #define SI_NUM_SAMPLER_VIEWS            (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
 158 #define SI_NUM_SAMPLER_STATES           SI_NUM_SAMPLERS
 159
 160 /* User constant buffers:   0..15
 161  * Driver state constants:  16
 162  */
 163 #define SI_NUM_USER_CONST_BUFFERS       16
 164 #define SI_DRIVER_STATE_CONST_BUF       SI_NUM_USER_CONST_BUFFERS
 165 #define SI_NUM_CONST_BUFFERS            (SI_DRIVER_STATE_CONST_BUF + 1)
 166
 167 /* Read-write buffer slots.
 168  *
 169  * Ring buffers:        0..1
 170  * Streamout buffers:   2..5
 171  */
 172 #define SI_RING_TESS_FACTOR     0 /* for HS (TCS)  */
 173 #define SI_RING_ESGS            0 /* for ES, GS */
 174 #define SI_RING_GSVS            1 /* for GS, VS */
 175 #define SI_RING_GSVS_1          2 /* 1, 2, 3 for GS */
 176 #define SI_RING_GSVS_2          3
 177 #define SI_RING_GSVS_3          4
 178 #define SI_NUM_RING_BUFFERS     5
 179 #define SI_SO_BUF_OFFSET        SI_NUM_RING_BUFFERS
 180 #define SI_NUM_RW_BUFFERS       (SI_SO_BUF_OFFSET + 4)
 181
 182 #define SI_NUM_VERTEX_BUFFERS   SI_MAX_ATTRIBS
 183
 184
 185 /* This represents descriptors in memory, such as buffer resources,
 186  * image resources, and sampler states.
 187  */
 188 struct si_descriptors {
 189         /* The list of descriptors in malloc'd memory. */
 190         uint32_t *list;
 191         /* The size of one descriptor. */
 192         unsigned element_dw_size;
 193         /* The maximum number of descriptors. */
 194         unsigned num_elements;
 195         /* Whether the list has been changed and should be re-uploaded. */
 196         bool list_dirty;
 197
 198         /* The buffer where the descriptors have been uploaded. */
 199         struct r600_resource *buffer;
 200         unsigned buffer_offset;
 201
 202         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 203         uint64_t enabled_mask;
 204
 205         /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
 206          * array will be stored. */
 207         unsigned shader_userdata_offset;
 208         /* Whether the pointer should be re-emitted. */
 209         bool pointer_dirty;
 210 };
 211
 212 struct si_sampler_views {
 213         struct si_descriptors           desc;
 214         struct pipe_sampler_view        *views[SI_NUM_SAMPLER_VIEWS];
 215 };
 216
 217 struct si_sampler_states {
 218         struct si_descriptors           desc;
 219         void                            *saved_states[2]; /* saved for u_blitter */
 220 };
 221
 222 struct si_buffer_resources {
 223         struct si_descriptors           desc;
 224         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 225         enum radeon_bo_priority         priority;
 226         struct pipe_resource            **buffers; /* this has num_buffers elements */
 227 };
 228
 229 #define si_pm4_block_idx(member) \
 230         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 231
 232 #define si_pm4_state_changed(sctx, member) \
 233         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 234
 235 #define si_pm4_bind_state(sctx, member, value) \
 236         do { \
 237                 (sctx)->queued.named.member = (value); \
 238         } while(0)
 239
 240 #define si_pm4_delete_state(sctx, member, value) \
 241         do { \
 242                 if ((sctx)->queued.named.member == (value)) { \
 243                         (sctx)->queued.named.member = NULL; \
 244                 } \
 245                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 246                                   si_pm4_block_idx(member)); \
 247         } while(0)
 248
 249 /* si_descriptors.c */
 250 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 251                         struct pipe_resource *buffer,
 252                         unsigned stride, unsigned num_records,
 253                         bool add_tid, bool swizzle,
 254                         unsigned element_size, unsigned index_stride, uint64_t offset);
 255 void si_init_all_descriptors(struct si_context *sctx);
 256 bool si_upload_shader_descriptors(struct si_context *sctx);
 257 void si_release_all_descriptors(struct si_context *sctx);
 258 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 259 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 260                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 261 void si_shader_change_notify(struct si_context *sctx);
 262 void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom);
 263
 264 /* si_state.c */
 265 struct si_shader_selector;
 266
 267 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 268                   struct r600_atom **list_elem,
 269                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 270 boolean si_is_format_supported(struct pipe_screen *screen,
 271                                enum pipe_format format,
 272                                enum pipe_texture_target target,
 273                                unsigned sample_count,
 274                                unsigned usage);
 275 void si_init_state_functions(struct si_context *sctx);
 276 unsigned cik_bank_wh(unsigned bankwh);
 277 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 278 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 279 unsigned cik_tile_split(unsigned tile_split);
 280 unsigned si_array_mode(unsigned mode);
 281 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
 282 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 283 struct pipe_sampler_view *
 284 si_create_sampler_view_custom(struct pipe_context *ctx,
 285                               struct pipe_resource *texture,
 286                               const struct pipe_sampler_view *state,
 287                               unsigned width0, unsigned height0,
 288                               unsigned force_level);
 289
 290 /* si_state_shader.c */
 291 bool si_update_shaders(struct si_context *sctx);
 292 void si_init_shader_functions(struct si_context *sctx);
 293
 294 /* si_state_draw.c */
 295 void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
 296 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 297 void si_trace_emit(struct si_context *sctx);
 298
 299 #endif