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radeonsi: determine accurately if line stippling is enabled for performance
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 unsigned wave_size = sctx->screen->ge_wave_size;
187
188 if (temp_verts_per_tg > wave_size && temp_verts_per_tg % wave_size < wave_size*3/4)
189 *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch;
190
191 if (sctx->chip_class == GFX6) {
192 /* GFX6 bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
194 */
195 unsigned one_wave = wave_size / max_verts_per_patch;
196 *num_patches = MIN2(*num_patches, one_wave);
197 }
198
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
202 *
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on GFX6 when there is no other
207 * SE to switch to.
208 */
209 if (has_primid_instancing_bug && tess_uses_primid)
210 *num_patches = 1;
211
212 sctx->last_num_patches = *num_patches;
213
214 output_patch0_offset = input_patch_size * *num_patches;
215 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
216
217 /* Compute userdata SGPRs. */
218 assert(((input_vertex_size / 4) & ~0xff) == 0);
219 assert(((output_vertex_size / 4) & ~0xff) == 0);
220 assert(((input_patch_size / 4) & ~0x1fff) == 0);
221 assert(((output_patch_size / 4) & ~0x1fff) == 0);
222 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
223 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
224 assert(num_tcs_input_cp <= 32);
225 assert(num_tcs_output_cp <= 32);
226
227 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
228 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
229
230 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
231 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
232 tcs_out_layout = (output_patch_size / 4) |
233 (num_tcs_input_cp << 13) |
234 ring_va;
235 tcs_out_offsets = (output_patch0_offset / 16) |
236 ((perpatch_output_offset / 16) << 16);
237 offchip_layout = *num_patches |
238 (num_tcs_output_cp << 6) |
239 (pervertex_output_patch_size * *num_patches << 12);
240
241 /* Compute the LDS size. */
242 lds_size = output_patch0_offset + output_patch_size * *num_patches;
243
244 if (sctx->chip_class >= GFX7) {
245 assert(lds_size <= 65536);
246 lds_size = align(lds_size, 512) / 512;
247 } else {
248 assert(lds_size <= 32768);
249 lds_size = align(lds_size, 256) / 256;
250 }
251
252 /* Set SI_SGPR_VS_STATE_BITS. */
253 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
254 C_VS_STATE_LS_OUT_VERTEX_SIZE;
255 sctx->current_vs_state |= tcs_in_layout;
256
257 /* We should be able to support in-shader LDS use with LLVM >= 9
258 * by just adding the lds_sizes together, but it has never
259 * been tested. */
260 assert(ls_current->config.lds_size == 0);
261
262 if (sctx->chip_class >= GFX9) {
263 unsigned hs_rsrc2 = ls_current->config.rsrc2;
264
265 if (sctx->chip_class >= GFX10)
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
267 else
268 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
269
270 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
271
272 /* Set userdata SGPRs for merged LS-HS. */
273 radeon_set_sh_reg_seq(cs,
274 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
275 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
276 radeon_emit(cs, offchip_layout);
277 radeon_emit(cs, tcs_out_offsets);
278 radeon_emit(cs, tcs_out_layout);
279 } else {
280 unsigned ls_rsrc2 = ls_current->config.rsrc2;
281
282 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
283 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
284
285 /* Due to a hw bug, RSRC2_LS must be written twice with another
286 * LS register written in between. */
287 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
288 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
289 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
290 radeon_emit(cs, ls_current->config.rsrc1);
291 radeon_emit(cs, ls_rsrc2);
292
293 /* Set userdata SGPRs for TCS. */
294 radeon_set_sh_reg_seq(cs,
295 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
296 radeon_emit(cs, offchip_layout);
297 radeon_emit(cs, tcs_out_offsets);
298 radeon_emit(cs, tcs_out_layout);
299 radeon_emit(cs, tcs_in_layout);
300 }
301
302 /* Set userdata SGPRs for TES. */
303 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
304 radeon_emit(cs, offchip_layout);
305 radeon_emit(cs, ring_va);
306
307 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
308 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
309 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
310
311 if (sctx->last_ls_hs_config != ls_hs_config) {
312 if (sctx->chip_class >= GFX7) {
313 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
314 ls_hs_config);
315 } else {
316 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
317 ls_hs_config);
318 }
319 sctx->last_ls_hs_config = ls_hs_config;
320 sctx->context_roll = true;
321 }
322 }
323
324 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
325 enum pipe_prim_type prim)
326 {
327 switch (prim) {
328 case PIPE_PRIM_PATCHES:
329 return info->count / info->vertices_per_patch;
330 case PIPE_PRIM_POLYGON:
331 return info->count >= 3;
332 case SI_PRIM_RECTANGLE_LIST:
333 return info->count / 3;
334 default:
335 return u_decomposed_prims_for_vertices(prim, info->count);
336 }
337 }
338
339 static unsigned
340 si_get_init_multi_vgt_param(struct si_screen *sscreen,
341 union si_vgt_param_key *key)
342 {
343 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
344 unsigned max_primgroup_in_wave = 2;
345
346 /* SWITCH_ON_EOP(0) is always preferable. */
347 bool wd_switch_on_eop = false;
348 bool ia_switch_on_eop = false;
349 bool ia_switch_on_eoi = false;
350 bool partial_vs_wave = false;
351 bool partial_es_wave = false;
352
353 if (key->u.uses_tess) {
354 /* SWITCH_ON_EOI must be set if PrimID is used. */
355 if (key->u.tess_uses_prim_id)
356 ia_switch_on_eoi = true;
357
358 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
359 if ((sscreen->info.family == CHIP_TAHITI ||
360 sscreen->info.family == CHIP_PITCAIRN ||
361 sscreen->info.family == CHIP_BONAIRE) &&
362 key->u.uses_gs)
363 partial_vs_wave = true;
364
365 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
366 if (sscreen->info.has_distributed_tess) {
367 if (key->u.uses_gs) {
368 if (sscreen->info.chip_class == GFX8)
369 partial_es_wave = true;
370 } else {
371 partial_vs_wave = true;
372 }
373 }
374 }
375
376 /* This is a hardware requirement. */
377 if (key->u.line_stipple_enabled ||
378 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
379 ia_switch_on_eop = true;
380 wd_switch_on_eop = true;
381 }
382
383 if (sscreen->info.chip_class >= GFX7) {
384 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
385 * 4 shader engines. Set 1 to pass the assertion below.
386 * The other cases are hardware requirements.
387 *
388 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
389 * for points, line strips, and tri strips.
390 */
391 if (sscreen->info.max_se <= 2 ||
392 key->u.prim == PIPE_PRIM_POLYGON ||
393 key->u.prim == PIPE_PRIM_LINE_LOOP ||
394 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
395 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
396 (key->u.primitive_restart &&
397 (sscreen->info.family < CHIP_POLARIS10 ||
398 (key->u.prim != PIPE_PRIM_POINTS &&
399 key->u.prim != PIPE_PRIM_LINE_STRIP &&
400 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
401 key->u.count_from_stream_output)
402 wd_switch_on_eop = true;
403
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sscreen->info.family == CHIP_HAWAII &&
408 key->u.uses_instancing)
409 wd_switch_on_eop = true;
410
411 /* Performance recommendation for 4 SE Gfx7-8 parts if
412 * instances are smaller than a primgroup.
413 * Assume indirect draws always use small instances.
414 * This is needed for good VS wave utilization.
415 */
416 if (sscreen->info.chip_class <= GFX8 &&
417 sscreen->info.max_se == 4 &&
418 key->u.multi_instances_smaller_than_primgroup)
419 wd_switch_on_eop = true;
420
421 /* Required on GFX7 and later. */
422 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
423 ia_switch_on_eoi = true;
424
425 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
426 * to work around a GS hang.
427 */
428 if (key->u.uses_gs &&
429 (sscreen->info.family == CHIP_TONGA ||
430 sscreen->info.family == CHIP_FIJI ||
431 sscreen->info.family == CHIP_POLARIS10 ||
432 sscreen->info.family == CHIP_POLARIS11 ||
433 sscreen->info.family == CHIP_POLARIS12 ||
434 sscreen->info.family == CHIP_VEGAM))
435 partial_vs_wave = true;
436
437 /* Required by Hawaii and, for some special cases, by GFX8. */
438 if (ia_switch_on_eoi &&
439 (sscreen->info.family == CHIP_HAWAII ||
440 (sscreen->info.chip_class == GFX8 &&
441 (key->u.uses_gs || max_primgroup_in_wave != 2))))
442 partial_vs_wave = true;
443
444 /* Instancing bug on Bonaire. */
445 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
446 key->u.uses_instancing)
447 partial_vs_wave = true;
448
449 /* This only applies to Polaris10 and later 4 SE chips.
450 * wd_switch_on_eop is already true on all other chips.
451 */
452 if (!wd_switch_on_eop && key->u.primitive_restart)
453 partial_vs_wave = true;
454
455 /* If the WD switch is false, the IA switch must be false too. */
456 assert(wd_switch_on_eop || !ia_switch_on_eop);
457 }
458
459 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
460 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
461 partial_es_wave = true;
462
463 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
464 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
465 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
466 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
467 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
468 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
469 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
470 max_primgroup_in_wave : 0) |
471 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
472 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
473 }
474
475 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
476 {
477 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
478 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
479 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
480 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
481 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
482 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
483 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
484 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
485 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
486 union si_vgt_param_key key;
487
488 key.index = 0;
489 key.u.prim = prim;
490 key.u.uses_instancing = uses_instancing;
491 key.u.multi_instances_smaller_than_primgroup = multi_instances;
492 key.u.primitive_restart = primitive_restart;
493 key.u.count_from_stream_output = count_from_so;
494 key.u.line_stipple_enabled = line_stipple;
495 key.u.uses_tess = uses_tess;
496 key.u.tess_uses_prim_id = tess_uses_primid;
497 key.u.uses_gs = uses_gs;
498
499 sctx->ia_multi_vgt_param[key.index] =
500 si_get_init_multi_vgt_param(sctx->screen, &key);
501 }
502 }
503
504 static bool si_is_line_stipple_enabled(struct si_context *sctx)
505 {
506 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
507
508 return rs->line_stipple_enable &&
509 sctx->current_rast_prim != PIPE_PRIM_POINTS &&
510 (rs->polygon_mode_is_lines ||
511 util_prim_is_lines(sctx->current_rast_prim));
512 }
513
514 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
515 const struct pipe_draw_info *info,
516 enum pipe_prim_type prim,
517 unsigned num_patches,
518 unsigned instance_count,
519 bool primitive_restart)
520 {
521 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
522 unsigned primgroup_size;
523 unsigned ia_multi_vgt_param;
524
525 if (sctx->tes_shader.cso) {
526 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
527 } else if (sctx->gs_shader.cso) {
528 primgroup_size = 64; /* recommended with a GS */
529 } else {
530 primgroup_size = 128; /* recommended without a GS and tess */
531 }
532
533 key.u.prim = prim;
534 key.u.uses_instancing = info->indirect || instance_count > 1;
535 key.u.multi_instances_smaller_than_primgroup =
536 info->indirect ||
537 (instance_count > 1 &&
538 (info->count_from_stream_output ||
539 si_num_prims_for_vertices(info, prim) < primgroup_size));
540 key.u.primitive_restart = primitive_restart;
541 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
542 key.u.line_stipple_enabled = si_is_line_stipple_enabled(sctx);
543
544 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
545 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
546
547 if (sctx->gs_shader.cso) {
548 /* GS requirement. */
549 if (sctx->chip_class <= GFX8 &&
550 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
551 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
552
553 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
554 * The hw doc says all multi-SE chips are affected, but Vulkan
555 * only applies it to Hawaii. Do what Vulkan does.
556 */
557 if (sctx->family == CHIP_HAWAII &&
558 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
559 (info->indirect ||
560 (instance_count > 1 &&
561 (info->count_from_stream_output ||
562 si_num_prims_for_vertices(info, prim) <= 1))))
563 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
564 }
565
566 return ia_multi_vgt_param;
567 }
568
569 static unsigned si_conv_prim_to_gs_out(unsigned mode)
570 {
571 static const int prim_conv[] = {
572 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
573 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
574 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
575 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
576 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
577 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
578 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
579 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
580 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
581 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
582 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
583 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
584 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
585 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
586 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
587 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
588 };
589 assert(mode < ARRAY_SIZE(prim_conv));
590
591 return prim_conv[mode];
592 }
593
594 /* rast_prim is the primitive type after GS. */
595 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
596 {
597 struct radeon_cmdbuf *cs = sctx->gfx_cs;
598 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
599 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
600 bool use_ngg = sctx->screen->use_ngg;
601
602 if (likely(rast_prim == sctx->last_rast_prim &&
603 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
604 (!use_ngg ||
605 rs->flatshade_first == sctx->last_flatshade_first)))
606 return;
607
608 if (util_prim_is_lines(rast_prim)) {
609 /* For lines, reset the stipple pattern at each primitive. Otherwise,
610 * reset the stipple pattern at each packet (line strips, line loops).
611 */
612 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
613 rs->pa_sc_line_stipple |
614 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
615 sctx->context_roll = true;
616 }
617
618 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
619
620 if (rast_prim != sctx->last_rast_prim &&
621 (sctx->ngg || sctx->gs_shader.cso)) {
622 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
623 sctx->context_roll = true;
624
625 if (use_ngg) {
626 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
627 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
628 }
629 }
630
631 if (use_ngg) {
632 unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
633 sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
634 sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
635 }
636
637 sctx->last_rast_prim = rast_prim;
638 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
639 sctx->last_flatshade_first = rs->flatshade_first;
640 }
641
642 static void si_emit_vs_state(struct si_context *sctx,
643 const struct pipe_draw_info *info)
644 {
645 sctx->current_vs_state &= C_VS_STATE_INDEXED;
646 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
647
648 if (sctx->num_vs_blit_sgprs) {
649 /* Re-emit the state after we leave u_blitter. */
650 sctx->last_vs_state = ~0;
651 return;
652 }
653
654 if (sctx->current_vs_state != sctx->last_vs_state) {
655 struct radeon_cmdbuf *cs = sctx->gfx_cs;
656
657 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
658 radeon_set_sh_reg(cs,
659 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
660 SI_SGPR_VS_STATE_BITS * 4,
661 sctx->current_vs_state);
662
663 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
664 * before the rasterizer.
665 *
666 * For TES or the GS copy shader without NGG:
667 */
668 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
669 R_00B130_SPI_SHADER_USER_DATA_VS_0) {
670 radeon_set_sh_reg(cs,
671 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
672 SI_SGPR_VS_STATE_BITS * 4,
673 sctx->current_vs_state);
674 }
675
676 /* For NGG: */
677 if (sctx->screen->use_ngg &&
678 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
679 R_00B230_SPI_SHADER_USER_DATA_GS_0) {
680 radeon_set_sh_reg(cs,
681 R_00B230_SPI_SHADER_USER_DATA_GS_0 +
682 SI_SGPR_VS_STATE_BITS * 4,
683 sctx->current_vs_state);
684 }
685
686 sctx->last_vs_state = sctx->current_vs_state;
687 }
688 }
689
690 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
691 bool primitive_restart,
692 unsigned restart_index)
693 {
694 return primitive_restart &&
695 (restart_index != sctx->last_restart_index ||
696 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
697 }
698
699 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
700 const struct pipe_draw_info *info,
701 enum pipe_prim_type prim,
702 unsigned num_patches,
703 unsigned instance_count,
704 bool primitive_restart)
705 {
706 struct radeon_cmdbuf *cs = sctx->gfx_cs;
707 unsigned ia_multi_vgt_param;
708
709 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
710 instance_count, primitive_restart);
711
712 /* Draw state. */
713 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
714 if (sctx->chip_class == GFX9)
715 radeon_set_uconfig_reg_idx(cs, sctx->screen,
716 R_030960_IA_MULTI_VGT_PARAM, 4,
717 ia_multi_vgt_param);
718 else if (sctx->chip_class >= GFX7)
719 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
720 else
721 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
722
723 sctx->last_multi_vgt_param = ia_multi_vgt_param;
724 }
725 }
726
727 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
728 * We overload last_multi_vgt_param.
729 */
730 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
731 {
732 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
733 unsigned ge_cntl;
734
735 if (sctx->ngg) {
736 if (sctx->tes_shader.cso) {
737 ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) |
738 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
739 S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
740 } else {
741 ge_cntl = si_get_vs_state(sctx)->ge_cntl;
742 }
743 } else {
744 unsigned primgroup_size;
745 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */;
746
747 if (sctx->tes_shader.cso) {
748 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
749 } else if (sctx->gs_shader.cso) {
750 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
751 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
752 } else {
753 primgroup_size = 128; /* recommended without a GS and tess */
754 }
755
756 ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
757 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
758 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
759 }
760
761 ge_cntl |= S_03096C_PACKET_TO_ONE_PA(si_is_line_stipple_enabled(sctx));
762
763 if (ge_cntl != sctx->last_multi_vgt_param) {
764 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
765 sctx->last_multi_vgt_param = ge_cntl;
766 }
767 }
768
769 static void si_emit_draw_registers(struct si_context *sctx,
770 const struct pipe_draw_info *info,
771 enum pipe_prim_type prim,
772 unsigned num_patches,
773 unsigned instance_count,
774 bool primitive_restart)
775 {
776 struct radeon_cmdbuf *cs = sctx->gfx_cs;
777 unsigned vgt_prim = si_conv_pipe_prim(prim);
778
779 if (sctx->chip_class >= GFX10)
780 gfx10_emit_ge_cntl(sctx, num_patches);
781 else
782 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
783 instance_count, primitive_restart);
784
785 if (vgt_prim != sctx->last_prim) {
786 if (sctx->chip_class >= GFX10)
787 radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
788 else if (sctx->chip_class >= GFX7)
789 radeon_set_uconfig_reg_idx(cs, sctx->screen,
790 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
791 else
792 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
793
794 sctx->last_prim = vgt_prim;
795 }
796
797 /* Primitive restart. */
798 if (primitive_restart != sctx->last_primitive_restart_en) {
799 if (sctx->chip_class >= GFX9)
800 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
801 primitive_restart);
802 else
803 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
804 primitive_restart);
805
806 sctx->last_primitive_restart_en = primitive_restart;
807
808 }
809 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
810 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
811 info->restart_index);
812 sctx->last_restart_index = info->restart_index;
813 sctx->context_roll = true;
814 }
815 }
816
817 static void si_emit_draw_packets(struct si_context *sctx,
818 const struct pipe_draw_info *info,
819 struct pipe_resource *indexbuf,
820 unsigned index_size,
821 unsigned index_offset,
822 unsigned instance_count,
823 bool dispatch_prim_discard_cs,
824 unsigned original_index_size)
825 {
826 struct pipe_draw_indirect_info *indirect = info->indirect;
827 struct radeon_cmdbuf *cs = sctx->gfx_cs;
828 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
829 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
830 uint32_t index_max_size = 0;
831 uint64_t index_va = 0;
832
833 if (info->count_from_stream_output) {
834 struct si_streamout_target *t =
835 (struct si_streamout_target*)info->count_from_stream_output;
836
837 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
838 t->stride_in_dw);
839 si_cp_copy_data(sctx, sctx->gfx_cs,
840 COPY_DATA_REG, NULL,
841 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
842 COPY_DATA_SRC_MEM, t->buf_filled_size,
843 t->buf_filled_size_offset);
844 }
845
846 /* draw packet */
847 if (index_size) {
848 if (index_size != sctx->last_index_size) {
849 unsigned index_type;
850
851 /* index type */
852 switch (index_size) {
853 case 1:
854 index_type = V_028A7C_VGT_INDEX_8;
855 break;
856 case 2:
857 index_type = V_028A7C_VGT_INDEX_16 |
858 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
859 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
860 break;
861 case 4:
862 index_type = V_028A7C_VGT_INDEX_32 |
863 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
864 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
865 break;
866 default:
867 assert(!"unreachable");
868 return;
869 }
870
871 if (sctx->chip_class >= GFX9) {
872 radeon_set_uconfig_reg_idx(cs, sctx->screen,
873 R_03090C_VGT_INDEX_TYPE, 2,
874 index_type);
875 } else {
876 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
877 radeon_emit(cs, index_type);
878 }
879
880 sctx->last_index_size = index_size;
881 }
882
883 if (original_index_size) {
884 index_max_size = (indexbuf->width0 - index_offset) /
885 original_index_size;
886 /* Skip draw calls with 0-sized index buffers.
887 * They cause a hang on some chips, like Navi10-14.
888 */
889 if (!index_max_size)
890 return;
891
892 index_va = si_resource(indexbuf)->gpu_address + index_offset;
893
894 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
895 si_resource(indexbuf),
896 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
897 }
898 } else {
899 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
900 * so the state must be re-emitted before the next indexed draw.
901 */
902 if (sctx->chip_class >= GFX7)
903 sctx->last_index_size = -1;
904 }
905
906 if (indirect) {
907 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
908
909 assert(indirect_va % 8 == 0);
910
911 si_invalidate_draw_sh_constants(sctx);
912
913 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
914 radeon_emit(cs, 1);
915 radeon_emit(cs, indirect_va);
916 radeon_emit(cs, indirect_va >> 32);
917
918 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
919 si_resource(indirect->buffer),
920 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
921
922 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
923 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
924
925 assert(indirect->offset % 4 == 0);
926
927 if (index_size) {
928 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
929 radeon_emit(cs, index_va);
930 radeon_emit(cs, index_va >> 32);
931
932 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
933 radeon_emit(cs, index_max_size);
934 }
935
936 if (!sctx->screen->has_draw_indirect_multi) {
937 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
938 : PKT3_DRAW_INDIRECT,
939 3, render_cond_bit));
940 radeon_emit(cs, indirect->offset);
941 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
942 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
943 radeon_emit(cs, di_src_sel);
944 } else {
945 uint64_t count_va = 0;
946
947 if (indirect->indirect_draw_count) {
948 struct si_resource *params_buf =
949 si_resource(indirect->indirect_draw_count);
950
951 radeon_add_to_buffer_list(
952 sctx, sctx->gfx_cs, params_buf,
953 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
954
955 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
956 }
957
958 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
959 PKT3_DRAW_INDIRECT_MULTI,
960 8, render_cond_bit));
961 radeon_emit(cs, indirect->offset);
962 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
963 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
964 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
965 S_2C3_DRAW_INDEX_ENABLE(1) |
966 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
967 radeon_emit(cs, indirect->draw_count);
968 radeon_emit(cs, count_va);
969 radeon_emit(cs, count_va >> 32);
970 radeon_emit(cs, indirect->stride);
971 radeon_emit(cs, di_src_sel);
972 }
973 } else {
974 int base_vertex;
975
976 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
977 sctx->last_instance_count != instance_count) {
978 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
979 radeon_emit(cs, instance_count);
980 sctx->last_instance_count = instance_count;
981 }
982
983 /* Base vertex and start instance. */
984 base_vertex = original_index_size ? info->index_bias : info->start;
985
986 if (sctx->num_vs_blit_sgprs) {
987 /* Re-emit draw constants after we leave u_blitter. */
988 si_invalidate_draw_sh_constants(sctx);
989
990 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
991 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
992 sctx->num_vs_blit_sgprs);
993 radeon_emit_array(cs, sctx->vs_blit_sh_data,
994 sctx->num_vs_blit_sgprs);
995 } else if (base_vertex != sctx->last_base_vertex ||
996 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
997 info->start_instance != sctx->last_start_instance ||
998 info->drawid != sctx->last_drawid ||
999 sh_base_reg != sctx->last_sh_base_reg) {
1000 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
1001 radeon_emit(cs, base_vertex);
1002 radeon_emit(cs, info->start_instance);
1003 radeon_emit(cs, info->drawid);
1004
1005 sctx->last_base_vertex = base_vertex;
1006 sctx->last_start_instance = info->start_instance;
1007 sctx->last_drawid = info->drawid;
1008 sctx->last_sh_base_reg = sh_base_reg;
1009 }
1010
1011 if (index_size) {
1012 if (dispatch_prim_discard_cs) {
1013 index_va += info->start * original_index_size;
1014 index_max_size = MIN2(index_max_size, info->count);
1015
1016 si_dispatch_prim_discard_cs_and_draw(sctx, info,
1017 original_index_size,
1018 base_vertex,
1019 index_va, index_max_size);
1020 return;
1021 }
1022
1023 index_va += info->start * index_size;
1024
1025 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1026 radeon_emit(cs, index_max_size);
1027 radeon_emit(cs, index_va);
1028 radeon_emit(cs, index_va >> 32);
1029 radeon_emit(cs, info->count);
1030 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
1031 } else {
1032 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1033 radeon_emit(cs, info->count);
1034 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1035 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
1036 }
1037 }
1038 }
1039
1040 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1041 unsigned cp_coher_cntl)
1042 {
1043 bool compute_ib = !sctx->has_graphics ||
1044 cs == sctx->prim_discard_compute_cs;
1045
1046 assert(sctx->chip_class <= GFX9);
1047
1048 if (sctx->chip_class == GFX9 || compute_ib) {
1049 /* Flush caches and wait for the caches to assert idle. */
1050 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
1051 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1052 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1053 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1054 radeon_emit(cs, 0); /* CP_COHER_BASE */
1055 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1056 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1057 } else {
1058 /* ACQUIRE_MEM is only required on a compute ring. */
1059 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1060 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1061 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1062 radeon_emit(cs, 0); /* CP_COHER_BASE */
1063 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1064 }
1065
1066 /* ACQUIRE_MEM has an implicit context roll if the current context
1067 * is busy. */
1068 if (!compute_ib)
1069 sctx->context_roll = true;
1070 }
1071
1072 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1073 {
1074 if (!si_compute_prim_discard_enabled(sctx))
1075 return;
1076
1077 if (!sctx->barrier_buf) {
1078 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1079 &sctx->barrier_buf_offset,
1080 (struct pipe_resource**)&sctx->barrier_buf);
1081 }
1082
1083 /* Emit a placeholder to signal the next compute IB to start.
1084 * See si_compute_prim_discard.c for explanation.
1085 */
1086 uint32_t signal = 1;
1087 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1088 4, V_370_MEM, V_370_ME, &signal);
1089
1090 sctx->last_pkt3_write_data =
1091 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1092
1093 /* Only the last occurence of WRITE_DATA will be executed.
1094 * The packet will be enabled in si_flush_gfx_cs.
1095 */
1096 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1097 }
1098
1099 void gfx10_emit_cache_flush(struct si_context *ctx)
1100 {
1101 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1102 uint32_t gcr_cntl = 0;
1103 unsigned cb_db_event = 0;
1104 unsigned flags = ctx->flags;
1105
1106 if (!ctx->has_graphics) {
1107 /* Only process compute flags. */
1108 flags &= SI_CONTEXT_INV_ICACHE |
1109 SI_CONTEXT_INV_SCACHE |
1110 SI_CONTEXT_INV_VCACHE |
1111 SI_CONTEXT_INV_L2 |
1112 SI_CONTEXT_WB_L2 |
1113 SI_CONTEXT_INV_L2_METADATA |
1114 SI_CONTEXT_CS_PARTIAL_FLUSH;
1115 }
1116
1117 /* We don't need these. */
1118 assert(!(flags & (SI_CONTEXT_VGT_STREAMOUT_SYNC |
1119 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1120
1121 if (flags & SI_CONTEXT_VGT_FLUSH) {
1122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1123 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1124 }
1125
1126 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1127 ctx->num_cb_cache_flushes++;
1128 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1129 ctx->num_db_cache_flushes++;
1130
1131 if (flags & SI_CONTEXT_INV_ICACHE)
1132 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1133 if (flags & SI_CONTEXT_INV_SCACHE) {
1134 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1135 * to FORWARD when both L1 and L2 are written out (WB or INV).
1136 */
1137 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1138 }
1139 if (flags & SI_CONTEXT_INV_VCACHE)
1140 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1141
1142 /* The L2 cache ops are:
1143 * - INV: - invalidate lines that reflect memory (were loaded from memory)
1144 * - don't touch lines that were overwritten (were stored by gfx clients)
1145 * - WB: - don't touch lines that reflect memory
1146 * - write back lines that were overwritten
1147 * - WB | INV: - invalidate lines that reflect memory
1148 * - write back lines that were overwritten
1149 *
1150 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1151 */
1152 if (flags & SI_CONTEXT_INV_L2) {
1153 /* Writeback and invalidate everything in L2. */
1154 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1155 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1156 ctx->num_L2_invalidates++;
1157 } else if (flags & SI_CONTEXT_WB_L2) {
1158 gcr_cntl |= S_586_GL2_WB(1) |
1159 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1160 } else if (flags & SI_CONTEXT_INV_L2_METADATA) {
1161 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1162 }
1163
1164 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1165 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1166 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1167 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1168 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1169 EVENT_INDEX(0));
1170 }
1171 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1172 /* Flush HTILE. Will wait for idle later. */
1173 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1174 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1175 EVENT_INDEX(0));
1176 }
1177
1178 /* First flush CB/DB, then L1/L2. */
1179 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1180
1181 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1182 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1183 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1184 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1185 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1186 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1187 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1188 } else {
1189 assert(0);
1190 }
1191 } else {
1192 /* Wait for graphics shaders to go idle if requested. */
1193 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1194 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1195 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1196 /* Only count explicit shader flushes, not implicit ones. */
1197 ctx->num_vs_flushes++;
1198 ctx->num_ps_flushes++;
1199 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1200 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1201 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1202 ctx->num_vs_flushes++;
1203 }
1204 }
1205
1206 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1207 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1208 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1209 ctx->num_cs_flushes++;
1210 ctx->compute_is_busy = false;
1211 }
1212
1213 if (cb_db_event) {
1214 /* CB/DB flush and invalidate (or possibly just a wait for a
1215 * meta flush) via RELEASE_MEM.
1216 *
1217 * Combine this with other cache flushes when possible; this
1218 * requires affected shaders to be idle, so do it after the
1219 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1220 * implied).
1221 */
1222 uint64_t va;
1223
1224 /* Do the flush (enqueue the event and wait for it). */
1225 va = ctx->wait_mem_scratch->gpu_address;
1226 ctx->wait_mem_number++;
1227
1228 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1229 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1230 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1231 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1232 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1233 assert(G_586_GL2_US(gcr_cntl) == 0);
1234 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1235 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1236 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1237 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1238 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1239
1240 gcr_cntl &= C_586_GLM_WB &
1241 C_586_GLM_INV &
1242 C_586_GLV_INV &
1243 C_586_GL1_INV &
1244 C_586_GL2_INV &
1245 C_586_GL2_WB; /* keep SEQ */
1246
1247 si_cp_release_mem(ctx, cs, cb_db_event,
1248 S_490_GLM_WB(glm_wb) |
1249 S_490_GLM_INV(glm_inv) |
1250 S_490_GLV_INV(glv_inv) |
1251 S_490_GL1_INV(gl1_inv) |
1252 S_490_GL2_INV(gl2_inv) |
1253 S_490_GL2_WB(gl2_wb) |
1254 S_490_SEQ(gcr_seq),
1255 EOP_DST_SEL_MEM,
1256 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1257 EOP_DATA_SEL_VALUE_32BIT,
1258 ctx->wait_mem_scratch, va,
1259 ctx->wait_mem_number, SI_NOT_QUERY);
1260 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1261 WAIT_REG_MEM_EQUAL);
1262 }
1263
1264 /* Ignore fields that only modify the behavior of other fields. */
1265 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1266 /* Flush caches and wait for the caches to assert idle.
1267 * The cache flush is executed in the ME, but the PFP waits
1268 * for completion.
1269 */
1270 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1271 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1272 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1273 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1274 radeon_emit(cs, 0); /* CP_COHER_BASE */
1275 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1276 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1277 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1278 } else if (cb_db_event ||
1279 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1280 SI_CONTEXT_PS_PARTIAL_FLUSH |
1281 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1282 /* We need to ensure that PFP waits as well. */
1283 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1284 radeon_emit(cs, 0);
1285 }
1286
1287 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1288 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1289 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1290 EVENT_INDEX(0));
1291 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1292 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1293 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1294 EVENT_INDEX(0));
1295 }
1296
1297 ctx->flags = 0;
1298 }
1299
1300 void si_emit_cache_flush(struct si_context *sctx)
1301 {
1302 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1303 uint32_t flags = sctx->flags;
1304
1305 if (!sctx->has_graphics) {
1306 /* Only process compute flags. */
1307 flags &= SI_CONTEXT_INV_ICACHE |
1308 SI_CONTEXT_INV_SCACHE |
1309 SI_CONTEXT_INV_VCACHE |
1310 SI_CONTEXT_INV_L2 |
1311 SI_CONTEXT_WB_L2 |
1312 SI_CONTEXT_INV_L2_METADATA |
1313 SI_CONTEXT_CS_PARTIAL_FLUSH;
1314 }
1315
1316 uint32_t cp_coher_cntl = 0;
1317 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1318 SI_CONTEXT_FLUSH_AND_INV_DB);
1319 const bool is_barrier = flush_cb_db ||
1320 /* INV_ICACHE == beginning of gfx IB. Checking
1321 * INV_ICACHE fixes corruption for DeusExMD with
1322 * compute-based culling, but I don't know why.
1323 */
1324 flags & (SI_CONTEXT_INV_ICACHE |
1325 SI_CONTEXT_PS_PARTIAL_FLUSH |
1326 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1327 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1328 sctx->compute_is_busy);
1329
1330 assert(sctx->chip_class <= GFX9);
1331
1332 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1333 sctx->num_cb_cache_flushes++;
1334 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1335 sctx->num_db_cache_flushes++;
1336
1337 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1338 * bit is set. An alternative way is to write SQC_CACHES, but that
1339 * doesn't seem to work reliably. Since the bug doesn't affect
1340 * correctness (it only does more work than necessary) and
1341 * the performance impact is likely negligible, there is no plan
1342 * to add a workaround for it.
1343 */
1344
1345 if (flags & SI_CONTEXT_INV_ICACHE)
1346 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1347 if (flags & SI_CONTEXT_INV_SCACHE)
1348 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1349
1350 if (sctx->chip_class <= GFX8) {
1351 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1352 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1353 S_0085F0_CB0_DEST_BASE_ENA(1) |
1354 S_0085F0_CB1_DEST_BASE_ENA(1) |
1355 S_0085F0_CB2_DEST_BASE_ENA(1) |
1356 S_0085F0_CB3_DEST_BASE_ENA(1) |
1357 S_0085F0_CB4_DEST_BASE_ENA(1) |
1358 S_0085F0_CB5_DEST_BASE_ENA(1) |
1359 S_0085F0_CB6_DEST_BASE_ENA(1) |
1360 S_0085F0_CB7_DEST_BASE_ENA(1);
1361
1362 /* Necessary for DCC */
1363 if (sctx->chip_class == GFX8)
1364 si_cp_release_mem(sctx, cs,
1365 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1366 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1367 EOP_DATA_SEL_DISCARD, NULL,
1368 0, 0, SI_NOT_QUERY);
1369 }
1370 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1371 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1372 S_0085F0_DB_DEST_BASE_ENA(1);
1373 }
1374
1375 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1376 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1377 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1378 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1379 }
1380 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1381 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1382 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1383 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1384 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1385 }
1386
1387 /* Wait for shader engines to go idle.
1388 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1389 * for everything including CB/DB cache flushes.
1390 */
1391 if (!flush_cb_db) {
1392 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1393 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1394 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1395 /* Only count explicit shader flushes, not implicit ones
1396 * done by SURFACE_SYNC.
1397 */
1398 sctx->num_vs_flushes++;
1399 sctx->num_ps_flushes++;
1400 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1401 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1402 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1403 sctx->num_vs_flushes++;
1404 }
1405 }
1406
1407 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1408 sctx->compute_is_busy) {
1409 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1410 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1411 sctx->num_cs_flushes++;
1412 sctx->compute_is_busy = false;
1413 }
1414
1415 /* VGT state synchronization. */
1416 if (flags & SI_CONTEXT_VGT_FLUSH) {
1417 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1418 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1419 }
1420 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1421 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1422 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1423 }
1424
1425 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1426 * wait for idle on GFX9. We have to use a TS event.
1427 */
1428 if (sctx->chip_class == GFX9 && flush_cb_db) {
1429 uint64_t va;
1430 unsigned tc_flags, cb_db_event;
1431
1432 /* Set the CB/DB flush event. */
1433 switch (flush_cb_db) {
1434 case SI_CONTEXT_FLUSH_AND_INV_CB:
1435 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1436 break;
1437 case SI_CONTEXT_FLUSH_AND_INV_DB:
1438 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1439 break;
1440 default:
1441 /* both CB & DB */
1442 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1443 }
1444
1445 /* These are the only allowed combinations. If you need to
1446 * do multiple operations at once, do them separately.
1447 * All operations that invalidate L2 also seem to invalidate
1448 * metadata. Volatile (VOL) and WC flushes are not listed here.
1449 *
1450 * TC | TC_WB = writeback & invalidate L2 & L1
1451 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1452 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1453 * TC | TC_NC = invalidate L2 for MTYPE == NC
1454 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1455 * TCL1 = invalidate L1
1456 */
1457 tc_flags = 0;
1458
1459 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1460 tc_flags = EVENT_TC_ACTION_ENA |
1461 EVENT_TC_MD_ACTION_ENA;
1462 }
1463
1464 /* Ideally flush TC together with CB/DB. */
1465 if (flags & SI_CONTEXT_INV_L2) {
1466 /* Writeback and invalidate everything in L2 & L1. */
1467 tc_flags = EVENT_TC_ACTION_ENA |
1468 EVENT_TC_WB_ACTION_ENA;
1469
1470 /* Clear the flags. */
1471 flags &= ~(SI_CONTEXT_INV_L2 |
1472 SI_CONTEXT_WB_L2 |
1473 SI_CONTEXT_INV_VCACHE);
1474 sctx->num_L2_invalidates++;
1475 }
1476
1477 /* Do the flush (enqueue the event and wait for it). */
1478 va = sctx->wait_mem_scratch->gpu_address;
1479 sctx->wait_mem_number++;
1480
1481 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1482 EOP_DST_SEL_MEM,
1483 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1484 EOP_DATA_SEL_VALUE_32BIT,
1485 sctx->wait_mem_scratch, va,
1486 sctx->wait_mem_number, SI_NOT_QUERY);
1487 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1488 WAIT_REG_MEM_EQUAL);
1489 }
1490
1491 /* Make sure ME is idle (it executes most packets) before continuing.
1492 * This prevents read-after-write hazards between PFP and ME.
1493 */
1494 if (sctx->has_graphics &&
1495 (cp_coher_cntl ||
1496 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1497 SI_CONTEXT_INV_VCACHE |
1498 SI_CONTEXT_INV_L2 |
1499 SI_CONTEXT_WB_L2)))) {
1500 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1501 radeon_emit(cs, 0);
1502 }
1503
1504 /* GFX6-GFX8 only:
1505 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1506 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1507 *
1508 * cp_coher_cntl should contain all necessary flags except TC flags
1509 * at this point.
1510 *
1511 * GFX6-GFX7 don't support L2 write-back.
1512 */
1513 if (flags & SI_CONTEXT_INV_L2 ||
1514 (sctx->chip_class <= GFX7 &&
1515 (flags & SI_CONTEXT_WB_L2))) {
1516 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1517 * WB must be set on GFX8+ when TC_ACTION is set.
1518 */
1519 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1520 S_0085F0_TC_ACTION_ENA(1) |
1521 S_0085F0_TCL1_ACTION_ENA(1) |
1522 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1523 cp_coher_cntl = 0;
1524 sctx->num_L2_invalidates++;
1525 } else {
1526 /* L1 invalidation and L2 writeback must be done separately,
1527 * because both operations can't be done together.
1528 */
1529 if (flags & SI_CONTEXT_WB_L2) {
1530 /* WB = write-back
1531 * NC = apply to non-coherent MTYPEs
1532 * (i.e. MTYPE <= 1, which is what we use everywhere)
1533 *
1534 * WB doesn't work without NC.
1535 */
1536 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1537 S_0301F0_TC_WB_ACTION_ENA(1) |
1538 S_0301F0_TC_NC_ACTION_ENA(1));
1539 cp_coher_cntl = 0;
1540 sctx->num_L2_writebacks++;
1541 }
1542 if (flags & SI_CONTEXT_INV_VCACHE) {
1543 /* Invalidate per-CU VMEM L1. */
1544 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1545 S_0085F0_TCL1_ACTION_ENA(1));
1546 cp_coher_cntl = 0;
1547 }
1548 }
1549
1550 /* If TC flushes haven't cleared this... */
1551 if (cp_coher_cntl)
1552 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1553
1554 if (is_barrier)
1555 si_prim_discard_signal_next_compute_ib_start(sctx);
1556
1557 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1558 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1559 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1560 EVENT_INDEX(0));
1561 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1562 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1563 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1564 EVENT_INDEX(0));
1565 }
1566
1567 sctx->flags = 0;
1568 }
1569
1570 static void si_get_draw_start_count(struct si_context *sctx,
1571 const struct pipe_draw_info *info,
1572 unsigned *start, unsigned *count)
1573 {
1574 struct pipe_draw_indirect_info *indirect = info->indirect;
1575
1576 if (indirect) {
1577 unsigned indirect_count;
1578 struct pipe_transfer *transfer;
1579 unsigned begin, end;
1580 unsigned map_size;
1581 unsigned *data;
1582
1583 if (indirect->indirect_draw_count) {
1584 data = pipe_buffer_map_range(&sctx->b,
1585 indirect->indirect_draw_count,
1586 indirect->indirect_draw_count_offset,
1587 sizeof(unsigned),
1588 PIPE_TRANSFER_READ, &transfer);
1589
1590 indirect_count = *data;
1591
1592 pipe_buffer_unmap(&sctx->b, transfer);
1593 } else {
1594 indirect_count = indirect->draw_count;
1595 }
1596
1597 if (!indirect_count) {
1598 *start = *count = 0;
1599 return;
1600 }
1601
1602 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1603 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1604 indirect->offset, map_size,
1605 PIPE_TRANSFER_READ, &transfer);
1606
1607 begin = UINT_MAX;
1608 end = 0;
1609
1610 for (unsigned i = 0; i < indirect_count; ++i) {
1611 unsigned count = data[0];
1612 unsigned start = data[2];
1613
1614 if (count > 0) {
1615 begin = MIN2(begin, start);
1616 end = MAX2(end, start + count);
1617 }
1618
1619 data += indirect->stride / sizeof(unsigned);
1620 }
1621
1622 pipe_buffer_unmap(&sctx->b, transfer);
1623
1624 if (begin < end) {
1625 *start = begin;
1626 *count = end - begin;
1627 } else {
1628 *start = *count = 0;
1629 }
1630 } else {
1631 *start = info->start;
1632 *count = info->count;
1633 }
1634 }
1635
1636 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1637 enum pipe_prim_type prim, unsigned instance_count,
1638 bool primitive_restart, unsigned skip_atom_mask)
1639 {
1640 unsigned num_patches = 0;
1641
1642 si_emit_rasterizer_prim_state(sctx);
1643 if (sctx->tes_shader.cso)
1644 si_emit_derived_tess_state(sctx, info, &num_patches);
1645
1646 /* Emit state atoms. */
1647 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1648 while (mask)
1649 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1650
1651 sctx->dirty_atoms &= skip_atom_mask;
1652
1653 /* Emit states. */
1654 mask = sctx->dirty_states;
1655 while (mask) {
1656 unsigned i = u_bit_scan(&mask);
1657 struct si_pm4_state *state = sctx->queued.array[i];
1658
1659 if (!state || sctx->emitted.array[i] == state)
1660 continue;
1661
1662 si_pm4_emit(sctx, state);
1663 sctx->emitted.array[i] = state;
1664 }
1665 sctx->dirty_states = 0;
1666
1667 /* Emit draw states. */
1668 si_emit_vs_state(sctx, info);
1669 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1670 primitive_restart);
1671 }
1672
1673 static bool
1674 si_all_vs_resources_read_only(struct si_context *sctx,
1675 struct pipe_resource *indexbuf)
1676 {
1677 struct radeon_winsys *ws = sctx->ws;
1678 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1679
1680 /* Index buffer. */
1681 if (indexbuf &&
1682 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1683 RADEON_USAGE_WRITE))
1684 goto has_write_reference;
1685
1686 /* Vertex buffers. */
1687 struct si_vertex_elements *velems = sctx->vertex_elements;
1688 unsigned num_velems = velems->count;
1689
1690 for (unsigned i = 0; i < num_velems; i++) {
1691 if (!((1 << i) & velems->first_vb_use_mask))
1692 continue;
1693
1694 unsigned vb_index = velems->vertex_buffer_index[i];
1695 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1696 if (!res)
1697 continue;
1698
1699 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1700 RADEON_USAGE_WRITE))
1701 goto has_write_reference;
1702 }
1703
1704 /* Constant and shader buffers. */
1705 struct si_descriptors *buffers =
1706 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1707 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1708 unsigned index = buffers->first_active_slot + i;
1709 struct pipe_resource *res =
1710 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1711 if (!res)
1712 continue;
1713
1714 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1715 RADEON_USAGE_WRITE))
1716 goto has_write_reference;
1717 }
1718
1719 /* Samplers. */
1720 struct si_shader_selector *vs = sctx->vs_shader.cso;
1721 if (vs->info.samplers_declared) {
1722 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1723
1724 for (unsigned i = 0; i < num_samplers; i++) {
1725 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1726 if (!view)
1727 continue;
1728
1729 if (ws->cs_is_buffer_referenced(cs,
1730 si_resource(view->texture)->buf,
1731 RADEON_USAGE_WRITE))
1732 goto has_write_reference;
1733 }
1734 }
1735
1736 /* Images. */
1737 if (vs->info.images_declared) {
1738 unsigned num_images = util_last_bit(vs->info.images_declared);
1739
1740 for (unsigned i = 0; i < num_images; i++) {
1741 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1742 if (!res)
1743 continue;
1744
1745 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1746 RADEON_USAGE_WRITE))
1747 goto has_write_reference;
1748 }
1749 }
1750
1751 return true;
1752
1753 has_write_reference:
1754 /* If the current gfx IB has enough packets, flush it to remove write
1755 * references to buffers.
1756 */
1757 if (cs->prev_dw + cs->current.cdw > 2048) {
1758 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1759 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1760 return true;
1761 }
1762 return false;
1763 }
1764
1765 static ALWAYS_INLINE bool pd_msg(const char *s)
1766 {
1767 if (SI_PRIM_DISCARD_DEBUG)
1768 printf("PD failed: %s\n", s);
1769 return false;
1770 }
1771
1772 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1773 {
1774 struct si_context *sctx = (struct si_context *)ctx;
1775 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1776 struct pipe_resource *indexbuf = info->index.resource;
1777 unsigned dirty_tex_counter, dirty_buf_counter;
1778 enum pipe_prim_type rast_prim, prim = info->mode;
1779 unsigned index_size = info->index_size;
1780 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1781 unsigned instance_count = info->instance_count;
1782 bool primitive_restart = info->primitive_restart &&
1783 (!sctx->screen->options.prim_restart_tri_strips_only ||
1784 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1785 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1786
1787 if (likely(!info->indirect)) {
1788 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1789 * no workaround for indirect draws, but we can at least skip
1790 * direct draws.
1791 */
1792 if (unlikely(!instance_count))
1793 return;
1794
1795 /* Handle count == 0. */
1796 if (unlikely(!info->count &&
1797 (index_size || !info->count_from_stream_output)))
1798 return;
1799 }
1800
1801 if (unlikely(!sctx->vs_shader.cso ||
1802 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1803 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1804 assert(0);
1805 return;
1806 }
1807
1808 /* Recompute and re-emit the texture resource states if needed. */
1809 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1810 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1811 sctx->last_dirty_tex_counter = dirty_tex_counter;
1812 sctx->framebuffer.dirty_cbufs |=
1813 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1814 sctx->framebuffer.dirty_zsbuf = true;
1815 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1816 si_update_all_texture_descriptors(sctx);
1817 }
1818
1819 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1820 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1821 sctx->last_dirty_buf_counter = dirty_buf_counter;
1822 /* Rebind all buffers unconditionally. */
1823 si_rebind_buffer(sctx, NULL);
1824 }
1825
1826 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1827
1828 /* Set the rasterization primitive type.
1829 *
1830 * This must be done after si_decompress_textures, which can call
1831 * draw_vbo recursively, and before si_update_shaders, which uses
1832 * current_rast_prim for this draw_vbo call. */
1833 if (sctx->gs_shader.cso) {
1834 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1835 rast_prim = sctx->gs_shader.cso->rast_prim;
1836 } else if (sctx->tes_shader.cso) {
1837 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1838 rast_prim = sctx->tes_shader.cso->rast_prim;
1839 } else if (util_rast_prim_is_triangles(prim)) {
1840 rast_prim = PIPE_PRIM_TRIANGLES;
1841 } else {
1842 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1843 rast_prim = prim;
1844 }
1845
1846 if (rast_prim != sctx->current_rast_prim) {
1847 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1848 util_prim_is_points_or_lines(rast_prim))
1849 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1850
1851 sctx->current_rast_prim = rast_prim;
1852 sctx->do_update_shaders = true;
1853 }
1854
1855 if (sctx->tes_shader.cso &&
1856 sctx->screen->info.has_ls_vgpr_init_bug) {
1857 /* Determine whether the LS VGPR fix should be applied.
1858 *
1859 * It is only required when num input CPs > num output CPs,
1860 * which cannot happen with the fixed function TCS. We should
1861 * also update this bit when switching from TCS to fixed
1862 * function TCS.
1863 */
1864 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1865 bool ls_vgpr_fix =
1866 tcs &&
1867 info->vertices_per_patch >
1868 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1869
1870 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1871 sctx->ls_vgpr_fix = ls_vgpr_fix;
1872 sctx->do_update_shaders = true;
1873 }
1874 }
1875
1876 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1877 /* Determine whether the GS triangle strip adjacency fix should
1878 * be applied. Rotate every other triangle if
1879 * - triangle strips with adjacency are fed to the GS and
1880 * - primitive restart is disabled (the rotation doesn't help
1881 * when the restart occurs after an odd number of triangles).
1882 */
1883 bool gs_tri_strip_adj_fix =
1884 !sctx->tes_shader.cso &&
1885 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1886 !primitive_restart;
1887
1888 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1889 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1890 sctx->do_update_shaders = true;
1891 }
1892 }
1893
1894 if (index_size) {
1895 /* Translate or upload, if needed. */
1896 /* 8-bit indices are supported on GFX8. */
1897 if (sctx->chip_class <= GFX7 && index_size == 1) {
1898 unsigned start, count, start_offset, size, offset;
1899 void *ptr;
1900
1901 si_get_draw_start_count(sctx, info, &start, &count);
1902 start_offset = start * 2;
1903 size = count * 2;
1904
1905 indexbuf = NULL;
1906 u_upload_alloc(ctx->stream_uploader, start_offset,
1907 size,
1908 si_optimal_tcc_alignment(sctx, size),
1909 &offset, &indexbuf, &ptr);
1910 if (!indexbuf)
1911 return;
1912
1913 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1914 index_offset + start,
1915 count, ptr);
1916
1917 /* info->start will be added by the drawing code */
1918 index_offset = offset - start_offset;
1919 index_size = 2;
1920 } else if (info->has_user_indices) {
1921 unsigned start_offset;
1922
1923 assert(!info->indirect);
1924 start_offset = info->start * index_size;
1925
1926 indexbuf = NULL;
1927 u_upload_data(ctx->stream_uploader, start_offset,
1928 info->count * index_size,
1929 sctx->screen->info.tcc_cache_line_size,
1930 (char*)info->index.user + start_offset,
1931 &index_offset, &indexbuf);
1932 if (!indexbuf)
1933 return;
1934
1935 /* info->start will be added by the drawing code */
1936 index_offset -= start_offset;
1937 } else if (sctx->chip_class <= GFX7 &&
1938 si_resource(indexbuf)->TC_L2_dirty) {
1939 /* GFX8 reads index buffers through TC L2, so it doesn't
1940 * need this. */
1941 sctx->flags |= SI_CONTEXT_WB_L2;
1942 si_resource(indexbuf)->TC_L2_dirty = false;
1943 }
1944 }
1945
1946 bool dispatch_prim_discard_cs = false;
1947 bool prim_discard_cs_instancing = false;
1948 unsigned original_index_size = index_size;
1949 unsigned direct_count = 0;
1950
1951 if (info->indirect) {
1952 struct pipe_draw_indirect_info *indirect = info->indirect;
1953
1954 /* Add the buffer size for memory checking in need_cs_space. */
1955 si_context_add_resource_size(sctx, indirect->buffer);
1956
1957 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1958 if (sctx->chip_class <= GFX8) {
1959 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1960 sctx->flags |= SI_CONTEXT_WB_L2;
1961 si_resource(indirect->buffer)->TC_L2_dirty = false;
1962 }
1963
1964 if (indirect->indirect_draw_count &&
1965 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1966 sctx->flags |= SI_CONTEXT_WB_L2;
1967 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1968 }
1969 }
1970 } else {
1971 /* Multiply by 3 for strips and fans to get an approximate vertex
1972 * count as triangles. */
1973 direct_count = info->count * instance_count *
1974 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1975 }
1976
1977 /* Determine if we can use the primitive discard compute shader. */
1978 if (si_compute_prim_discard_enabled(sctx) &&
1979 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1980 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1981 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1982 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1983 (primitive_restart ?
1984 /* Supported prim types with primitive restart: */
1985 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1986 /* Disallow instancing with primitive restart: */
1987 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1988 /* Supported prim types without primitive restart + allow instancing: */
1989 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1990 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1991 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1992 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1993 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1994 (instance_count == 1 ||
1995 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1996 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1997 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1998 (!sctx->render_cond || pd_msg("render condition")) &&
1999 /* Forced enablement ignores pipeline statistics queries. */
2000 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
2001 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
2002 pd_msg("pipestat or primgen query")) &&
2003 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
2004 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
2005 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
2006 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
2007 !rs->polygon_mode_enabled &&
2008 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
2009 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
2010 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
2011 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
2012 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
2013 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2014 !sctx->vs_shader.cso->so.num_outputs &&
2015 #else
2016 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
2017 #endif
2018 /* Check that all buffers are used for read only, because compute
2019 * dispatches can run ahead. */
2020 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
2021 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
2022 case SI_PRIM_DISCARD_ENABLED:
2023 original_index_size = index_size;
2024 prim_discard_cs_instancing = instance_count > 1;
2025 dispatch_prim_discard_cs = true;
2026
2027 /* The compute shader changes/lowers the following: */
2028 prim = PIPE_PRIM_TRIANGLES;
2029 index_size = 4;
2030 instance_count = 1;
2031 primitive_restart = false;
2032 sctx->compute_num_verts_rejected -= direct_count;
2033 sctx->compute_num_verts_accepted += direct_count;
2034 break;
2035 case SI_PRIM_DISCARD_DISABLED:
2036 break;
2037 case SI_PRIM_DISCARD_DRAW_SPLIT:
2038 sctx->compute_num_verts_rejected -= direct_count;
2039 goto return_cleanup;
2040 }
2041 }
2042
2043 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
2044 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
2045 sctx->do_update_shaders = true;
2046 }
2047
2048 if (sctx->do_update_shaders && !si_update_shaders(sctx))
2049 goto return_cleanup;
2050
2051 si_need_gfx_cs_space(sctx);
2052
2053 if (sctx->bo_list_add_all_gfx_resources)
2054 si_gfx_resources_add_all_to_bo_list(sctx);
2055
2056 /* Since we've called si_context_add_resource_size for vertex buffers,
2057 * this must be called after si_need_cs_space, because we must let
2058 * need_cs_space flush before we add buffers to the buffer list.
2059 */
2060 if (!si_upload_vertex_buffer_descriptors(sctx))
2061 goto return_cleanup;
2062
2063 /* Vega10/Raven scissor bug workaround. When any context register is
2064 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2065 * registers must be written too.
2066 */
2067 unsigned masked_atoms = 0;
2068
2069 if (sctx->screen->info.has_gfx9_scissor_bug) {
2070 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2071
2072 if (info->count_from_stream_output ||
2073 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2074 sctx->dirty_states & si_states_that_always_roll_context())
2075 sctx->context_roll = true;
2076 }
2077
2078 /* Use optimal packet order based on whether we need to sync the pipeline. */
2079 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2080 SI_CONTEXT_FLUSH_AND_INV_DB |
2081 SI_CONTEXT_PS_PARTIAL_FLUSH |
2082 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2083 /* If we have to wait for idle, set all states first, so that all
2084 * SET packets are processed in parallel with previous draw calls.
2085 * Then draw and prefetch at the end. This ensures that the time
2086 * the CUs are idle is very short.
2087 */
2088 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2089 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2090
2091 if (!si_upload_graphics_shader_descriptors(sctx))
2092 goto return_cleanup;
2093
2094 /* Emit all states except possibly render condition. */
2095 si_emit_all_states(sctx, info, prim, instance_count,
2096 primitive_restart, masked_atoms);
2097 sctx->emit_cache_flush(sctx);
2098 /* <-- CUs are idle here. */
2099
2100 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2101 sctx->atoms.s.render_cond.emit(sctx);
2102
2103 if (sctx->screen->info.has_gfx9_scissor_bug &&
2104 (sctx->context_roll ||
2105 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2106 sctx->atoms.s.scissors.emit(sctx);
2107
2108 sctx->dirty_atoms = 0;
2109
2110 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2111 instance_count, dispatch_prim_discard_cs,
2112 original_index_size);
2113 /* <-- CUs are busy here. */
2114
2115 /* Start prefetches after the draw has been started. Both will run
2116 * in parallel, but starting the draw first is more important.
2117 */
2118 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2119 cik_emit_prefetch_L2(sctx, false);
2120 } else {
2121 /* If we don't wait for idle, start prefetches first, then set
2122 * states, and draw at the end.
2123 */
2124 if (sctx->flags)
2125 sctx->emit_cache_flush(sctx);
2126
2127 /* Only prefetch the API VS and VBO descriptors. */
2128 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2129 cik_emit_prefetch_L2(sctx, true);
2130
2131 if (!si_upload_graphics_shader_descriptors(sctx))
2132 goto return_cleanup;
2133
2134 si_emit_all_states(sctx, info, prim, instance_count,
2135 primitive_restart, masked_atoms);
2136
2137 if (sctx->screen->info.has_gfx9_scissor_bug &&
2138 (sctx->context_roll ||
2139 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2140 sctx->atoms.s.scissors.emit(sctx);
2141
2142 sctx->dirty_atoms = 0;
2143
2144 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2145 instance_count, dispatch_prim_discard_cs,
2146 original_index_size);
2147
2148 /* Prefetch the remaining shaders after the draw has been
2149 * started. */
2150 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2151 cik_emit_prefetch_L2(sctx, false);
2152 }
2153
2154 /* Mark the displayable dcc buffer as dirty in order to update
2155 * it on the next call to si_flush_resource. */
2156 if (sctx->screen->info.use_display_dcc_with_retile_blit) {
2157 /* Don't use si_update_fb_dirtiness_after_rendering because it'll
2158 * cause unnecessary texture decompressions on each draw. */
2159 unsigned displayable_dcc_cb_mask = sctx->framebuffer.displayable_dcc_cb_mask;
2160 while (displayable_dcc_cb_mask) {
2161 unsigned i = u_bit_scan(&displayable_dcc_cb_mask);
2162 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2163 struct si_texture *tex = (struct si_texture*) surf->texture;
2164 tex->displayable_dcc_dirty = true;
2165 }
2166 }
2167
2168 /* Clear the context roll flag after the draw call. */
2169 sctx->context_roll = false;
2170
2171 if (unlikely(sctx->current_saved_cs)) {
2172 si_trace_emit(sctx);
2173 si_log_draw_state(sctx, sctx->log);
2174 }
2175
2176 /* Workaround for a VGT hang when streamout is enabled.
2177 * It must be done after drawing. */
2178 if ((sctx->family == CHIP_HAWAII ||
2179 sctx->family == CHIP_TONGA ||
2180 sctx->family == CHIP_FIJI) &&
2181 si_get_strmout_en(sctx)) {
2182 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2183 }
2184
2185 if (unlikely(sctx->decompression_enabled)) {
2186 sctx->num_decompress_calls++;
2187 } else {
2188 sctx->num_draw_calls++;
2189 if (sctx->framebuffer.state.nr_cbufs > 1)
2190 sctx->num_mrt_draw_calls++;
2191 if (primitive_restart)
2192 sctx->num_prim_restart_calls++;
2193 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2194 sctx->num_spill_draw_calls++;
2195 }
2196
2197 return_cleanup:
2198 if (index_size && indexbuf != info->index.resource)
2199 pipe_resource_reference(&indexbuf, NULL);
2200 }
2201
2202 static void
2203 si_draw_rectangle(struct blitter_context *blitter,
2204 void *vertex_elements_cso,
2205 blitter_get_vs_func get_vs,
2206 int x1, int y1, int x2, int y2,
2207 float depth, unsigned num_instances,
2208 enum blitter_attrib_type type,
2209 const union blitter_attrib *attrib)
2210 {
2211 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2212 struct si_context *sctx = (struct si_context*)pipe;
2213
2214 /* Pack position coordinates as signed int16. */
2215 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2216 ((uint32_t)(y1 & 0xffff) << 16);
2217 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2218 ((uint32_t)(y2 & 0xffff) << 16);
2219 sctx->vs_blit_sh_data[2] = fui(depth);
2220
2221 switch (type) {
2222 case UTIL_BLITTER_ATTRIB_COLOR:
2223 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2224 sizeof(float)*4);
2225 break;
2226 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2227 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2228 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2229 sizeof(attrib->texcoord));
2230 break;
2231 case UTIL_BLITTER_ATTRIB_NONE:;
2232 }
2233
2234 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2235
2236 struct pipe_draw_info info = {};
2237 info.mode = SI_PRIM_RECTANGLE_LIST;
2238 info.count = 3;
2239 info.instance_count = num_instances;
2240
2241 /* Don't set per-stage shader pointers for VS. */
2242 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2243 sctx->vertex_buffer_pointer_dirty = false;
2244
2245 si_draw_vbo(pipe, &info);
2246 }
2247
2248 void si_trace_emit(struct si_context *sctx)
2249 {
2250 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2251 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2252
2253 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2254 0, 4, V_370_MEM, V_370_ME, &trace_id);
2255
2256 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2257 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2258
2259 if (sctx->log)
2260 u_log_flush(sctx->log);
2261 }
2262
2263 void si_init_draw_functions(struct si_context *sctx)
2264 {
2265 sctx->b.draw_vbo = si_draw_vbo;
2266
2267 sctx->blitter->draw_rectangle = si_draw_rectangle;
2268
2269 si_init_ia_multi_vgt_param_table(sctx);
2270 }