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radeonsi/gfx10: implement si_emit_derived_tess_state
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 /* We should be able to support in-shader LDS use with LLVM >= 9
256 * by just adding the lds_sizes together, but it has never
257 * been tested. */
258 assert(ls_current->config.lds_size == 0);
259
260 if (sctx->chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2;
262
263 if (sctx->chip_class >= GFX10)
264 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
265 else
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
267
268 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
269
270 /* Set userdata SGPRs for merged LS-HS. */
271 radeon_set_sh_reg_seq(cs,
272 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
273 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
274 radeon_emit(cs, offchip_layout);
275 radeon_emit(cs, tcs_out_offsets);
276 radeon_emit(cs, tcs_out_layout);
277 } else {
278 unsigned ls_rsrc2 = ls_current->config.rsrc2;
279
280 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
281 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
282
283 /* Due to a hw bug, RSRC2_LS must be written twice with another
284 * LS register written in between. */
285 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
286 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
287 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
288 radeon_emit(cs, ls_current->config.rsrc1);
289 radeon_emit(cs, ls_rsrc2);
290
291 /* Set userdata SGPRs for TCS. */
292 radeon_set_sh_reg_seq(cs,
293 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
294 radeon_emit(cs, offchip_layout);
295 radeon_emit(cs, tcs_out_offsets);
296 radeon_emit(cs, tcs_out_layout);
297 radeon_emit(cs, tcs_in_layout);
298 }
299
300 /* Set userdata SGPRs for TES. */
301 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
302 radeon_emit(cs, offchip_layout);
303 radeon_emit(cs, ring_va);
304
305 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
306 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
307 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
308
309 if (sctx->last_ls_hs_config != ls_hs_config) {
310 if (sctx->chip_class >= GFX7) {
311 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
312 ls_hs_config);
313 } else {
314 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
315 ls_hs_config);
316 }
317 sctx->last_ls_hs_config = ls_hs_config;
318 sctx->context_roll = true;
319 }
320 }
321
322 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
323 enum pipe_prim_type prim)
324 {
325 switch (prim) {
326 case PIPE_PRIM_PATCHES:
327 return info->count / info->vertices_per_patch;
328 case PIPE_PRIM_POLYGON:
329 return info->count >= 3;
330 case SI_PRIM_RECTANGLE_LIST:
331 return info->count / 3;
332 default:
333 return u_decomposed_prims_for_vertices(prim, info->count);
334 }
335 }
336
337 static unsigned
338 si_get_init_multi_vgt_param(struct si_screen *sscreen,
339 union si_vgt_param_key *key)
340 {
341 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
342 unsigned max_primgroup_in_wave = 2;
343
344 /* SWITCH_ON_EOP(0) is always preferable. */
345 bool wd_switch_on_eop = false;
346 bool ia_switch_on_eop = false;
347 bool ia_switch_on_eoi = false;
348 bool partial_vs_wave = false;
349 bool partial_es_wave = false;
350
351 if (key->u.uses_tess) {
352 /* SWITCH_ON_EOI must be set if PrimID is used. */
353 if (key->u.tess_uses_prim_id)
354 ia_switch_on_eoi = true;
355
356 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
357 if ((sscreen->info.family == CHIP_TAHITI ||
358 sscreen->info.family == CHIP_PITCAIRN ||
359 sscreen->info.family == CHIP_BONAIRE) &&
360 key->u.uses_gs)
361 partial_vs_wave = true;
362
363 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
364 if (sscreen->has_distributed_tess) {
365 if (key->u.uses_gs) {
366 if (sscreen->info.chip_class == GFX8)
367 partial_es_wave = true;
368 } else {
369 partial_vs_wave = true;
370 }
371 }
372 }
373
374 /* This is a hardware requirement. */
375 if (key->u.line_stipple_enabled ||
376 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
377 ia_switch_on_eop = true;
378 wd_switch_on_eop = true;
379 }
380
381 if (sscreen->info.chip_class >= GFX7) {
382 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
383 * 4 shader engines. Set 1 to pass the assertion below.
384 * The other cases are hardware requirements.
385 *
386 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
387 * for points, line strips, and tri strips.
388 */
389 if (sscreen->info.max_se <= 2 ||
390 key->u.prim == PIPE_PRIM_POLYGON ||
391 key->u.prim == PIPE_PRIM_LINE_LOOP ||
392 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
393 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
394 (key->u.primitive_restart &&
395 (sscreen->info.family < CHIP_POLARIS10 ||
396 (key->u.prim != PIPE_PRIM_POINTS &&
397 key->u.prim != PIPE_PRIM_LINE_STRIP &&
398 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
399 key->u.count_from_stream_output)
400 wd_switch_on_eop = true;
401
402 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
403 * We don't know that for indirect drawing, so treat it as
404 * always problematic. */
405 if (sscreen->info.family == CHIP_HAWAII &&
406 key->u.uses_instancing)
407 wd_switch_on_eop = true;
408
409 /* Performance recommendation for 4 SE Gfx7-8 parts if
410 * instances are smaller than a primgroup.
411 * Assume indirect draws always use small instances.
412 * This is needed for good VS wave utilization.
413 */
414 if (sscreen->info.chip_class <= GFX8 &&
415 sscreen->info.max_se == 4 &&
416 key->u.multi_instances_smaller_than_primgroup)
417 wd_switch_on_eop = true;
418
419 /* Required on GFX7 and later. */
420 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
421 ia_switch_on_eoi = true;
422
423 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
424 * to work around a GS hang.
425 */
426 if (key->u.uses_gs &&
427 (sscreen->info.family == CHIP_TONGA ||
428 sscreen->info.family == CHIP_FIJI ||
429 sscreen->info.family == CHIP_POLARIS10 ||
430 sscreen->info.family == CHIP_POLARIS11 ||
431 sscreen->info.family == CHIP_POLARIS12 ||
432 sscreen->info.family == CHIP_VEGAM))
433 partial_vs_wave = true;
434
435 /* Required by Hawaii and, for some special cases, by GFX8. */
436 if (ia_switch_on_eoi &&
437 (sscreen->info.family == CHIP_HAWAII ||
438 (sscreen->info.chip_class == GFX8 &&
439 (key->u.uses_gs || max_primgroup_in_wave != 2))))
440 partial_vs_wave = true;
441
442 /* Instancing bug on Bonaire. */
443 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
444 key->u.uses_instancing)
445 partial_vs_wave = true;
446
447 /* This only applies to Polaris10 and later 4 SE chips.
448 * wd_switch_on_eop is already true on all other chips.
449 */
450 if (!wd_switch_on_eop && key->u.primitive_restart)
451 partial_vs_wave = true;
452
453 /* If the WD switch is false, the IA switch must be false too. */
454 assert(wd_switch_on_eop || !ia_switch_on_eop);
455 }
456
457 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
458 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
459 partial_es_wave = true;
460
461 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
462 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
463 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
464 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
465 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
466 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
467 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
468 max_primgroup_in_wave : 0) |
469 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
470 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
471 }
472
473 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
474 {
475 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
476 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
477 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
478 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
479 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
480 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
481 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
482 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
483 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
484 union si_vgt_param_key key;
485
486 key.index = 0;
487 key.u.prim = prim;
488 key.u.uses_instancing = uses_instancing;
489 key.u.multi_instances_smaller_than_primgroup = multi_instances;
490 key.u.primitive_restart = primitive_restart;
491 key.u.count_from_stream_output = count_from_so;
492 key.u.line_stipple_enabled = line_stipple;
493 key.u.uses_tess = uses_tess;
494 key.u.tess_uses_prim_id = tess_uses_primid;
495 key.u.uses_gs = uses_gs;
496
497 sctx->ia_multi_vgt_param[key.index] =
498 si_get_init_multi_vgt_param(sctx->screen, &key);
499 }
500 }
501
502 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
503 const struct pipe_draw_info *info,
504 enum pipe_prim_type prim,
505 unsigned num_patches,
506 unsigned instance_count,
507 bool primitive_restart)
508 {
509 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
510 unsigned primgroup_size;
511 unsigned ia_multi_vgt_param;
512
513 if (sctx->tes_shader.cso) {
514 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
515 } else if (sctx->gs_shader.cso) {
516 primgroup_size = 64; /* recommended with a GS */
517 } else {
518 primgroup_size = 128; /* recommended without a GS and tess */
519 }
520
521 key.u.prim = prim;
522 key.u.uses_instancing = info->indirect || instance_count > 1;
523 key.u.multi_instances_smaller_than_primgroup =
524 info->indirect ||
525 (instance_count > 1 &&
526 (info->count_from_stream_output ||
527 si_num_prims_for_vertices(info, prim) < primgroup_size));
528 key.u.primitive_restart = primitive_restart;
529 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
530
531 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
532 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
533
534 if (sctx->gs_shader.cso) {
535 /* GS requirement. */
536 if (sctx->chip_class <= GFX8 &&
537 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
538 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
539
540 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
541 * The hw doc says all multi-SE chips are affected, but Vulkan
542 * only applies it to Hawaii. Do what Vulkan does.
543 */
544 if (sctx->family == CHIP_HAWAII &&
545 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
546 (info->indirect ||
547 (instance_count > 1 &&
548 (info->count_from_stream_output ||
549 si_num_prims_for_vertices(info, prim) <= 1))))
550 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
551 }
552
553 return ia_multi_vgt_param;
554 }
555
556 static unsigned si_conv_prim_to_gs_out(unsigned mode)
557 {
558 static const int prim_conv[] = {
559 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
560 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
561 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
562 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
563 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
564 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
565 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
566 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
567 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
568 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
569 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
570 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
571 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
572 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
573 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
574 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
575 };
576 assert(mode < ARRAY_SIZE(prim_conv));
577
578 return prim_conv[mode];
579 }
580
581 /* rast_prim is the primitive type after GS. */
582 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
583 {
584 struct radeon_cmdbuf *cs = sctx->gfx_cs;
585 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
586 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
587
588 if (likely(rast_prim == sctx->last_rast_prim &&
589 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple))
590 return;
591
592 if (util_prim_is_lines(rast_prim)) {
593 /* For lines, reset the stipple pattern at each primitive. Otherwise,
594 * reset the stipple pattern at each packet (line strips, line loops).
595 */
596 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
597 rs->pa_sc_line_stipple |
598 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
599 sctx->context_roll = true;
600 }
601
602 if (rast_prim != sctx->last_rast_prim &&
603 (sctx->ngg || sctx->gs_shader.cso)) {
604 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
605 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
606 sctx->context_roll = true;
607
608 if (sctx->chip_class >= GFX10) {
609 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
610 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
611 }
612 }
613
614 sctx->last_rast_prim = rast_prim;
615 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
616 }
617
618 static void si_emit_vs_state(struct si_context *sctx,
619 const struct pipe_draw_info *info)
620 {
621 sctx->current_vs_state &= C_VS_STATE_INDEXED;
622 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
623
624 if (sctx->num_vs_blit_sgprs) {
625 /* Re-emit the state after we leave u_blitter. */
626 sctx->last_vs_state = ~0;
627 return;
628 }
629
630 if (sctx->current_vs_state != sctx->last_vs_state) {
631 struct radeon_cmdbuf *cs = sctx->gfx_cs;
632
633 /* For the API vertex shader (VS_STATE_INDEXED). */
634 radeon_set_sh_reg(cs,
635 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
636 SI_SGPR_VS_STATE_BITS * 4,
637 sctx->current_vs_state);
638
639 /* For vertex color clamping, which is done in the last stage
640 * before the rasterizer. */
641 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
642 /* GS copy shader or TES if GS is missing. */
643 radeon_set_sh_reg(cs,
644 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
645 SI_SGPR_VS_STATE_BITS * 4,
646 sctx->current_vs_state);
647 }
648
649 sctx->last_vs_state = sctx->current_vs_state;
650 }
651 }
652
653 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
654 bool primitive_restart,
655 unsigned restart_index)
656 {
657 return primitive_restart &&
658 (restart_index != sctx->last_restart_index ||
659 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
660 }
661
662 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
663 const struct pipe_draw_info *info,
664 enum pipe_prim_type prim,
665 unsigned num_patches,
666 unsigned instance_count,
667 bool primitive_restart)
668 {
669 struct radeon_cmdbuf *cs = sctx->gfx_cs;
670 unsigned ia_multi_vgt_param;
671
672 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
673 instance_count, primitive_restart);
674
675 /* Draw state. */
676 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
677 if (sctx->chip_class >= GFX9)
678 radeon_set_uconfig_reg_idx(cs, sctx->screen,
679 R_030960_IA_MULTI_VGT_PARAM, 4,
680 ia_multi_vgt_param);
681 else if (sctx->chip_class >= GFX7)
682 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
683 else
684 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
685
686 sctx->last_multi_vgt_param = ia_multi_vgt_param;
687 }
688 }
689
690 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
691 * We overload last_multi_vgt_param.
692 */
693 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
694 {
695 if (sctx->ngg)
696 return; /* set during PM4 emit */
697
698 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
699 unsigned primgroup_size;
700 unsigned vertgroup_size;
701
702 if (sctx->tes_shader.cso) {
703 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
704 vertgroup_size = 0;
705 } else if (sctx->gs_shader.cso) {
706 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
707 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
708 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
709 } else {
710 primgroup_size = 128; /* recommended without a GS and tess */
711 vertgroup_size = 0;
712 }
713
714 unsigned ge_cntl =
715 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
716 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
717 S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
718 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
719
720 if (ge_cntl != sctx->last_multi_vgt_param) {
721 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
722 sctx->last_multi_vgt_param = ge_cntl;
723 }
724 }
725
726 static void si_emit_draw_registers(struct si_context *sctx,
727 const struct pipe_draw_info *info,
728 enum pipe_prim_type prim,
729 unsigned num_patches,
730 unsigned instance_count,
731 bool primitive_restart)
732 {
733 struct radeon_cmdbuf *cs = sctx->gfx_cs;
734 unsigned vgt_prim = si_conv_pipe_prim(info->mode);
735
736 if (sctx->chip_class >= GFX10)
737 gfx10_emit_ge_cntl(sctx, num_patches);
738 else
739 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
740 instance_count, primitive_restart);
741
742 if (vgt_prim != sctx->last_prim) {
743 if (sctx->chip_class >= GFX7)
744 radeon_set_uconfig_reg_idx(cs, sctx->screen,
745 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
746 else
747 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
748
749 sctx->last_prim = vgt_prim;
750 }
751
752 /* Primitive restart. */
753 if (primitive_restart != sctx->last_primitive_restart_en) {
754 if (sctx->chip_class >= GFX9)
755 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
756 primitive_restart);
757 else
758 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
759 primitive_restart);
760
761 sctx->last_primitive_restart_en = primitive_restart;
762
763 }
764 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
765 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
766 info->restart_index);
767 sctx->last_restart_index = info->restart_index;
768 sctx->context_roll = true;
769 }
770 }
771
772 static void si_emit_draw_packets(struct si_context *sctx,
773 const struct pipe_draw_info *info,
774 struct pipe_resource *indexbuf,
775 unsigned index_size,
776 unsigned index_offset,
777 unsigned instance_count,
778 bool dispatch_prim_discard_cs,
779 unsigned original_index_size)
780 {
781 struct pipe_draw_indirect_info *indirect = info->indirect;
782 struct radeon_cmdbuf *cs = sctx->gfx_cs;
783 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
784 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
785 uint32_t index_max_size = 0;
786 uint64_t index_va = 0;
787
788 if (info->count_from_stream_output) {
789 struct si_streamout_target *t =
790 (struct si_streamout_target*)info->count_from_stream_output;
791
792 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
793 t->stride_in_dw);
794 si_cp_copy_data(sctx, sctx->gfx_cs,
795 COPY_DATA_REG, NULL,
796 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
797 COPY_DATA_SRC_MEM, t->buf_filled_size,
798 t->buf_filled_size_offset);
799 }
800
801 /* draw packet */
802 if (index_size) {
803 if (index_size != sctx->last_index_size) {
804 unsigned index_type;
805
806 /* index type */
807 switch (index_size) {
808 case 1:
809 index_type = V_028A7C_VGT_INDEX_8;
810 break;
811 case 2:
812 index_type = V_028A7C_VGT_INDEX_16 |
813 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
814 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
815 break;
816 case 4:
817 index_type = V_028A7C_VGT_INDEX_32 |
818 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
819 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
820 break;
821 default:
822 assert(!"unreachable");
823 return;
824 }
825
826 if (sctx->chip_class >= GFX9) {
827 radeon_set_uconfig_reg_idx(cs, sctx->screen,
828 R_03090C_VGT_INDEX_TYPE, 2,
829 index_type);
830 } else {
831 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
832 radeon_emit(cs, index_type);
833 }
834
835 sctx->last_index_size = index_size;
836 }
837
838 if (original_index_size) {
839 index_max_size = (indexbuf->width0 - index_offset) /
840 original_index_size;
841 index_va = si_resource(indexbuf)->gpu_address + index_offset;
842
843 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
844 si_resource(indexbuf),
845 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
846 }
847 } else {
848 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
849 * so the state must be re-emitted before the next indexed draw.
850 */
851 if (sctx->chip_class >= GFX7)
852 sctx->last_index_size = -1;
853 }
854
855 if (indirect) {
856 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
857
858 assert(indirect_va % 8 == 0);
859
860 si_invalidate_draw_sh_constants(sctx);
861
862 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
863 radeon_emit(cs, 1);
864 radeon_emit(cs, indirect_va);
865 radeon_emit(cs, indirect_va >> 32);
866
867 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
868 si_resource(indirect->buffer),
869 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
870
871 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
872 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
873
874 assert(indirect->offset % 4 == 0);
875
876 if (index_size) {
877 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
878 radeon_emit(cs, index_va);
879 radeon_emit(cs, index_va >> 32);
880
881 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
882 radeon_emit(cs, index_max_size);
883 }
884
885 if (!sctx->screen->has_draw_indirect_multi) {
886 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
887 : PKT3_DRAW_INDIRECT,
888 3, render_cond_bit));
889 radeon_emit(cs, indirect->offset);
890 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
891 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
892 radeon_emit(cs, di_src_sel);
893 } else {
894 uint64_t count_va = 0;
895
896 if (indirect->indirect_draw_count) {
897 struct si_resource *params_buf =
898 si_resource(indirect->indirect_draw_count);
899
900 radeon_add_to_buffer_list(
901 sctx, sctx->gfx_cs, params_buf,
902 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
903
904 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
905 }
906
907 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
908 PKT3_DRAW_INDIRECT_MULTI,
909 8, render_cond_bit));
910 radeon_emit(cs, indirect->offset);
911 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
912 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
913 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
914 S_2C3_DRAW_INDEX_ENABLE(1) |
915 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
916 radeon_emit(cs, indirect->draw_count);
917 radeon_emit(cs, count_va);
918 radeon_emit(cs, count_va >> 32);
919 radeon_emit(cs, indirect->stride);
920 radeon_emit(cs, di_src_sel);
921 }
922 } else {
923 int base_vertex;
924
925 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
926 sctx->last_instance_count != instance_count) {
927 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
928 radeon_emit(cs, instance_count);
929 sctx->last_instance_count = instance_count;
930 }
931
932 /* Base vertex and start instance. */
933 base_vertex = original_index_size ? info->index_bias : info->start;
934
935 if (sctx->num_vs_blit_sgprs) {
936 /* Re-emit draw constants after we leave u_blitter. */
937 si_invalidate_draw_sh_constants(sctx);
938
939 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
940 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
941 sctx->num_vs_blit_sgprs);
942 radeon_emit_array(cs, sctx->vs_blit_sh_data,
943 sctx->num_vs_blit_sgprs);
944 } else if (base_vertex != sctx->last_base_vertex ||
945 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
946 info->start_instance != sctx->last_start_instance ||
947 info->drawid != sctx->last_drawid ||
948 sh_base_reg != sctx->last_sh_base_reg) {
949 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
950 radeon_emit(cs, base_vertex);
951 radeon_emit(cs, info->start_instance);
952 radeon_emit(cs, info->drawid);
953
954 sctx->last_base_vertex = base_vertex;
955 sctx->last_start_instance = info->start_instance;
956 sctx->last_drawid = info->drawid;
957 sctx->last_sh_base_reg = sh_base_reg;
958 }
959
960 if (index_size) {
961 if (dispatch_prim_discard_cs) {
962 index_va += info->start * original_index_size;
963 index_max_size = MIN2(index_max_size, info->count);
964
965 si_dispatch_prim_discard_cs_and_draw(sctx, info,
966 original_index_size,
967 base_vertex,
968 index_va, index_max_size);
969 return;
970 }
971
972 index_va += info->start * index_size;
973
974 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
975 radeon_emit(cs, index_max_size);
976 radeon_emit(cs, index_va);
977 radeon_emit(cs, index_va >> 32);
978 radeon_emit(cs, info->count);
979 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
980 } else {
981 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
982 radeon_emit(cs, info->count);
983 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
984 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
985 }
986 }
987 }
988
989 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
990 unsigned cp_coher_cntl)
991 {
992 bool compute_ib = !sctx->has_graphics ||
993 cs == sctx->prim_discard_compute_cs;
994
995 if (sctx->chip_class >= GFX9 || compute_ib) {
996 /* Flush caches and wait for the caches to assert idle. */
997 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
998 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
999 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1000 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1001 radeon_emit(cs, 0); /* CP_COHER_BASE */
1002 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1003 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1004 } else {
1005 /* ACQUIRE_MEM is only required on a compute ring. */
1006 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1007 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1008 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1009 radeon_emit(cs, 0); /* CP_COHER_BASE */
1010 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1011 }
1012
1013 /* ACQUIRE_MEM has an implicit context roll if the current context
1014 * is busy. */
1015 if (!compute_ib)
1016 sctx->context_roll = true;
1017 }
1018
1019 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1020 {
1021 if (!si_compute_prim_discard_enabled(sctx))
1022 return;
1023
1024 if (!sctx->barrier_buf) {
1025 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1026 &sctx->barrier_buf_offset,
1027 (struct pipe_resource**)&sctx->barrier_buf);
1028 }
1029
1030 /* Emit a placeholder to signal the next compute IB to start.
1031 * See si_compute_prim_discard.c for explanation.
1032 */
1033 uint32_t signal = 1;
1034 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1035 4, V_370_MEM, V_370_ME, &signal);
1036
1037 sctx->last_pkt3_write_data =
1038 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1039
1040 /* Only the last occurence of WRITE_DATA will be executed.
1041 * The packet will be enabled in si_flush_gfx_cs.
1042 */
1043 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1044 }
1045
1046 void gfx10_emit_cache_flush(struct si_context *ctx)
1047 {
1048 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1049 uint32_t gcr_cntl = 0;
1050 unsigned cb_db_event = 0;
1051 unsigned flags = ctx->flags;
1052
1053 if (!ctx->has_graphics) {
1054 /* Only process compute flags. */
1055 flags &= SI_CONTEXT_INV_ICACHE |
1056 SI_CONTEXT_INV_SCACHE |
1057 SI_CONTEXT_INV_VCACHE |
1058 SI_CONTEXT_INV_L2 |
1059 SI_CONTEXT_WB_L2 |
1060 SI_CONTEXT_INV_L2_METADATA |
1061 SI_CONTEXT_CS_PARTIAL_FLUSH;
1062 }
1063
1064 /* We don't need these. */
1065 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
1066 SI_CONTEXT_VGT_STREAMOUT_SYNC |
1067 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1068
1069 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1070 ctx->num_cb_cache_flushes++;
1071 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1072 ctx->num_db_cache_flushes++;
1073
1074 if (flags & SI_CONTEXT_INV_ICACHE)
1075 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1076 if (flags & SI_CONTEXT_INV_SCACHE) {
1077 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1078 * to FORWARD when both L1 and L2 are written out (WB or INV).
1079 */
1080 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1081 }
1082 if (flags & SI_CONTEXT_INV_VCACHE)
1083 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1084 if (flags & SI_CONTEXT_INV_L2) {
1085 /* Writeback and invalidate everything in L2. */
1086 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1087 ctx->num_L2_invalidates++;
1088 } else if (flags & SI_CONTEXT_WB_L2) {
1089 /* Writeback but do not invalidate. */
1090 gcr_cntl |= S_586_GL2_WB(1);
1091 }
1092 if (flags & SI_CONTEXT_INV_L2_METADATA)
1093 gcr_cntl |= S_586_GLM_INV(1);
1094
1095 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1096 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1097 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1098 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1099 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1100 EVENT_INDEX(0));
1101 }
1102 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1103 /* Flush HTILE. Will wait for idle later. */
1104 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1105 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1106 EVENT_INDEX(0));
1107 }
1108
1109 /* First flush CB/DB, then L1/L2. */
1110 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1111
1112 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1113 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1114 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1115 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1116 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1117 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1118 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1119 } else {
1120 assert(0);
1121 }
1122 } else {
1123 /* Wait for graphics shaders to go idle if requested. */
1124 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1126 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1127 /* Only count explicit shader flushes, not implicit ones. */
1128 ctx->num_vs_flushes++;
1129 ctx->num_ps_flushes++;
1130 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1131 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1132 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1133 ctx->num_vs_flushes++;
1134 }
1135 }
1136
1137 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1138 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1139 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1140 ctx->num_cs_flushes++;
1141 ctx->compute_is_busy = false;
1142 }
1143
1144 if (cb_db_event) {
1145 /* CB/DB flush and invalidate (or possibly just a wait for a
1146 * meta flush) via RELEASE_MEM.
1147 *
1148 * Combine this with other cache flushes when possible; this
1149 * requires affected shaders to be idle, so do it after the
1150 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1151 * implied).
1152 */
1153 uint64_t va;
1154
1155 /* Do the flush (enqueue the event and wait for it). */
1156 va = ctx->wait_mem_scratch->gpu_address;
1157 ctx->wait_mem_number++;
1158
1159 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1160 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1161 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1162 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1163 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1164 assert(G_586_GL2_US(gcr_cntl) == 0);
1165 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1166 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1167 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1168 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1169 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1170
1171 gcr_cntl &= C_586_GLM_WB &
1172 C_586_GLM_INV &
1173 C_586_GLV_INV &
1174 C_586_GL1_INV &
1175 C_586_GL2_INV &
1176 C_586_GL2_WB; /* keep SEQ */
1177
1178 si_cp_release_mem(ctx, cs, cb_db_event,
1179 S_490_GLM_WB(glm_wb) |
1180 S_490_GLM_INV(glm_inv) |
1181 S_490_GLV_INV(glv_inv) |
1182 S_490_GL1_INV(gl1_inv) |
1183 S_490_GL2_INV(gl2_inv) |
1184 S_490_GL2_WB(gl2_wb) |
1185 S_490_SEQ(gcr_seq),
1186 EOP_DST_SEL_MEM,
1187 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1188 EOP_DATA_SEL_VALUE_32BIT,
1189 ctx->wait_mem_scratch, va,
1190 ctx->wait_mem_number, SI_NOT_QUERY);
1191 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1192 WAIT_REG_MEM_EQUAL);
1193 }
1194
1195 /* Ignore fields that only modify the behavior of other fields. */
1196 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1197 /* Flush caches and wait for the caches to assert idle.
1198 * The cache flush is executed in the ME, but the PFP waits
1199 * for completion.
1200 */
1201 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1202 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1203 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1204 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1205 radeon_emit(cs, 0); /* CP_COHER_BASE */
1206 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1207 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1208 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1209 } else if (cb_db_event ||
1210 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1211 SI_CONTEXT_PS_PARTIAL_FLUSH |
1212 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1213 /* We need to ensure that PFP waits as well. */
1214 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1215 radeon_emit(cs, 0);
1216 }
1217
1218 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1219 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1220 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1221 EVENT_INDEX(0));
1222 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1223 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1224 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1225 EVENT_INDEX(0));
1226 }
1227
1228 ctx->flags = 0;
1229 }
1230
1231 void si_emit_cache_flush(struct si_context *sctx)
1232 {
1233 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1234 uint32_t flags = sctx->flags;
1235
1236 if (!sctx->has_graphics) {
1237 /* Only process compute flags. */
1238 flags &= SI_CONTEXT_INV_ICACHE |
1239 SI_CONTEXT_INV_SCACHE |
1240 SI_CONTEXT_INV_VCACHE |
1241 SI_CONTEXT_INV_L2 |
1242 SI_CONTEXT_WB_L2 |
1243 SI_CONTEXT_INV_L2_METADATA |
1244 SI_CONTEXT_CS_PARTIAL_FLUSH;
1245 }
1246
1247 uint32_t cp_coher_cntl = 0;
1248 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1249 SI_CONTEXT_FLUSH_AND_INV_DB);
1250 const bool is_barrier = flush_cb_db ||
1251 /* INV_ICACHE == beginning of gfx IB. Checking
1252 * INV_ICACHE fixes corruption for DeusExMD with
1253 * compute-based culling, but I don't know why.
1254 */
1255 flags & (SI_CONTEXT_INV_ICACHE |
1256 SI_CONTEXT_PS_PARTIAL_FLUSH |
1257 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1258 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1259 sctx->compute_is_busy);
1260
1261 assert(sctx->chip_class <= GFX9);
1262
1263 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1264 sctx->num_cb_cache_flushes++;
1265 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1266 sctx->num_db_cache_flushes++;
1267
1268 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1269 * bit is set. An alternative way is to write SQC_CACHES, but that
1270 * doesn't seem to work reliably. Since the bug doesn't affect
1271 * correctness (it only does more work than necessary) and
1272 * the performance impact is likely negligible, there is no plan
1273 * to add a workaround for it.
1274 */
1275
1276 if (flags & SI_CONTEXT_INV_ICACHE)
1277 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1278 if (flags & SI_CONTEXT_INV_SCACHE)
1279 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1280
1281 if (sctx->chip_class <= GFX8) {
1282 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1283 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1284 S_0085F0_CB0_DEST_BASE_ENA(1) |
1285 S_0085F0_CB1_DEST_BASE_ENA(1) |
1286 S_0085F0_CB2_DEST_BASE_ENA(1) |
1287 S_0085F0_CB3_DEST_BASE_ENA(1) |
1288 S_0085F0_CB4_DEST_BASE_ENA(1) |
1289 S_0085F0_CB5_DEST_BASE_ENA(1) |
1290 S_0085F0_CB6_DEST_BASE_ENA(1) |
1291 S_0085F0_CB7_DEST_BASE_ENA(1);
1292
1293 /* Necessary for DCC */
1294 if (sctx->chip_class == GFX8)
1295 si_cp_release_mem(sctx, cs,
1296 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1297 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1298 EOP_DATA_SEL_DISCARD, NULL,
1299 0, 0, SI_NOT_QUERY);
1300 }
1301 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1302 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1303 S_0085F0_DB_DEST_BASE_ENA(1);
1304 }
1305
1306 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1307 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1308 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1309 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1310 }
1311 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1312 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1313 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1314 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1315 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1316 }
1317
1318 /* Wait for shader engines to go idle.
1319 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1320 * for everything including CB/DB cache flushes.
1321 */
1322 if (!flush_cb_db) {
1323 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1324 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1325 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1326 /* Only count explicit shader flushes, not implicit ones
1327 * done by SURFACE_SYNC.
1328 */
1329 sctx->num_vs_flushes++;
1330 sctx->num_ps_flushes++;
1331 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1332 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1333 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1334 sctx->num_vs_flushes++;
1335 }
1336 }
1337
1338 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1339 sctx->compute_is_busy) {
1340 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1341 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1342 sctx->num_cs_flushes++;
1343 sctx->compute_is_busy = false;
1344 }
1345
1346 /* VGT state synchronization. */
1347 if (flags & SI_CONTEXT_VGT_FLUSH) {
1348 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1349 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1350 }
1351 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1352 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1353 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1354 }
1355
1356 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1357 * wait for idle on GFX9. We have to use a TS event.
1358 */
1359 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1360 uint64_t va;
1361 unsigned tc_flags, cb_db_event;
1362
1363 /* Set the CB/DB flush event. */
1364 switch (flush_cb_db) {
1365 case SI_CONTEXT_FLUSH_AND_INV_CB:
1366 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1367 break;
1368 case SI_CONTEXT_FLUSH_AND_INV_DB:
1369 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1370 break;
1371 default:
1372 /* both CB & DB */
1373 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1374 }
1375
1376 /* These are the only allowed combinations. If you need to
1377 * do multiple operations at once, do them separately.
1378 * All operations that invalidate L2 also seem to invalidate
1379 * metadata. Volatile (VOL) and WC flushes are not listed here.
1380 *
1381 * TC | TC_WB = writeback & invalidate L2 & L1
1382 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1383 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1384 * TC | TC_NC = invalidate L2 for MTYPE == NC
1385 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1386 * TCL1 = invalidate L1
1387 */
1388 tc_flags = 0;
1389
1390 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1391 tc_flags = EVENT_TC_ACTION_ENA |
1392 EVENT_TC_MD_ACTION_ENA;
1393 }
1394
1395 /* Ideally flush TC together with CB/DB. */
1396 if (flags & SI_CONTEXT_INV_L2) {
1397 /* Writeback and invalidate everything in L2 & L1. */
1398 tc_flags = EVENT_TC_ACTION_ENA |
1399 EVENT_TC_WB_ACTION_ENA;
1400
1401 /* Clear the flags. */
1402 flags &= ~(SI_CONTEXT_INV_L2 |
1403 SI_CONTEXT_WB_L2 |
1404 SI_CONTEXT_INV_VCACHE);
1405 sctx->num_L2_invalidates++;
1406 }
1407
1408 /* Do the flush (enqueue the event and wait for it). */
1409 va = sctx->wait_mem_scratch->gpu_address;
1410 sctx->wait_mem_number++;
1411
1412 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1413 EOP_DST_SEL_MEM,
1414 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1415 EOP_DATA_SEL_VALUE_32BIT,
1416 sctx->wait_mem_scratch, va,
1417 sctx->wait_mem_number, SI_NOT_QUERY);
1418 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1419 WAIT_REG_MEM_EQUAL);
1420 }
1421
1422 /* Make sure ME is idle (it executes most packets) before continuing.
1423 * This prevents read-after-write hazards between PFP and ME.
1424 */
1425 if (sctx->has_graphics &&
1426 (cp_coher_cntl ||
1427 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1428 SI_CONTEXT_INV_VCACHE |
1429 SI_CONTEXT_INV_L2 |
1430 SI_CONTEXT_WB_L2)))) {
1431 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1432 radeon_emit(cs, 0);
1433 }
1434
1435 /* GFX6-GFX8 only:
1436 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1437 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1438 *
1439 * cp_coher_cntl should contain all necessary flags except TC flags
1440 * at this point.
1441 *
1442 * GFX6-GFX7 don't support L2 write-back.
1443 */
1444 if (flags & SI_CONTEXT_INV_L2 ||
1445 (sctx->chip_class <= GFX7 &&
1446 (flags & SI_CONTEXT_WB_L2))) {
1447 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1448 * WB must be set on GFX8+ when TC_ACTION is set.
1449 */
1450 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1451 S_0085F0_TC_ACTION_ENA(1) |
1452 S_0085F0_TCL1_ACTION_ENA(1) |
1453 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1454 cp_coher_cntl = 0;
1455 sctx->num_L2_invalidates++;
1456 } else {
1457 /* L1 invalidation and L2 writeback must be done separately,
1458 * because both operations can't be done together.
1459 */
1460 if (flags & SI_CONTEXT_WB_L2) {
1461 /* WB = write-back
1462 * NC = apply to non-coherent MTYPEs
1463 * (i.e. MTYPE <= 1, which is what we use everywhere)
1464 *
1465 * WB doesn't work without NC.
1466 */
1467 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1468 S_0301F0_TC_WB_ACTION_ENA(1) |
1469 S_0301F0_TC_NC_ACTION_ENA(1));
1470 cp_coher_cntl = 0;
1471 sctx->num_L2_writebacks++;
1472 }
1473 if (flags & SI_CONTEXT_INV_VCACHE) {
1474 /* Invalidate per-CU VMEM L1. */
1475 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1476 S_0085F0_TCL1_ACTION_ENA(1));
1477 cp_coher_cntl = 0;
1478 }
1479 }
1480
1481 /* If TC flushes haven't cleared this... */
1482 if (cp_coher_cntl)
1483 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1484
1485 if (is_barrier)
1486 si_prim_discard_signal_next_compute_ib_start(sctx);
1487
1488 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1489 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1490 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1491 EVENT_INDEX(0));
1492 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1493 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1494 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1495 EVENT_INDEX(0));
1496 }
1497
1498 sctx->flags = 0;
1499 }
1500
1501 static void si_get_draw_start_count(struct si_context *sctx,
1502 const struct pipe_draw_info *info,
1503 unsigned *start, unsigned *count)
1504 {
1505 struct pipe_draw_indirect_info *indirect = info->indirect;
1506
1507 if (indirect) {
1508 unsigned indirect_count;
1509 struct pipe_transfer *transfer;
1510 unsigned begin, end;
1511 unsigned map_size;
1512 unsigned *data;
1513
1514 if (indirect->indirect_draw_count) {
1515 data = pipe_buffer_map_range(&sctx->b,
1516 indirect->indirect_draw_count,
1517 indirect->indirect_draw_count_offset,
1518 sizeof(unsigned),
1519 PIPE_TRANSFER_READ, &transfer);
1520
1521 indirect_count = *data;
1522
1523 pipe_buffer_unmap(&sctx->b, transfer);
1524 } else {
1525 indirect_count = indirect->draw_count;
1526 }
1527
1528 if (!indirect_count) {
1529 *start = *count = 0;
1530 return;
1531 }
1532
1533 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1534 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1535 indirect->offset, map_size,
1536 PIPE_TRANSFER_READ, &transfer);
1537
1538 begin = UINT_MAX;
1539 end = 0;
1540
1541 for (unsigned i = 0; i < indirect_count; ++i) {
1542 unsigned count = data[0];
1543 unsigned start = data[2];
1544
1545 if (count > 0) {
1546 begin = MIN2(begin, start);
1547 end = MAX2(end, start + count);
1548 }
1549
1550 data += indirect->stride / sizeof(unsigned);
1551 }
1552
1553 pipe_buffer_unmap(&sctx->b, transfer);
1554
1555 if (begin < end) {
1556 *start = begin;
1557 *count = end - begin;
1558 } else {
1559 *start = *count = 0;
1560 }
1561 } else {
1562 *start = info->start;
1563 *count = info->count;
1564 }
1565 }
1566
1567 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1568 enum pipe_prim_type prim, unsigned instance_count,
1569 bool primitive_restart, unsigned skip_atom_mask)
1570 {
1571 unsigned num_patches = 0;
1572
1573 si_emit_rasterizer_prim_state(sctx);
1574 if (sctx->tes_shader.cso)
1575 si_emit_derived_tess_state(sctx, info, &num_patches);
1576
1577 /* Emit state atoms. */
1578 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1579 while (mask)
1580 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1581
1582 sctx->dirty_atoms &= skip_atom_mask;
1583
1584 /* Emit states. */
1585 mask = sctx->dirty_states;
1586 while (mask) {
1587 unsigned i = u_bit_scan(&mask);
1588 struct si_pm4_state *state = sctx->queued.array[i];
1589
1590 if (!state || sctx->emitted.array[i] == state)
1591 continue;
1592
1593 si_pm4_emit(sctx, state);
1594 sctx->emitted.array[i] = state;
1595 }
1596 sctx->dirty_states = 0;
1597
1598 /* Emit draw states. */
1599 si_emit_vs_state(sctx, info);
1600 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1601 primitive_restart);
1602 }
1603
1604 static bool
1605 si_all_vs_resources_read_only(struct si_context *sctx,
1606 struct pipe_resource *indexbuf)
1607 {
1608 struct radeon_winsys *ws = sctx->ws;
1609 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1610
1611 /* Index buffer. */
1612 if (indexbuf &&
1613 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1614 RADEON_USAGE_WRITE))
1615 goto has_write_reference;
1616
1617 /* Vertex buffers. */
1618 struct si_vertex_elements *velems = sctx->vertex_elements;
1619 unsigned num_velems = velems->count;
1620
1621 for (unsigned i = 0; i < num_velems; i++) {
1622 if (!((1 << i) & velems->first_vb_use_mask))
1623 continue;
1624
1625 unsigned vb_index = velems->vertex_buffer_index[i];
1626 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1627 if (!res)
1628 continue;
1629
1630 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1631 RADEON_USAGE_WRITE))
1632 goto has_write_reference;
1633 }
1634
1635 /* Constant and shader buffers. */
1636 struct si_descriptors *buffers =
1637 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1638 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1639 unsigned index = buffers->first_active_slot + i;
1640 struct pipe_resource *res =
1641 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1642 if (!res)
1643 continue;
1644
1645 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1646 RADEON_USAGE_WRITE))
1647 goto has_write_reference;
1648 }
1649
1650 /* Samplers. */
1651 struct si_shader_selector *vs = sctx->vs_shader.cso;
1652 if (vs->info.samplers_declared) {
1653 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1654
1655 for (unsigned i = 0; i < num_samplers; i++) {
1656 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1657 if (!view)
1658 continue;
1659
1660 if (ws->cs_is_buffer_referenced(cs,
1661 si_resource(view->texture)->buf,
1662 RADEON_USAGE_WRITE))
1663 goto has_write_reference;
1664 }
1665 }
1666
1667 /* Images. */
1668 if (vs->info.images_declared) {
1669 unsigned num_images = util_last_bit(vs->info.images_declared);
1670
1671 for (unsigned i = 0; i < num_images; i++) {
1672 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1673 if (!res)
1674 continue;
1675
1676 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1677 RADEON_USAGE_WRITE))
1678 goto has_write_reference;
1679 }
1680 }
1681
1682 return true;
1683
1684 has_write_reference:
1685 /* If the current gfx IB has enough packets, flush it to remove write
1686 * references to buffers.
1687 */
1688 if (cs->prev_dw + cs->current.cdw > 2048) {
1689 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1690 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1691 return true;
1692 }
1693 return false;
1694 }
1695
1696 static ALWAYS_INLINE bool pd_msg(const char *s)
1697 {
1698 if (SI_PRIM_DISCARD_DEBUG)
1699 printf("PD failed: %s\n", s);
1700 return false;
1701 }
1702
1703 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1704 {
1705 struct si_context *sctx = (struct si_context *)ctx;
1706 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1707 struct pipe_resource *indexbuf = info->index.resource;
1708 unsigned dirty_tex_counter, dirty_buf_counter;
1709 enum pipe_prim_type rast_prim, prim = info->mode;
1710 unsigned index_size = info->index_size;
1711 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1712 unsigned instance_count = info->instance_count;
1713 bool primitive_restart = info->primitive_restart &&
1714 (!sctx->screen->options.prim_restart_tri_strips_only ||
1715 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1716 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1717
1718 if (likely(!info->indirect)) {
1719 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1720 * no workaround for indirect draws, but we can at least skip
1721 * direct draws.
1722 */
1723 if (unlikely(!instance_count))
1724 return;
1725
1726 /* Handle count == 0. */
1727 if (unlikely(!info->count &&
1728 (index_size || !info->count_from_stream_output)))
1729 return;
1730 }
1731
1732 if (unlikely(!sctx->vs_shader.cso ||
1733 !rs ||
1734 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1735 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1736 assert(0);
1737 return;
1738 }
1739
1740 /* Recompute and re-emit the texture resource states if needed. */
1741 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1742 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1743 sctx->last_dirty_tex_counter = dirty_tex_counter;
1744 sctx->framebuffer.dirty_cbufs |=
1745 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1746 sctx->framebuffer.dirty_zsbuf = true;
1747 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1748 si_update_all_texture_descriptors(sctx);
1749 }
1750
1751 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1752 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1753 sctx->last_dirty_buf_counter = dirty_buf_counter;
1754 /* Rebind all buffers unconditionally. */
1755 si_rebind_buffer(sctx, NULL);
1756 }
1757
1758 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1759
1760 /* Set the rasterization primitive type.
1761 *
1762 * This must be done after si_decompress_textures, which can call
1763 * draw_vbo recursively, and before si_update_shaders, which uses
1764 * current_rast_prim for this draw_vbo call. */
1765 if (sctx->gs_shader.cso)
1766 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1767 else if (sctx->tes_shader.cso) {
1768 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1769 rast_prim = PIPE_PRIM_POINTS;
1770 else
1771 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1772 } else
1773 rast_prim = prim;
1774
1775 if (rast_prim != sctx->current_rast_prim) {
1776 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1777 util_prim_is_points_or_lines(rast_prim))
1778 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1779
1780 sctx->current_rast_prim = rast_prim;
1781 sctx->do_update_shaders = true;
1782 }
1783
1784 if (sctx->tes_shader.cso &&
1785 sctx->screen->has_ls_vgpr_init_bug) {
1786 /* Determine whether the LS VGPR fix should be applied.
1787 *
1788 * It is only required when num input CPs > num output CPs,
1789 * which cannot happen with the fixed function TCS. We should
1790 * also update this bit when switching from TCS to fixed
1791 * function TCS.
1792 */
1793 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1794 bool ls_vgpr_fix =
1795 tcs &&
1796 info->vertices_per_patch >
1797 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1798
1799 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1800 sctx->ls_vgpr_fix = ls_vgpr_fix;
1801 sctx->do_update_shaders = true;
1802 }
1803 }
1804
1805 if (sctx->gs_shader.cso) {
1806 /* Determine whether the GS triangle strip adjacency fix should
1807 * be applied. Rotate every other triangle if
1808 * - triangle strips with adjacency are fed to the GS and
1809 * - primitive restart is disabled (the rotation doesn't help
1810 * when the restart occurs after an odd number of triangles).
1811 */
1812 bool gs_tri_strip_adj_fix =
1813 !sctx->tes_shader.cso &&
1814 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1815 !primitive_restart;
1816
1817 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1818 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1819 sctx->do_update_shaders = true;
1820 }
1821 }
1822
1823 if (index_size) {
1824 /* Translate or upload, if needed. */
1825 /* 8-bit indices are supported on GFX8. */
1826 if (sctx->chip_class <= GFX7 && index_size == 1) {
1827 unsigned start, count, start_offset, size, offset;
1828 void *ptr;
1829
1830 si_get_draw_start_count(sctx, info, &start, &count);
1831 start_offset = start * 2;
1832 size = count * 2;
1833
1834 indexbuf = NULL;
1835 u_upload_alloc(ctx->stream_uploader, start_offset,
1836 size,
1837 si_optimal_tcc_alignment(sctx, size),
1838 &offset, &indexbuf, &ptr);
1839 if (!indexbuf)
1840 return;
1841
1842 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1843 index_offset + start,
1844 count, ptr);
1845
1846 /* info->start will be added by the drawing code */
1847 index_offset = offset - start_offset;
1848 index_size = 2;
1849 } else if (info->has_user_indices) {
1850 unsigned start_offset;
1851
1852 assert(!info->indirect);
1853 start_offset = info->start * index_size;
1854
1855 indexbuf = NULL;
1856 u_upload_data(ctx->stream_uploader, start_offset,
1857 info->count * index_size,
1858 sctx->screen->info.tcc_cache_line_size,
1859 (char*)info->index.user + start_offset,
1860 &index_offset, &indexbuf);
1861 if (!indexbuf)
1862 return;
1863
1864 /* info->start will be added by the drawing code */
1865 index_offset -= start_offset;
1866 } else if (sctx->chip_class <= GFX7 &&
1867 si_resource(indexbuf)->TC_L2_dirty) {
1868 /* GFX8 reads index buffers through TC L2, so it doesn't
1869 * need this. */
1870 sctx->flags |= SI_CONTEXT_WB_L2;
1871 si_resource(indexbuf)->TC_L2_dirty = false;
1872 }
1873 }
1874
1875 bool dispatch_prim_discard_cs = false;
1876 bool prim_discard_cs_instancing = false;
1877 unsigned original_index_size = index_size;
1878 unsigned direct_count = 0;
1879
1880 if (info->indirect) {
1881 struct pipe_draw_indirect_info *indirect = info->indirect;
1882
1883 /* Add the buffer size for memory checking in need_cs_space. */
1884 si_context_add_resource_size(sctx, indirect->buffer);
1885
1886 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1887 if (sctx->chip_class <= GFX8) {
1888 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1889 sctx->flags |= SI_CONTEXT_WB_L2;
1890 si_resource(indirect->buffer)->TC_L2_dirty = false;
1891 }
1892
1893 if (indirect->indirect_draw_count &&
1894 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1895 sctx->flags |= SI_CONTEXT_WB_L2;
1896 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1897 }
1898 }
1899 } else {
1900 /* Multiply by 3 for strips and fans to get an approximate vertex
1901 * count as triangles. */
1902 direct_count = info->count * instance_count *
1903 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1904 }
1905
1906 /* Determine if we can use the primitive discard compute shader. */
1907 if (si_compute_prim_discard_enabled(sctx) &&
1908 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1909 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1910 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1911 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1912 (primitive_restart ?
1913 /* Supported prim types with primitive restart: */
1914 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1915 /* Disallow instancing with primitive restart: */
1916 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1917 /* Supported prim types without primitive restart + allow instancing: */
1918 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1919 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1920 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1921 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1922 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1923 (instance_count == 1 ||
1924 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1925 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1926 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1927 (!sctx->render_cond || pd_msg("render condition")) &&
1928 /* Forced enablement ignores pipeline statistics queries. */
1929 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1930 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1931 pd_msg("pipestat or primgen query")) &&
1932 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1933 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1934 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1935 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1936 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1937 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1938 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1939 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1940 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1941 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1942 !sctx->vs_shader.cso->so.num_outputs &&
1943 #else
1944 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1945 #endif
1946 /* Check that all buffers are used for read only, because compute
1947 * dispatches can run ahead. */
1948 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1949 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1950 case SI_PRIM_DISCARD_ENABLED:
1951 original_index_size = index_size;
1952 prim_discard_cs_instancing = instance_count > 1;
1953 dispatch_prim_discard_cs = true;
1954
1955 /* The compute shader changes/lowers the following: */
1956 prim = PIPE_PRIM_TRIANGLES;
1957 index_size = 4;
1958 instance_count = 1;
1959 primitive_restart = false;
1960 sctx->compute_num_verts_rejected -= direct_count;
1961 sctx->compute_num_verts_accepted += direct_count;
1962 break;
1963 case SI_PRIM_DISCARD_DISABLED:
1964 break;
1965 case SI_PRIM_DISCARD_DRAW_SPLIT:
1966 sctx->compute_num_verts_rejected -= direct_count;
1967 goto return_cleanup;
1968 }
1969 }
1970
1971 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1972 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1973 sctx->do_update_shaders = true;
1974 }
1975
1976 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1977 goto return_cleanup;
1978
1979 si_need_gfx_cs_space(sctx);
1980
1981 if (sctx->bo_list_add_all_gfx_resources)
1982 si_gfx_resources_add_all_to_bo_list(sctx);
1983
1984 /* Since we've called si_context_add_resource_size for vertex buffers,
1985 * this must be called after si_need_cs_space, because we must let
1986 * need_cs_space flush before we add buffers to the buffer list.
1987 */
1988 if (!si_upload_vertex_buffer_descriptors(sctx))
1989 goto return_cleanup;
1990
1991 /* Vega10/Raven scissor bug workaround. When any context register is
1992 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1993 * registers must be written too.
1994 */
1995 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1996 unsigned masked_atoms = 0;
1997
1998 if (has_gfx9_scissor_bug) {
1999 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2000
2001 if (info->count_from_stream_output ||
2002 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2003 sctx->dirty_states & si_states_that_always_roll_context())
2004 sctx->context_roll = true;
2005 }
2006
2007 /* Use optimal packet order based on whether we need to sync the pipeline. */
2008 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2009 SI_CONTEXT_FLUSH_AND_INV_DB |
2010 SI_CONTEXT_PS_PARTIAL_FLUSH |
2011 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2012 /* If we have to wait for idle, set all states first, so that all
2013 * SET packets are processed in parallel with previous draw calls.
2014 * Then draw and prefetch at the end. This ensures that the time
2015 * the CUs are idle is very short.
2016 */
2017 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2018 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2019
2020 if (!si_upload_graphics_shader_descriptors(sctx))
2021 goto return_cleanup;
2022
2023 /* Emit all states except possibly render condition. */
2024 si_emit_all_states(sctx, info, prim, instance_count,
2025 primitive_restart, masked_atoms);
2026 sctx->emit_cache_flush(sctx);
2027 /* <-- CUs are idle here. */
2028
2029 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2030 sctx->atoms.s.render_cond.emit(sctx);
2031
2032 if (has_gfx9_scissor_bug &&
2033 (sctx->context_roll ||
2034 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2035 sctx->atoms.s.scissors.emit(sctx);
2036
2037 sctx->dirty_atoms = 0;
2038
2039 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2040 instance_count, dispatch_prim_discard_cs,
2041 original_index_size);
2042 /* <-- CUs are busy here. */
2043
2044 /* Start prefetches after the draw has been started. Both will run
2045 * in parallel, but starting the draw first is more important.
2046 */
2047 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2048 cik_emit_prefetch_L2(sctx, false);
2049 } else {
2050 /* If we don't wait for idle, start prefetches first, then set
2051 * states, and draw at the end.
2052 */
2053 if (sctx->flags)
2054 sctx->emit_cache_flush(sctx);
2055
2056 /* Only prefetch the API VS and VBO descriptors. */
2057 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2058 cik_emit_prefetch_L2(sctx, true);
2059
2060 if (!si_upload_graphics_shader_descriptors(sctx))
2061 goto return_cleanup;
2062
2063 si_emit_all_states(sctx, info, prim, instance_count,
2064 primitive_restart, masked_atoms);
2065
2066 if (has_gfx9_scissor_bug &&
2067 (sctx->context_roll ||
2068 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2069 sctx->atoms.s.scissors.emit(sctx);
2070
2071 sctx->dirty_atoms = 0;
2072
2073 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2074 instance_count, dispatch_prim_discard_cs,
2075 original_index_size);
2076
2077 /* Prefetch the remaining shaders after the draw has been
2078 * started. */
2079 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2080 cik_emit_prefetch_L2(sctx, false);
2081 }
2082
2083 /* Clear the context roll flag after the draw call. */
2084 sctx->context_roll = false;
2085
2086 if (unlikely(sctx->current_saved_cs)) {
2087 si_trace_emit(sctx);
2088 si_log_draw_state(sctx, sctx->log);
2089 }
2090
2091 /* Workaround for a VGT hang when streamout is enabled.
2092 * It must be done after drawing. */
2093 if ((sctx->family == CHIP_HAWAII ||
2094 sctx->family == CHIP_TONGA ||
2095 sctx->family == CHIP_FIJI) &&
2096 si_get_strmout_en(sctx)) {
2097 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2098 }
2099
2100 if (unlikely(sctx->decompression_enabled)) {
2101 sctx->num_decompress_calls++;
2102 } else {
2103 sctx->num_draw_calls++;
2104 if (sctx->framebuffer.state.nr_cbufs > 1)
2105 sctx->num_mrt_draw_calls++;
2106 if (primitive_restart)
2107 sctx->num_prim_restart_calls++;
2108 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2109 sctx->num_spill_draw_calls++;
2110 }
2111
2112 return_cleanup:
2113 if (index_size && indexbuf != info->index.resource)
2114 pipe_resource_reference(&indexbuf, NULL);
2115 }
2116
2117 static void
2118 si_draw_rectangle(struct blitter_context *blitter,
2119 void *vertex_elements_cso,
2120 blitter_get_vs_func get_vs,
2121 int x1, int y1, int x2, int y2,
2122 float depth, unsigned num_instances,
2123 enum blitter_attrib_type type,
2124 const union blitter_attrib *attrib)
2125 {
2126 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2127 struct si_context *sctx = (struct si_context*)pipe;
2128
2129 /* Pack position coordinates as signed int16. */
2130 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2131 ((uint32_t)(y1 & 0xffff) << 16);
2132 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2133 ((uint32_t)(y2 & 0xffff) << 16);
2134 sctx->vs_blit_sh_data[2] = fui(depth);
2135
2136 switch (type) {
2137 case UTIL_BLITTER_ATTRIB_COLOR:
2138 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2139 sizeof(float)*4);
2140 break;
2141 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2142 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2143 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2144 sizeof(attrib->texcoord));
2145 break;
2146 case UTIL_BLITTER_ATTRIB_NONE:;
2147 }
2148
2149 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2150
2151 struct pipe_draw_info info = {};
2152 info.mode = SI_PRIM_RECTANGLE_LIST;
2153 info.count = 3;
2154 info.instance_count = num_instances;
2155
2156 /* Don't set per-stage shader pointers for VS. */
2157 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2158 sctx->vertex_buffer_pointer_dirty = false;
2159
2160 si_draw_vbo(pipe, &info);
2161 }
2162
2163 void si_trace_emit(struct si_context *sctx)
2164 {
2165 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2166 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2167
2168 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2169 0, 4, V_370_MEM, V_370_ME, &trace_id);
2170
2171 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2172 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2173
2174 if (sctx->log)
2175 u_log_flush(sctx->log);
2176 }
2177
2178 void si_init_draw_functions(struct si_context *sctx)
2179 {
2180 sctx->b.draw_vbo = si_draw_vbo;
2181
2182 sctx->blitter->draw_rectangle = si_draw_rectangle;
2183
2184 si_init_ia_multi_vgt_param_table(sctx);
2185 }