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radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when available
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static bool si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_cmdbuf *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return false;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = ls->lshs_vertex_stride;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While CIK can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance.
169 * The hardware can do more, but the radeonsi shader constant is
170 * limited to 6 bits.
171 */
172 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
173
174 /* When distributed tessellation is unsupported, switch between SEs
175 * at a higher frequency to compensate for it.
176 */
177 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
178 *num_patches = MIN2(*num_patches, 16); /* recommended */
179
180 /* Make sure that vector lanes are reasonably occupied. It probably
181 * doesn't matter much because this is LS-HS, and TES is likely to
182 * occupy significantly more CUs.
183 */
184 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
185 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
186 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
187
188 if (sctx->chip_class == SI) {
189 /* SI bug workaround, related to power management. Limit LS-HS
190 * threadgroups to only one wave.
191 */
192 unsigned one_wave = 64 / max_verts_per_patch;
193 *num_patches = MIN2(*num_patches, one_wave);
194 }
195
196 /* The VGT HS block increments the patch ID unconditionally
197 * within a single threadgroup. This results in incorrect
198 * patch IDs when instanced draws are used.
199 *
200 * The intended solution is to restrict threadgroups to
201 * a single instance by setting SWITCH_ON_EOI, which
202 * should cause IA to split instances up. However, this
203 * doesn't work correctly on SI when there is no other
204 * SE to switch to.
205 */
206 if (has_primid_instancing_bug && tess_uses_primid)
207 *num_patches = 1;
208
209 sctx->last_num_patches = *num_patches;
210
211 output_patch0_offset = input_patch_size * *num_patches;
212 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
213
214 /* Compute userdata SGPRs. */
215 assert(((input_vertex_size / 4) & ~0xff) == 0);
216 assert(((output_vertex_size / 4) & ~0xff) == 0);
217 assert(((input_patch_size / 4) & ~0x1fff) == 0);
218 assert(((output_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
220 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
221 assert(num_tcs_input_cp <= 32);
222 assert(num_tcs_output_cp <= 32);
223
224 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
225 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
226
227 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
228 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
229 tcs_out_layout = (output_patch_size / 4) |
230 (num_tcs_input_cp << 13) |
231 ring_va;
232 tcs_out_offsets = (output_patch0_offset / 16) |
233 ((perpatch_output_offset / 16) << 16);
234 offchip_layout = *num_patches |
235 (num_tcs_output_cp << 6) |
236 (pervertex_output_patch_size * *num_patches << 12);
237
238 /* Compute the LDS size. */
239 lds_size = output_patch0_offset + output_patch_size * *num_patches;
240
241 if (sctx->chip_class >= CIK) {
242 assert(lds_size <= 65536);
243 lds_size = align(lds_size, 512) / 512;
244 } else {
245 assert(lds_size <= 32768);
246 lds_size = align(lds_size, 256) / 256;
247 }
248
249 /* Set SI_SGPR_VS_STATE_BITS. */
250 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
251 C_VS_STATE_LS_OUT_VERTEX_SIZE;
252 sctx->current_vs_state |= tcs_in_layout;
253
254 if (sctx->chip_class >= GFX9) {
255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
256 S_00B42C_LDS_SIZE(lds_size);
257
258 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
259
260 /* Set userdata SGPRs for merged LS-HS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
263 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout);
267 } else {
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
269
270 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
271 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
272
273 /* Due to a hw bug, RSRC2_LS must be written twice with another
274 * LS register written in between. */
275 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
276 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
280
281 /* Set userdata SGPRs for TCS. */
282 radeon_set_sh_reg_seq(cs,
283 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout);
287 radeon_emit(cs, tcs_in_layout);
288 }
289
290 /* Set userdata SGPRs for TES. */
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
292 radeon_emit(cs, offchip_layout);
293 radeon_emit(cs, ring_va);
294
295 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
296 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
297 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
298
299 if (sctx->last_ls_hs_config != ls_hs_config) {
300 if (sctx->chip_class >= CIK) {
301 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
302 ls_hs_config);
303 } else {
304 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
305 ls_hs_config);
306 }
307 sctx->last_ls_hs_config = ls_hs_config;
308 return true; /* true if the context rolls */
309 }
310 return false;
311 }
312
313 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
314 {
315 switch (info->mode) {
316 case PIPE_PRIM_PATCHES:
317 return info->count / info->vertices_per_patch;
318 case SI_PRIM_RECTANGLE_LIST:
319 return info->count / 3;
320 default:
321 return u_prims_for_vertices(info->mode, info->count);
322 }
323 }
324
325 static unsigned
326 si_get_init_multi_vgt_param(struct si_screen *sscreen,
327 union si_vgt_param_key *key)
328 {
329 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
330 unsigned max_primgroup_in_wave = 2;
331
332 /* SWITCH_ON_EOP(0) is always preferable. */
333 bool wd_switch_on_eop = false;
334 bool ia_switch_on_eop = false;
335 bool ia_switch_on_eoi = false;
336 bool partial_vs_wave = false;
337 bool partial_es_wave = false;
338
339 if (key->u.uses_tess) {
340 /* SWITCH_ON_EOI must be set if PrimID is used. */
341 if (key->u.tess_uses_prim_id)
342 ia_switch_on_eoi = true;
343
344 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
345 if ((sscreen->info.family == CHIP_TAHITI ||
346 sscreen->info.family == CHIP_PITCAIRN ||
347 sscreen->info.family == CHIP_BONAIRE) &&
348 key->u.uses_gs)
349 partial_vs_wave = true;
350
351 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
352 if (sscreen->has_distributed_tess) {
353 if (key->u.uses_gs) {
354 if (sscreen->info.chip_class <= VI)
355 partial_es_wave = true;
356
357 /* GPU hang workaround. */
358 if (sscreen->info.family == CHIP_TONGA ||
359 sscreen->info.family == CHIP_FIJI ||
360 sscreen->info.family == CHIP_POLARIS10 ||
361 sscreen->info.family == CHIP_POLARIS11 ||
362 sscreen->info.family == CHIP_POLARIS12 ||
363 sscreen->info.family == CHIP_VEGAM)
364 partial_vs_wave = true;
365 } else {
366 partial_vs_wave = true;
367 }
368 }
369 }
370
371 /* This is a hardware requirement. */
372 if (key->u.line_stipple_enabled ||
373 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
374 ia_switch_on_eop = true;
375 wd_switch_on_eop = true;
376 }
377
378 if (sscreen->info.chip_class >= CIK) {
379 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
380 * 4 shader engines. Set 1 to pass the assertion below.
381 * The other cases are hardware requirements.
382 *
383 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
384 * for points, line strips, and tri strips.
385 */
386 if (sscreen->info.max_se <= 2 ||
387 key->u.prim == PIPE_PRIM_POLYGON ||
388 key->u.prim == PIPE_PRIM_LINE_LOOP ||
389 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
390 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
391 (key->u.primitive_restart &&
392 (sscreen->info.family < CHIP_POLARIS10 ||
393 (key->u.prim != PIPE_PRIM_POINTS &&
394 key->u.prim != PIPE_PRIM_LINE_STRIP &&
395 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
396 key->u.count_from_stream_output)
397 wd_switch_on_eop = true;
398
399 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
400 * We don't know that for indirect drawing, so treat it as
401 * always problematic. */
402 if (sscreen->info.family == CHIP_HAWAII &&
403 key->u.uses_instancing)
404 wd_switch_on_eop = true;
405
406 /* Performance recommendation for 4 SE Gfx7-8 parts if
407 * instances are smaller than a primgroup.
408 * Assume indirect draws always use small instances.
409 * This is needed for good VS wave utilization.
410 */
411 if (sscreen->info.chip_class <= VI &&
412 sscreen->info.max_se == 4 &&
413 key->u.multi_instances_smaller_than_primgroup)
414 wd_switch_on_eop = true;
415
416 /* Required on CIK and later. */
417 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
418 ia_switch_on_eoi = true;
419
420 /* Required by Hawaii and, for some special cases, by VI. */
421 if (ia_switch_on_eoi &&
422 (sscreen->info.family == CHIP_HAWAII ||
423 (sscreen->info.chip_class == VI &&
424 (key->u.uses_gs || max_primgroup_in_wave != 2))))
425 partial_vs_wave = true;
426
427 /* Instancing bug on Bonaire. */
428 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
429 key->u.uses_instancing)
430 partial_vs_wave = true;
431
432 /* This only applies to Polaris10 and later 4 SE chips.
433 * wd_switch_on_eop is already true on all other chips.
434 */
435 if (!wd_switch_on_eop && key->u.primitive_restart)
436 partial_vs_wave = true;
437
438 /* If the WD switch is false, the IA switch must be false too. */
439 assert(wd_switch_on_eop || !ia_switch_on_eop);
440 }
441
442 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
443 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
444 partial_es_wave = true;
445
446 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
447 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
448 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
449 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
450 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
451 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
452 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
453 max_primgroup_in_wave : 0) |
454 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
455 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
456 }
457
458 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
459 {
460 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
461 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
462 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
463 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
464 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
465 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
466 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
467 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
468 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
469 union si_vgt_param_key key;
470
471 key.index = 0;
472 key.u.prim = prim;
473 key.u.uses_instancing = uses_instancing;
474 key.u.multi_instances_smaller_than_primgroup = multi_instances;
475 key.u.primitive_restart = primitive_restart;
476 key.u.count_from_stream_output = count_from_so;
477 key.u.line_stipple_enabled = line_stipple;
478 key.u.uses_tess = uses_tess;
479 key.u.tess_uses_prim_id = tess_uses_primid;
480 key.u.uses_gs = uses_gs;
481
482 sctx->ia_multi_vgt_param[key.index] =
483 si_get_init_multi_vgt_param(sctx->screen, &key);
484 }
485 }
486
487 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
488 const struct pipe_draw_info *info,
489 unsigned num_patches)
490 {
491 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
492 unsigned primgroup_size;
493 unsigned ia_multi_vgt_param;
494
495 if (sctx->tes_shader.cso) {
496 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
497 } else if (sctx->gs_shader.cso) {
498 primgroup_size = 64; /* recommended with a GS */
499 } else {
500 primgroup_size = 128; /* recommended without a GS and tess */
501 }
502
503 key.u.prim = info->mode;
504 key.u.uses_instancing = info->indirect || info->instance_count > 1;
505 key.u.multi_instances_smaller_than_primgroup =
506 info->indirect ||
507 (info->instance_count > 1 &&
508 (info->count_from_stream_output ||
509 si_num_prims_for_vertices(info) < primgroup_size));
510 key.u.primitive_restart = info->primitive_restart;
511 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
512
513 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
514 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
515
516 if (sctx->gs_shader.cso) {
517 /* GS requirement. */
518 if (sctx->chip_class <= VI &&
519 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
520 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
521
522 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
523 * The hw doc says all multi-SE chips are affected, but Vulkan
524 * only applies it to Hawaii. Do what Vulkan does.
525 */
526 if (sctx->family == CHIP_HAWAII &&
527 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
528 (info->indirect ||
529 (info->instance_count > 1 &&
530 (info->count_from_stream_output ||
531 si_num_prims_for_vertices(info) <= 1))))
532 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
533 }
534
535 return ia_multi_vgt_param;
536 }
537
538 /* rast_prim is the primitive type after GS. */
539 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
540 {
541 struct radeon_cmdbuf *cs = sctx->gfx_cs;
542 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
543 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
544
545 /* Skip this if not rendering lines. */
546 if (!util_prim_is_lines(rast_prim))
547 return false;
548
549 if (rast_prim == sctx->last_rast_prim &&
550 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
551 return false;
552
553 /* For lines, reset the stipple pattern at each primitive. Otherwise,
554 * reset the stipple pattern at each packet (line strips, line loops).
555 */
556 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
557 rs->pa_sc_line_stipple |
558 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
559
560 sctx->last_rast_prim = rast_prim;
561 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
562 return true; /* true if the context rolls */
563 }
564
565 static void si_emit_vs_state(struct si_context *sctx,
566 const struct pipe_draw_info *info)
567 {
568 sctx->current_vs_state &= C_VS_STATE_INDEXED;
569 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
570
571 if (sctx->num_vs_blit_sgprs) {
572 /* Re-emit the state after we leave u_blitter. */
573 sctx->last_vs_state = ~0;
574 return;
575 }
576
577 if (sctx->current_vs_state != sctx->last_vs_state) {
578 struct radeon_cmdbuf *cs = sctx->gfx_cs;
579
580 /* For the API vertex shader (VS_STATE_INDEXED). */
581 radeon_set_sh_reg(cs,
582 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
583 SI_SGPR_VS_STATE_BITS * 4,
584 sctx->current_vs_state);
585
586 /* For vertex color clamping, which is done in the last stage
587 * before the rasterizer. */
588 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
589 /* GS copy shader or TES if GS is missing. */
590 radeon_set_sh_reg(cs,
591 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
592 SI_SGPR_VS_STATE_BITS * 4,
593 sctx->current_vs_state);
594 }
595
596 sctx->last_vs_state = sctx->current_vs_state;
597 }
598 }
599
600 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
601 const struct pipe_draw_info *info)
602 {
603 return info->primitive_restart &&
604 (info->restart_index != sctx->last_restart_index ||
605 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
606 }
607
608 static void si_emit_draw_registers(struct si_context *sctx,
609 const struct pipe_draw_info *info,
610 unsigned num_patches)
611 {
612 struct radeon_cmdbuf *cs = sctx->gfx_cs;
613 unsigned prim = si_conv_pipe_prim(info->mode);
614 unsigned ia_multi_vgt_param;
615
616 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
617
618 /* Draw state. */
619 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
620 if (sctx->chip_class >= GFX9)
621 radeon_set_uconfig_reg_idx(cs, sctx->screen,
622 R_030960_IA_MULTI_VGT_PARAM, 4,
623 ia_multi_vgt_param);
624 else if (sctx->chip_class >= CIK)
625 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
626 else
627 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
628
629 sctx->last_multi_vgt_param = ia_multi_vgt_param;
630 }
631 if (prim != sctx->last_prim) {
632 if (sctx->chip_class >= CIK)
633 radeon_set_uconfig_reg_idx(cs, sctx->screen,
634 R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
635 else
636 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
637
638 sctx->last_prim = prim;
639 }
640
641 /* Primitive restart. */
642 if (info->primitive_restart != sctx->last_primitive_restart_en) {
643 if (sctx->chip_class >= GFX9)
644 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
645 info->primitive_restart);
646 else
647 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
648 info->primitive_restart);
649
650 sctx->last_primitive_restart_en = info->primitive_restart;
651
652 }
653 if (si_prim_restart_index_changed(sctx, info)) {
654 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
655 info->restart_index);
656 sctx->last_restart_index = info->restart_index;
657 }
658 }
659
660 static void si_emit_draw_packets(struct si_context *sctx,
661 const struct pipe_draw_info *info,
662 struct pipe_resource *indexbuf,
663 unsigned index_size,
664 unsigned index_offset)
665 {
666 struct pipe_draw_indirect_info *indirect = info->indirect;
667 struct radeon_cmdbuf *cs = sctx->gfx_cs;
668 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
669 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
670 uint32_t index_max_size = 0;
671 uint64_t index_va = 0;
672
673 if (info->count_from_stream_output) {
674 struct si_streamout_target *t =
675 (struct si_streamout_target*)info->count_from_stream_output;
676 uint64_t va = t->buf_filled_size->gpu_address +
677 t->buf_filled_size_offset;
678
679 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
680 t->stride_in_dw);
681
682 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
683 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
684 COPY_DATA_DST_SEL(COPY_DATA_REG) |
685 COPY_DATA_WR_CONFIRM);
686 radeon_emit(cs, va); /* src address lo */
687 radeon_emit(cs, va >> 32); /* src address hi */
688 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
689 radeon_emit(cs, 0); /* unused */
690
691 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
692 t->buf_filled_size, RADEON_USAGE_READ,
693 RADEON_PRIO_SO_FILLED_SIZE);
694 }
695
696 /* draw packet */
697 if (index_size) {
698 if (index_size != sctx->last_index_size) {
699 unsigned index_type;
700
701 /* index type */
702 switch (index_size) {
703 case 1:
704 index_type = V_028A7C_VGT_INDEX_8;
705 break;
706 case 2:
707 index_type = V_028A7C_VGT_INDEX_16 |
708 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
709 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
710 break;
711 case 4:
712 index_type = V_028A7C_VGT_INDEX_32 |
713 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
714 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
715 break;
716 default:
717 assert(!"unreachable");
718 return;
719 }
720
721 if (sctx->chip_class >= GFX9) {
722 radeon_set_uconfig_reg_idx(cs, sctx->screen,
723 R_03090C_VGT_INDEX_TYPE, 2,
724 index_type);
725 } else {
726 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
727 radeon_emit(cs, index_type);
728 }
729
730 sctx->last_index_size = index_size;
731 }
732
733 index_max_size = (indexbuf->width0 - index_offset) /
734 index_size;
735 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
736
737 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
738 r600_resource(indexbuf),
739 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
740 } else {
741 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
742 * so the state must be re-emitted before the next indexed draw.
743 */
744 if (sctx->chip_class >= CIK)
745 sctx->last_index_size = -1;
746 }
747
748 if (indirect) {
749 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
750
751 assert(indirect_va % 8 == 0);
752
753 si_invalidate_draw_sh_constants(sctx);
754
755 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
756 radeon_emit(cs, 1);
757 radeon_emit(cs, indirect_va);
758 radeon_emit(cs, indirect_va >> 32);
759
760 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
761 r600_resource(indirect->buffer),
762 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
763
764 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
765 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
766
767 assert(indirect->offset % 4 == 0);
768
769 if (index_size) {
770 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
771 radeon_emit(cs, index_va);
772 radeon_emit(cs, index_va >> 32);
773
774 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
775 radeon_emit(cs, index_max_size);
776 }
777
778 if (!sctx->screen->has_draw_indirect_multi) {
779 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
780 : PKT3_DRAW_INDIRECT,
781 3, render_cond_bit));
782 radeon_emit(cs, indirect->offset);
783 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
784 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
785 radeon_emit(cs, di_src_sel);
786 } else {
787 uint64_t count_va = 0;
788
789 if (indirect->indirect_draw_count) {
790 struct r600_resource *params_buf =
791 r600_resource(indirect->indirect_draw_count);
792
793 radeon_add_to_buffer_list(
794 sctx, sctx->gfx_cs, params_buf,
795 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
796
797 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
798 }
799
800 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
801 PKT3_DRAW_INDIRECT_MULTI,
802 8, render_cond_bit));
803 radeon_emit(cs, indirect->offset);
804 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
805 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
806 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
807 S_2C3_DRAW_INDEX_ENABLE(1) |
808 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
809 radeon_emit(cs, indirect->draw_count);
810 radeon_emit(cs, count_va);
811 radeon_emit(cs, count_va >> 32);
812 radeon_emit(cs, indirect->stride);
813 radeon_emit(cs, di_src_sel);
814 }
815 } else {
816 int base_vertex;
817
818 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
819 radeon_emit(cs, info->instance_count);
820
821 /* Base vertex and start instance. */
822 base_vertex = index_size ? info->index_bias : info->start;
823
824 if (sctx->num_vs_blit_sgprs) {
825 /* Re-emit draw constants after we leave u_blitter. */
826 si_invalidate_draw_sh_constants(sctx);
827
828 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
829 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
830 sctx->num_vs_blit_sgprs);
831 radeon_emit_array(cs, sctx->vs_blit_sh_data,
832 sctx->num_vs_blit_sgprs);
833 } else if (base_vertex != sctx->last_base_vertex ||
834 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
835 info->start_instance != sctx->last_start_instance ||
836 info->drawid != sctx->last_drawid ||
837 sh_base_reg != sctx->last_sh_base_reg) {
838 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
839 radeon_emit(cs, base_vertex);
840 radeon_emit(cs, info->start_instance);
841 radeon_emit(cs, info->drawid);
842
843 sctx->last_base_vertex = base_vertex;
844 sctx->last_start_instance = info->start_instance;
845 sctx->last_drawid = info->drawid;
846 sctx->last_sh_base_reg = sh_base_reg;
847 }
848
849 if (index_size) {
850 index_va += info->start * index_size;
851
852 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
853 radeon_emit(cs, index_max_size);
854 radeon_emit(cs, index_va);
855 radeon_emit(cs, index_va >> 32);
856 radeon_emit(cs, info->count);
857 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
858 } else {
859 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
860 radeon_emit(cs, info->count);
861 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
862 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
863 }
864 }
865 }
866
867 static void si_emit_surface_sync(struct si_context *sctx,
868 unsigned cp_coher_cntl)
869 {
870 struct radeon_cmdbuf *cs = sctx->gfx_cs;
871
872 if (sctx->chip_class >= GFX9) {
873 /* Flush caches and wait for the caches to assert idle. */
874 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
875 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
876 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
877 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
878 radeon_emit(cs, 0); /* CP_COHER_BASE */
879 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
880 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
881 } else {
882 /* ACQUIRE_MEM is only required on a compute ring. */
883 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
884 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
885 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
886 radeon_emit(cs, 0); /* CP_COHER_BASE */
887 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
888 }
889 }
890
891 void si_emit_cache_flush(struct si_context *sctx)
892 {
893 struct radeon_cmdbuf *cs = sctx->gfx_cs;
894 uint32_t flags = sctx->flags;
895 uint32_t cp_coher_cntl = 0;
896 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
897 SI_CONTEXT_FLUSH_AND_INV_DB);
898
899 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
900 sctx->num_cb_cache_flushes++;
901 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
902 sctx->num_db_cache_flushes++;
903
904 /* SI has a bug that it always flushes ICACHE and KCACHE if either
905 * bit is set. An alternative way is to write SQC_CACHES, but that
906 * doesn't seem to work reliably. Since the bug doesn't affect
907 * correctness (it only does more work than necessary) and
908 * the performance impact is likely negligible, there is no plan
909 * to add a workaround for it.
910 */
911
912 if (flags & SI_CONTEXT_INV_ICACHE)
913 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
914 if (flags & SI_CONTEXT_INV_SMEM_L1)
915 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
916
917 if (sctx->chip_class <= VI) {
918 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
919 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
920 S_0085F0_CB0_DEST_BASE_ENA(1) |
921 S_0085F0_CB1_DEST_BASE_ENA(1) |
922 S_0085F0_CB2_DEST_BASE_ENA(1) |
923 S_0085F0_CB3_DEST_BASE_ENA(1) |
924 S_0085F0_CB4_DEST_BASE_ENA(1) |
925 S_0085F0_CB5_DEST_BASE_ENA(1) |
926 S_0085F0_CB6_DEST_BASE_ENA(1) |
927 S_0085F0_CB7_DEST_BASE_ENA(1);
928
929 /* Necessary for DCC */
930 if (sctx->chip_class == VI)
931 si_cp_release_mem(sctx,
932 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
933 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
934 EOP_DATA_SEL_DISCARD, NULL,
935 0, 0, SI_NOT_QUERY);
936 }
937 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
938 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
939 S_0085F0_DB_DEST_BASE_ENA(1);
940 }
941
942 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
943 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
944 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
945 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
946 }
947 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
948 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
949 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
950 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
951 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
952 }
953
954 /* Wait for shader engines to go idle.
955 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
956 * for everything including CB/DB cache flushes.
957 */
958 if (!flush_cb_db) {
959 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
961 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
962 /* Only count explicit shader flushes, not implicit ones
963 * done by SURFACE_SYNC.
964 */
965 sctx->num_vs_flushes++;
966 sctx->num_ps_flushes++;
967 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
968 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
969 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
970 sctx->num_vs_flushes++;
971 }
972 }
973
974 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
975 sctx->compute_is_busy) {
976 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
977 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
978 sctx->num_cs_flushes++;
979 sctx->compute_is_busy = false;
980 }
981
982 /* VGT state synchronization. */
983 if (flags & SI_CONTEXT_VGT_FLUSH) {
984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
985 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
986 }
987 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
988 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
989 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
990 }
991
992 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
993 * wait for idle on GFX9. We have to use a TS event.
994 */
995 if (sctx->chip_class >= GFX9 && flush_cb_db) {
996 uint64_t va;
997 unsigned tc_flags, cb_db_event;
998
999 /* Set the CB/DB flush event. */
1000 switch (flush_cb_db) {
1001 case SI_CONTEXT_FLUSH_AND_INV_CB:
1002 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1003 break;
1004 case SI_CONTEXT_FLUSH_AND_INV_DB:
1005 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1006 break;
1007 default:
1008 /* both CB & DB */
1009 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1010 }
1011
1012 /* These are the only allowed combinations. If you need to
1013 * do multiple operations at once, do them separately.
1014 * All operations that invalidate L2 also seem to invalidate
1015 * metadata. Volatile (VOL) and WC flushes are not listed here.
1016 *
1017 * TC | TC_WB = writeback & invalidate L2 & L1
1018 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1019 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1020 * TC | TC_NC = invalidate L2 for MTYPE == NC
1021 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1022 * TCL1 = invalidate L1
1023 */
1024 tc_flags = 0;
1025
1026 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1027 tc_flags = EVENT_TC_ACTION_ENA |
1028 EVENT_TC_MD_ACTION_ENA;
1029 }
1030
1031 /* Ideally flush TC together with CB/DB. */
1032 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1033 /* Writeback and invalidate everything in L2 & L1. */
1034 tc_flags = EVENT_TC_ACTION_ENA |
1035 EVENT_TC_WB_ACTION_ENA;
1036
1037 /* Clear the flags. */
1038 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1039 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1040 SI_CONTEXT_INV_VMEM_L1);
1041 sctx->num_L2_invalidates++;
1042 }
1043
1044 /* Do the flush (enqueue the event and wait for it). */
1045 va = sctx->wait_mem_scratch->gpu_address;
1046 sctx->wait_mem_number++;
1047
1048 si_cp_release_mem(sctx, cb_db_event, tc_flags,
1049 EOP_DST_SEL_MEM,
1050 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1051 EOP_DATA_SEL_VALUE_32BIT,
1052 sctx->wait_mem_scratch, va,
1053 sctx->wait_mem_number, SI_NOT_QUERY);
1054 si_cp_wait_mem(sctx, va, sctx->wait_mem_number, 0xffffffff, 0);
1055 }
1056
1057 /* Make sure ME is idle (it executes most packets) before continuing.
1058 * This prevents read-after-write hazards between PFP and ME.
1059 */
1060 if (cp_coher_cntl ||
1061 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1062 SI_CONTEXT_INV_VMEM_L1 |
1063 SI_CONTEXT_INV_GLOBAL_L2 |
1064 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1065 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1066 radeon_emit(cs, 0);
1067 }
1068
1069 /* SI-CI-VI only:
1070 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1071 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1072 *
1073 * cp_coher_cntl should contain all necessary flags except TC flags
1074 * at this point.
1075 *
1076 * SI-CIK don't support L2 write-back.
1077 */
1078 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1079 (sctx->chip_class <= CIK &&
1080 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1081 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1082 * WB must be set on VI+ when TC_ACTION is set.
1083 */
1084 si_emit_surface_sync(sctx, cp_coher_cntl |
1085 S_0085F0_TC_ACTION_ENA(1) |
1086 S_0085F0_TCL1_ACTION_ENA(1) |
1087 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1088 cp_coher_cntl = 0;
1089 sctx->num_L2_invalidates++;
1090 } else {
1091 /* L1 invalidation and L2 writeback must be done separately,
1092 * because both operations can't be done together.
1093 */
1094 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1095 /* WB = write-back
1096 * NC = apply to non-coherent MTYPEs
1097 * (i.e. MTYPE <= 1, which is what we use everywhere)
1098 *
1099 * WB doesn't work without NC.
1100 */
1101 si_emit_surface_sync(sctx, cp_coher_cntl |
1102 S_0301F0_TC_WB_ACTION_ENA(1) |
1103 S_0301F0_TC_NC_ACTION_ENA(1));
1104 cp_coher_cntl = 0;
1105 sctx->num_L2_writebacks++;
1106 }
1107 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1108 /* Invalidate per-CU VMEM L1. */
1109 si_emit_surface_sync(sctx, cp_coher_cntl |
1110 S_0085F0_TCL1_ACTION_ENA(1));
1111 cp_coher_cntl = 0;
1112 }
1113 }
1114
1115 /* If TC flushes haven't cleared this... */
1116 if (cp_coher_cntl)
1117 si_emit_surface_sync(sctx, cp_coher_cntl);
1118
1119 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1120 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1121 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1122 EVENT_INDEX(0));
1123 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1124 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1125 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1126 EVENT_INDEX(0));
1127 }
1128
1129 sctx->flags = 0;
1130 }
1131
1132 static void si_get_draw_start_count(struct si_context *sctx,
1133 const struct pipe_draw_info *info,
1134 unsigned *start, unsigned *count)
1135 {
1136 struct pipe_draw_indirect_info *indirect = info->indirect;
1137
1138 if (indirect) {
1139 unsigned indirect_count;
1140 struct pipe_transfer *transfer;
1141 unsigned begin, end;
1142 unsigned map_size;
1143 unsigned *data;
1144
1145 if (indirect->indirect_draw_count) {
1146 data = pipe_buffer_map_range(&sctx->b,
1147 indirect->indirect_draw_count,
1148 indirect->indirect_draw_count_offset,
1149 sizeof(unsigned),
1150 PIPE_TRANSFER_READ, &transfer);
1151
1152 indirect_count = *data;
1153
1154 pipe_buffer_unmap(&sctx->b, transfer);
1155 } else {
1156 indirect_count = indirect->draw_count;
1157 }
1158
1159 if (!indirect_count) {
1160 *start = *count = 0;
1161 return;
1162 }
1163
1164 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1165 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1166 indirect->offset, map_size,
1167 PIPE_TRANSFER_READ, &transfer);
1168
1169 begin = UINT_MAX;
1170 end = 0;
1171
1172 for (unsigned i = 0; i < indirect_count; ++i) {
1173 unsigned count = data[0];
1174 unsigned start = data[2];
1175
1176 if (count > 0) {
1177 begin = MIN2(begin, start);
1178 end = MAX2(end, start + count);
1179 }
1180
1181 data += indirect->stride / sizeof(unsigned);
1182 }
1183
1184 pipe_buffer_unmap(&sctx->b, transfer);
1185
1186 if (begin < end) {
1187 *start = begin;
1188 *count = end - begin;
1189 } else {
1190 *start = *count = 0;
1191 }
1192 } else {
1193 *start = info->start;
1194 *count = info->count;
1195 }
1196 }
1197
1198 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1199 unsigned skip_atom_mask)
1200 {
1201 unsigned num_patches = 0;
1202 /* Vega10/Raven scissor bug workaround. When any context register is
1203 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1204 * registers must be written too.
1205 */
1206 bool handle_scissor_bug = (sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1207 !si_is_atom_dirty(sctx, &sctx->atoms.s.scissors);
1208 bool context_roll = false; /* set correctly for GFX9 only */
1209
1210 context_roll |= si_emit_rasterizer_prim_state(sctx);
1211 if (sctx->tes_shader.cso)
1212 context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
1213
1214 if (handle_scissor_bug &&
1215 (info->count_from_stream_output ||
1216 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1217 sctx->dirty_states & si_states_that_always_roll_context() ||
1218 si_prim_restart_index_changed(sctx, info)))
1219 context_roll = true;
1220
1221 sctx->context_roll_counter = 0;
1222
1223 /* Emit state atoms. */
1224 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1225 while (mask)
1226 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1227
1228 sctx->dirty_atoms &= skip_atom_mask;
1229
1230 /* Emit states. */
1231 mask = sctx->dirty_states;
1232 while (mask) {
1233 unsigned i = u_bit_scan(&mask);
1234 struct si_pm4_state *state = sctx->queued.array[i];
1235
1236 if (!state || sctx->emitted.array[i] == state)
1237 continue;
1238
1239 si_pm4_emit(sctx, state);
1240 sctx->emitted.array[i] = state;
1241 }
1242 sctx->dirty_states = 0;
1243
1244 if (handle_scissor_bug &&
1245 (context_roll || sctx->context_roll_counter)) {
1246 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1247 sctx->atoms.s.scissors.emit(sctx);
1248 }
1249
1250 /* Emit draw states. */
1251 si_emit_vs_state(sctx, info);
1252 si_emit_draw_registers(sctx, info, num_patches);
1253 }
1254
1255 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1256 {
1257 struct si_context *sctx = (struct si_context *)ctx;
1258 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1259 struct pipe_resource *indexbuf = info->index.resource;
1260 unsigned dirty_tex_counter;
1261 enum pipe_prim_type rast_prim;
1262 unsigned index_size = info->index_size;
1263 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1264
1265 if (likely(!info->indirect)) {
1266 /* SI-CI treat instance_count==0 as instance_count==1. There is
1267 * no workaround for indirect draws, but we can at least skip
1268 * direct draws.
1269 */
1270 if (unlikely(!info->instance_count))
1271 return;
1272
1273 /* Handle count == 0. */
1274 if (unlikely(!info->count &&
1275 (index_size || !info->count_from_stream_output)))
1276 return;
1277 }
1278
1279 if (unlikely(!sctx->vs_shader.cso ||
1280 !rs ||
1281 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1282 (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
1283 assert(0);
1284 return;
1285 }
1286
1287 /* Recompute and re-emit the texture resource states if needed. */
1288 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1289 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1290 sctx->last_dirty_tex_counter = dirty_tex_counter;
1291 sctx->framebuffer.dirty_cbufs |=
1292 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1293 sctx->framebuffer.dirty_zsbuf = true;
1294 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1295 si_update_all_texture_descriptors(sctx);
1296 }
1297
1298 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1299
1300 /* Set the rasterization primitive type.
1301 *
1302 * This must be done after si_decompress_textures, which can call
1303 * draw_vbo recursively, and before si_update_shaders, which uses
1304 * current_rast_prim for this draw_vbo call. */
1305 if (sctx->gs_shader.cso)
1306 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1307 else if (sctx->tes_shader.cso) {
1308 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1309 rast_prim = PIPE_PRIM_POINTS;
1310 else
1311 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1312 } else
1313 rast_prim = info->mode;
1314
1315 if (rast_prim != sctx->current_rast_prim) {
1316 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1317 util_prim_is_points_or_lines(rast_prim))
1318 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1319
1320 sctx->current_rast_prim = rast_prim;
1321 sctx->do_update_shaders = true;
1322 }
1323
1324 if (sctx->tes_shader.cso &&
1325 sctx->screen->has_ls_vgpr_init_bug) {
1326 /* Determine whether the LS VGPR fix should be applied.
1327 *
1328 * It is only required when num input CPs > num output CPs,
1329 * which cannot happen with the fixed function TCS. We should
1330 * also update this bit when switching from TCS to fixed
1331 * function TCS.
1332 */
1333 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1334 bool ls_vgpr_fix =
1335 tcs &&
1336 info->vertices_per_patch >
1337 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1338
1339 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1340 sctx->ls_vgpr_fix = ls_vgpr_fix;
1341 sctx->do_update_shaders = true;
1342 }
1343 }
1344
1345 if (sctx->gs_shader.cso) {
1346 /* Determine whether the GS triangle strip adjacency fix should
1347 * be applied. Rotate every other triangle if
1348 * - triangle strips with adjacency are fed to the GS and
1349 * - primitive restart is disabled (the rotation doesn't help
1350 * when the restart occurs after an odd number of triangles).
1351 */
1352 bool gs_tri_strip_adj_fix =
1353 !sctx->tes_shader.cso &&
1354 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1355 !info->primitive_restart;
1356
1357 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1358 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1359 sctx->do_update_shaders = true;
1360 }
1361 }
1362
1363 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1364 return;
1365
1366 if (index_size) {
1367 /* Translate or upload, if needed. */
1368 /* 8-bit indices are supported on VI. */
1369 if (sctx->chip_class <= CIK && index_size == 1) {
1370 unsigned start, count, start_offset, size, offset;
1371 void *ptr;
1372
1373 si_get_draw_start_count(sctx, info, &start, &count);
1374 start_offset = start * 2;
1375 size = count * 2;
1376
1377 indexbuf = NULL;
1378 u_upload_alloc(ctx->stream_uploader, start_offset,
1379 size,
1380 si_optimal_tcc_alignment(sctx, size),
1381 &offset, &indexbuf, &ptr);
1382 if (!indexbuf)
1383 return;
1384
1385 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1386 index_offset + start,
1387 count, ptr);
1388
1389 /* info->start will be added by the drawing code */
1390 index_offset = offset - start_offset;
1391 index_size = 2;
1392 } else if (info->has_user_indices) {
1393 unsigned start_offset;
1394
1395 assert(!info->indirect);
1396 start_offset = info->start * index_size;
1397
1398 indexbuf = NULL;
1399 u_upload_data(ctx->stream_uploader, start_offset,
1400 info->count * index_size,
1401 sctx->screen->info.tcc_cache_line_size,
1402 (char*)info->index.user + start_offset,
1403 &index_offset, &indexbuf);
1404 if (!indexbuf)
1405 return;
1406
1407 /* info->start will be added by the drawing code */
1408 index_offset -= start_offset;
1409 } else if (sctx->chip_class <= CIK &&
1410 r600_resource(indexbuf)->TC_L2_dirty) {
1411 /* VI reads index buffers through TC L2, so it doesn't
1412 * need this. */
1413 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1414 r600_resource(indexbuf)->TC_L2_dirty = false;
1415 }
1416 }
1417
1418 if (info->indirect) {
1419 struct pipe_draw_indirect_info *indirect = info->indirect;
1420
1421 /* Add the buffer size for memory checking in need_cs_space. */
1422 si_context_add_resource_size(sctx, indirect->buffer);
1423
1424 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1425 if (sctx->chip_class <= VI) {
1426 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1427 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1428 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1429 }
1430
1431 if (indirect->indirect_draw_count &&
1432 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1433 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1434 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1435 }
1436 }
1437 }
1438
1439 si_need_gfx_cs_space(sctx);
1440
1441 /* Since we've called si_context_add_resource_size for vertex buffers,
1442 * this must be called after si_need_cs_space, because we must let
1443 * need_cs_space flush before we add buffers to the buffer list.
1444 */
1445 if (!si_upload_vertex_buffer_descriptors(sctx))
1446 return;
1447
1448 /* Use optimal packet order based on whether we need to sync the pipeline. */
1449 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1450 SI_CONTEXT_FLUSH_AND_INV_DB |
1451 SI_CONTEXT_PS_PARTIAL_FLUSH |
1452 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1453 /* If we have to wait for idle, set all states first, so that all
1454 * SET packets are processed in parallel with previous draw calls.
1455 * Then draw and prefetch at the end. This ensures that the time
1456 * the CUs are idle is very short.
1457 */
1458 unsigned masked_atoms = 0;
1459
1460 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1461 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1462
1463 if (!si_upload_graphics_shader_descriptors(sctx))
1464 return;
1465
1466 /* Emit all states except possibly render condition. */
1467 si_emit_all_states(sctx, info, masked_atoms);
1468 si_emit_cache_flush(sctx);
1469 /* <-- CUs are idle here. */
1470
1471 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1472 sctx->atoms.s.render_cond.emit(sctx);
1473 sctx->dirty_atoms = 0;
1474
1475 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1476 /* <-- CUs are busy here. */
1477
1478 /* Start prefetches after the draw has been started. Both will run
1479 * in parallel, but starting the draw first is more important.
1480 */
1481 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1482 cik_emit_prefetch_L2(sctx, false);
1483 } else {
1484 /* If we don't wait for idle, start prefetches first, then set
1485 * states, and draw at the end.
1486 */
1487 if (sctx->flags)
1488 si_emit_cache_flush(sctx);
1489
1490 /* Only prefetch the API VS and VBO descriptors. */
1491 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1492 cik_emit_prefetch_L2(sctx, true);
1493
1494 if (!si_upload_graphics_shader_descriptors(sctx))
1495 return;
1496
1497 si_emit_all_states(sctx, info, 0);
1498 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1499
1500 /* Prefetch the remaining shaders after the draw has been
1501 * started. */
1502 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1503 cik_emit_prefetch_L2(sctx, false);
1504 }
1505
1506 if (unlikely(sctx->current_saved_cs)) {
1507 si_trace_emit(sctx);
1508 si_log_draw_state(sctx, sctx->log);
1509 }
1510
1511 /* Workaround for a VGT hang when streamout is enabled.
1512 * It must be done after drawing. */
1513 if ((sctx->family == CHIP_HAWAII ||
1514 sctx->family == CHIP_TONGA ||
1515 sctx->family == CHIP_FIJI) &&
1516 si_get_strmout_en(sctx)) {
1517 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1518 }
1519
1520 if (unlikely(sctx->decompression_enabled)) {
1521 sctx->num_decompress_calls++;
1522 } else {
1523 sctx->num_draw_calls++;
1524 if (sctx->framebuffer.state.nr_cbufs > 1)
1525 sctx->num_mrt_draw_calls++;
1526 if (info->primitive_restart)
1527 sctx->num_prim_restart_calls++;
1528 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1529 sctx->num_spill_draw_calls++;
1530 }
1531 if (index_size && indexbuf != info->index.resource)
1532 pipe_resource_reference(&indexbuf, NULL);
1533 }
1534
1535 static void
1536 si_draw_rectangle(struct blitter_context *blitter,
1537 void *vertex_elements_cso,
1538 blitter_get_vs_func get_vs,
1539 int x1, int y1, int x2, int y2,
1540 float depth, unsigned num_instances,
1541 enum blitter_attrib_type type,
1542 const union blitter_attrib *attrib)
1543 {
1544 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1545 struct si_context *sctx = (struct si_context*)pipe;
1546
1547 /* Pack position coordinates as signed int16. */
1548 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1549 ((uint32_t)(y1 & 0xffff) << 16);
1550 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1551 ((uint32_t)(y2 & 0xffff) << 16);
1552 sctx->vs_blit_sh_data[2] = fui(depth);
1553
1554 switch (type) {
1555 case UTIL_BLITTER_ATTRIB_COLOR:
1556 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1557 sizeof(float)*4);
1558 break;
1559 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1560 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1561 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1562 sizeof(attrib->texcoord));
1563 break;
1564 case UTIL_BLITTER_ATTRIB_NONE:;
1565 }
1566
1567 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
1568
1569 struct pipe_draw_info info = {};
1570 info.mode = SI_PRIM_RECTANGLE_LIST;
1571 info.count = 3;
1572 info.instance_count = num_instances;
1573
1574 /* Don't set per-stage shader pointers for VS. */
1575 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1576 sctx->vertex_buffer_pointer_dirty = false;
1577
1578 si_draw_vbo(pipe, &info);
1579 }
1580
1581 void si_trace_emit(struct si_context *sctx)
1582 {
1583 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1584 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1585 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1586
1587 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1588 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1589 S_370_WR_CONFIRM(1) |
1590 S_370_ENGINE_SEL(V_370_ME));
1591 radeon_emit(cs, va);
1592 radeon_emit(cs, va >> 32);
1593 radeon_emit(cs, trace_id);
1594 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1595 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1596
1597 if (sctx->log)
1598 u_log_flush(sctx->log);
1599 }
1600
1601 void si_init_draw_functions(struct si_context *sctx)
1602 {
1603 sctx->b.draw_vbo = si_draw_vbo;
1604
1605 sctx->blitter->draw_rectangle = si_draw_rectangle;
1606
1607 si_init_ia_multi_vgt_param_table(sctx);
1608 }