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radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gs
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static void si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_winsys_cs *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = num_tcs_inputs * 16;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
150
151 /* Make sure that the data fits in LDS. This assumes the shaders only
152 * use LDS for the inputs and outputs.
153 *
154 * While CIK can use 64K per threadgroup, there is a hang on Stoney
155 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
156 * uses 32K at most on all GCN chips.
157 */
158 hardware_lds_size = 32768;
159 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
160 output_patch_size));
161
162 /* Make sure the output data fits in the offchip buffer */
163 *num_patches = MIN2(*num_patches,
164 (sctx->screen->tess_offchip_block_dw_size * 4) /
165 output_patch_size);
166
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
169 */
170 *num_patches = MIN2(*num_patches, 40);
171
172 if (sctx->chip_class == SI) {
173 /* SI bug workaround, related to power management. Limit LS-HS
174 * threadgroups to only one wave.
175 */
176 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
177 *num_patches = MIN2(*num_patches, one_wave);
178 }
179
180 /* The VGT HS block increments the patch ID unconditionally
181 * within a single threadgroup. This results in incorrect
182 * patch IDs when instanced draws are used.
183 *
184 * The intended solution is to restrict threadgroups to
185 * a single instance by setting SWITCH_ON_EOI, which
186 * should cause IA to split instances up. However, this
187 * doesn't work correctly on SI when there is no other
188 * SE to switch to.
189 */
190 if (has_primid_instancing_bug && tess_uses_primid)
191 *num_patches = 1;
192
193 sctx->last_num_patches = *num_patches;
194
195 output_patch0_offset = input_patch_size * *num_patches;
196 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
197
198 /* Compute userdata SGPRs. */
199 assert(((input_vertex_size / 4) & ~0xff) == 0);
200 assert(((output_vertex_size / 4) & ~0xff) == 0);
201 assert(((input_patch_size / 4) & ~0x1fff) == 0);
202 assert(((output_patch_size / 4) & ~0x1fff) == 0);
203 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
204 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
205 assert(num_tcs_input_cp <= 32);
206 assert(num_tcs_output_cp <= 32);
207
208 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
209 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
210
211 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
212 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
213 tcs_out_layout = (output_patch_size / 4) |
214 (num_tcs_input_cp << 13) |
215 ring_va;
216 tcs_out_offsets = (output_patch0_offset / 16) |
217 ((perpatch_output_offset / 16) << 16);
218 offchip_layout = *num_patches |
219 (num_tcs_output_cp << 6) |
220 (pervertex_output_patch_size * *num_patches << 12);
221
222 /* Compute the LDS size. */
223 lds_size = output_patch0_offset + output_patch_size * *num_patches;
224
225 if (sctx->chip_class >= CIK) {
226 assert(lds_size <= 65536);
227 lds_size = align(lds_size, 512) / 512;
228 } else {
229 assert(lds_size <= 32768);
230 lds_size = align(lds_size, 256) / 256;
231 }
232
233 /* Set SI_SGPR_VS_STATE_BITS. */
234 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
235 C_VS_STATE_LS_OUT_VERTEX_SIZE;
236 sctx->current_vs_state |= tcs_in_layout;
237
238 if (sctx->chip_class >= GFX9) {
239 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
240 S_00B42C_LDS_SIZE(lds_size);
241
242 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
243
244 /* Set userdata SGPRs for merged LS-HS. */
245 radeon_set_sh_reg_seq(cs,
246 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
247 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
248 radeon_emit(cs, offchip_layout);
249 radeon_emit(cs, tcs_out_offsets);
250 radeon_emit(cs, tcs_out_layout);
251 } else {
252 unsigned ls_rsrc2 = ls_current->config.rsrc2;
253
254 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
255 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
256
257 /* Due to a hw bug, RSRC2_LS must be written twice with another
258 * LS register written in between. */
259 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
260 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
261 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
262 radeon_emit(cs, ls_current->config.rsrc1);
263 radeon_emit(cs, ls_rsrc2);
264
265 /* Set userdata SGPRs for TCS. */
266 radeon_set_sh_reg_seq(cs,
267 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
268 radeon_emit(cs, offchip_layout);
269 radeon_emit(cs, tcs_out_offsets);
270 radeon_emit(cs, tcs_out_layout);
271 radeon_emit(cs, tcs_in_layout);
272 }
273
274 /* Set userdata SGPRs for TES. */
275 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
276 radeon_emit(cs, offchip_layout);
277 radeon_emit(cs, ring_va);
278
279 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
280 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
281 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
282
283 if (sctx->chip_class >= CIK)
284 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
285 ls_hs_config);
286 else
287 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
288 ls_hs_config);
289 }
290
291 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
292 {
293 switch (info->mode) {
294 case PIPE_PRIM_PATCHES:
295 return info->count / info->vertices_per_patch;
296 case SI_PRIM_RECTANGLE_LIST:
297 return info->count / 3;
298 default:
299 return u_prims_for_vertices(info->mode, info->count);
300 }
301 }
302
303 static unsigned
304 si_get_init_multi_vgt_param(struct si_screen *sscreen,
305 union si_vgt_param_key *key)
306 {
307 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
308 unsigned max_primgroup_in_wave = 2;
309
310 /* SWITCH_ON_EOP(0) is always preferable. */
311 bool wd_switch_on_eop = false;
312 bool ia_switch_on_eop = false;
313 bool ia_switch_on_eoi = false;
314 bool partial_vs_wave = false;
315 bool partial_es_wave = false;
316
317 if (key->u.uses_tess) {
318 /* SWITCH_ON_EOI must be set if PrimID is used. */
319 if (key->u.tess_uses_prim_id)
320 ia_switch_on_eoi = true;
321
322 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
323 if ((sscreen->info.family == CHIP_TAHITI ||
324 sscreen->info.family == CHIP_PITCAIRN ||
325 sscreen->info.family == CHIP_BONAIRE) &&
326 key->u.uses_gs)
327 partial_vs_wave = true;
328
329 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
330 if (sscreen->has_distributed_tess) {
331 if (key->u.uses_gs) {
332 if (sscreen->info.chip_class <= VI)
333 partial_es_wave = true;
334
335 /* GPU hang workaround. */
336 if (sscreen->info.family == CHIP_TONGA ||
337 sscreen->info.family == CHIP_FIJI ||
338 sscreen->info.family == CHIP_POLARIS10 ||
339 sscreen->info.family == CHIP_POLARIS11 ||
340 sscreen->info.family == CHIP_POLARIS12 ||
341 sscreen->info.family == CHIP_VEGAM)
342 partial_vs_wave = true;
343 } else {
344 partial_vs_wave = true;
345 }
346 }
347 }
348
349 /* This is a hardware requirement. */
350 if (key->u.line_stipple_enabled ||
351 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
352 ia_switch_on_eop = true;
353 wd_switch_on_eop = true;
354 }
355
356 if (sscreen->info.chip_class >= CIK) {
357 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
358 * 4 shader engines. Set 1 to pass the assertion below.
359 * The other cases are hardware requirements.
360 *
361 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
362 * for points, line strips, and tri strips.
363 */
364 if (sscreen->info.max_se < 4 ||
365 key->u.prim == PIPE_PRIM_POLYGON ||
366 key->u.prim == PIPE_PRIM_LINE_LOOP ||
367 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
368 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
369 (key->u.primitive_restart &&
370 (sscreen->info.family < CHIP_POLARIS10 ||
371 (key->u.prim != PIPE_PRIM_POINTS &&
372 key->u.prim != PIPE_PRIM_LINE_STRIP &&
373 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
374 key->u.count_from_stream_output)
375 wd_switch_on_eop = true;
376
377 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
378 * We don't know that for indirect drawing, so treat it as
379 * always problematic. */
380 if (sscreen->info.family == CHIP_HAWAII &&
381 key->u.uses_instancing)
382 wd_switch_on_eop = true;
383
384 /* Performance recommendation for 4 SE Gfx7-8 parts if
385 * instances are smaller than a primgroup.
386 * Assume indirect draws always use small instances.
387 * This is needed for good VS wave utilization.
388 */
389 if (sscreen->info.chip_class <= VI &&
390 sscreen->info.max_se == 4 &&
391 key->u.multi_instances_smaller_than_primgroup)
392 wd_switch_on_eop = true;
393
394 /* Required on CIK and later. */
395 if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
396 ia_switch_on_eoi = true;
397
398 /* Required by Hawaii and, for some special cases, by VI. */
399 if (ia_switch_on_eoi &&
400 (sscreen->info.family == CHIP_HAWAII ||
401 (sscreen->info.chip_class == VI &&
402 (key->u.uses_gs || max_primgroup_in_wave != 2))))
403 partial_vs_wave = true;
404
405 /* Instancing bug on Bonaire. */
406 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
407 key->u.uses_instancing)
408 partial_vs_wave = true;
409
410 /* If the WD switch is false, the IA switch must be false too. */
411 assert(wd_switch_on_eop || !ia_switch_on_eop);
412 }
413
414 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
415 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
416 partial_es_wave = true;
417
418 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
419 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
420 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
421 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
422 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
423 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
424 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
425 max_primgroup_in_wave : 0) |
426 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
427 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
428 }
429
430 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
431 {
432 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
433 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
434 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
435 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
436 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
437 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
438 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
439 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
440 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
441 union si_vgt_param_key key;
442
443 key.index = 0;
444 key.u.prim = prim;
445 key.u.uses_instancing = uses_instancing;
446 key.u.multi_instances_smaller_than_primgroup = multi_instances;
447 key.u.primitive_restart = primitive_restart;
448 key.u.count_from_stream_output = count_from_so;
449 key.u.line_stipple_enabled = line_stipple;
450 key.u.uses_tess = uses_tess;
451 key.u.tess_uses_prim_id = tess_uses_primid;
452 key.u.uses_gs = uses_gs;
453
454 sctx->ia_multi_vgt_param[key.index] =
455 si_get_init_multi_vgt_param(sctx->screen, &key);
456 }
457 }
458
459 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
460 const struct pipe_draw_info *info,
461 unsigned num_patches)
462 {
463 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
464 unsigned primgroup_size;
465 unsigned ia_multi_vgt_param;
466
467 if (sctx->tes_shader.cso) {
468 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
469 } else if (sctx->gs_shader.cso) {
470 primgroup_size = 64; /* recommended with a GS */
471 } else {
472 primgroup_size = 128; /* recommended without a GS and tess */
473 }
474
475 key.u.prim = info->mode;
476 key.u.uses_instancing = info->indirect || info->instance_count > 1;
477 key.u.multi_instances_smaller_than_primgroup =
478 info->indirect ||
479 (info->instance_count > 1 &&
480 (info->count_from_stream_output ||
481 si_num_prims_for_vertices(info) < primgroup_size));
482 key.u.primitive_restart = info->primitive_restart;
483 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
484
485 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
486 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
487
488 if (sctx->gs_shader.cso) {
489 /* GS requirement. */
490 if (sctx->chip_class <= VI &&
491 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
492 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
493
494 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
495 * The hw doc says all multi-SE chips are affected, but Vulkan
496 * only applies it to Hawaii. Do what Vulkan does.
497 */
498 if (sctx->family == CHIP_HAWAII &&
499 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
500 (info->indirect ||
501 (info->instance_count > 1 &&
502 (info->count_from_stream_output ||
503 si_num_prims_for_vertices(info) <= 1))))
504 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
505 }
506
507 return ia_multi_vgt_param;
508 }
509
510 /* rast_prim is the primitive type after GS. */
511 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
512 {
513 struct radeon_winsys_cs *cs = sctx->gfx_cs;
514 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
515 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
516
517 /* Skip this if not rendering lines. */
518 if (rast_prim != PIPE_PRIM_LINES &&
519 rast_prim != PIPE_PRIM_LINE_LOOP &&
520 rast_prim != PIPE_PRIM_LINE_STRIP &&
521 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
522 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
523 return;
524
525 if (rast_prim == sctx->last_rast_prim &&
526 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
527 return;
528
529 /* For lines, reset the stipple pattern at each primitive. Otherwise,
530 * reset the stipple pattern at each packet (line strips, line loops).
531 */
532 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
533 rs->pa_sc_line_stipple |
534 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
535
536 sctx->last_rast_prim = rast_prim;
537 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
538 }
539
540 static void si_emit_vs_state(struct si_context *sctx,
541 const struct pipe_draw_info *info)
542 {
543 sctx->current_vs_state &= C_VS_STATE_INDEXED;
544 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
545
546 if (sctx->num_vs_blit_sgprs) {
547 /* Re-emit the state after we leave u_blitter. */
548 sctx->last_vs_state = ~0;
549 return;
550 }
551
552 if (sctx->current_vs_state != sctx->last_vs_state) {
553 struct radeon_winsys_cs *cs = sctx->gfx_cs;
554
555 radeon_set_sh_reg(cs,
556 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
557 SI_SGPR_VS_STATE_BITS * 4,
558 sctx->current_vs_state);
559
560 sctx->last_vs_state = sctx->current_vs_state;
561 }
562 }
563
564 static void si_emit_draw_registers(struct si_context *sctx,
565 const struct pipe_draw_info *info,
566 unsigned num_patches)
567 {
568 struct radeon_winsys_cs *cs = sctx->gfx_cs;
569 unsigned prim = si_conv_pipe_prim(info->mode);
570 unsigned ia_multi_vgt_param;
571
572 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
573
574 /* Draw state. */
575 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
576 if (sctx->chip_class >= GFX9)
577 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
578 else if (sctx->chip_class >= CIK)
579 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
580 else
581 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
582
583 sctx->last_multi_vgt_param = ia_multi_vgt_param;
584 }
585 if (prim != sctx->last_prim) {
586 if (sctx->chip_class >= CIK)
587 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
588 else
589 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
590
591 sctx->last_prim = prim;
592 }
593
594 /* Primitive restart. */
595 if (info->primitive_restart != sctx->last_primitive_restart_en) {
596 if (sctx->chip_class >= GFX9)
597 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
598 info->primitive_restart);
599 else
600 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
601 info->primitive_restart);
602
603 sctx->last_primitive_restart_en = info->primitive_restart;
604
605 }
606 if (info->primitive_restart &&
607 (info->restart_index != sctx->last_restart_index ||
608 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
609 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
610 info->restart_index);
611 sctx->last_restart_index = info->restart_index;
612 }
613 }
614
615 static void si_emit_draw_packets(struct si_context *sctx,
616 const struct pipe_draw_info *info,
617 struct pipe_resource *indexbuf,
618 unsigned index_size,
619 unsigned index_offset)
620 {
621 struct pipe_draw_indirect_info *indirect = info->indirect;
622 struct radeon_winsys_cs *cs = sctx->gfx_cs;
623 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
624 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
625 uint32_t index_max_size = 0;
626 uint64_t index_va = 0;
627
628 if (info->count_from_stream_output) {
629 struct si_streamout_target *t =
630 (struct si_streamout_target*)info->count_from_stream_output;
631 uint64_t va = t->buf_filled_size->gpu_address +
632 t->buf_filled_size_offset;
633
634 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
635 t->stride_in_dw);
636
637 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
638 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
639 COPY_DATA_DST_SEL(COPY_DATA_REG) |
640 COPY_DATA_WR_CONFIRM);
641 radeon_emit(cs, va); /* src address lo */
642 radeon_emit(cs, va >> 32); /* src address hi */
643 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
644 radeon_emit(cs, 0); /* unused */
645
646 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
647 t->buf_filled_size, RADEON_USAGE_READ,
648 RADEON_PRIO_SO_FILLED_SIZE);
649 }
650
651 /* draw packet */
652 if (index_size) {
653 if (index_size != sctx->last_index_size) {
654 unsigned index_type;
655
656 /* index type */
657 switch (index_size) {
658 case 1:
659 index_type = V_028A7C_VGT_INDEX_8;
660 break;
661 case 2:
662 index_type = V_028A7C_VGT_INDEX_16 |
663 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
664 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
665 break;
666 case 4:
667 index_type = V_028A7C_VGT_INDEX_32 |
668 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
669 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
670 break;
671 default:
672 assert(!"unreachable");
673 return;
674 }
675
676 if (sctx->chip_class >= GFX9) {
677 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
678 2, index_type);
679 } else {
680 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
681 radeon_emit(cs, index_type);
682 }
683
684 sctx->last_index_size = index_size;
685 }
686
687 index_max_size = (indexbuf->width0 - index_offset) /
688 index_size;
689 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
690
691 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
692 r600_resource(indexbuf),
693 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
694 } else {
695 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
696 * so the state must be re-emitted before the next indexed draw.
697 */
698 if (sctx->chip_class >= CIK)
699 sctx->last_index_size = -1;
700 }
701
702 if (indirect) {
703 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
704
705 assert(indirect_va % 8 == 0);
706
707 si_invalidate_draw_sh_constants(sctx);
708
709 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
710 radeon_emit(cs, 1);
711 radeon_emit(cs, indirect_va);
712 radeon_emit(cs, indirect_va >> 32);
713
714 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
715 r600_resource(indirect->buffer),
716 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
717
718 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
719 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
720
721 assert(indirect->offset % 4 == 0);
722
723 if (index_size) {
724 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
725 radeon_emit(cs, index_va);
726 radeon_emit(cs, index_va >> 32);
727
728 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
729 radeon_emit(cs, index_max_size);
730 }
731
732 if (!sctx->screen->has_draw_indirect_multi) {
733 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
734 : PKT3_DRAW_INDIRECT,
735 3, render_cond_bit));
736 radeon_emit(cs, indirect->offset);
737 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
738 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
739 radeon_emit(cs, di_src_sel);
740 } else {
741 uint64_t count_va = 0;
742
743 if (indirect->indirect_draw_count) {
744 struct r600_resource *params_buf =
745 r600_resource(indirect->indirect_draw_count);
746
747 radeon_add_to_buffer_list(
748 sctx, sctx->gfx_cs, params_buf,
749 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
750
751 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
752 }
753
754 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
755 PKT3_DRAW_INDIRECT_MULTI,
756 8, render_cond_bit));
757 radeon_emit(cs, indirect->offset);
758 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
759 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
760 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
761 S_2C3_DRAW_INDEX_ENABLE(1) |
762 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
763 radeon_emit(cs, indirect->draw_count);
764 radeon_emit(cs, count_va);
765 radeon_emit(cs, count_va >> 32);
766 radeon_emit(cs, indirect->stride);
767 radeon_emit(cs, di_src_sel);
768 }
769 } else {
770 int base_vertex;
771
772 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
773 radeon_emit(cs, info->instance_count);
774
775 /* Base vertex and start instance. */
776 base_vertex = index_size ? info->index_bias : info->start;
777
778 if (sctx->num_vs_blit_sgprs) {
779 /* Re-emit draw constants after we leave u_blitter. */
780 si_invalidate_draw_sh_constants(sctx);
781
782 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
783 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
784 sctx->num_vs_blit_sgprs);
785 radeon_emit_array(cs, sctx->vs_blit_sh_data,
786 sctx->num_vs_blit_sgprs);
787 } else if (base_vertex != sctx->last_base_vertex ||
788 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
789 info->start_instance != sctx->last_start_instance ||
790 info->drawid != sctx->last_drawid ||
791 sh_base_reg != sctx->last_sh_base_reg) {
792 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
793 radeon_emit(cs, base_vertex);
794 radeon_emit(cs, info->start_instance);
795 radeon_emit(cs, info->drawid);
796
797 sctx->last_base_vertex = base_vertex;
798 sctx->last_start_instance = info->start_instance;
799 sctx->last_drawid = info->drawid;
800 sctx->last_sh_base_reg = sh_base_reg;
801 }
802
803 if (index_size) {
804 index_va += info->start * index_size;
805
806 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
807 radeon_emit(cs, index_max_size);
808 radeon_emit(cs, index_va);
809 radeon_emit(cs, index_va >> 32);
810 radeon_emit(cs, info->count);
811 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
812 } else {
813 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
814 radeon_emit(cs, info->count);
815 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
816 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
817 }
818 }
819 }
820
821 static void si_emit_surface_sync(struct si_context *sctx,
822 unsigned cp_coher_cntl)
823 {
824 struct radeon_winsys_cs *cs = sctx->gfx_cs;
825
826 if (sctx->chip_class >= GFX9) {
827 /* Flush caches and wait for the caches to assert idle. */
828 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
829 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
830 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
831 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
832 radeon_emit(cs, 0); /* CP_COHER_BASE */
833 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
834 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
835 } else {
836 /* ACQUIRE_MEM is only required on a compute ring. */
837 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
838 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
839 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
840 radeon_emit(cs, 0); /* CP_COHER_BASE */
841 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
842 }
843 }
844
845 void si_emit_cache_flush(struct si_context *sctx)
846 {
847 struct radeon_winsys_cs *cs = sctx->gfx_cs;
848 uint32_t flags = sctx->flags;
849 uint32_t cp_coher_cntl = 0;
850 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
851 SI_CONTEXT_FLUSH_AND_INV_DB);
852
853 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
854 sctx->num_cb_cache_flushes++;
855 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
856 sctx->num_db_cache_flushes++;
857
858 /* SI has a bug that it always flushes ICACHE and KCACHE if either
859 * bit is set. An alternative way is to write SQC_CACHES, but that
860 * doesn't seem to work reliably. Since the bug doesn't affect
861 * correctness (it only does more work than necessary) and
862 * the performance impact is likely negligible, there is no plan
863 * to add a workaround for it.
864 */
865
866 if (flags & SI_CONTEXT_INV_ICACHE)
867 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
868 if (flags & SI_CONTEXT_INV_SMEM_L1)
869 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
870
871 if (sctx->chip_class <= VI) {
872 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
873 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
874 S_0085F0_CB0_DEST_BASE_ENA(1) |
875 S_0085F0_CB1_DEST_BASE_ENA(1) |
876 S_0085F0_CB2_DEST_BASE_ENA(1) |
877 S_0085F0_CB3_DEST_BASE_ENA(1) |
878 S_0085F0_CB4_DEST_BASE_ENA(1) |
879 S_0085F0_CB5_DEST_BASE_ENA(1) |
880 S_0085F0_CB6_DEST_BASE_ENA(1) |
881 S_0085F0_CB7_DEST_BASE_ENA(1);
882
883 /* Necessary for DCC */
884 if (sctx->chip_class == VI)
885 si_gfx_write_event_eop(sctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
886 0, EOP_DATA_SEL_DISCARD, NULL,
887 0, 0, SI_NOT_QUERY);
888 }
889 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
890 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
891 S_0085F0_DB_DEST_BASE_ENA(1);
892 }
893
894 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
895 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
896 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
897 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
898 }
899 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
900 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
901 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
902 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
903 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
904 }
905
906 /* Wait for shader engines to go idle.
907 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
908 * for everything including CB/DB cache flushes.
909 */
910 if (!flush_cb_db) {
911 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
912 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
913 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
914 /* Only count explicit shader flushes, not implicit ones
915 * done by SURFACE_SYNC.
916 */
917 sctx->num_vs_flushes++;
918 sctx->num_ps_flushes++;
919 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
920 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
921 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
922 sctx->num_vs_flushes++;
923 }
924 }
925
926 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
927 sctx->compute_is_busy) {
928 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
929 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
930 sctx->num_cs_flushes++;
931 sctx->compute_is_busy = false;
932 }
933
934 /* VGT state synchronization. */
935 if (flags & SI_CONTEXT_VGT_FLUSH) {
936 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
937 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
938 }
939 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
940 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
941 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
942 }
943
944 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
945 * wait for idle on GFX9. We have to use a TS event.
946 */
947 if (sctx->chip_class >= GFX9 && flush_cb_db) {
948 uint64_t va;
949 unsigned tc_flags, cb_db_event;
950
951 /* Set the CB/DB flush event. */
952 switch (flush_cb_db) {
953 case SI_CONTEXT_FLUSH_AND_INV_CB:
954 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
955 break;
956 case SI_CONTEXT_FLUSH_AND_INV_DB:
957 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
958 break;
959 default:
960 /* both CB & DB */
961 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
962 }
963
964 /* These are the only allowed combinations. If you need to
965 * do multiple operations at once, do them separately.
966 * All operations that invalidate L2 also seem to invalidate
967 * metadata. Volatile (VOL) and WC flushes are not listed here.
968 *
969 * TC | TC_WB = writeback & invalidate L2 & L1
970 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
971 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
972 * TC | TC_NC = invalidate L2 for MTYPE == NC
973 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
974 * TCL1 = invalidate L1
975 */
976 tc_flags = 0;
977
978 if (flags & SI_CONTEXT_INV_L2_METADATA) {
979 tc_flags = EVENT_TC_ACTION_ENA |
980 EVENT_TC_MD_ACTION_ENA;
981 }
982
983 /* Ideally flush TC together with CB/DB. */
984 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
985 /* Writeback and invalidate everything in L2 & L1. */
986 tc_flags = EVENT_TC_ACTION_ENA |
987 EVENT_TC_WB_ACTION_ENA;
988
989 /* Clear the flags. */
990 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
991 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
992 SI_CONTEXT_INV_VMEM_L1);
993 sctx->num_L2_invalidates++;
994 }
995
996 /* Do the flush (enqueue the event and wait for it). */
997 va = sctx->wait_mem_scratch->gpu_address;
998 sctx->wait_mem_number++;
999
1000 si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
1001 EOP_DATA_SEL_VALUE_32BIT,
1002 sctx->wait_mem_scratch, va,
1003 sctx->wait_mem_number, SI_NOT_QUERY);
1004 si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
1005 }
1006
1007 /* Make sure ME is idle (it executes most packets) before continuing.
1008 * This prevents read-after-write hazards between PFP and ME.
1009 */
1010 if (cp_coher_cntl ||
1011 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1012 SI_CONTEXT_INV_VMEM_L1 |
1013 SI_CONTEXT_INV_GLOBAL_L2 |
1014 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1015 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1016 radeon_emit(cs, 0);
1017 }
1018
1019 /* SI-CI-VI only:
1020 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1021 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1022 *
1023 * cp_coher_cntl should contain all necessary flags except TC flags
1024 * at this point.
1025 *
1026 * SI-CIK don't support L2 write-back.
1027 */
1028 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1029 (sctx->chip_class <= CIK &&
1030 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1031 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1032 * WB must be set on VI+ when TC_ACTION is set.
1033 */
1034 si_emit_surface_sync(sctx, cp_coher_cntl |
1035 S_0085F0_TC_ACTION_ENA(1) |
1036 S_0085F0_TCL1_ACTION_ENA(1) |
1037 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1038 cp_coher_cntl = 0;
1039 sctx->num_L2_invalidates++;
1040 } else {
1041 /* L1 invalidation and L2 writeback must be done separately,
1042 * because both operations can't be done together.
1043 */
1044 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1045 /* WB = write-back
1046 * NC = apply to non-coherent MTYPEs
1047 * (i.e. MTYPE <= 1, which is what we use everywhere)
1048 *
1049 * WB doesn't work without NC.
1050 */
1051 si_emit_surface_sync(sctx, cp_coher_cntl |
1052 S_0301F0_TC_WB_ACTION_ENA(1) |
1053 S_0301F0_TC_NC_ACTION_ENA(1));
1054 cp_coher_cntl = 0;
1055 sctx->num_L2_writebacks++;
1056 }
1057 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1058 /* Invalidate per-CU VMEM L1. */
1059 si_emit_surface_sync(sctx, cp_coher_cntl |
1060 S_0085F0_TCL1_ACTION_ENA(1));
1061 cp_coher_cntl = 0;
1062 }
1063 }
1064
1065 /* If TC flushes haven't cleared this... */
1066 if (cp_coher_cntl)
1067 si_emit_surface_sync(sctx, cp_coher_cntl);
1068
1069 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1070 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1071 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1072 EVENT_INDEX(0));
1073 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1074 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1075 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1076 EVENT_INDEX(0));
1077 }
1078
1079 sctx->flags = 0;
1080 }
1081
1082 static void si_get_draw_start_count(struct si_context *sctx,
1083 const struct pipe_draw_info *info,
1084 unsigned *start, unsigned *count)
1085 {
1086 struct pipe_draw_indirect_info *indirect = info->indirect;
1087
1088 if (indirect) {
1089 unsigned indirect_count;
1090 struct pipe_transfer *transfer;
1091 unsigned begin, end;
1092 unsigned map_size;
1093 unsigned *data;
1094
1095 if (indirect->indirect_draw_count) {
1096 data = pipe_buffer_map_range(&sctx->b,
1097 indirect->indirect_draw_count,
1098 indirect->indirect_draw_count_offset,
1099 sizeof(unsigned),
1100 PIPE_TRANSFER_READ, &transfer);
1101
1102 indirect_count = *data;
1103
1104 pipe_buffer_unmap(&sctx->b, transfer);
1105 } else {
1106 indirect_count = indirect->draw_count;
1107 }
1108
1109 if (!indirect_count) {
1110 *start = *count = 0;
1111 return;
1112 }
1113
1114 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1115 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1116 indirect->offset, map_size,
1117 PIPE_TRANSFER_READ, &transfer);
1118
1119 begin = UINT_MAX;
1120 end = 0;
1121
1122 for (unsigned i = 0; i < indirect_count; ++i) {
1123 unsigned count = data[0];
1124 unsigned start = data[2];
1125
1126 if (count > 0) {
1127 begin = MIN2(begin, start);
1128 end = MAX2(end, start + count);
1129 }
1130
1131 data += indirect->stride / sizeof(unsigned);
1132 }
1133
1134 pipe_buffer_unmap(&sctx->b, transfer);
1135
1136 if (begin < end) {
1137 *start = begin;
1138 *count = end - begin;
1139 } else {
1140 *start = *count = 0;
1141 }
1142 } else {
1143 *start = info->start;
1144 *count = info->count;
1145 }
1146 }
1147
1148 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1149 unsigned skip_atom_mask)
1150 {
1151 /* Emit state atoms. */
1152 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1153 while (mask)
1154 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1155
1156 sctx->dirty_atoms &= skip_atom_mask;
1157
1158 /* Emit states. */
1159 mask = sctx->dirty_states;
1160 while (mask) {
1161 unsigned i = u_bit_scan(&mask);
1162 struct si_pm4_state *state = sctx->queued.array[i];
1163
1164 if (!state || sctx->emitted.array[i] == state)
1165 continue;
1166
1167 si_pm4_emit(sctx, state);
1168 sctx->emitted.array[i] = state;
1169 }
1170 sctx->dirty_states = 0;
1171
1172 /* Emit draw states. */
1173 unsigned num_patches = 0;
1174
1175 si_emit_rasterizer_prim_state(sctx);
1176 if (sctx->tes_shader.cso)
1177 si_emit_derived_tess_state(sctx, info, &num_patches);
1178 si_emit_vs_state(sctx, info);
1179 si_emit_draw_registers(sctx, info, num_patches);
1180 }
1181
1182 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1183 {
1184 struct si_context *sctx = (struct si_context *)ctx;
1185 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1186 struct pipe_resource *indexbuf = info->index.resource;
1187 unsigned dirty_tex_counter;
1188 enum pipe_prim_type rast_prim;
1189 unsigned index_size = info->index_size;
1190 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1191
1192 if (likely(!info->indirect)) {
1193 /* SI-CI treat instance_count==0 as instance_count==1. There is
1194 * no workaround for indirect draws, but we can at least skip
1195 * direct draws.
1196 */
1197 if (unlikely(!info->instance_count))
1198 return;
1199
1200 /* Handle count == 0. */
1201 if (unlikely(!info->count &&
1202 (index_size || !info->count_from_stream_output)))
1203 return;
1204 }
1205
1206 if (unlikely(!sctx->vs_shader.cso)) {
1207 assert(0);
1208 return;
1209 }
1210 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1211 assert(0);
1212 return;
1213 }
1214 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1215 assert(0);
1216 return;
1217 }
1218
1219 /* Recompute and re-emit the texture resource states if needed. */
1220 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1221 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1222 sctx->last_dirty_tex_counter = dirty_tex_counter;
1223 sctx->framebuffer.dirty_cbufs |=
1224 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1225 sctx->framebuffer.dirty_zsbuf = true;
1226 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1227 si_update_all_texture_descriptors(sctx);
1228 }
1229
1230 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1231
1232 /* Set the rasterization primitive type.
1233 *
1234 * This must be done after si_decompress_textures, which can call
1235 * draw_vbo recursively, and before si_update_shaders, which uses
1236 * current_rast_prim for this draw_vbo call. */
1237 if (sctx->gs_shader.cso)
1238 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1239 else if (sctx->tes_shader.cso) {
1240 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1241 rast_prim = PIPE_PRIM_POINTS;
1242 else
1243 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1244 } else
1245 rast_prim = info->mode;
1246
1247 if (rast_prim != sctx->current_rast_prim) {
1248 bool old_is_poly = sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES;
1249 bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
1250 if (old_is_poly != new_is_poly) {
1251 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1252 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1253 }
1254
1255 sctx->current_rast_prim = rast_prim;
1256 sctx->do_update_shaders = true;
1257 }
1258
1259 if (sctx->tes_shader.cso &&
1260 sctx->screen->has_ls_vgpr_init_bug) {
1261 /* Determine whether the LS VGPR fix should be applied.
1262 *
1263 * It is only required when num input CPs > num output CPs,
1264 * which cannot happen with the fixed function TCS. We should
1265 * also update this bit when switching from TCS to fixed
1266 * function TCS.
1267 */
1268 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1269 bool ls_vgpr_fix =
1270 tcs &&
1271 info->vertices_per_patch >
1272 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1273
1274 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1275 sctx->ls_vgpr_fix = ls_vgpr_fix;
1276 sctx->do_update_shaders = true;
1277 }
1278 }
1279
1280 if (sctx->gs_shader.cso) {
1281 /* Determine whether the GS triangle strip adjacency fix should
1282 * be applied. Rotate every other triangle if
1283 * - triangle strips with adjacency are fed to the GS and
1284 * - primitive restart is disabled (the rotation doesn't help
1285 * when the restart occurs after an odd number of triangles).
1286 */
1287 bool gs_tri_strip_adj_fix =
1288 !sctx->tes_shader.cso &&
1289 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1290 !info->primitive_restart;
1291
1292 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1293 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1294 sctx->do_update_shaders = true;
1295 }
1296 }
1297
1298 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1299 return;
1300
1301 if (index_size) {
1302 /* Translate or upload, if needed. */
1303 /* 8-bit indices are supported on VI. */
1304 if (sctx->chip_class <= CIK && index_size == 1) {
1305 unsigned start, count, start_offset, size, offset;
1306 void *ptr;
1307
1308 si_get_draw_start_count(sctx, info, &start, &count);
1309 start_offset = start * 2;
1310 size = count * 2;
1311
1312 indexbuf = NULL;
1313 u_upload_alloc(ctx->stream_uploader, start_offset,
1314 size,
1315 si_optimal_tcc_alignment(sctx, size),
1316 &offset, &indexbuf, &ptr);
1317 if (!indexbuf)
1318 return;
1319
1320 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1321 index_offset + start,
1322 count, ptr);
1323
1324 /* info->start will be added by the drawing code */
1325 index_offset = offset - start_offset;
1326 index_size = 2;
1327 } else if (info->has_user_indices) {
1328 unsigned start_offset;
1329
1330 assert(!info->indirect);
1331 start_offset = info->start * index_size;
1332
1333 indexbuf = NULL;
1334 u_upload_data(ctx->stream_uploader, start_offset,
1335 info->count * index_size,
1336 sctx->screen->info.tcc_cache_line_size,
1337 (char*)info->index.user + start_offset,
1338 &index_offset, &indexbuf);
1339 if (!indexbuf)
1340 return;
1341
1342 /* info->start will be added by the drawing code */
1343 index_offset -= start_offset;
1344 } else if (sctx->chip_class <= CIK &&
1345 r600_resource(indexbuf)->TC_L2_dirty) {
1346 /* VI reads index buffers through TC L2, so it doesn't
1347 * need this. */
1348 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1349 r600_resource(indexbuf)->TC_L2_dirty = false;
1350 }
1351 }
1352
1353 if (info->indirect) {
1354 struct pipe_draw_indirect_info *indirect = info->indirect;
1355
1356 /* Add the buffer size for memory checking in need_cs_space. */
1357 si_context_add_resource_size(sctx, indirect->buffer);
1358
1359 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1360 if (sctx->chip_class <= VI) {
1361 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1362 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1363 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1364 }
1365
1366 if (indirect->indirect_draw_count &&
1367 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1368 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1369 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1370 }
1371 }
1372 }
1373
1374 si_need_gfx_cs_space(sctx);
1375
1376 /* Since we've called si_context_add_resource_size for vertex buffers,
1377 * this must be called after si_need_cs_space, because we must let
1378 * need_cs_space flush before we add buffers to the buffer list.
1379 */
1380 if (!si_upload_vertex_buffer_descriptors(sctx))
1381 return;
1382
1383 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1384 * scissor registers are changed. There is also a more efficient but
1385 * more involved alternative workaround.
1386 */
1387 if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1388 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)) {
1389 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1390 si_emit_cache_flush(sctx);
1391 }
1392
1393 /* Use optimal packet order based on whether we need to sync the pipeline. */
1394 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1395 SI_CONTEXT_FLUSH_AND_INV_DB |
1396 SI_CONTEXT_PS_PARTIAL_FLUSH |
1397 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1398 /* If we have to wait for idle, set all states first, so that all
1399 * SET packets are processed in parallel with previous draw calls.
1400 * Then draw and prefetch at the end. This ensures that the time
1401 * the CUs are idle is very short.
1402 */
1403 unsigned masked_atoms = 0;
1404
1405 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1406 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1407
1408 if (!si_upload_graphics_shader_descriptors(sctx))
1409 return;
1410
1411 /* Emit all states except possibly render condition. */
1412 si_emit_all_states(sctx, info, masked_atoms);
1413 si_emit_cache_flush(sctx);
1414 /* <-- CUs are idle here. */
1415
1416 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1417 sctx->atoms.s.render_cond.emit(sctx);
1418 sctx->dirty_atoms = 0;
1419
1420 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1421 /* <-- CUs are busy here. */
1422
1423 /* Start prefetches after the draw has been started. Both will run
1424 * in parallel, but starting the draw first is more important.
1425 */
1426 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1427 cik_emit_prefetch_L2(sctx, false);
1428 } else {
1429 /* If we don't wait for idle, start prefetches first, then set
1430 * states, and draw at the end.
1431 */
1432 if (sctx->flags)
1433 si_emit_cache_flush(sctx);
1434
1435 /* Only prefetch the API VS and VBO descriptors. */
1436 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1437 cik_emit_prefetch_L2(sctx, true);
1438
1439 if (!si_upload_graphics_shader_descriptors(sctx))
1440 return;
1441
1442 si_emit_all_states(sctx, info, 0);
1443 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1444
1445 /* Prefetch the remaining shaders after the draw has been
1446 * started. */
1447 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1448 cik_emit_prefetch_L2(sctx, false);
1449 }
1450
1451 if (unlikely(sctx->current_saved_cs)) {
1452 si_trace_emit(sctx);
1453 si_log_draw_state(sctx, sctx->log);
1454 }
1455
1456 /* Workaround for a VGT hang when streamout is enabled.
1457 * It must be done after drawing. */
1458 if ((sctx->family == CHIP_HAWAII ||
1459 sctx->family == CHIP_TONGA ||
1460 sctx->family == CHIP_FIJI) &&
1461 si_get_strmout_en(sctx)) {
1462 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1463 }
1464
1465 if (unlikely(sctx->decompression_enabled)) {
1466 sctx->num_decompress_calls++;
1467 } else {
1468 sctx->num_draw_calls++;
1469 if (sctx->framebuffer.state.nr_cbufs > 1)
1470 sctx->num_mrt_draw_calls++;
1471 if (info->primitive_restart)
1472 sctx->num_prim_restart_calls++;
1473 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1474 sctx->num_spill_draw_calls++;
1475 }
1476 if (index_size && indexbuf != info->index.resource)
1477 pipe_resource_reference(&indexbuf, NULL);
1478 }
1479
1480 void si_draw_rectangle(struct blitter_context *blitter,
1481 void *vertex_elements_cso,
1482 blitter_get_vs_func get_vs,
1483 int x1, int y1, int x2, int y2,
1484 float depth, unsigned num_instances,
1485 enum blitter_attrib_type type,
1486 const union blitter_attrib *attrib)
1487 {
1488 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1489 struct si_context *sctx = (struct si_context*)pipe;
1490
1491 /* Pack position coordinates as signed int16. */
1492 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1493 ((uint32_t)(y1 & 0xffff) << 16);
1494 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1495 ((uint32_t)(y2 & 0xffff) << 16);
1496 sctx->vs_blit_sh_data[2] = fui(depth);
1497
1498 switch (type) {
1499 case UTIL_BLITTER_ATTRIB_COLOR:
1500 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1501 sizeof(float)*4);
1502 break;
1503 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1504 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1505 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1506 sizeof(attrib->texcoord));
1507 break;
1508 case UTIL_BLITTER_ATTRIB_NONE:;
1509 }
1510
1511 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1512
1513 struct pipe_draw_info info = {};
1514 info.mode = SI_PRIM_RECTANGLE_LIST;
1515 info.count = 3;
1516 info.instance_count = num_instances;
1517
1518 /* Don't set per-stage shader pointers for VS. */
1519 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1520 sctx->vertex_buffer_pointer_dirty = false;
1521
1522 si_draw_vbo(pipe, &info);
1523 }
1524
1525 void si_trace_emit(struct si_context *sctx)
1526 {
1527 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1528 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1529 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1530
1531 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1532 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1533 S_370_WR_CONFIRM(1) |
1534 S_370_ENGINE_SEL(V_370_ME));
1535 radeon_emit(cs, va);
1536 radeon_emit(cs, va >> 32);
1537 radeon_emit(cs, trace_id);
1538 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1539 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1540
1541 if (sctx->log)
1542 u_log_flush(sctx->log);
1543 }