projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/gfx10: fix vertex color clamping for TES
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 /* We should be able to support in-shader LDS use with LLVM >= 9
256 * by just adding the lds_sizes together, but it has never
257 * been tested. */
258 assert(ls_current->config.lds_size == 0);
259
260 if (sctx->chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2;
262
263 if (sctx->chip_class >= GFX10)
264 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
265 else
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
267
268 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
269
270 /* Set userdata SGPRs for merged LS-HS. */
271 radeon_set_sh_reg_seq(cs,
272 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
273 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
274 radeon_emit(cs, offchip_layout);
275 radeon_emit(cs, tcs_out_offsets);
276 radeon_emit(cs, tcs_out_layout);
277 } else {
278 unsigned ls_rsrc2 = ls_current->config.rsrc2;
279
280 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
281 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
282
283 /* Due to a hw bug, RSRC2_LS must be written twice with another
284 * LS register written in between. */
285 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
286 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
287 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
288 radeon_emit(cs, ls_current->config.rsrc1);
289 radeon_emit(cs, ls_rsrc2);
290
291 /* Set userdata SGPRs for TCS. */
292 radeon_set_sh_reg_seq(cs,
293 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
294 radeon_emit(cs, offchip_layout);
295 radeon_emit(cs, tcs_out_offsets);
296 radeon_emit(cs, tcs_out_layout);
297 radeon_emit(cs, tcs_in_layout);
298 }
299
300 /* Set userdata SGPRs for TES. */
301 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
302 radeon_emit(cs, offchip_layout);
303 radeon_emit(cs, ring_va);
304
305 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
306 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
307 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
308
309 if (sctx->last_ls_hs_config != ls_hs_config) {
310 if (sctx->chip_class >= GFX7) {
311 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
312 ls_hs_config);
313 } else {
314 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
315 ls_hs_config);
316 }
317 sctx->last_ls_hs_config = ls_hs_config;
318 sctx->context_roll = true;
319 }
320 }
321
322 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
323 enum pipe_prim_type prim)
324 {
325 switch (prim) {
326 case PIPE_PRIM_PATCHES:
327 return info->count / info->vertices_per_patch;
328 case PIPE_PRIM_POLYGON:
329 return info->count >= 3;
330 case SI_PRIM_RECTANGLE_LIST:
331 return info->count / 3;
332 default:
333 return u_decomposed_prims_for_vertices(prim, info->count);
334 }
335 }
336
337 static unsigned
338 si_get_init_multi_vgt_param(struct si_screen *sscreen,
339 union si_vgt_param_key *key)
340 {
341 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
342 unsigned max_primgroup_in_wave = 2;
343
344 /* SWITCH_ON_EOP(0) is always preferable. */
345 bool wd_switch_on_eop = false;
346 bool ia_switch_on_eop = false;
347 bool ia_switch_on_eoi = false;
348 bool partial_vs_wave = false;
349 bool partial_es_wave = false;
350
351 if (key->u.uses_tess) {
352 /* SWITCH_ON_EOI must be set if PrimID is used. */
353 if (key->u.tess_uses_prim_id)
354 ia_switch_on_eoi = true;
355
356 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
357 if ((sscreen->info.family == CHIP_TAHITI ||
358 sscreen->info.family == CHIP_PITCAIRN ||
359 sscreen->info.family == CHIP_BONAIRE) &&
360 key->u.uses_gs)
361 partial_vs_wave = true;
362
363 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
364 if (sscreen->has_distributed_tess) {
365 if (key->u.uses_gs) {
366 if (sscreen->info.chip_class == GFX8)
367 partial_es_wave = true;
368 } else {
369 partial_vs_wave = true;
370 }
371 }
372 }
373
374 /* This is a hardware requirement. */
375 if (key->u.line_stipple_enabled ||
376 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
377 ia_switch_on_eop = true;
378 wd_switch_on_eop = true;
379 }
380
381 if (sscreen->info.chip_class >= GFX7) {
382 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
383 * 4 shader engines. Set 1 to pass the assertion below.
384 * The other cases are hardware requirements.
385 *
386 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
387 * for points, line strips, and tri strips.
388 */
389 if (sscreen->info.max_se <= 2 ||
390 key->u.prim == PIPE_PRIM_POLYGON ||
391 key->u.prim == PIPE_PRIM_LINE_LOOP ||
392 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
393 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
394 (key->u.primitive_restart &&
395 (sscreen->info.family < CHIP_POLARIS10 ||
396 (key->u.prim != PIPE_PRIM_POINTS &&
397 key->u.prim != PIPE_PRIM_LINE_STRIP &&
398 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
399 key->u.count_from_stream_output)
400 wd_switch_on_eop = true;
401
402 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
403 * We don't know that for indirect drawing, so treat it as
404 * always problematic. */
405 if (sscreen->info.family == CHIP_HAWAII &&
406 key->u.uses_instancing)
407 wd_switch_on_eop = true;
408
409 /* Performance recommendation for 4 SE Gfx7-8 parts if
410 * instances are smaller than a primgroup.
411 * Assume indirect draws always use small instances.
412 * This is needed for good VS wave utilization.
413 */
414 if (sscreen->info.chip_class <= GFX8 &&
415 sscreen->info.max_se == 4 &&
416 key->u.multi_instances_smaller_than_primgroup)
417 wd_switch_on_eop = true;
418
419 /* Required on GFX7 and later. */
420 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
421 ia_switch_on_eoi = true;
422
423 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
424 * to work around a GS hang.
425 */
426 if (key->u.uses_gs &&
427 (sscreen->info.family == CHIP_TONGA ||
428 sscreen->info.family == CHIP_FIJI ||
429 sscreen->info.family == CHIP_POLARIS10 ||
430 sscreen->info.family == CHIP_POLARIS11 ||
431 sscreen->info.family == CHIP_POLARIS12 ||
432 sscreen->info.family == CHIP_VEGAM))
433 partial_vs_wave = true;
434
435 /* Required by Hawaii and, for some special cases, by GFX8. */
436 if (ia_switch_on_eoi &&
437 (sscreen->info.family == CHIP_HAWAII ||
438 (sscreen->info.chip_class == GFX8 &&
439 (key->u.uses_gs || max_primgroup_in_wave != 2))))
440 partial_vs_wave = true;
441
442 /* Instancing bug on Bonaire. */
443 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
444 key->u.uses_instancing)
445 partial_vs_wave = true;
446
447 /* This only applies to Polaris10 and later 4 SE chips.
448 * wd_switch_on_eop is already true on all other chips.
449 */
450 if (!wd_switch_on_eop && key->u.primitive_restart)
451 partial_vs_wave = true;
452
453 /* If the WD switch is false, the IA switch must be false too. */
454 assert(wd_switch_on_eop || !ia_switch_on_eop);
455 }
456
457 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
458 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
459 partial_es_wave = true;
460
461 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
462 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
463 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
464 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
465 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
466 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
467 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
468 max_primgroup_in_wave : 0) |
469 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
470 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
471 }
472
473 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
474 {
475 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
476 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
477 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
478 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
479 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
480 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
481 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
482 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
483 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
484 union si_vgt_param_key key;
485
486 key.index = 0;
487 key.u.prim = prim;
488 key.u.uses_instancing = uses_instancing;
489 key.u.multi_instances_smaller_than_primgroup = multi_instances;
490 key.u.primitive_restart = primitive_restart;
491 key.u.count_from_stream_output = count_from_so;
492 key.u.line_stipple_enabled = line_stipple;
493 key.u.uses_tess = uses_tess;
494 key.u.tess_uses_prim_id = tess_uses_primid;
495 key.u.uses_gs = uses_gs;
496
497 sctx->ia_multi_vgt_param[key.index] =
498 si_get_init_multi_vgt_param(sctx->screen, &key);
499 }
500 }
501
502 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
503 const struct pipe_draw_info *info,
504 enum pipe_prim_type prim,
505 unsigned num_patches,
506 unsigned instance_count,
507 bool primitive_restart)
508 {
509 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
510 unsigned primgroup_size;
511 unsigned ia_multi_vgt_param;
512
513 if (sctx->tes_shader.cso) {
514 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
515 } else if (sctx->gs_shader.cso) {
516 primgroup_size = 64; /* recommended with a GS */
517 } else {
518 primgroup_size = 128; /* recommended without a GS and tess */
519 }
520
521 key.u.prim = prim;
522 key.u.uses_instancing = info->indirect || instance_count > 1;
523 key.u.multi_instances_smaller_than_primgroup =
524 info->indirect ||
525 (instance_count > 1 &&
526 (info->count_from_stream_output ||
527 si_num_prims_for_vertices(info, prim) < primgroup_size));
528 key.u.primitive_restart = primitive_restart;
529 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
530
531 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
532 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
533
534 if (sctx->gs_shader.cso) {
535 /* GS requirement. */
536 if (sctx->chip_class <= GFX8 &&
537 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
538 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
539
540 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
541 * The hw doc says all multi-SE chips are affected, but Vulkan
542 * only applies it to Hawaii. Do what Vulkan does.
543 */
544 if (sctx->family == CHIP_HAWAII &&
545 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
546 (info->indirect ||
547 (instance_count > 1 &&
548 (info->count_from_stream_output ||
549 si_num_prims_for_vertices(info, prim) <= 1))))
550 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
551 }
552
553 return ia_multi_vgt_param;
554 }
555
556 static unsigned si_conv_prim_to_gs_out(unsigned mode)
557 {
558 static const int prim_conv[] = {
559 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
560 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
561 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
562 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
563 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
564 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
565 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
566 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
567 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
568 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
569 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
570 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
571 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
572 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
573 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
574 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
575 };
576 assert(mode < ARRAY_SIZE(prim_conv));
577
578 return prim_conv[mode];
579 }
580
581 /* rast_prim is the primitive type after GS. */
582 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
583 {
584 struct radeon_cmdbuf *cs = sctx->gfx_cs;
585 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
586 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
587
588 if (likely(rast_prim == sctx->last_rast_prim &&
589 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple))
590 return;
591
592 if (util_prim_is_lines(rast_prim)) {
593 /* For lines, reset the stipple pattern at each primitive. Otherwise,
594 * reset the stipple pattern at each packet (line strips, line loops).
595 */
596 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
597 rs->pa_sc_line_stipple |
598 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
599 sctx->context_roll = true;
600 }
601
602 if (rast_prim != sctx->last_rast_prim &&
603 (sctx->ngg || sctx->gs_shader.cso)) {
604 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
605 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
606 sctx->context_roll = true;
607
608 if (sctx->chip_class >= GFX10) {
609 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
610 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
611 }
612 }
613
614 sctx->last_rast_prim = rast_prim;
615 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
616 }
617
618 static void si_emit_vs_state(struct si_context *sctx,
619 const struct pipe_draw_info *info)
620 {
621 sctx->current_vs_state &= C_VS_STATE_INDEXED;
622 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
623
624 if (sctx->num_vs_blit_sgprs) {
625 /* Re-emit the state after we leave u_blitter. */
626 sctx->last_vs_state = ~0;
627 return;
628 }
629
630 if (sctx->current_vs_state != sctx->last_vs_state) {
631 struct radeon_cmdbuf *cs = sctx->gfx_cs;
632
633 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
634 radeon_set_sh_reg(cs,
635 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
636 SI_SGPR_VS_STATE_BITS * 4,
637 sctx->current_vs_state);
638
639 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
640 * before the rasterizer.
641 *
642 * For TES or the GS copy shader without NGG:
643 */
644 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
645 R_00B130_SPI_SHADER_USER_DATA_VS_0) {
646 radeon_set_sh_reg(cs,
647 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
648 SI_SGPR_VS_STATE_BITS * 4,
649 sctx->current_vs_state);
650 }
651
652 /* For NGG: */
653 if (sctx->chip_class >= GFX10 &&
654 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
655 R_00B230_SPI_SHADER_USER_DATA_GS_0) {
656 radeon_set_sh_reg(cs,
657 R_00B230_SPI_SHADER_USER_DATA_GS_0 +
658 SI_SGPR_VS_STATE_BITS * 4,
659 sctx->current_vs_state);
660 }
661
662 sctx->last_vs_state = sctx->current_vs_state;
663 }
664 }
665
666 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
667 bool primitive_restart,
668 unsigned restart_index)
669 {
670 return primitive_restart &&
671 (restart_index != sctx->last_restart_index ||
672 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
673 }
674
675 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
676 const struct pipe_draw_info *info,
677 enum pipe_prim_type prim,
678 unsigned num_patches,
679 unsigned instance_count,
680 bool primitive_restart)
681 {
682 struct radeon_cmdbuf *cs = sctx->gfx_cs;
683 unsigned ia_multi_vgt_param;
684
685 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
686 instance_count, primitive_restart);
687
688 /* Draw state. */
689 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
690 if (sctx->chip_class >= GFX9)
691 radeon_set_uconfig_reg_idx(cs, sctx->screen,
692 R_030960_IA_MULTI_VGT_PARAM, 4,
693 ia_multi_vgt_param);
694 else if (sctx->chip_class >= GFX7)
695 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
696 else
697 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
698
699 sctx->last_multi_vgt_param = ia_multi_vgt_param;
700 }
701 }
702
703 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
704 * We overload last_multi_vgt_param.
705 */
706 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
707 {
708 if (sctx->ngg)
709 return; /* set during PM4 emit */
710
711 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
712 unsigned primgroup_size;
713 unsigned vertgroup_size;
714
715 if (sctx->tes_shader.cso) {
716 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
717 vertgroup_size = 0;
718 } else if (sctx->gs_shader.cso) {
719 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
720 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
721 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
722 } else {
723 primgroup_size = 128; /* recommended without a GS and tess */
724 vertgroup_size = 0;
725 }
726
727 unsigned ge_cntl =
728 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
729 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
730 S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
731 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
732
733 if (ge_cntl != sctx->last_multi_vgt_param) {
734 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
735 sctx->last_multi_vgt_param = ge_cntl;
736 }
737 }
738
739 static void si_emit_draw_registers(struct si_context *sctx,
740 const struct pipe_draw_info *info,
741 enum pipe_prim_type prim,
742 unsigned num_patches,
743 unsigned instance_count,
744 bool primitive_restart)
745 {
746 struct radeon_cmdbuf *cs = sctx->gfx_cs;
747 unsigned vgt_prim = si_conv_pipe_prim(info->mode);
748
749 if (sctx->chip_class >= GFX10)
750 gfx10_emit_ge_cntl(sctx, num_patches);
751 else
752 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
753 instance_count, primitive_restart);
754
755 if (vgt_prim != sctx->last_prim) {
756 if (sctx->chip_class >= GFX7)
757 radeon_set_uconfig_reg_idx(cs, sctx->screen,
758 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
759 else
760 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
761
762 sctx->last_prim = vgt_prim;
763 }
764
765 /* Primitive restart. */
766 if (primitive_restart != sctx->last_primitive_restart_en) {
767 if (sctx->chip_class >= GFX9)
768 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
769 primitive_restart);
770 else
771 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
772 primitive_restart);
773
774 sctx->last_primitive_restart_en = primitive_restart;
775
776 }
777 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
778 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
779 info->restart_index);
780 sctx->last_restart_index = info->restart_index;
781 sctx->context_roll = true;
782 }
783 }
784
785 static void si_emit_draw_packets(struct si_context *sctx,
786 const struct pipe_draw_info *info,
787 struct pipe_resource *indexbuf,
788 unsigned index_size,
789 unsigned index_offset,
790 unsigned instance_count,
791 bool dispatch_prim_discard_cs,
792 unsigned original_index_size)
793 {
794 struct pipe_draw_indirect_info *indirect = info->indirect;
795 struct radeon_cmdbuf *cs = sctx->gfx_cs;
796 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
797 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
798 uint32_t index_max_size = 0;
799 uint64_t index_va = 0;
800
801 if (info->count_from_stream_output) {
802 struct si_streamout_target *t =
803 (struct si_streamout_target*)info->count_from_stream_output;
804
805 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
806 t->stride_in_dw);
807 si_cp_copy_data(sctx, sctx->gfx_cs,
808 COPY_DATA_REG, NULL,
809 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
810 COPY_DATA_SRC_MEM, t->buf_filled_size,
811 t->buf_filled_size_offset);
812 }
813
814 /* draw packet */
815 if (index_size) {
816 if (index_size != sctx->last_index_size) {
817 unsigned index_type;
818
819 /* index type */
820 switch (index_size) {
821 case 1:
822 index_type = V_028A7C_VGT_INDEX_8;
823 break;
824 case 2:
825 index_type = V_028A7C_VGT_INDEX_16 |
826 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
827 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
828 break;
829 case 4:
830 index_type = V_028A7C_VGT_INDEX_32 |
831 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
832 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
833 break;
834 default:
835 assert(!"unreachable");
836 return;
837 }
838
839 if (sctx->chip_class >= GFX9) {
840 radeon_set_uconfig_reg_idx(cs, sctx->screen,
841 R_03090C_VGT_INDEX_TYPE, 2,
842 index_type);
843 } else {
844 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
845 radeon_emit(cs, index_type);
846 }
847
848 sctx->last_index_size = index_size;
849 }
850
851 if (original_index_size) {
852 index_max_size = (indexbuf->width0 - index_offset) /
853 original_index_size;
854 index_va = si_resource(indexbuf)->gpu_address + index_offset;
855
856 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
857 si_resource(indexbuf),
858 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
859 }
860 } else {
861 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
862 * so the state must be re-emitted before the next indexed draw.
863 */
864 if (sctx->chip_class >= GFX7)
865 sctx->last_index_size = -1;
866 }
867
868 if (indirect) {
869 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
870
871 assert(indirect_va % 8 == 0);
872
873 si_invalidate_draw_sh_constants(sctx);
874
875 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
876 radeon_emit(cs, 1);
877 radeon_emit(cs, indirect_va);
878 radeon_emit(cs, indirect_va >> 32);
879
880 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
881 si_resource(indirect->buffer),
882 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
883
884 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
885 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
886
887 assert(indirect->offset % 4 == 0);
888
889 if (index_size) {
890 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
891 radeon_emit(cs, index_va);
892 radeon_emit(cs, index_va >> 32);
893
894 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
895 radeon_emit(cs, index_max_size);
896 }
897
898 if (!sctx->screen->has_draw_indirect_multi) {
899 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
900 : PKT3_DRAW_INDIRECT,
901 3, render_cond_bit));
902 radeon_emit(cs, indirect->offset);
903 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
904 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
905 radeon_emit(cs, di_src_sel);
906 } else {
907 uint64_t count_va = 0;
908
909 if (indirect->indirect_draw_count) {
910 struct si_resource *params_buf =
911 si_resource(indirect->indirect_draw_count);
912
913 radeon_add_to_buffer_list(
914 sctx, sctx->gfx_cs, params_buf,
915 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
916
917 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
918 }
919
920 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
921 PKT3_DRAW_INDIRECT_MULTI,
922 8, render_cond_bit));
923 radeon_emit(cs, indirect->offset);
924 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
925 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
926 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
927 S_2C3_DRAW_INDEX_ENABLE(1) |
928 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
929 radeon_emit(cs, indirect->draw_count);
930 radeon_emit(cs, count_va);
931 radeon_emit(cs, count_va >> 32);
932 radeon_emit(cs, indirect->stride);
933 radeon_emit(cs, di_src_sel);
934 }
935 } else {
936 int base_vertex;
937
938 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
939 sctx->last_instance_count != instance_count) {
940 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
941 radeon_emit(cs, instance_count);
942 sctx->last_instance_count = instance_count;
943 }
944
945 /* Base vertex and start instance. */
946 base_vertex = original_index_size ? info->index_bias : info->start;
947
948 if (sctx->num_vs_blit_sgprs) {
949 /* Re-emit draw constants after we leave u_blitter. */
950 si_invalidate_draw_sh_constants(sctx);
951
952 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
953 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
954 sctx->num_vs_blit_sgprs);
955 radeon_emit_array(cs, sctx->vs_blit_sh_data,
956 sctx->num_vs_blit_sgprs);
957 } else if (base_vertex != sctx->last_base_vertex ||
958 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
959 info->start_instance != sctx->last_start_instance ||
960 info->drawid != sctx->last_drawid ||
961 sh_base_reg != sctx->last_sh_base_reg) {
962 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
963 radeon_emit(cs, base_vertex);
964 radeon_emit(cs, info->start_instance);
965 radeon_emit(cs, info->drawid);
966
967 sctx->last_base_vertex = base_vertex;
968 sctx->last_start_instance = info->start_instance;
969 sctx->last_drawid = info->drawid;
970 sctx->last_sh_base_reg = sh_base_reg;
971 }
972
973 if (index_size) {
974 if (dispatch_prim_discard_cs) {
975 index_va += info->start * original_index_size;
976 index_max_size = MIN2(index_max_size, info->count);
977
978 si_dispatch_prim_discard_cs_and_draw(sctx, info,
979 original_index_size,
980 base_vertex,
981 index_va, index_max_size);
982 return;
983 }
984
985 index_va += info->start * index_size;
986
987 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
988 radeon_emit(cs, index_max_size);
989 radeon_emit(cs, index_va);
990 radeon_emit(cs, index_va >> 32);
991 radeon_emit(cs, info->count);
992 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
993 } else {
994 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
995 radeon_emit(cs, info->count);
996 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
997 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
998 }
999 }
1000 }
1001
1002 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1003 unsigned cp_coher_cntl)
1004 {
1005 bool compute_ib = !sctx->has_graphics ||
1006 cs == sctx->prim_discard_compute_cs;
1007
1008 if (sctx->chip_class >= GFX9 || compute_ib) {
1009 /* Flush caches and wait for the caches to assert idle. */
1010 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
1011 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1012 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1013 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1014 radeon_emit(cs, 0); /* CP_COHER_BASE */
1015 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1016 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1017 } else {
1018 /* ACQUIRE_MEM is only required on a compute ring. */
1019 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1020 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1021 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1022 radeon_emit(cs, 0); /* CP_COHER_BASE */
1023 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1024 }
1025
1026 /* ACQUIRE_MEM has an implicit context roll if the current context
1027 * is busy. */
1028 if (!compute_ib)
1029 sctx->context_roll = true;
1030 }
1031
1032 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1033 {
1034 if (!si_compute_prim_discard_enabled(sctx))
1035 return;
1036
1037 if (!sctx->barrier_buf) {
1038 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1039 &sctx->barrier_buf_offset,
1040 (struct pipe_resource**)&sctx->barrier_buf);
1041 }
1042
1043 /* Emit a placeholder to signal the next compute IB to start.
1044 * See si_compute_prim_discard.c for explanation.
1045 */
1046 uint32_t signal = 1;
1047 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1048 4, V_370_MEM, V_370_ME, &signal);
1049
1050 sctx->last_pkt3_write_data =
1051 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1052
1053 /* Only the last occurence of WRITE_DATA will be executed.
1054 * The packet will be enabled in si_flush_gfx_cs.
1055 */
1056 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1057 }
1058
1059 void gfx10_emit_cache_flush(struct si_context *ctx)
1060 {
1061 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1062 uint32_t gcr_cntl = 0;
1063 unsigned cb_db_event = 0;
1064 unsigned flags = ctx->flags;
1065
1066 if (!ctx->has_graphics) {
1067 /* Only process compute flags. */
1068 flags &= SI_CONTEXT_INV_ICACHE |
1069 SI_CONTEXT_INV_SCACHE |
1070 SI_CONTEXT_INV_VCACHE |
1071 SI_CONTEXT_INV_L2 |
1072 SI_CONTEXT_WB_L2 |
1073 SI_CONTEXT_INV_L2_METADATA |
1074 SI_CONTEXT_CS_PARTIAL_FLUSH;
1075 }
1076
1077 /* We don't need these. */
1078 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
1079 SI_CONTEXT_VGT_STREAMOUT_SYNC |
1080 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1081
1082 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1083 ctx->num_cb_cache_flushes++;
1084 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1085 ctx->num_db_cache_flushes++;
1086
1087 if (flags & SI_CONTEXT_INV_ICACHE)
1088 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1089 if (flags & SI_CONTEXT_INV_SCACHE) {
1090 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1091 * to FORWARD when both L1 and L2 are written out (WB or INV).
1092 */
1093 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1094 }
1095 if (flags & SI_CONTEXT_INV_VCACHE)
1096 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1097 if (flags & SI_CONTEXT_INV_L2) {
1098 /* Writeback and invalidate everything in L2. */
1099 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1100 ctx->num_L2_invalidates++;
1101 } else if (flags & SI_CONTEXT_WB_L2) {
1102 /* Writeback but do not invalidate. */
1103 gcr_cntl |= S_586_GL2_WB(1);
1104 }
1105 if (flags & SI_CONTEXT_INV_L2_METADATA)
1106 gcr_cntl |= S_586_GLM_INV(1);
1107
1108 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1109 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1110 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1111 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1112 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1113 EVENT_INDEX(0));
1114 }
1115 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1116 /* Flush HTILE. Will wait for idle later. */
1117 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1118 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1119 EVENT_INDEX(0));
1120 }
1121
1122 /* First flush CB/DB, then L1/L2. */
1123 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1124
1125 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1126 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1127 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1128 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1129 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1130 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1131 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1132 } else {
1133 assert(0);
1134 }
1135 } else {
1136 /* Wait for graphics shaders to go idle if requested. */
1137 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1138 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1139 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1140 /* Only count explicit shader flushes, not implicit ones. */
1141 ctx->num_vs_flushes++;
1142 ctx->num_ps_flushes++;
1143 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1145 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1146 ctx->num_vs_flushes++;
1147 }
1148 }
1149
1150 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1151 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1152 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1153 ctx->num_cs_flushes++;
1154 ctx->compute_is_busy = false;
1155 }
1156
1157 if (cb_db_event) {
1158 /* CB/DB flush and invalidate (or possibly just a wait for a
1159 * meta flush) via RELEASE_MEM.
1160 *
1161 * Combine this with other cache flushes when possible; this
1162 * requires affected shaders to be idle, so do it after the
1163 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1164 * implied).
1165 */
1166 uint64_t va;
1167
1168 /* Do the flush (enqueue the event and wait for it). */
1169 va = ctx->wait_mem_scratch->gpu_address;
1170 ctx->wait_mem_number++;
1171
1172 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1173 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1174 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1175 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1176 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1177 assert(G_586_GL2_US(gcr_cntl) == 0);
1178 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1179 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1180 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1181 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1182 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1183
1184 gcr_cntl &= C_586_GLM_WB &
1185 C_586_GLM_INV &
1186 C_586_GLV_INV &
1187 C_586_GL1_INV &
1188 C_586_GL2_INV &
1189 C_586_GL2_WB; /* keep SEQ */
1190
1191 si_cp_release_mem(ctx, cs, cb_db_event,
1192 S_490_GLM_WB(glm_wb) |
1193 S_490_GLM_INV(glm_inv) |
1194 S_490_GLV_INV(glv_inv) |
1195 S_490_GL1_INV(gl1_inv) |
1196 S_490_GL2_INV(gl2_inv) |
1197 S_490_GL2_WB(gl2_wb) |
1198 S_490_SEQ(gcr_seq),
1199 EOP_DST_SEL_MEM,
1200 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1201 EOP_DATA_SEL_VALUE_32BIT,
1202 ctx->wait_mem_scratch, va,
1203 ctx->wait_mem_number, SI_NOT_QUERY);
1204 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1205 WAIT_REG_MEM_EQUAL);
1206 }
1207
1208 /* Ignore fields that only modify the behavior of other fields. */
1209 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1210 /* Flush caches and wait for the caches to assert idle.
1211 * The cache flush is executed in the ME, but the PFP waits
1212 * for completion.
1213 */
1214 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1215 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1216 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1217 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1218 radeon_emit(cs, 0); /* CP_COHER_BASE */
1219 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1220 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1221 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1222 } else if (cb_db_event ||
1223 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1224 SI_CONTEXT_PS_PARTIAL_FLUSH |
1225 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1226 /* We need to ensure that PFP waits as well. */
1227 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1228 radeon_emit(cs, 0);
1229 }
1230
1231 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1232 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1233 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1234 EVENT_INDEX(0));
1235 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1236 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1237 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1238 EVENT_INDEX(0));
1239 }
1240
1241 ctx->flags = 0;
1242 }
1243
1244 void si_emit_cache_flush(struct si_context *sctx)
1245 {
1246 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1247 uint32_t flags = sctx->flags;
1248
1249 if (!sctx->has_graphics) {
1250 /* Only process compute flags. */
1251 flags &= SI_CONTEXT_INV_ICACHE |
1252 SI_CONTEXT_INV_SCACHE |
1253 SI_CONTEXT_INV_VCACHE |
1254 SI_CONTEXT_INV_L2 |
1255 SI_CONTEXT_WB_L2 |
1256 SI_CONTEXT_INV_L2_METADATA |
1257 SI_CONTEXT_CS_PARTIAL_FLUSH;
1258 }
1259
1260 uint32_t cp_coher_cntl = 0;
1261 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1262 SI_CONTEXT_FLUSH_AND_INV_DB);
1263 const bool is_barrier = flush_cb_db ||
1264 /* INV_ICACHE == beginning of gfx IB. Checking
1265 * INV_ICACHE fixes corruption for DeusExMD with
1266 * compute-based culling, but I don't know why.
1267 */
1268 flags & (SI_CONTEXT_INV_ICACHE |
1269 SI_CONTEXT_PS_PARTIAL_FLUSH |
1270 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1271 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1272 sctx->compute_is_busy);
1273
1274 assert(sctx->chip_class <= GFX9);
1275
1276 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1277 sctx->num_cb_cache_flushes++;
1278 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1279 sctx->num_db_cache_flushes++;
1280
1281 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1282 * bit is set. An alternative way is to write SQC_CACHES, but that
1283 * doesn't seem to work reliably. Since the bug doesn't affect
1284 * correctness (it only does more work than necessary) and
1285 * the performance impact is likely negligible, there is no plan
1286 * to add a workaround for it.
1287 */
1288
1289 if (flags & SI_CONTEXT_INV_ICACHE)
1290 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1291 if (flags & SI_CONTEXT_INV_SCACHE)
1292 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1293
1294 if (sctx->chip_class <= GFX8) {
1295 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1296 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1297 S_0085F0_CB0_DEST_BASE_ENA(1) |
1298 S_0085F0_CB1_DEST_BASE_ENA(1) |
1299 S_0085F0_CB2_DEST_BASE_ENA(1) |
1300 S_0085F0_CB3_DEST_BASE_ENA(1) |
1301 S_0085F0_CB4_DEST_BASE_ENA(1) |
1302 S_0085F0_CB5_DEST_BASE_ENA(1) |
1303 S_0085F0_CB6_DEST_BASE_ENA(1) |
1304 S_0085F0_CB7_DEST_BASE_ENA(1);
1305
1306 /* Necessary for DCC */
1307 if (sctx->chip_class == GFX8)
1308 si_cp_release_mem(sctx, cs,
1309 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1310 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1311 EOP_DATA_SEL_DISCARD, NULL,
1312 0, 0, SI_NOT_QUERY);
1313 }
1314 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1315 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1316 S_0085F0_DB_DEST_BASE_ENA(1);
1317 }
1318
1319 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1320 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1321 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1322 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1323 }
1324 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1325 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1326 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1327 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1328 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1329 }
1330
1331 /* Wait for shader engines to go idle.
1332 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1333 * for everything including CB/DB cache flushes.
1334 */
1335 if (!flush_cb_db) {
1336 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1337 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1338 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1339 /* Only count explicit shader flushes, not implicit ones
1340 * done by SURFACE_SYNC.
1341 */
1342 sctx->num_vs_flushes++;
1343 sctx->num_ps_flushes++;
1344 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1345 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1346 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1347 sctx->num_vs_flushes++;
1348 }
1349 }
1350
1351 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1352 sctx->compute_is_busy) {
1353 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1354 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1355 sctx->num_cs_flushes++;
1356 sctx->compute_is_busy = false;
1357 }
1358
1359 /* VGT state synchronization. */
1360 if (flags & SI_CONTEXT_VGT_FLUSH) {
1361 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1362 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1363 }
1364 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1365 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1366 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1367 }
1368
1369 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1370 * wait for idle on GFX9. We have to use a TS event.
1371 */
1372 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1373 uint64_t va;
1374 unsigned tc_flags, cb_db_event;
1375
1376 /* Set the CB/DB flush event. */
1377 switch (flush_cb_db) {
1378 case SI_CONTEXT_FLUSH_AND_INV_CB:
1379 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1380 break;
1381 case SI_CONTEXT_FLUSH_AND_INV_DB:
1382 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1383 break;
1384 default:
1385 /* both CB & DB */
1386 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1387 }
1388
1389 /* These are the only allowed combinations. If you need to
1390 * do multiple operations at once, do them separately.
1391 * All operations that invalidate L2 also seem to invalidate
1392 * metadata. Volatile (VOL) and WC flushes are not listed here.
1393 *
1394 * TC | TC_WB = writeback & invalidate L2 & L1
1395 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1396 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1397 * TC | TC_NC = invalidate L2 for MTYPE == NC
1398 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1399 * TCL1 = invalidate L1
1400 */
1401 tc_flags = 0;
1402
1403 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1404 tc_flags = EVENT_TC_ACTION_ENA |
1405 EVENT_TC_MD_ACTION_ENA;
1406 }
1407
1408 /* Ideally flush TC together with CB/DB. */
1409 if (flags & SI_CONTEXT_INV_L2) {
1410 /* Writeback and invalidate everything in L2 & L1. */
1411 tc_flags = EVENT_TC_ACTION_ENA |
1412 EVENT_TC_WB_ACTION_ENA;
1413
1414 /* Clear the flags. */
1415 flags &= ~(SI_CONTEXT_INV_L2 |
1416 SI_CONTEXT_WB_L2 |
1417 SI_CONTEXT_INV_VCACHE);
1418 sctx->num_L2_invalidates++;
1419 }
1420
1421 /* Do the flush (enqueue the event and wait for it). */
1422 va = sctx->wait_mem_scratch->gpu_address;
1423 sctx->wait_mem_number++;
1424
1425 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1426 EOP_DST_SEL_MEM,
1427 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1428 EOP_DATA_SEL_VALUE_32BIT,
1429 sctx->wait_mem_scratch, va,
1430 sctx->wait_mem_number, SI_NOT_QUERY);
1431 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1432 WAIT_REG_MEM_EQUAL);
1433 }
1434
1435 /* Make sure ME is idle (it executes most packets) before continuing.
1436 * This prevents read-after-write hazards between PFP and ME.
1437 */
1438 if (sctx->has_graphics &&
1439 (cp_coher_cntl ||
1440 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1441 SI_CONTEXT_INV_VCACHE |
1442 SI_CONTEXT_INV_L2 |
1443 SI_CONTEXT_WB_L2)))) {
1444 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1445 radeon_emit(cs, 0);
1446 }
1447
1448 /* GFX6-GFX8 only:
1449 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1450 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1451 *
1452 * cp_coher_cntl should contain all necessary flags except TC flags
1453 * at this point.
1454 *
1455 * GFX6-GFX7 don't support L2 write-back.
1456 */
1457 if (flags & SI_CONTEXT_INV_L2 ||
1458 (sctx->chip_class <= GFX7 &&
1459 (flags & SI_CONTEXT_WB_L2))) {
1460 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1461 * WB must be set on GFX8+ when TC_ACTION is set.
1462 */
1463 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1464 S_0085F0_TC_ACTION_ENA(1) |
1465 S_0085F0_TCL1_ACTION_ENA(1) |
1466 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1467 cp_coher_cntl = 0;
1468 sctx->num_L2_invalidates++;
1469 } else {
1470 /* L1 invalidation and L2 writeback must be done separately,
1471 * because both operations can't be done together.
1472 */
1473 if (flags & SI_CONTEXT_WB_L2) {
1474 /* WB = write-back
1475 * NC = apply to non-coherent MTYPEs
1476 * (i.e. MTYPE <= 1, which is what we use everywhere)
1477 *
1478 * WB doesn't work without NC.
1479 */
1480 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1481 S_0301F0_TC_WB_ACTION_ENA(1) |
1482 S_0301F0_TC_NC_ACTION_ENA(1));
1483 cp_coher_cntl = 0;
1484 sctx->num_L2_writebacks++;
1485 }
1486 if (flags & SI_CONTEXT_INV_VCACHE) {
1487 /* Invalidate per-CU VMEM L1. */
1488 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1489 S_0085F0_TCL1_ACTION_ENA(1));
1490 cp_coher_cntl = 0;
1491 }
1492 }
1493
1494 /* If TC flushes haven't cleared this... */
1495 if (cp_coher_cntl)
1496 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1497
1498 if (is_barrier)
1499 si_prim_discard_signal_next_compute_ib_start(sctx);
1500
1501 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1502 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1503 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1504 EVENT_INDEX(0));
1505 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1506 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1507 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1508 EVENT_INDEX(0));
1509 }
1510
1511 sctx->flags = 0;
1512 }
1513
1514 static void si_get_draw_start_count(struct si_context *sctx,
1515 const struct pipe_draw_info *info,
1516 unsigned *start, unsigned *count)
1517 {
1518 struct pipe_draw_indirect_info *indirect = info->indirect;
1519
1520 if (indirect) {
1521 unsigned indirect_count;
1522 struct pipe_transfer *transfer;
1523 unsigned begin, end;
1524 unsigned map_size;
1525 unsigned *data;
1526
1527 if (indirect->indirect_draw_count) {
1528 data = pipe_buffer_map_range(&sctx->b,
1529 indirect->indirect_draw_count,
1530 indirect->indirect_draw_count_offset,
1531 sizeof(unsigned),
1532 PIPE_TRANSFER_READ, &transfer);
1533
1534 indirect_count = *data;
1535
1536 pipe_buffer_unmap(&sctx->b, transfer);
1537 } else {
1538 indirect_count = indirect->draw_count;
1539 }
1540
1541 if (!indirect_count) {
1542 *start = *count = 0;
1543 return;
1544 }
1545
1546 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1547 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1548 indirect->offset, map_size,
1549 PIPE_TRANSFER_READ, &transfer);
1550
1551 begin = UINT_MAX;
1552 end = 0;
1553
1554 for (unsigned i = 0; i < indirect_count; ++i) {
1555 unsigned count = data[0];
1556 unsigned start = data[2];
1557
1558 if (count > 0) {
1559 begin = MIN2(begin, start);
1560 end = MAX2(end, start + count);
1561 }
1562
1563 data += indirect->stride / sizeof(unsigned);
1564 }
1565
1566 pipe_buffer_unmap(&sctx->b, transfer);
1567
1568 if (begin < end) {
1569 *start = begin;
1570 *count = end - begin;
1571 } else {
1572 *start = *count = 0;
1573 }
1574 } else {
1575 *start = info->start;
1576 *count = info->count;
1577 }
1578 }
1579
1580 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1581 enum pipe_prim_type prim, unsigned instance_count,
1582 bool primitive_restart, unsigned skip_atom_mask)
1583 {
1584 unsigned num_patches = 0;
1585
1586 si_emit_rasterizer_prim_state(sctx);
1587 if (sctx->tes_shader.cso)
1588 si_emit_derived_tess_state(sctx, info, &num_patches);
1589
1590 /* Emit state atoms. */
1591 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1592 while (mask)
1593 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1594
1595 sctx->dirty_atoms &= skip_atom_mask;
1596
1597 /* Emit states. */
1598 mask = sctx->dirty_states;
1599 while (mask) {
1600 unsigned i = u_bit_scan(&mask);
1601 struct si_pm4_state *state = sctx->queued.array[i];
1602
1603 if (!state || sctx->emitted.array[i] == state)
1604 continue;
1605
1606 si_pm4_emit(sctx, state);
1607 sctx->emitted.array[i] = state;
1608 }
1609 sctx->dirty_states = 0;
1610
1611 /* Emit draw states. */
1612 si_emit_vs_state(sctx, info);
1613 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1614 primitive_restart);
1615 }
1616
1617 static bool
1618 si_all_vs_resources_read_only(struct si_context *sctx,
1619 struct pipe_resource *indexbuf)
1620 {
1621 struct radeon_winsys *ws = sctx->ws;
1622 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1623
1624 /* Index buffer. */
1625 if (indexbuf &&
1626 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1627 RADEON_USAGE_WRITE))
1628 goto has_write_reference;
1629
1630 /* Vertex buffers. */
1631 struct si_vertex_elements *velems = sctx->vertex_elements;
1632 unsigned num_velems = velems->count;
1633
1634 for (unsigned i = 0; i < num_velems; i++) {
1635 if (!((1 << i) & velems->first_vb_use_mask))
1636 continue;
1637
1638 unsigned vb_index = velems->vertex_buffer_index[i];
1639 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1640 if (!res)
1641 continue;
1642
1643 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1644 RADEON_USAGE_WRITE))
1645 goto has_write_reference;
1646 }
1647
1648 /* Constant and shader buffers. */
1649 struct si_descriptors *buffers =
1650 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1651 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1652 unsigned index = buffers->first_active_slot + i;
1653 struct pipe_resource *res =
1654 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1655 if (!res)
1656 continue;
1657
1658 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1659 RADEON_USAGE_WRITE))
1660 goto has_write_reference;
1661 }
1662
1663 /* Samplers. */
1664 struct si_shader_selector *vs = sctx->vs_shader.cso;
1665 if (vs->info.samplers_declared) {
1666 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1667
1668 for (unsigned i = 0; i < num_samplers; i++) {
1669 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1670 if (!view)
1671 continue;
1672
1673 if (ws->cs_is_buffer_referenced(cs,
1674 si_resource(view->texture)->buf,
1675 RADEON_USAGE_WRITE))
1676 goto has_write_reference;
1677 }
1678 }
1679
1680 /* Images. */
1681 if (vs->info.images_declared) {
1682 unsigned num_images = util_last_bit(vs->info.images_declared);
1683
1684 for (unsigned i = 0; i < num_images; i++) {
1685 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1686 if (!res)
1687 continue;
1688
1689 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1690 RADEON_USAGE_WRITE))
1691 goto has_write_reference;
1692 }
1693 }
1694
1695 return true;
1696
1697 has_write_reference:
1698 /* If the current gfx IB has enough packets, flush it to remove write
1699 * references to buffers.
1700 */
1701 if (cs->prev_dw + cs->current.cdw > 2048) {
1702 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1703 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1704 return true;
1705 }
1706 return false;
1707 }
1708
1709 static ALWAYS_INLINE bool pd_msg(const char *s)
1710 {
1711 if (SI_PRIM_DISCARD_DEBUG)
1712 printf("PD failed: %s\n", s);
1713 return false;
1714 }
1715
1716 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1717 {
1718 struct si_context *sctx = (struct si_context *)ctx;
1719 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1720 struct pipe_resource *indexbuf = info->index.resource;
1721 unsigned dirty_tex_counter, dirty_buf_counter;
1722 enum pipe_prim_type rast_prim, prim = info->mode;
1723 unsigned index_size = info->index_size;
1724 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1725 unsigned instance_count = info->instance_count;
1726 bool primitive_restart = info->primitive_restart &&
1727 (!sctx->screen->options.prim_restart_tri_strips_only ||
1728 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1729 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1730
1731 if (likely(!info->indirect)) {
1732 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1733 * no workaround for indirect draws, but we can at least skip
1734 * direct draws.
1735 */
1736 if (unlikely(!instance_count))
1737 return;
1738
1739 /* Handle count == 0. */
1740 if (unlikely(!info->count &&
1741 (index_size || !info->count_from_stream_output)))
1742 return;
1743 }
1744
1745 if (unlikely(!sctx->vs_shader.cso ||
1746 !rs ||
1747 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1748 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1749 assert(0);
1750 return;
1751 }
1752
1753 /* Recompute and re-emit the texture resource states if needed. */
1754 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1755 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1756 sctx->last_dirty_tex_counter = dirty_tex_counter;
1757 sctx->framebuffer.dirty_cbufs |=
1758 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1759 sctx->framebuffer.dirty_zsbuf = true;
1760 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1761 si_update_all_texture_descriptors(sctx);
1762 }
1763
1764 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1765 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1766 sctx->last_dirty_buf_counter = dirty_buf_counter;
1767 /* Rebind all buffers unconditionally. */
1768 si_rebind_buffer(sctx, NULL);
1769 }
1770
1771 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1772
1773 /* Set the rasterization primitive type.
1774 *
1775 * This must be done after si_decompress_textures, which can call
1776 * draw_vbo recursively, and before si_update_shaders, which uses
1777 * current_rast_prim for this draw_vbo call. */
1778 if (sctx->gs_shader.cso)
1779 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1780 else if (sctx->tes_shader.cso) {
1781 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1782 rast_prim = PIPE_PRIM_POINTS;
1783 else
1784 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1785 } else
1786 rast_prim = prim;
1787
1788 if (rast_prim != sctx->current_rast_prim) {
1789 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1790 util_prim_is_points_or_lines(rast_prim))
1791 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1792
1793 sctx->current_rast_prim = rast_prim;
1794 sctx->do_update_shaders = true;
1795 }
1796
1797 if (sctx->tes_shader.cso &&
1798 sctx->screen->has_ls_vgpr_init_bug) {
1799 /* Determine whether the LS VGPR fix should be applied.
1800 *
1801 * It is only required when num input CPs > num output CPs,
1802 * which cannot happen with the fixed function TCS. We should
1803 * also update this bit when switching from TCS to fixed
1804 * function TCS.
1805 */
1806 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1807 bool ls_vgpr_fix =
1808 tcs &&
1809 info->vertices_per_patch >
1810 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1811
1812 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1813 sctx->ls_vgpr_fix = ls_vgpr_fix;
1814 sctx->do_update_shaders = true;
1815 }
1816 }
1817
1818 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1819 /* Determine whether the GS triangle strip adjacency fix should
1820 * be applied. Rotate every other triangle if
1821 * - triangle strips with adjacency are fed to the GS and
1822 * - primitive restart is disabled (the rotation doesn't help
1823 * when the restart occurs after an odd number of triangles).
1824 */
1825 bool gs_tri_strip_adj_fix =
1826 !sctx->tes_shader.cso &&
1827 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1828 !primitive_restart;
1829
1830 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1831 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1832 sctx->do_update_shaders = true;
1833 }
1834 }
1835
1836 if (index_size) {
1837 /* Translate or upload, if needed. */
1838 /* 8-bit indices are supported on GFX8. */
1839 if (sctx->chip_class <= GFX7 && index_size == 1) {
1840 unsigned start, count, start_offset, size, offset;
1841 void *ptr;
1842
1843 si_get_draw_start_count(sctx, info, &start, &count);
1844 start_offset = start * 2;
1845 size = count * 2;
1846
1847 indexbuf = NULL;
1848 u_upload_alloc(ctx->stream_uploader, start_offset,
1849 size,
1850 si_optimal_tcc_alignment(sctx, size),
1851 &offset, &indexbuf, &ptr);
1852 if (!indexbuf)
1853 return;
1854
1855 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1856 index_offset + start,
1857 count, ptr);
1858
1859 /* info->start will be added by the drawing code */
1860 index_offset = offset - start_offset;
1861 index_size = 2;
1862 } else if (info->has_user_indices) {
1863 unsigned start_offset;
1864
1865 assert(!info->indirect);
1866 start_offset = info->start * index_size;
1867
1868 indexbuf = NULL;
1869 u_upload_data(ctx->stream_uploader, start_offset,
1870 info->count * index_size,
1871 sctx->screen->info.tcc_cache_line_size,
1872 (char*)info->index.user + start_offset,
1873 &index_offset, &indexbuf);
1874 if (!indexbuf)
1875 return;
1876
1877 /* info->start will be added by the drawing code */
1878 index_offset -= start_offset;
1879 } else if (sctx->chip_class <= GFX7 &&
1880 si_resource(indexbuf)->TC_L2_dirty) {
1881 /* GFX8 reads index buffers through TC L2, so it doesn't
1882 * need this. */
1883 sctx->flags |= SI_CONTEXT_WB_L2;
1884 si_resource(indexbuf)->TC_L2_dirty = false;
1885 }
1886 }
1887
1888 bool dispatch_prim_discard_cs = false;
1889 bool prim_discard_cs_instancing = false;
1890 unsigned original_index_size = index_size;
1891 unsigned direct_count = 0;
1892
1893 if (info->indirect) {
1894 struct pipe_draw_indirect_info *indirect = info->indirect;
1895
1896 /* Add the buffer size for memory checking in need_cs_space. */
1897 si_context_add_resource_size(sctx, indirect->buffer);
1898
1899 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1900 if (sctx->chip_class <= GFX8) {
1901 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1902 sctx->flags |= SI_CONTEXT_WB_L2;
1903 si_resource(indirect->buffer)->TC_L2_dirty = false;
1904 }
1905
1906 if (indirect->indirect_draw_count &&
1907 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1908 sctx->flags |= SI_CONTEXT_WB_L2;
1909 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1910 }
1911 }
1912 } else {
1913 /* Multiply by 3 for strips and fans to get an approximate vertex
1914 * count as triangles. */
1915 direct_count = info->count * instance_count *
1916 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1917 }
1918
1919 /* Determine if we can use the primitive discard compute shader. */
1920 if (si_compute_prim_discard_enabled(sctx) &&
1921 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1922 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1923 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1924 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1925 (primitive_restart ?
1926 /* Supported prim types with primitive restart: */
1927 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1928 /* Disallow instancing with primitive restart: */
1929 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1930 /* Supported prim types without primitive restart + allow instancing: */
1931 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1932 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1933 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1934 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1935 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1936 (instance_count == 1 ||
1937 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1938 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1939 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1940 (!sctx->render_cond || pd_msg("render condition")) &&
1941 /* Forced enablement ignores pipeline statistics queries. */
1942 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1943 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1944 pd_msg("pipestat or primgen query")) &&
1945 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1946 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1947 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1948 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1949 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1950 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1951 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1952 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1953 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1954 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1955 !sctx->vs_shader.cso->so.num_outputs &&
1956 #else
1957 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1958 #endif
1959 /* Check that all buffers are used for read only, because compute
1960 * dispatches can run ahead. */
1961 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1962 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1963 case SI_PRIM_DISCARD_ENABLED:
1964 original_index_size = index_size;
1965 prim_discard_cs_instancing = instance_count > 1;
1966 dispatch_prim_discard_cs = true;
1967
1968 /* The compute shader changes/lowers the following: */
1969 prim = PIPE_PRIM_TRIANGLES;
1970 index_size = 4;
1971 instance_count = 1;
1972 primitive_restart = false;
1973 sctx->compute_num_verts_rejected -= direct_count;
1974 sctx->compute_num_verts_accepted += direct_count;
1975 break;
1976 case SI_PRIM_DISCARD_DISABLED:
1977 break;
1978 case SI_PRIM_DISCARD_DRAW_SPLIT:
1979 sctx->compute_num_verts_rejected -= direct_count;
1980 goto return_cleanup;
1981 }
1982 }
1983
1984 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1985 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1986 sctx->do_update_shaders = true;
1987 }
1988
1989 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1990 goto return_cleanup;
1991
1992 si_need_gfx_cs_space(sctx);
1993
1994 if (sctx->bo_list_add_all_gfx_resources)
1995 si_gfx_resources_add_all_to_bo_list(sctx);
1996
1997 /* Since we've called si_context_add_resource_size for vertex buffers,
1998 * this must be called after si_need_cs_space, because we must let
1999 * need_cs_space flush before we add buffers to the buffer list.
2000 */
2001 if (!si_upload_vertex_buffer_descriptors(sctx))
2002 goto return_cleanup;
2003
2004 /* Vega10/Raven scissor bug workaround. When any context register is
2005 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2006 * registers must be written too.
2007 */
2008 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
2009 unsigned masked_atoms = 0;
2010
2011 if (has_gfx9_scissor_bug) {
2012 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2013
2014 if (info->count_from_stream_output ||
2015 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2016 sctx->dirty_states & si_states_that_always_roll_context())
2017 sctx->context_roll = true;
2018 }
2019
2020 /* Use optimal packet order based on whether we need to sync the pipeline. */
2021 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2022 SI_CONTEXT_FLUSH_AND_INV_DB |
2023 SI_CONTEXT_PS_PARTIAL_FLUSH |
2024 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2025 /* If we have to wait for idle, set all states first, so that all
2026 * SET packets are processed in parallel with previous draw calls.
2027 * Then draw and prefetch at the end. This ensures that the time
2028 * the CUs are idle is very short.
2029 */
2030 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2031 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2032
2033 if (!si_upload_graphics_shader_descriptors(sctx))
2034 goto return_cleanup;
2035
2036 /* Emit all states except possibly render condition. */
2037 si_emit_all_states(sctx, info, prim, instance_count,
2038 primitive_restart, masked_atoms);
2039 sctx->emit_cache_flush(sctx);
2040 /* <-- CUs are idle here. */
2041
2042 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2043 sctx->atoms.s.render_cond.emit(sctx);
2044
2045 if (has_gfx9_scissor_bug &&
2046 (sctx->context_roll ||
2047 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2048 sctx->atoms.s.scissors.emit(sctx);
2049
2050 sctx->dirty_atoms = 0;
2051
2052 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2053 instance_count, dispatch_prim_discard_cs,
2054 original_index_size);
2055 /* <-- CUs are busy here. */
2056
2057 /* Start prefetches after the draw has been started. Both will run
2058 * in parallel, but starting the draw first is more important.
2059 */
2060 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2061 cik_emit_prefetch_L2(sctx, false);
2062 } else {
2063 /* If we don't wait for idle, start prefetches first, then set
2064 * states, and draw at the end.
2065 */
2066 if (sctx->flags)
2067 sctx->emit_cache_flush(sctx);
2068
2069 /* Only prefetch the API VS and VBO descriptors. */
2070 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2071 cik_emit_prefetch_L2(sctx, true);
2072
2073 if (!si_upload_graphics_shader_descriptors(sctx))
2074 goto return_cleanup;
2075
2076 si_emit_all_states(sctx, info, prim, instance_count,
2077 primitive_restart, masked_atoms);
2078
2079 if (has_gfx9_scissor_bug &&
2080 (sctx->context_roll ||
2081 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2082 sctx->atoms.s.scissors.emit(sctx);
2083
2084 sctx->dirty_atoms = 0;
2085
2086 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2087 instance_count, dispatch_prim_discard_cs,
2088 original_index_size);
2089
2090 /* Prefetch the remaining shaders after the draw has been
2091 * started. */
2092 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2093 cik_emit_prefetch_L2(sctx, false);
2094 }
2095
2096 /* Clear the context roll flag after the draw call. */
2097 sctx->context_roll = false;
2098
2099 if (unlikely(sctx->current_saved_cs)) {
2100 si_trace_emit(sctx);
2101 si_log_draw_state(sctx, sctx->log);
2102 }
2103
2104 /* Workaround for a VGT hang when streamout is enabled.
2105 * It must be done after drawing. */
2106 if ((sctx->family == CHIP_HAWAII ||
2107 sctx->family == CHIP_TONGA ||
2108 sctx->family == CHIP_FIJI) &&
2109 si_get_strmout_en(sctx)) {
2110 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2111 }
2112
2113 if (unlikely(sctx->decompression_enabled)) {
2114 sctx->num_decompress_calls++;
2115 } else {
2116 sctx->num_draw_calls++;
2117 if (sctx->framebuffer.state.nr_cbufs > 1)
2118 sctx->num_mrt_draw_calls++;
2119 if (primitive_restart)
2120 sctx->num_prim_restart_calls++;
2121 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2122 sctx->num_spill_draw_calls++;
2123 }
2124
2125 return_cleanup:
2126 if (index_size && indexbuf != info->index.resource)
2127 pipe_resource_reference(&indexbuf, NULL);
2128 }
2129
2130 static void
2131 si_draw_rectangle(struct blitter_context *blitter,
2132 void *vertex_elements_cso,
2133 blitter_get_vs_func get_vs,
2134 int x1, int y1, int x2, int y2,
2135 float depth, unsigned num_instances,
2136 enum blitter_attrib_type type,
2137 const union blitter_attrib *attrib)
2138 {
2139 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2140 struct si_context *sctx = (struct si_context*)pipe;
2141
2142 /* Pack position coordinates as signed int16. */
2143 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2144 ((uint32_t)(y1 & 0xffff) << 16);
2145 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2146 ((uint32_t)(y2 & 0xffff) << 16);
2147 sctx->vs_blit_sh_data[2] = fui(depth);
2148
2149 switch (type) {
2150 case UTIL_BLITTER_ATTRIB_COLOR:
2151 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2152 sizeof(float)*4);
2153 break;
2154 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2155 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2156 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2157 sizeof(attrib->texcoord));
2158 break;
2159 case UTIL_BLITTER_ATTRIB_NONE:;
2160 }
2161
2162 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2163
2164 struct pipe_draw_info info = {};
2165 info.mode = SI_PRIM_RECTANGLE_LIST;
2166 info.count = 3;
2167 info.instance_count = num_instances;
2168
2169 /* Don't set per-stage shader pointers for VS. */
2170 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2171 sctx->vertex_buffer_pointer_dirty = false;
2172
2173 si_draw_vbo(pipe, &info);
2174 }
2175
2176 void si_trace_emit(struct si_context *sctx)
2177 {
2178 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2179 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2180
2181 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2182 0, 4, V_370_MEM, V_370_ME, &trace_id);
2183
2184 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2185 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2186
2187 if (sctx->log)
2188 u_log_flush(sctx->log);
2189 }
2190
2191 void si_init_draw_functions(struct si_context *sctx)
2192 {
2193 sctx->b.draw_vbo = si_draw_vbo;
2194
2195 sctx->blitter->draw_rectangle = si_draw_rectangle;
2196
2197 si_init_ia_multi_vgt_param_table(sctx);
2198 }