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radeonsi: also apply the GS hang workaround to draws without tessellation
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static bool si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_cmdbuf *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return false;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = ls->lshs_vertex_stride;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While CIK can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance.
169 * The hardware can do more, but the radeonsi shader constant is
170 * limited to 6 bits.
171 */
172 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
173
174 /* When distributed tessellation is unsupported, switch between SEs
175 * at a higher frequency to compensate for it.
176 */
177 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
178 *num_patches = MIN2(*num_patches, 16); /* recommended */
179
180 /* Make sure that vector lanes are reasonably occupied. It probably
181 * doesn't matter much because this is LS-HS, and TES is likely to
182 * occupy significantly more CUs.
183 */
184 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
185 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
186 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
187
188 if (sctx->chip_class == SI) {
189 /* SI bug workaround, related to power management. Limit LS-HS
190 * threadgroups to only one wave.
191 */
192 unsigned one_wave = 64 / max_verts_per_patch;
193 *num_patches = MIN2(*num_patches, one_wave);
194 }
195
196 /* The VGT HS block increments the patch ID unconditionally
197 * within a single threadgroup. This results in incorrect
198 * patch IDs when instanced draws are used.
199 *
200 * The intended solution is to restrict threadgroups to
201 * a single instance by setting SWITCH_ON_EOI, which
202 * should cause IA to split instances up. However, this
203 * doesn't work correctly on SI when there is no other
204 * SE to switch to.
205 */
206 if (has_primid_instancing_bug && tess_uses_primid)
207 *num_patches = 1;
208
209 sctx->last_num_patches = *num_patches;
210
211 output_patch0_offset = input_patch_size * *num_patches;
212 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
213
214 /* Compute userdata SGPRs. */
215 assert(((input_vertex_size / 4) & ~0xff) == 0);
216 assert(((output_vertex_size / 4) & ~0xff) == 0);
217 assert(((input_patch_size / 4) & ~0x1fff) == 0);
218 assert(((output_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
220 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
221 assert(num_tcs_input_cp <= 32);
222 assert(num_tcs_output_cp <= 32);
223
224 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
225 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
226
227 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
228 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
229 tcs_out_layout = (output_patch_size / 4) |
230 (num_tcs_input_cp << 13) |
231 ring_va;
232 tcs_out_offsets = (output_patch0_offset / 16) |
233 ((perpatch_output_offset / 16) << 16);
234 offchip_layout = *num_patches |
235 (num_tcs_output_cp << 6) |
236 (pervertex_output_patch_size * *num_patches << 12);
237
238 /* Compute the LDS size. */
239 lds_size = output_patch0_offset + output_patch_size * *num_patches;
240
241 if (sctx->chip_class >= CIK) {
242 assert(lds_size <= 65536);
243 lds_size = align(lds_size, 512) / 512;
244 } else {
245 assert(lds_size <= 32768);
246 lds_size = align(lds_size, 256) / 256;
247 }
248
249 /* Set SI_SGPR_VS_STATE_BITS. */
250 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
251 C_VS_STATE_LS_OUT_VERTEX_SIZE;
252 sctx->current_vs_state |= tcs_in_layout;
253
254 if (sctx->chip_class >= GFX9) {
255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
256 S_00B42C_LDS_SIZE(lds_size);
257
258 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
259
260 /* Set userdata SGPRs for merged LS-HS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
263 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout);
267 } else {
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
269
270 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
271 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
272
273 /* Due to a hw bug, RSRC2_LS must be written twice with another
274 * LS register written in between. */
275 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
276 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
280
281 /* Set userdata SGPRs for TCS. */
282 radeon_set_sh_reg_seq(cs,
283 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout);
287 radeon_emit(cs, tcs_in_layout);
288 }
289
290 /* Set userdata SGPRs for TES. */
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
292 radeon_emit(cs, offchip_layout);
293 radeon_emit(cs, ring_va);
294
295 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
296 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
297 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
298
299 if (sctx->last_ls_hs_config != ls_hs_config) {
300 if (sctx->chip_class >= CIK) {
301 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
302 ls_hs_config);
303 } else {
304 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
305 ls_hs_config);
306 }
307 sctx->last_ls_hs_config = ls_hs_config;
308 return true; /* true if the context rolls */
309 }
310 return false;
311 }
312
313 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
314 {
315 switch (info->mode) {
316 case PIPE_PRIM_PATCHES:
317 return info->count / info->vertices_per_patch;
318 case PIPE_PRIM_POLYGON:
319 return info->count >= 3;
320 case SI_PRIM_RECTANGLE_LIST:
321 return info->count / 3;
322 default:
323 return u_decomposed_prims_for_vertices(info->mode, info->count);
324 }
325 }
326
327 static unsigned
328 si_get_init_multi_vgt_param(struct si_screen *sscreen,
329 union si_vgt_param_key *key)
330 {
331 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
332 unsigned max_primgroup_in_wave = 2;
333
334 /* SWITCH_ON_EOP(0) is always preferable. */
335 bool wd_switch_on_eop = false;
336 bool ia_switch_on_eop = false;
337 bool ia_switch_on_eoi = false;
338 bool partial_vs_wave = false;
339 bool partial_es_wave = false;
340
341 if (key->u.uses_tess) {
342 /* SWITCH_ON_EOI must be set if PrimID is used. */
343 if (key->u.tess_uses_prim_id)
344 ia_switch_on_eoi = true;
345
346 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
347 if ((sscreen->info.family == CHIP_TAHITI ||
348 sscreen->info.family == CHIP_PITCAIRN ||
349 sscreen->info.family == CHIP_BONAIRE) &&
350 key->u.uses_gs)
351 partial_vs_wave = true;
352
353 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= VI) */
354 if (sscreen->has_distributed_tess) {
355 if (key->u.uses_gs) {
356 if (sscreen->info.chip_class == VI)
357 partial_es_wave = true;
358 } else {
359 partial_vs_wave = true;
360 }
361 }
362 }
363
364 /* This is a hardware requirement. */
365 if (key->u.line_stipple_enabled ||
366 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
367 ia_switch_on_eop = true;
368 wd_switch_on_eop = true;
369 }
370
371 if (sscreen->info.chip_class >= CIK) {
372 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
373 * 4 shader engines. Set 1 to pass the assertion below.
374 * The other cases are hardware requirements.
375 *
376 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
377 * for points, line strips, and tri strips.
378 */
379 if (sscreen->info.max_se <= 2 ||
380 key->u.prim == PIPE_PRIM_POLYGON ||
381 key->u.prim == PIPE_PRIM_LINE_LOOP ||
382 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
383 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
384 (key->u.primitive_restart &&
385 (sscreen->info.family < CHIP_POLARIS10 ||
386 (key->u.prim != PIPE_PRIM_POINTS &&
387 key->u.prim != PIPE_PRIM_LINE_STRIP &&
388 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
389 key->u.count_from_stream_output)
390 wd_switch_on_eop = true;
391
392 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
393 * We don't know that for indirect drawing, so treat it as
394 * always problematic. */
395 if (sscreen->info.family == CHIP_HAWAII &&
396 key->u.uses_instancing)
397 wd_switch_on_eop = true;
398
399 /* Performance recommendation for 4 SE Gfx7-8 parts if
400 * instances are smaller than a primgroup.
401 * Assume indirect draws always use small instances.
402 * This is needed for good VS wave utilization.
403 */
404 if (sscreen->info.chip_class <= VI &&
405 sscreen->info.max_se == 4 &&
406 key->u.multi_instances_smaller_than_primgroup)
407 wd_switch_on_eop = true;
408
409 /* Required on CIK and later. */
410 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
411 ia_switch_on_eoi = true;
412
413 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
414 * to work around a GS hang.
415 */
416 if (key->u.uses_gs &&
417 (sscreen->info.family == CHIP_TONGA ||
418 sscreen->info.family == CHIP_FIJI ||
419 sscreen->info.family == CHIP_POLARIS10 ||
420 sscreen->info.family == CHIP_POLARIS11 ||
421 sscreen->info.family == CHIP_POLARIS12 ||
422 sscreen->info.family == CHIP_VEGAM))
423 partial_vs_wave = true;
424
425 /* Required by Hawaii and, for some special cases, by VI. */
426 if (ia_switch_on_eoi &&
427 (sscreen->info.family == CHIP_HAWAII ||
428 (sscreen->info.chip_class == VI &&
429 (key->u.uses_gs || max_primgroup_in_wave != 2))))
430 partial_vs_wave = true;
431
432 /* Instancing bug on Bonaire. */
433 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
434 key->u.uses_instancing)
435 partial_vs_wave = true;
436
437 /* This only applies to Polaris10 and later 4 SE chips.
438 * wd_switch_on_eop is already true on all other chips.
439 */
440 if (!wd_switch_on_eop && key->u.primitive_restart)
441 partial_vs_wave = true;
442
443 /* If the WD switch is false, the IA switch must be false too. */
444 assert(wd_switch_on_eop || !ia_switch_on_eop);
445 }
446
447 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
448 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
449 partial_es_wave = true;
450
451 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
452 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
453 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
454 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
455 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
456 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
457 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
458 max_primgroup_in_wave : 0) |
459 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
460 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
461 }
462
463 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
464 {
465 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
466 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
467 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
468 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
469 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
470 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
471 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
472 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
473 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
474 union si_vgt_param_key key;
475
476 key.index = 0;
477 key.u.prim = prim;
478 key.u.uses_instancing = uses_instancing;
479 key.u.multi_instances_smaller_than_primgroup = multi_instances;
480 key.u.primitive_restart = primitive_restart;
481 key.u.count_from_stream_output = count_from_so;
482 key.u.line_stipple_enabled = line_stipple;
483 key.u.uses_tess = uses_tess;
484 key.u.tess_uses_prim_id = tess_uses_primid;
485 key.u.uses_gs = uses_gs;
486
487 sctx->ia_multi_vgt_param[key.index] =
488 si_get_init_multi_vgt_param(sctx->screen, &key);
489 }
490 }
491
492 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
493 const struct pipe_draw_info *info,
494 unsigned num_patches)
495 {
496 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
497 unsigned primgroup_size;
498 unsigned ia_multi_vgt_param;
499
500 if (sctx->tes_shader.cso) {
501 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
502 } else if (sctx->gs_shader.cso) {
503 primgroup_size = 64; /* recommended with a GS */
504 } else {
505 primgroup_size = 128; /* recommended without a GS and tess */
506 }
507
508 key.u.prim = info->mode;
509 key.u.uses_instancing = info->indirect || info->instance_count > 1;
510 key.u.multi_instances_smaller_than_primgroup =
511 info->indirect ||
512 (info->instance_count > 1 &&
513 (info->count_from_stream_output ||
514 si_num_prims_for_vertices(info) < primgroup_size));
515 key.u.primitive_restart = info->primitive_restart;
516 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
517
518 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
519 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
520
521 if (sctx->gs_shader.cso) {
522 /* GS requirement. */
523 if (sctx->chip_class <= VI &&
524 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
525 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
526
527 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
528 * The hw doc says all multi-SE chips are affected, but Vulkan
529 * only applies it to Hawaii. Do what Vulkan does.
530 */
531 if (sctx->family == CHIP_HAWAII &&
532 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
533 (info->indirect ||
534 (info->instance_count > 1 &&
535 (info->count_from_stream_output ||
536 si_num_prims_for_vertices(info) <= 1))))
537 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
538 }
539
540 return ia_multi_vgt_param;
541 }
542
543 /* rast_prim is the primitive type after GS. */
544 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
545 {
546 struct radeon_cmdbuf *cs = sctx->gfx_cs;
547 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
548 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
549
550 /* Skip this if not rendering lines. */
551 if (!util_prim_is_lines(rast_prim))
552 return false;
553
554 if (rast_prim == sctx->last_rast_prim &&
555 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
556 return false;
557
558 /* For lines, reset the stipple pattern at each primitive. Otherwise,
559 * reset the stipple pattern at each packet (line strips, line loops).
560 */
561 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
562 rs->pa_sc_line_stipple |
563 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
564
565 sctx->last_rast_prim = rast_prim;
566 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
567 return true; /* true if the context rolls */
568 }
569
570 static void si_emit_vs_state(struct si_context *sctx,
571 const struct pipe_draw_info *info)
572 {
573 sctx->current_vs_state &= C_VS_STATE_INDEXED;
574 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
575
576 if (sctx->num_vs_blit_sgprs) {
577 /* Re-emit the state after we leave u_blitter. */
578 sctx->last_vs_state = ~0;
579 return;
580 }
581
582 if (sctx->current_vs_state != sctx->last_vs_state) {
583 struct radeon_cmdbuf *cs = sctx->gfx_cs;
584
585 /* For the API vertex shader (VS_STATE_INDEXED). */
586 radeon_set_sh_reg(cs,
587 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
588 SI_SGPR_VS_STATE_BITS * 4,
589 sctx->current_vs_state);
590
591 /* For vertex color clamping, which is done in the last stage
592 * before the rasterizer. */
593 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
594 /* GS copy shader or TES if GS is missing. */
595 radeon_set_sh_reg(cs,
596 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
597 SI_SGPR_VS_STATE_BITS * 4,
598 sctx->current_vs_state);
599 }
600
601 sctx->last_vs_state = sctx->current_vs_state;
602 }
603 }
604
605 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
606 const struct pipe_draw_info *info)
607 {
608 return info->primitive_restart &&
609 (info->restart_index != sctx->last_restart_index ||
610 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
611 }
612
613 static void si_emit_draw_registers(struct si_context *sctx,
614 const struct pipe_draw_info *info,
615 unsigned num_patches)
616 {
617 struct radeon_cmdbuf *cs = sctx->gfx_cs;
618 unsigned prim = si_conv_pipe_prim(info->mode);
619 unsigned ia_multi_vgt_param;
620
621 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
622
623 /* Draw state. */
624 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
625 if (sctx->chip_class >= GFX9)
626 radeon_set_uconfig_reg_idx(cs, sctx->screen,
627 R_030960_IA_MULTI_VGT_PARAM, 4,
628 ia_multi_vgt_param);
629 else if (sctx->chip_class >= CIK)
630 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
631 else
632 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
633
634 sctx->last_multi_vgt_param = ia_multi_vgt_param;
635 }
636 if (prim != sctx->last_prim) {
637 if (sctx->chip_class >= CIK)
638 radeon_set_uconfig_reg_idx(cs, sctx->screen,
639 R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
640 else
641 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
642
643 sctx->last_prim = prim;
644 }
645
646 /* Primitive restart. */
647 if (info->primitive_restart != sctx->last_primitive_restart_en) {
648 if (sctx->chip_class >= GFX9)
649 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
650 info->primitive_restart);
651 else
652 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
653 info->primitive_restart);
654
655 sctx->last_primitive_restart_en = info->primitive_restart;
656
657 }
658 if (si_prim_restart_index_changed(sctx, info)) {
659 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
660 info->restart_index);
661 sctx->last_restart_index = info->restart_index;
662 }
663 }
664
665 static void si_emit_draw_packets(struct si_context *sctx,
666 const struct pipe_draw_info *info,
667 struct pipe_resource *indexbuf,
668 unsigned index_size,
669 unsigned index_offset)
670 {
671 struct pipe_draw_indirect_info *indirect = info->indirect;
672 struct radeon_cmdbuf *cs = sctx->gfx_cs;
673 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
674 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
675 uint32_t index_max_size = 0;
676 uint64_t index_va = 0;
677
678 if (info->count_from_stream_output) {
679 struct si_streamout_target *t =
680 (struct si_streamout_target*)info->count_from_stream_output;
681 uint64_t va = t->buf_filled_size->gpu_address +
682 t->buf_filled_size_offset;
683
684 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
685 t->stride_in_dw);
686
687 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
688 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
689 COPY_DATA_DST_SEL(COPY_DATA_REG) |
690 COPY_DATA_WR_CONFIRM);
691 radeon_emit(cs, va); /* src address lo */
692 radeon_emit(cs, va >> 32); /* src address hi */
693 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
694 radeon_emit(cs, 0); /* unused */
695
696 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
697 t->buf_filled_size, RADEON_USAGE_READ,
698 RADEON_PRIO_SO_FILLED_SIZE);
699 }
700
701 /* draw packet */
702 if (index_size) {
703 if (index_size != sctx->last_index_size) {
704 unsigned index_type;
705
706 /* index type */
707 switch (index_size) {
708 case 1:
709 index_type = V_028A7C_VGT_INDEX_8;
710 break;
711 case 2:
712 index_type = V_028A7C_VGT_INDEX_16 |
713 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
714 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
715 break;
716 case 4:
717 index_type = V_028A7C_VGT_INDEX_32 |
718 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
719 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
720 break;
721 default:
722 assert(!"unreachable");
723 return;
724 }
725
726 if (sctx->chip_class >= GFX9) {
727 radeon_set_uconfig_reg_idx(cs, sctx->screen,
728 R_03090C_VGT_INDEX_TYPE, 2,
729 index_type);
730 } else {
731 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
732 radeon_emit(cs, index_type);
733 }
734
735 sctx->last_index_size = index_size;
736 }
737
738 index_max_size = (indexbuf->width0 - index_offset) /
739 index_size;
740 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
741
742 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
743 r600_resource(indexbuf),
744 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
745 } else {
746 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
747 * so the state must be re-emitted before the next indexed draw.
748 */
749 if (sctx->chip_class >= CIK)
750 sctx->last_index_size = -1;
751 }
752
753 if (indirect) {
754 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
755
756 assert(indirect_va % 8 == 0);
757
758 si_invalidate_draw_sh_constants(sctx);
759
760 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
761 radeon_emit(cs, 1);
762 radeon_emit(cs, indirect_va);
763 radeon_emit(cs, indirect_va >> 32);
764
765 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
766 r600_resource(indirect->buffer),
767 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
768
769 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
770 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
771
772 assert(indirect->offset % 4 == 0);
773
774 if (index_size) {
775 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
776 radeon_emit(cs, index_va);
777 radeon_emit(cs, index_va >> 32);
778
779 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
780 radeon_emit(cs, index_max_size);
781 }
782
783 if (!sctx->screen->has_draw_indirect_multi) {
784 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
785 : PKT3_DRAW_INDIRECT,
786 3, render_cond_bit));
787 radeon_emit(cs, indirect->offset);
788 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
789 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
790 radeon_emit(cs, di_src_sel);
791 } else {
792 uint64_t count_va = 0;
793
794 if (indirect->indirect_draw_count) {
795 struct r600_resource *params_buf =
796 r600_resource(indirect->indirect_draw_count);
797
798 radeon_add_to_buffer_list(
799 sctx, sctx->gfx_cs, params_buf,
800 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
801
802 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
803 }
804
805 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
806 PKT3_DRAW_INDIRECT_MULTI,
807 8, render_cond_bit));
808 radeon_emit(cs, indirect->offset);
809 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
810 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
811 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
812 S_2C3_DRAW_INDEX_ENABLE(1) |
813 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
814 radeon_emit(cs, indirect->draw_count);
815 radeon_emit(cs, count_va);
816 radeon_emit(cs, count_va >> 32);
817 radeon_emit(cs, indirect->stride);
818 radeon_emit(cs, di_src_sel);
819 }
820 } else {
821 unsigned instance_count = info->instance_count;
822 int base_vertex;
823
824 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
825 sctx->last_instance_count != instance_count) {
826 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
827 radeon_emit(cs, instance_count);
828 sctx->last_instance_count = instance_count;
829 }
830
831 /* Base vertex and start instance. */
832 base_vertex = index_size ? info->index_bias : info->start;
833
834 if (sctx->num_vs_blit_sgprs) {
835 /* Re-emit draw constants after we leave u_blitter. */
836 si_invalidate_draw_sh_constants(sctx);
837
838 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
839 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
840 sctx->num_vs_blit_sgprs);
841 radeon_emit_array(cs, sctx->vs_blit_sh_data,
842 sctx->num_vs_blit_sgprs);
843 } else if (base_vertex != sctx->last_base_vertex ||
844 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
845 info->start_instance != sctx->last_start_instance ||
846 info->drawid != sctx->last_drawid ||
847 sh_base_reg != sctx->last_sh_base_reg) {
848 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
849 radeon_emit(cs, base_vertex);
850 radeon_emit(cs, info->start_instance);
851 radeon_emit(cs, info->drawid);
852
853 sctx->last_base_vertex = base_vertex;
854 sctx->last_start_instance = info->start_instance;
855 sctx->last_drawid = info->drawid;
856 sctx->last_sh_base_reg = sh_base_reg;
857 }
858
859 if (index_size) {
860 index_va += info->start * index_size;
861
862 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
863 radeon_emit(cs, index_max_size);
864 radeon_emit(cs, index_va);
865 radeon_emit(cs, index_va >> 32);
866 radeon_emit(cs, info->count);
867 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
868 } else {
869 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
870 radeon_emit(cs, info->count);
871 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
872 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
873 }
874 }
875 }
876
877 static void si_emit_surface_sync(struct si_context *sctx,
878 unsigned cp_coher_cntl)
879 {
880 struct radeon_cmdbuf *cs = sctx->gfx_cs;
881
882 if (sctx->chip_class >= GFX9) {
883 /* Flush caches and wait for the caches to assert idle. */
884 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
885 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
886 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
887 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
888 radeon_emit(cs, 0); /* CP_COHER_BASE */
889 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
890 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
891 } else {
892 /* ACQUIRE_MEM is only required on a compute ring. */
893 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
894 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
895 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
896 radeon_emit(cs, 0); /* CP_COHER_BASE */
897 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
898 }
899 }
900
901 void si_emit_cache_flush(struct si_context *sctx)
902 {
903 struct radeon_cmdbuf *cs = sctx->gfx_cs;
904 uint32_t flags = sctx->flags;
905 uint32_t cp_coher_cntl = 0;
906 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
907 SI_CONTEXT_FLUSH_AND_INV_DB);
908
909 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
910 sctx->num_cb_cache_flushes++;
911 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
912 sctx->num_db_cache_flushes++;
913
914 /* SI has a bug that it always flushes ICACHE and KCACHE if either
915 * bit is set. An alternative way is to write SQC_CACHES, but that
916 * doesn't seem to work reliably. Since the bug doesn't affect
917 * correctness (it only does more work than necessary) and
918 * the performance impact is likely negligible, there is no plan
919 * to add a workaround for it.
920 */
921
922 if (flags & SI_CONTEXT_INV_ICACHE)
923 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
924 if (flags & SI_CONTEXT_INV_SMEM_L1)
925 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
926
927 if (sctx->chip_class <= VI) {
928 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
929 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
930 S_0085F0_CB0_DEST_BASE_ENA(1) |
931 S_0085F0_CB1_DEST_BASE_ENA(1) |
932 S_0085F0_CB2_DEST_BASE_ENA(1) |
933 S_0085F0_CB3_DEST_BASE_ENA(1) |
934 S_0085F0_CB4_DEST_BASE_ENA(1) |
935 S_0085F0_CB5_DEST_BASE_ENA(1) |
936 S_0085F0_CB6_DEST_BASE_ENA(1) |
937 S_0085F0_CB7_DEST_BASE_ENA(1);
938
939 /* Necessary for DCC */
940 if (sctx->chip_class == VI)
941 si_cp_release_mem(sctx,
942 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
943 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
944 EOP_DATA_SEL_DISCARD, NULL,
945 0, 0, SI_NOT_QUERY);
946 }
947 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
948 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
949 S_0085F0_DB_DEST_BASE_ENA(1);
950 }
951
952 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
953 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
954 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
955 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
956 }
957 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
958 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
959 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
961 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
962 }
963
964 /* Wait for shader engines to go idle.
965 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
966 * for everything including CB/DB cache flushes.
967 */
968 if (!flush_cb_db) {
969 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
970 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
971 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
972 /* Only count explicit shader flushes, not implicit ones
973 * done by SURFACE_SYNC.
974 */
975 sctx->num_vs_flushes++;
976 sctx->num_ps_flushes++;
977 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
979 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
980 sctx->num_vs_flushes++;
981 }
982 }
983
984 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
985 sctx->compute_is_busy) {
986 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
987 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
988 sctx->num_cs_flushes++;
989 sctx->compute_is_busy = false;
990 }
991
992 /* VGT state synchronization. */
993 if (flags & SI_CONTEXT_VGT_FLUSH) {
994 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
995 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
996 }
997 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
998 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
999 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1000 }
1001
1002 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1003 * wait for idle on GFX9. We have to use a TS event.
1004 */
1005 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1006 uint64_t va;
1007 unsigned tc_flags, cb_db_event;
1008
1009 /* Set the CB/DB flush event. */
1010 switch (flush_cb_db) {
1011 case SI_CONTEXT_FLUSH_AND_INV_CB:
1012 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1013 break;
1014 case SI_CONTEXT_FLUSH_AND_INV_DB:
1015 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1016 break;
1017 default:
1018 /* both CB & DB */
1019 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1020 }
1021
1022 /* These are the only allowed combinations. If you need to
1023 * do multiple operations at once, do them separately.
1024 * All operations that invalidate L2 also seem to invalidate
1025 * metadata. Volatile (VOL) and WC flushes are not listed here.
1026 *
1027 * TC | TC_WB = writeback & invalidate L2 & L1
1028 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1029 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1030 * TC | TC_NC = invalidate L2 for MTYPE == NC
1031 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1032 * TCL1 = invalidate L1
1033 */
1034 tc_flags = 0;
1035
1036 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1037 tc_flags = EVENT_TC_ACTION_ENA |
1038 EVENT_TC_MD_ACTION_ENA;
1039 }
1040
1041 /* Ideally flush TC together with CB/DB. */
1042 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1043 /* Writeback and invalidate everything in L2 & L1. */
1044 tc_flags = EVENT_TC_ACTION_ENA |
1045 EVENT_TC_WB_ACTION_ENA;
1046
1047 /* Clear the flags. */
1048 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1049 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1050 SI_CONTEXT_INV_VMEM_L1);
1051 sctx->num_L2_invalidates++;
1052 }
1053
1054 /* Do the flush (enqueue the event and wait for it). */
1055 va = sctx->wait_mem_scratch->gpu_address;
1056 sctx->wait_mem_number++;
1057
1058 si_cp_release_mem(sctx, cb_db_event, tc_flags,
1059 EOP_DST_SEL_MEM,
1060 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1061 EOP_DATA_SEL_VALUE_32BIT,
1062 sctx->wait_mem_scratch, va,
1063 sctx->wait_mem_number, SI_NOT_QUERY);
1064 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1065 WAIT_REG_MEM_EQUAL);
1066 }
1067
1068 /* Make sure ME is idle (it executes most packets) before continuing.
1069 * This prevents read-after-write hazards between PFP and ME.
1070 */
1071 if (cp_coher_cntl ||
1072 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1073 SI_CONTEXT_INV_VMEM_L1 |
1074 SI_CONTEXT_INV_GLOBAL_L2 |
1075 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1076 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1077 radeon_emit(cs, 0);
1078 }
1079
1080 /* SI-CI-VI only:
1081 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1082 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1083 *
1084 * cp_coher_cntl should contain all necessary flags except TC flags
1085 * at this point.
1086 *
1087 * SI-CIK don't support L2 write-back.
1088 */
1089 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1090 (sctx->chip_class <= CIK &&
1091 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1092 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1093 * WB must be set on VI+ when TC_ACTION is set.
1094 */
1095 si_emit_surface_sync(sctx, cp_coher_cntl |
1096 S_0085F0_TC_ACTION_ENA(1) |
1097 S_0085F0_TCL1_ACTION_ENA(1) |
1098 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1099 cp_coher_cntl = 0;
1100 sctx->num_L2_invalidates++;
1101 } else {
1102 /* L1 invalidation and L2 writeback must be done separately,
1103 * because both operations can't be done together.
1104 */
1105 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1106 /* WB = write-back
1107 * NC = apply to non-coherent MTYPEs
1108 * (i.e. MTYPE <= 1, which is what we use everywhere)
1109 *
1110 * WB doesn't work without NC.
1111 */
1112 si_emit_surface_sync(sctx, cp_coher_cntl |
1113 S_0301F0_TC_WB_ACTION_ENA(1) |
1114 S_0301F0_TC_NC_ACTION_ENA(1));
1115 cp_coher_cntl = 0;
1116 sctx->num_L2_writebacks++;
1117 }
1118 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1119 /* Invalidate per-CU VMEM L1. */
1120 si_emit_surface_sync(sctx, cp_coher_cntl |
1121 S_0085F0_TCL1_ACTION_ENA(1));
1122 cp_coher_cntl = 0;
1123 }
1124 }
1125
1126 /* If TC flushes haven't cleared this... */
1127 if (cp_coher_cntl)
1128 si_emit_surface_sync(sctx, cp_coher_cntl);
1129
1130 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1131 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1132 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1133 EVENT_INDEX(0));
1134 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1135 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1136 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1137 EVENT_INDEX(0));
1138 }
1139
1140 sctx->flags = 0;
1141 }
1142
1143 static void si_get_draw_start_count(struct si_context *sctx,
1144 const struct pipe_draw_info *info,
1145 unsigned *start, unsigned *count)
1146 {
1147 struct pipe_draw_indirect_info *indirect = info->indirect;
1148
1149 if (indirect) {
1150 unsigned indirect_count;
1151 struct pipe_transfer *transfer;
1152 unsigned begin, end;
1153 unsigned map_size;
1154 unsigned *data;
1155
1156 if (indirect->indirect_draw_count) {
1157 data = pipe_buffer_map_range(&sctx->b,
1158 indirect->indirect_draw_count,
1159 indirect->indirect_draw_count_offset,
1160 sizeof(unsigned),
1161 PIPE_TRANSFER_READ, &transfer);
1162
1163 indirect_count = *data;
1164
1165 pipe_buffer_unmap(&sctx->b, transfer);
1166 } else {
1167 indirect_count = indirect->draw_count;
1168 }
1169
1170 if (!indirect_count) {
1171 *start = *count = 0;
1172 return;
1173 }
1174
1175 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1176 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1177 indirect->offset, map_size,
1178 PIPE_TRANSFER_READ, &transfer);
1179
1180 begin = UINT_MAX;
1181 end = 0;
1182
1183 for (unsigned i = 0; i < indirect_count; ++i) {
1184 unsigned count = data[0];
1185 unsigned start = data[2];
1186
1187 if (count > 0) {
1188 begin = MIN2(begin, start);
1189 end = MAX2(end, start + count);
1190 }
1191
1192 data += indirect->stride / sizeof(unsigned);
1193 }
1194
1195 pipe_buffer_unmap(&sctx->b, transfer);
1196
1197 if (begin < end) {
1198 *start = begin;
1199 *count = end - begin;
1200 } else {
1201 *start = *count = 0;
1202 }
1203 } else {
1204 *start = info->start;
1205 *count = info->count;
1206 }
1207 }
1208
1209 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1210 unsigned skip_atom_mask)
1211 {
1212 unsigned num_patches = 0;
1213 /* Vega10/Raven scissor bug workaround. When any context register is
1214 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1215 * registers must be written too.
1216 */
1217 bool handle_scissor_bug = (sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1218 !si_is_atom_dirty(sctx, &sctx->atoms.s.scissors);
1219 bool context_roll = false; /* set correctly for GFX9 only */
1220
1221 context_roll |= si_emit_rasterizer_prim_state(sctx);
1222 if (sctx->tes_shader.cso)
1223 context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
1224
1225 if (handle_scissor_bug &&
1226 (info->count_from_stream_output ||
1227 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1228 sctx->dirty_states & si_states_that_always_roll_context() ||
1229 si_prim_restart_index_changed(sctx, info)))
1230 context_roll = true;
1231
1232 sctx->context_roll_counter = 0;
1233
1234 /* Emit state atoms. */
1235 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1236 while (mask)
1237 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1238
1239 sctx->dirty_atoms &= skip_atom_mask;
1240
1241 /* Emit states. */
1242 mask = sctx->dirty_states;
1243 while (mask) {
1244 unsigned i = u_bit_scan(&mask);
1245 struct si_pm4_state *state = sctx->queued.array[i];
1246
1247 if (!state || sctx->emitted.array[i] == state)
1248 continue;
1249
1250 si_pm4_emit(sctx, state);
1251 sctx->emitted.array[i] = state;
1252 }
1253 sctx->dirty_states = 0;
1254
1255 if (handle_scissor_bug &&
1256 (context_roll || sctx->context_roll_counter)) {
1257 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1258 sctx->atoms.s.scissors.emit(sctx);
1259 }
1260
1261 /* Emit draw states. */
1262 si_emit_vs_state(sctx, info);
1263 si_emit_draw_registers(sctx, info, num_patches);
1264 }
1265
1266 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1267 {
1268 struct si_context *sctx = (struct si_context *)ctx;
1269 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1270 struct pipe_resource *indexbuf = info->index.resource;
1271 unsigned dirty_tex_counter;
1272 enum pipe_prim_type rast_prim;
1273 unsigned index_size = info->index_size;
1274 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1275
1276 if (likely(!info->indirect)) {
1277 /* SI-CI treat instance_count==0 as instance_count==1. There is
1278 * no workaround for indirect draws, but we can at least skip
1279 * direct draws.
1280 */
1281 if (unlikely(!info->instance_count))
1282 return;
1283
1284 /* Handle count == 0. */
1285 if (unlikely(!info->count &&
1286 (index_size || !info->count_from_stream_output)))
1287 return;
1288 }
1289
1290 if (unlikely(!sctx->vs_shader.cso ||
1291 !rs ||
1292 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1293 (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
1294 assert(0);
1295 return;
1296 }
1297
1298 /* Recompute and re-emit the texture resource states if needed. */
1299 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1300 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1301 sctx->last_dirty_tex_counter = dirty_tex_counter;
1302 sctx->framebuffer.dirty_cbufs |=
1303 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1304 sctx->framebuffer.dirty_zsbuf = true;
1305 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1306 si_update_all_texture_descriptors(sctx);
1307 }
1308
1309 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1310
1311 /* Set the rasterization primitive type.
1312 *
1313 * This must be done after si_decompress_textures, which can call
1314 * draw_vbo recursively, and before si_update_shaders, which uses
1315 * current_rast_prim for this draw_vbo call. */
1316 if (sctx->gs_shader.cso)
1317 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1318 else if (sctx->tes_shader.cso) {
1319 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1320 rast_prim = PIPE_PRIM_POINTS;
1321 else
1322 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1323 } else
1324 rast_prim = info->mode;
1325
1326 if (rast_prim != sctx->current_rast_prim) {
1327 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1328 util_prim_is_points_or_lines(rast_prim))
1329 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1330
1331 sctx->current_rast_prim = rast_prim;
1332 sctx->do_update_shaders = true;
1333 }
1334
1335 if (sctx->tes_shader.cso &&
1336 sctx->screen->has_ls_vgpr_init_bug) {
1337 /* Determine whether the LS VGPR fix should be applied.
1338 *
1339 * It is only required when num input CPs > num output CPs,
1340 * which cannot happen with the fixed function TCS. We should
1341 * also update this bit when switching from TCS to fixed
1342 * function TCS.
1343 */
1344 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1345 bool ls_vgpr_fix =
1346 tcs &&
1347 info->vertices_per_patch >
1348 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1349
1350 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1351 sctx->ls_vgpr_fix = ls_vgpr_fix;
1352 sctx->do_update_shaders = true;
1353 }
1354 }
1355
1356 if (sctx->gs_shader.cso) {
1357 /* Determine whether the GS triangle strip adjacency fix should
1358 * be applied. Rotate every other triangle if
1359 * - triangle strips with adjacency are fed to the GS and
1360 * - primitive restart is disabled (the rotation doesn't help
1361 * when the restart occurs after an odd number of triangles).
1362 */
1363 bool gs_tri_strip_adj_fix =
1364 !sctx->tes_shader.cso &&
1365 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1366 !info->primitive_restart;
1367
1368 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1369 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1370 sctx->do_update_shaders = true;
1371 }
1372 }
1373
1374 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1375 return;
1376
1377 if (index_size) {
1378 /* Translate or upload, if needed. */
1379 /* 8-bit indices are supported on VI. */
1380 if (sctx->chip_class <= CIK && index_size == 1) {
1381 unsigned start, count, start_offset, size, offset;
1382 void *ptr;
1383
1384 si_get_draw_start_count(sctx, info, &start, &count);
1385 start_offset = start * 2;
1386 size = count * 2;
1387
1388 indexbuf = NULL;
1389 u_upload_alloc(ctx->stream_uploader, start_offset,
1390 size,
1391 si_optimal_tcc_alignment(sctx, size),
1392 &offset, &indexbuf, &ptr);
1393 if (!indexbuf)
1394 return;
1395
1396 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1397 index_offset + start,
1398 count, ptr);
1399
1400 /* info->start will be added by the drawing code */
1401 index_offset = offset - start_offset;
1402 index_size = 2;
1403 } else if (info->has_user_indices) {
1404 unsigned start_offset;
1405
1406 assert(!info->indirect);
1407 start_offset = info->start * index_size;
1408
1409 indexbuf = NULL;
1410 u_upload_data(ctx->stream_uploader, start_offset,
1411 info->count * index_size,
1412 sctx->screen->info.tcc_cache_line_size,
1413 (char*)info->index.user + start_offset,
1414 &index_offset, &indexbuf);
1415 if (!indexbuf)
1416 return;
1417
1418 /* info->start will be added by the drawing code */
1419 index_offset -= start_offset;
1420 } else if (sctx->chip_class <= CIK &&
1421 r600_resource(indexbuf)->TC_L2_dirty) {
1422 /* VI reads index buffers through TC L2, so it doesn't
1423 * need this. */
1424 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1425 r600_resource(indexbuf)->TC_L2_dirty = false;
1426 }
1427 }
1428
1429 if (info->indirect) {
1430 struct pipe_draw_indirect_info *indirect = info->indirect;
1431
1432 /* Add the buffer size for memory checking in need_cs_space. */
1433 si_context_add_resource_size(sctx, indirect->buffer);
1434
1435 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1436 if (sctx->chip_class <= VI) {
1437 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1438 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1439 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1440 }
1441
1442 if (indirect->indirect_draw_count &&
1443 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1444 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1445 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1446 }
1447 }
1448 }
1449
1450 si_need_gfx_cs_space(sctx);
1451
1452 /* Since we've called si_context_add_resource_size for vertex buffers,
1453 * this must be called after si_need_cs_space, because we must let
1454 * need_cs_space flush before we add buffers to the buffer list.
1455 */
1456 if (!si_upload_vertex_buffer_descriptors(sctx))
1457 return;
1458
1459 /* Use optimal packet order based on whether we need to sync the pipeline. */
1460 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1461 SI_CONTEXT_FLUSH_AND_INV_DB |
1462 SI_CONTEXT_PS_PARTIAL_FLUSH |
1463 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1464 /* If we have to wait for idle, set all states first, so that all
1465 * SET packets are processed in parallel with previous draw calls.
1466 * Then draw and prefetch at the end. This ensures that the time
1467 * the CUs are idle is very short.
1468 */
1469 unsigned masked_atoms = 0;
1470
1471 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1472 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1473
1474 if (!si_upload_graphics_shader_descriptors(sctx))
1475 return;
1476
1477 /* Emit all states except possibly render condition. */
1478 si_emit_all_states(sctx, info, masked_atoms);
1479 si_emit_cache_flush(sctx);
1480 /* <-- CUs are idle here. */
1481
1482 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1483 sctx->atoms.s.render_cond.emit(sctx);
1484 sctx->dirty_atoms = 0;
1485
1486 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1487 /* <-- CUs are busy here. */
1488
1489 /* Start prefetches after the draw has been started. Both will run
1490 * in parallel, but starting the draw first is more important.
1491 */
1492 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1493 cik_emit_prefetch_L2(sctx, false);
1494 } else {
1495 /* If we don't wait for idle, start prefetches first, then set
1496 * states, and draw at the end.
1497 */
1498 if (sctx->flags)
1499 si_emit_cache_flush(sctx);
1500
1501 /* Only prefetch the API VS and VBO descriptors. */
1502 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1503 cik_emit_prefetch_L2(sctx, true);
1504
1505 if (!si_upload_graphics_shader_descriptors(sctx))
1506 return;
1507
1508 si_emit_all_states(sctx, info, 0);
1509 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1510
1511 /* Prefetch the remaining shaders after the draw has been
1512 * started. */
1513 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1514 cik_emit_prefetch_L2(sctx, false);
1515 }
1516
1517 if (unlikely(sctx->current_saved_cs)) {
1518 si_trace_emit(sctx);
1519 si_log_draw_state(sctx, sctx->log);
1520 }
1521
1522 /* Workaround for a VGT hang when streamout is enabled.
1523 * It must be done after drawing. */
1524 if ((sctx->family == CHIP_HAWAII ||
1525 sctx->family == CHIP_TONGA ||
1526 sctx->family == CHIP_FIJI) &&
1527 si_get_strmout_en(sctx)) {
1528 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1529 }
1530
1531 if (unlikely(sctx->decompression_enabled)) {
1532 sctx->num_decompress_calls++;
1533 } else {
1534 sctx->num_draw_calls++;
1535 if (sctx->framebuffer.state.nr_cbufs > 1)
1536 sctx->num_mrt_draw_calls++;
1537 if (info->primitive_restart)
1538 sctx->num_prim_restart_calls++;
1539 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1540 sctx->num_spill_draw_calls++;
1541 }
1542 if (index_size && indexbuf != info->index.resource)
1543 pipe_resource_reference(&indexbuf, NULL);
1544 }
1545
1546 static void
1547 si_draw_rectangle(struct blitter_context *blitter,
1548 void *vertex_elements_cso,
1549 blitter_get_vs_func get_vs,
1550 int x1, int y1, int x2, int y2,
1551 float depth, unsigned num_instances,
1552 enum blitter_attrib_type type,
1553 const union blitter_attrib *attrib)
1554 {
1555 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1556 struct si_context *sctx = (struct si_context*)pipe;
1557
1558 /* Pack position coordinates as signed int16. */
1559 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1560 ((uint32_t)(y1 & 0xffff) << 16);
1561 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1562 ((uint32_t)(y2 & 0xffff) << 16);
1563 sctx->vs_blit_sh_data[2] = fui(depth);
1564
1565 switch (type) {
1566 case UTIL_BLITTER_ATTRIB_COLOR:
1567 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1568 sizeof(float)*4);
1569 break;
1570 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1571 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1572 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1573 sizeof(attrib->texcoord));
1574 break;
1575 case UTIL_BLITTER_ATTRIB_NONE:;
1576 }
1577
1578 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
1579
1580 struct pipe_draw_info info = {};
1581 info.mode = SI_PRIM_RECTANGLE_LIST;
1582 info.count = 3;
1583 info.instance_count = num_instances;
1584
1585 /* Don't set per-stage shader pointers for VS. */
1586 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1587 sctx->vertex_buffer_pointer_dirty = false;
1588
1589 si_draw_vbo(pipe, &info);
1590 }
1591
1592 void si_trace_emit(struct si_context *sctx)
1593 {
1594 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1595 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1596 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1597
1598 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1599 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1600 S_370_WR_CONFIRM(1) |
1601 S_370_ENGINE_SEL(V_370_ME));
1602 radeon_emit(cs, va);
1603 radeon_emit(cs, va >> 32);
1604 radeon_emit(cs, trace_id);
1605 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1606 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1607
1608 if (sctx->log)
1609 u_log_flush(sctx->log);
1610 }
1611
1612 void si_init_draw_functions(struct si_context *sctx)
1613 {
1614 sctx->b.draw_vbo = si_draw_vbo;
1615
1616 sctx->blitter->draw_rectangle = si_draw_rectangle;
1617
1618 si_init_ia_multi_vgt_param_table(sctx);
1619 }