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radeonsi/gfx9: implement the scissor bug workaround without performance drop
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static bool si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_winsys_cs *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return false;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = num_tcs_inputs * 16;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
150
151 /* Make sure that the data fits in LDS. This assumes the shaders only
152 * use LDS for the inputs and outputs.
153 *
154 * While CIK can use 64K per threadgroup, there is a hang on Stoney
155 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
156 * uses 32K at most on all GCN chips.
157 */
158 hardware_lds_size = 32768;
159 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
160 output_patch_size));
161
162 /* Make sure the output data fits in the offchip buffer */
163 *num_patches = MIN2(*num_patches,
164 (sctx->screen->tess_offchip_block_dw_size * 4) /
165 output_patch_size);
166
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
169 */
170 *num_patches = MIN2(*num_patches, 40);
171
172 if (sctx->chip_class == SI) {
173 /* SI bug workaround, related to power management. Limit LS-HS
174 * threadgroups to only one wave.
175 */
176 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
177 *num_patches = MIN2(*num_patches, one_wave);
178 }
179
180 /* The VGT HS block increments the patch ID unconditionally
181 * within a single threadgroup. This results in incorrect
182 * patch IDs when instanced draws are used.
183 *
184 * The intended solution is to restrict threadgroups to
185 * a single instance by setting SWITCH_ON_EOI, which
186 * should cause IA to split instances up. However, this
187 * doesn't work correctly on SI when there is no other
188 * SE to switch to.
189 */
190 if (has_primid_instancing_bug && tess_uses_primid)
191 *num_patches = 1;
192
193 sctx->last_num_patches = *num_patches;
194
195 output_patch0_offset = input_patch_size * *num_patches;
196 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
197
198 /* Compute userdata SGPRs. */
199 assert(((input_vertex_size / 4) & ~0xff) == 0);
200 assert(((output_vertex_size / 4) & ~0xff) == 0);
201 assert(((input_patch_size / 4) & ~0x1fff) == 0);
202 assert(((output_patch_size / 4) & ~0x1fff) == 0);
203 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
204 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
205 assert(num_tcs_input_cp <= 32);
206 assert(num_tcs_output_cp <= 32);
207
208 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
209 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
210
211 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
212 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
213 tcs_out_layout = (output_patch_size / 4) |
214 (num_tcs_input_cp << 13) |
215 ring_va;
216 tcs_out_offsets = (output_patch0_offset / 16) |
217 ((perpatch_output_offset / 16) << 16);
218 offchip_layout = *num_patches |
219 (num_tcs_output_cp << 6) |
220 (pervertex_output_patch_size * *num_patches << 12);
221
222 /* Compute the LDS size. */
223 lds_size = output_patch0_offset + output_patch_size * *num_patches;
224
225 if (sctx->chip_class >= CIK) {
226 assert(lds_size <= 65536);
227 lds_size = align(lds_size, 512) / 512;
228 } else {
229 assert(lds_size <= 32768);
230 lds_size = align(lds_size, 256) / 256;
231 }
232
233 /* Set SI_SGPR_VS_STATE_BITS. */
234 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
235 C_VS_STATE_LS_OUT_VERTEX_SIZE;
236 sctx->current_vs_state |= tcs_in_layout;
237
238 if (sctx->chip_class >= GFX9) {
239 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
240 S_00B42C_LDS_SIZE(lds_size);
241
242 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
243
244 /* Set userdata SGPRs for merged LS-HS. */
245 radeon_set_sh_reg_seq(cs,
246 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
247 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
248 radeon_emit(cs, offchip_layout);
249 radeon_emit(cs, tcs_out_offsets);
250 radeon_emit(cs, tcs_out_layout);
251 } else {
252 unsigned ls_rsrc2 = ls_current->config.rsrc2;
253
254 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
255 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
256
257 /* Due to a hw bug, RSRC2_LS must be written twice with another
258 * LS register written in between. */
259 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
260 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
261 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
262 radeon_emit(cs, ls_current->config.rsrc1);
263 radeon_emit(cs, ls_rsrc2);
264
265 /* Set userdata SGPRs for TCS. */
266 radeon_set_sh_reg_seq(cs,
267 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
268 radeon_emit(cs, offchip_layout);
269 radeon_emit(cs, tcs_out_offsets);
270 radeon_emit(cs, tcs_out_layout);
271 radeon_emit(cs, tcs_in_layout);
272 }
273
274 /* Set userdata SGPRs for TES. */
275 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
276 radeon_emit(cs, offchip_layout);
277 radeon_emit(cs, ring_va);
278
279 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
280 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
281 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
282
283 if (sctx->last_ls_hs_config != ls_hs_config) {
284 if (sctx->chip_class >= CIK) {
285 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
286 ls_hs_config);
287 } else {
288 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
289 ls_hs_config);
290 }
291 sctx->last_ls_hs_config = ls_hs_config;
292 return true; /* true if the context rolls */
293 }
294 return false;
295 }
296
297 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
298 {
299 switch (info->mode) {
300 case PIPE_PRIM_PATCHES:
301 return info->count / info->vertices_per_patch;
302 case SI_PRIM_RECTANGLE_LIST:
303 return info->count / 3;
304 default:
305 return u_prims_for_vertices(info->mode, info->count);
306 }
307 }
308
309 static unsigned
310 si_get_init_multi_vgt_param(struct si_screen *sscreen,
311 union si_vgt_param_key *key)
312 {
313 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
314 unsigned max_primgroup_in_wave = 2;
315
316 /* SWITCH_ON_EOP(0) is always preferable. */
317 bool wd_switch_on_eop = false;
318 bool ia_switch_on_eop = false;
319 bool ia_switch_on_eoi = false;
320 bool partial_vs_wave = false;
321 bool partial_es_wave = false;
322
323 if (key->u.uses_tess) {
324 /* SWITCH_ON_EOI must be set if PrimID is used. */
325 if (key->u.tess_uses_prim_id)
326 ia_switch_on_eoi = true;
327
328 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
329 if ((sscreen->info.family == CHIP_TAHITI ||
330 sscreen->info.family == CHIP_PITCAIRN ||
331 sscreen->info.family == CHIP_BONAIRE) &&
332 key->u.uses_gs)
333 partial_vs_wave = true;
334
335 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
336 if (sscreen->has_distributed_tess) {
337 if (key->u.uses_gs) {
338 if (sscreen->info.chip_class <= VI)
339 partial_es_wave = true;
340
341 /* GPU hang workaround. */
342 if (sscreen->info.family == CHIP_TONGA ||
343 sscreen->info.family == CHIP_FIJI ||
344 sscreen->info.family == CHIP_POLARIS10 ||
345 sscreen->info.family == CHIP_POLARIS11 ||
346 sscreen->info.family == CHIP_POLARIS12 ||
347 sscreen->info.family == CHIP_VEGAM)
348 partial_vs_wave = true;
349 } else {
350 partial_vs_wave = true;
351 }
352 }
353 }
354
355 /* This is a hardware requirement. */
356 if (key->u.line_stipple_enabled ||
357 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
358 ia_switch_on_eop = true;
359 wd_switch_on_eop = true;
360 }
361
362 if (sscreen->info.chip_class >= CIK) {
363 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
364 * 4 shader engines. Set 1 to pass the assertion below.
365 * The other cases are hardware requirements.
366 *
367 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
368 * for points, line strips, and tri strips.
369 */
370 if (sscreen->info.max_se < 4 ||
371 key->u.prim == PIPE_PRIM_POLYGON ||
372 key->u.prim == PIPE_PRIM_LINE_LOOP ||
373 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
374 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
375 (key->u.primitive_restart &&
376 (sscreen->info.family < CHIP_POLARIS10 ||
377 (key->u.prim != PIPE_PRIM_POINTS &&
378 key->u.prim != PIPE_PRIM_LINE_STRIP &&
379 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
380 key->u.count_from_stream_output)
381 wd_switch_on_eop = true;
382
383 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
384 * We don't know that for indirect drawing, so treat it as
385 * always problematic. */
386 if (sscreen->info.family == CHIP_HAWAII &&
387 key->u.uses_instancing)
388 wd_switch_on_eop = true;
389
390 /* Performance recommendation for 4 SE Gfx7-8 parts if
391 * instances are smaller than a primgroup.
392 * Assume indirect draws always use small instances.
393 * This is needed for good VS wave utilization.
394 */
395 if (sscreen->info.chip_class <= VI &&
396 sscreen->info.max_se == 4 &&
397 key->u.multi_instances_smaller_than_primgroup)
398 wd_switch_on_eop = true;
399
400 /* Required on CIK and later. */
401 if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
402 ia_switch_on_eoi = true;
403
404 /* Required by Hawaii and, for some special cases, by VI. */
405 if (ia_switch_on_eoi &&
406 (sscreen->info.family == CHIP_HAWAII ||
407 (sscreen->info.chip_class == VI &&
408 (key->u.uses_gs || max_primgroup_in_wave != 2))))
409 partial_vs_wave = true;
410
411 /* Instancing bug on Bonaire. */
412 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
413 key->u.uses_instancing)
414 partial_vs_wave = true;
415
416 /* If the WD switch is false, the IA switch must be false too. */
417 assert(wd_switch_on_eop || !ia_switch_on_eop);
418 }
419
420 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
421 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
422 partial_es_wave = true;
423
424 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
425 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
426 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
427 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
428 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
429 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
430 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
431 max_primgroup_in_wave : 0) |
432 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
433 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
434 }
435
436 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
437 {
438 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
439 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
440 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
441 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
442 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
443 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
444 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
445 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
446 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
447 union si_vgt_param_key key;
448
449 key.index = 0;
450 key.u.prim = prim;
451 key.u.uses_instancing = uses_instancing;
452 key.u.multi_instances_smaller_than_primgroup = multi_instances;
453 key.u.primitive_restart = primitive_restart;
454 key.u.count_from_stream_output = count_from_so;
455 key.u.line_stipple_enabled = line_stipple;
456 key.u.uses_tess = uses_tess;
457 key.u.tess_uses_prim_id = tess_uses_primid;
458 key.u.uses_gs = uses_gs;
459
460 sctx->ia_multi_vgt_param[key.index] =
461 si_get_init_multi_vgt_param(sctx->screen, &key);
462 }
463 }
464
465 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
466 const struct pipe_draw_info *info,
467 unsigned num_patches)
468 {
469 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
470 unsigned primgroup_size;
471 unsigned ia_multi_vgt_param;
472
473 if (sctx->tes_shader.cso) {
474 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
475 } else if (sctx->gs_shader.cso) {
476 primgroup_size = 64; /* recommended with a GS */
477 } else {
478 primgroup_size = 128; /* recommended without a GS and tess */
479 }
480
481 key.u.prim = info->mode;
482 key.u.uses_instancing = info->indirect || info->instance_count > 1;
483 key.u.multi_instances_smaller_than_primgroup =
484 info->indirect ||
485 (info->instance_count > 1 &&
486 (info->count_from_stream_output ||
487 si_num_prims_for_vertices(info) < primgroup_size));
488 key.u.primitive_restart = info->primitive_restart;
489 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
490
491 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
492 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
493
494 if (sctx->gs_shader.cso) {
495 /* GS requirement. */
496 if (sctx->chip_class <= VI &&
497 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
498 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
499
500 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
501 * The hw doc says all multi-SE chips are affected, but Vulkan
502 * only applies it to Hawaii. Do what Vulkan does.
503 */
504 if (sctx->family == CHIP_HAWAII &&
505 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
506 (info->indirect ||
507 (info->instance_count > 1 &&
508 (info->count_from_stream_output ||
509 si_num_prims_for_vertices(info) <= 1))))
510 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
511 }
512
513 return ia_multi_vgt_param;
514 }
515
516 /* rast_prim is the primitive type after GS. */
517 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
518 {
519 struct radeon_winsys_cs *cs = sctx->gfx_cs;
520 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
521 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
522
523 /* Skip this if not rendering lines. */
524 if (rast_prim != PIPE_PRIM_LINES &&
525 rast_prim != PIPE_PRIM_LINE_LOOP &&
526 rast_prim != PIPE_PRIM_LINE_STRIP &&
527 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
528 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
529 return false;
530
531 if (rast_prim == sctx->last_rast_prim &&
532 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
533 return false;
534
535 /* For lines, reset the stipple pattern at each primitive. Otherwise,
536 * reset the stipple pattern at each packet (line strips, line loops).
537 */
538 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
539 rs->pa_sc_line_stipple |
540 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
541
542 sctx->last_rast_prim = rast_prim;
543 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
544 return true; /* true if the context rolls */
545 }
546
547 static void si_emit_vs_state(struct si_context *sctx,
548 const struct pipe_draw_info *info)
549 {
550 sctx->current_vs_state &= C_VS_STATE_INDEXED;
551 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
552
553 if (sctx->num_vs_blit_sgprs) {
554 /* Re-emit the state after we leave u_blitter. */
555 sctx->last_vs_state = ~0;
556 return;
557 }
558
559 if (sctx->current_vs_state != sctx->last_vs_state) {
560 struct radeon_winsys_cs *cs = sctx->gfx_cs;
561
562 radeon_set_sh_reg(cs,
563 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
564 SI_SGPR_VS_STATE_BITS * 4,
565 sctx->current_vs_state);
566
567 sctx->last_vs_state = sctx->current_vs_state;
568 }
569 }
570
571 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
572 const struct pipe_draw_info *info)
573 {
574 return info->primitive_restart &&
575 (info->restart_index != sctx->last_restart_index ||
576 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
577 }
578
579 static void si_emit_draw_registers(struct si_context *sctx,
580 const struct pipe_draw_info *info,
581 unsigned num_patches)
582 {
583 struct radeon_winsys_cs *cs = sctx->gfx_cs;
584 unsigned prim = si_conv_pipe_prim(info->mode);
585 unsigned ia_multi_vgt_param;
586
587 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
588
589 /* Draw state. */
590 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
591 if (sctx->chip_class >= GFX9)
592 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
593 else if (sctx->chip_class >= CIK)
594 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
595 else
596 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
597
598 sctx->last_multi_vgt_param = ia_multi_vgt_param;
599 }
600 if (prim != sctx->last_prim) {
601 if (sctx->chip_class >= CIK)
602 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
603 else
604 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
605
606 sctx->last_prim = prim;
607 }
608
609 /* Primitive restart. */
610 if (info->primitive_restart != sctx->last_primitive_restart_en) {
611 if (sctx->chip_class >= GFX9)
612 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
613 info->primitive_restart);
614 else
615 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
616 info->primitive_restart);
617
618 sctx->last_primitive_restart_en = info->primitive_restart;
619
620 }
621 if (si_prim_restart_index_changed(sctx, info)) {
622 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
623 info->restart_index);
624 sctx->last_restart_index = info->restart_index;
625 }
626 }
627
628 static void si_emit_draw_packets(struct si_context *sctx,
629 const struct pipe_draw_info *info,
630 struct pipe_resource *indexbuf,
631 unsigned index_size,
632 unsigned index_offset)
633 {
634 struct pipe_draw_indirect_info *indirect = info->indirect;
635 struct radeon_winsys_cs *cs = sctx->gfx_cs;
636 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
637 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
638 uint32_t index_max_size = 0;
639 uint64_t index_va = 0;
640
641 if (info->count_from_stream_output) {
642 struct si_streamout_target *t =
643 (struct si_streamout_target*)info->count_from_stream_output;
644 uint64_t va = t->buf_filled_size->gpu_address +
645 t->buf_filled_size_offset;
646
647 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
648 t->stride_in_dw);
649
650 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
651 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
652 COPY_DATA_DST_SEL(COPY_DATA_REG) |
653 COPY_DATA_WR_CONFIRM);
654 radeon_emit(cs, va); /* src address lo */
655 radeon_emit(cs, va >> 32); /* src address hi */
656 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
657 radeon_emit(cs, 0); /* unused */
658
659 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
660 t->buf_filled_size, RADEON_USAGE_READ,
661 RADEON_PRIO_SO_FILLED_SIZE);
662 }
663
664 /* draw packet */
665 if (index_size) {
666 if (index_size != sctx->last_index_size) {
667 unsigned index_type;
668
669 /* index type */
670 switch (index_size) {
671 case 1:
672 index_type = V_028A7C_VGT_INDEX_8;
673 break;
674 case 2:
675 index_type = V_028A7C_VGT_INDEX_16 |
676 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
677 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
678 break;
679 case 4:
680 index_type = V_028A7C_VGT_INDEX_32 |
681 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
682 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
683 break;
684 default:
685 assert(!"unreachable");
686 return;
687 }
688
689 if (sctx->chip_class >= GFX9) {
690 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
691 2, index_type);
692 } else {
693 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
694 radeon_emit(cs, index_type);
695 }
696
697 sctx->last_index_size = index_size;
698 }
699
700 index_max_size = (indexbuf->width0 - index_offset) /
701 index_size;
702 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
703
704 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
705 r600_resource(indexbuf),
706 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
707 } else {
708 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
709 * so the state must be re-emitted before the next indexed draw.
710 */
711 if (sctx->chip_class >= CIK)
712 sctx->last_index_size = -1;
713 }
714
715 if (indirect) {
716 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
717
718 assert(indirect_va % 8 == 0);
719
720 si_invalidate_draw_sh_constants(sctx);
721
722 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
723 radeon_emit(cs, 1);
724 radeon_emit(cs, indirect_va);
725 radeon_emit(cs, indirect_va >> 32);
726
727 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
728 r600_resource(indirect->buffer),
729 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
730
731 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
732 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
733
734 assert(indirect->offset % 4 == 0);
735
736 if (index_size) {
737 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
738 radeon_emit(cs, index_va);
739 radeon_emit(cs, index_va >> 32);
740
741 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
742 radeon_emit(cs, index_max_size);
743 }
744
745 if (!sctx->screen->has_draw_indirect_multi) {
746 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
747 : PKT3_DRAW_INDIRECT,
748 3, render_cond_bit));
749 radeon_emit(cs, indirect->offset);
750 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
751 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
752 radeon_emit(cs, di_src_sel);
753 } else {
754 uint64_t count_va = 0;
755
756 if (indirect->indirect_draw_count) {
757 struct r600_resource *params_buf =
758 r600_resource(indirect->indirect_draw_count);
759
760 radeon_add_to_buffer_list(
761 sctx, sctx->gfx_cs, params_buf,
762 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
763
764 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
765 }
766
767 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
768 PKT3_DRAW_INDIRECT_MULTI,
769 8, render_cond_bit));
770 radeon_emit(cs, indirect->offset);
771 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
772 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
773 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
774 S_2C3_DRAW_INDEX_ENABLE(1) |
775 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
776 radeon_emit(cs, indirect->draw_count);
777 radeon_emit(cs, count_va);
778 radeon_emit(cs, count_va >> 32);
779 radeon_emit(cs, indirect->stride);
780 radeon_emit(cs, di_src_sel);
781 }
782 } else {
783 int base_vertex;
784
785 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
786 radeon_emit(cs, info->instance_count);
787
788 /* Base vertex and start instance. */
789 base_vertex = index_size ? info->index_bias : info->start;
790
791 if (sctx->num_vs_blit_sgprs) {
792 /* Re-emit draw constants after we leave u_blitter. */
793 si_invalidate_draw_sh_constants(sctx);
794
795 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
796 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
797 sctx->num_vs_blit_sgprs);
798 radeon_emit_array(cs, sctx->vs_blit_sh_data,
799 sctx->num_vs_blit_sgprs);
800 } else if (base_vertex != sctx->last_base_vertex ||
801 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
802 info->start_instance != sctx->last_start_instance ||
803 info->drawid != sctx->last_drawid ||
804 sh_base_reg != sctx->last_sh_base_reg) {
805 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
806 radeon_emit(cs, base_vertex);
807 radeon_emit(cs, info->start_instance);
808 radeon_emit(cs, info->drawid);
809
810 sctx->last_base_vertex = base_vertex;
811 sctx->last_start_instance = info->start_instance;
812 sctx->last_drawid = info->drawid;
813 sctx->last_sh_base_reg = sh_base_reg;
814 }
815
816 if (index_size) {
817 index_va += info->start * index_size;
818
819 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
820 radeon_emit(cs, index_max_size);
821 radeon_emit(cs, index_va);
822 radeon_emit(cs, index_va >> 32);
823 radeon_emit(cs, info->count);
824 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
825 } else {
826 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
827 radeon_emit(cs, info->count);
828 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
829 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
830 }
831 }
832 }
833
834 static void si_emit_surface_sync(struct si_context *sctx,
835 unsigned cp_coher_cntl)
836 {
837 struct radeon_winsys_cs *cs = sctx->gfx_cs;
838
839 if (sctx->chip_class >= GFX9) {
840 /* Flush caches and wait for the caches to assert idle. */
841 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
842 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
843 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
844 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
845 radeon_emit(cs, 0); /* CP_COHER_BASE */
846 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
847 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
848 } else {
849 /* ACQUIRE_MEM is only required on a compute ring. */
850 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
851 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
852 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
853 radeon_emit(cs, 0); /* CP_COHER_BASE */
854 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
855 }
856 }
857
858 void si_emit_cache_flush(struct si_context *sctx)
859 {
860 struct radeon_winsys_cs *cs = sctx->gfx_cs;
861 uint32_t flags = sctx->flags;
862 uint32_t cp_coher_cntl = 0;
863 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
864 SI_CONTEXT_FLUSH_AND_INV_DB);
865
866 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
867 sctx->num_cb_cache_flushes++;
868 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
869 sctx->num_db_cache_flushes++;
870
871 /* SI has a bug that it always flushes ICACHE and KCACHE if either
872 * bit is set. An alternative way is to write SQC_CACHES, but that
873 * doesn't seem to work reliably. Since the bug doesn't affect
874 * correctness (it only does more work than necessary) and
875 * the performance impact is likely negligible, there is no plan
876 * to add a workaround for it.
877 */
878
879 if (flags & SI_CONTEXT_INV_ICACHE)
880 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
881 if (flags & SI_CONTEXT_INV_SMEM_L1)
882 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
883
884 if (sctx->chip_class <= VI) {
885 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
886 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
887 S_0085F0_CB0_DEST_BASE_ENA(1) |
888 S_0085F0_CB1_DEST_BASE_ENA(1) |
889 S_0085F0_CB2_DEST_BASE_ENA(1) |
890 S_0085F0_CB3_DEST_BASE_ENA(1) |
891 S_0085F0_CB4_DEST_BASE_ENA(1) |
892 S_0085F0_CB5_DEST_BASE_ENA(1) |
893 S_0085F0_CB6_DEST_BASE_ENA(1) |
894 S_0085F0_CB7_DEST_BASE_ENA(1);
895
896 /* Necessary for DCC */
897 if (sctx->chip_class == VI)
898 si_gfx_write_event_eop(sctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
899 0, EOP_DATA_SEL_DISCARD, NULL,
900 0, 0, SI_NOT_QUERY);
901 }
902 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
903 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
904 S_0085F0_DB_DEST_BASE_ENA(1);
905 }
906
907 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
908 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
909 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
910 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
911 }
912 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
913 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
914 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
915 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
916 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
917 }
918
919 /* Wait for shader engines to go idle.
920 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
921 * for everything including CB/DB cache flushes.
922 */
923 if (!flush_cb_db) {
924 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
926 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
927 /* Only count explicit shader flushes, not implicit ones
928 * done by SURFACE_SYNC.
929 */
930 sctx->num_vs_flushes++;
931 sctx->num_ps_flushes++;
932 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
933 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
934 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
935 sctx->num_vs_flushes++;
936 }
937 }
938
939 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
940 sctx->compute_is_busy) {
941 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
942 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
943 sctx->num_cs_flushes++;
944 sctx->compute_is_busy = false;
945 }
946
947 /* VGT state synchronization. */
948 if (flags & SI_CONTEXT_VGT_FLUSH) {
949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
950 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
951 }
952 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
953 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
954 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
955 }
956
957 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
958 * wait for idle on GFX9. We have to use a TS event.
959 */
960 if (sctx->chip_class >= GFX9 && flush_cb_db) {
961 uint64_t va;
962 unsigned tc_flags, cb_db_event;
963
964 /* Set the CB/DB flush event. */
965 switch (flush_cb_db) {
966 case SI_CONTEXT_FLUSH_AND_INV_CB:
967 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
968 break;
969 case SI_CONTEXT_FLUSH_AND_INV_DB:
970 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
971 break;
972 default:
973 /* both CB & DB */
974 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
975 }
976
977 /* These are the only allowed combinations. If you need to
978 * do multiple operations at once, do them separately.
979 * All operations that invalidate L2 also seem to invalidate
980 * metadata. Volatile (VOL) and WC flushes are not listed here.
981 *
982 * TC | TC_WB = writeback & invalidate L2 & L1
983 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
984 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
985 * TC | TC_NC = invalidate L2 for MTYPE == NC
986 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
987 * TCL1 = invalidate L1
988 */
989 tc_flags = 0;
990
991 if (flags & SI_CONTEXT_INV_L2_METADATA) {
992 tc_flags = EVENT_TC_ACTION_ENA |
993 EVENT_TC_MD_ACTION_ENA;
994 }
995
996 /* Ideally flush TC together with CB/DB. */
997 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
998 /* Writeback and invalidate everything in L2 & L1. */
999 tc_flags = EVENT_TC_ACTION_ENA |
1000 EVENT_TC_WB_ACTION_ENA;
1001
1002 /* Clear the flags. */
1003 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1004 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1005 SI_CONTEXT_INV_VMEM_L1);
1006 sctx->num_L2_invalidates++;
1007 }
1008
1009 /* Do the flush (enqueue the event and wait for it). */
1010 va = sctx->wait_mem_scratch->gpu_address;
1011 sctx->wait_mem_number++;
1012
1013 si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
1014 EOP_DATA_SEL_VALUE_32BIT,
1015 sctx->wait_mem_scratch, va,
1016 sctx->wait_mem_number, SI_NOT_QUERY);
1017 si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
1018 }
1019
1020 /* Make sure ME is idle (it executes most packets) before continuing.
1021 * This prevents read-after-write hazards between PFP and ME.
1022 */
1023 if (cp_coher_cntl ||
1024 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1025 SI_CONTEXT_INV_VMEM_L1 |
1026 SI_CONTEXT_INV_GLOBAL_L2 |
1027 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1028 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1029 radeon_emit(cs, 0);
1030 }
1031
1032 /* SI-CI-VI only:
1033 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1034 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1035 *
1036 * cp_coher_cntl should contain all necessary flags except TC flags
1037 * at this point.
1038 *
1039 * SI-CIK don't support L2 write-back.
1040 */
1041 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1042 (sctx->chip_class <= CIK &&
1043 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1044 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1045 * WB must be set on VI+ when TC_ACTION is set.
1046 */
1047 si_emit_surface_sync(sctx, cp_coher_cntl |
1048 S_0085F0_TC_ACTION_ENA(1) |
1049 S_0085F0_TCL1_ACTION_ENA(1) |
1050 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1051 cp_coher_cntl = 0;
1052 sctx->num_L2_invalidates++;
1053 } else {
1054 /* L1 invalidation and L2 writeback must be done separately,
1055 * because both operations can't be done together.
1056 */
1057 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1058 /* WB = write-back
1059 * NC = apply to non-coherent MTYPEs
1060 * (i.e. MTYPE <= 1, which is what we use everywhere)
1061 *
1062 * WB doesn't work without NC.
1063 */
1064 si_emit_surface_sync(sctx, cp_coher_cntl |
1065 S_0301F0_TC_WB_ACTION_ENA(1) |
1066 S_0301F0_TC_NC_ACTION_ENA(1));
1067 cp_coher_cntl = 0;
1068 sctx->num_L2_writebacks++;
1069 }
1070 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1071 /* Invalidate per-CU VMEM L1. */
1072 si_emit_surface_sync(sctx, cp_coher_cntl |
1073 S_0085F0_TCL1_ACTION_ENA(1));
1074 cp_coher_cntl = 0;
1075 }
1076 }
1077
1078 /* If TC flushes haven't cleared this... */
1079 if (cp_coher_cntl)
1080 si_emit_surface_sync(sctx, cp_coher_cntl);
1081
1082 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1083 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1084 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1085 EVENT_INDEX(0));
1086 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1087 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1088 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1089 EVENT_INDEX(0));
1090 }
1091
1092 sctx->flags = 0;
1093 }
1094
1095 static void si_get_draw_start_count(struct si_context *sctx,
1096 const struct pipe_draw_info *info,
1097 unsigned *start, unsigned *count)
1098 {
1099 struct pipe_draw_indirect_info *indirect = info->indirect;
1100
1101 if (indirect) {
1102 unsigned indirect_count;
1103 struct pipe_transfer *transfer;
1104 unsigned begin, end;
1105 unsigned map_size;
1106 unsigned *data;
1107
1108 if (indirect->indirect_draw_count) {
1109 data = pipe_buffer_map_range(&sctx->b,
1110 indirect->indirect_draw_count,
1111 indirect->indirect_draw_count_offset,
1112 sizeof(unsigned),
1113 PIPE_TRANSFER_READ, &transfer);
1114
1115 indirect_count = *data;
1116
1117 pipe_buffer_unmap(&sctx->b, transfer);
1118 } else {
1119 indirect_count = indirect->draw_count;
1120 }
1121
1122 if (!indirect_count) {
1123 *start = *count = 0;
1124 return;
1125 }
1126
1127 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1128 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1129 indirect->offset, map_size,
1130 PIPE_TRANSFER_READ, &transfer);
1131
1132 begin = UINT_MAX;
1133 end = 0;
1134
1135 for (unsigned i = 0; i < indirect_count; ++i) {
1136 unsigned count = data[0];
1137 unsigned start = data[2];
1138
1139 if (count > 0) {
1140 begin = MIN2(begin, start);
1141 end = MAX2(end, start + count);
1142 }
1143
1144 data += indirect->stride / sizeof(unsigned);
1145 }
1146
1147 pipe_buffer_unmap(&sctx->b, transfer);
1148
1149 if (begin < end) {
1150 *start = begin;
1151 *count = end - begin;
1152 } else {
1153 *start = *count = 0;
1154 }
1155 } else {
1156 *start = info->start;
1157 *count = info->count;
1158 }
1159 }
1160
1161 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1162 unsigned skip_atom_mask)
1163 {
1164 unsigned num_patches = 0;
1165 bool context_roll = false; /* set correctly for GFX9 only */
1166
1167 context_roll |= si_emit_rasterizer_prim_state(sctx);
1168 if (sctx->tes_shader.cso)
1169 context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
1170 if (info->count_from_stream_output)
1171 context_roll = true;
1172
1173 /* Vega10/Raven scissor bug workaround. When any context register is
1174 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1175 * registers must be written too.
1176 */
1177 if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1178 (context_roll ||
1179 sctx->dirty_atoms & si_atoms_that_roll_context() ||
1180 sctx->dirty_states & si_states_that_roll_context() ||
1181 si_prim_restart_index_changed(sctx, info))) {
1182 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1183 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1184 }
1185
1186 /* Emit state atoms. */
1187 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1188 while (mask)
1189 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1190
1191 sctx->dirty_atoms &= skip_atom_mask;
1192
1193 /* Emit states. */
1194 mask = sctx->dirty_states;
1195 while (mask) {
1196 unsigned i = u_bit_scan(&mask);
1197 struct si_pm4_state *state = sctx->queued.array[i];
1198
1199 if (!state || sctx->emitted.array[i] == state)
1200 continue;
1201
1202 si_pm4_emit(sctx, state);
1203 sctx->emitted.array[i] = state;
1204 }
1205 sctx->dirty_states = 0;
1206
1207 /* Emit draw states. */
1208 si_emit_vs_state(sctx, info);
1209 si_emit_draw_registers(sctx, info, num_patches);
1210 }
1211
1212 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1213 {
1214 struct si_context *sctx = (struct si_context *)ctx;
1215 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1216 struct pipe_resource *indexbuf = info->index.resource;
1217 unsigned dirty_tex_counter;
1218 enum pipe_prim_type rast_prim;
1219 unsigned index_size = info->index_size;
1220 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1221
1222 if (likely(!info->indirect)) {
1223 /* SI-CI treat instance_count==0 as instance_count==1. There is
1224 * no workaround for indirect draws, but we can at least skip
1225 * direct draws.
1226 */
1227 if (unlikely(!info->instance_count))
1228 return;
1229
1230 /* Handle count == 0. */
1231 if (unlikely(!info->count &&
1232 (index_size || !info->count_from_stream_output)))
1233 return;
1234 }
1235
1236 if (unlikely(!sctx->vs_shader.cso)) {
1237 assert(0);
1238 return;
1239 }
1240 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1241 assert(0);
1242 return;
1243 }
1244 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1245 assert(0);
1246 return;
1247 }
1248
1249 /* Recompute and re-emit the texture resource states if needed. */
1250 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1251 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1252 sctx->last_dirty_tex_counter = dirty_tex_counter;
1253 sctx->framebuffer.dirty_cbufs |=
1254 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1255 sctx->framebuffer.dirty_zsbuf = true;
1256 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1257 si_update_all_texture_descriptors(sctx);
1258 }
1259
1260 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1261
1262 /* Set the rasterization primitive type.
1263 *
1264 * This must be done after si_decompress_textures, which can call
1265 * draw_vbo recursively, and before si_update_shaders, which uses
1266 * current_rast_prim for this draw_vbo call. */
1267 if (sctx->gs_shader.cso)
1268 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1269 else if (sctx->tes_shader.cso) {
1270 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1271 rast_prim = PIPE_PRIM_POINTS;
1272 else
1273 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1274 } else
1275 rast_prim = info->mode;
1276
1277 if (rast_prim != sctx->current_rast_prim) {
1278 bool old_is_poly = sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES;
1279 bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
1280 if (old_is_poly != new_is_poly) {
1281 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1282 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1283 }
1284
1285 sctx->current_rast_prim = rast_prim;
1286 sctx->do_update_shaders = true;
1287 }
1288
1289 if (sctx->tes_shader.cso &&
1290 sctx->screen->has_ls_vgpr_init_bug) {
1291 /* Determine whether the LS VGPR fix should be applied.
1292 *
1293 * It is only required when num input CPs > num output CPs,
1294 * which cannot happen with the fixed function TCS. We should
1295 * also update this bit when switching from TCS to fixed
1296 * function TCS.
1297 */
1298 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1299 bool ls_vgpr_fix =
1300 tcs &&
1301 info->vertices_per_patch >
1302 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1303
1304 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1305 sctx->ls_vgpr_fix = ls_vgpr_fix;
1306 sctx->do_update_shaders = true;
1307 }
1308 }
1309
1310 if (sctx->gs_shader.cso) {
1311 /* Determine whether the GS triangle strip adjacency fix should
1312 * be applied. Rotate every other triangle if
1313 * - triangle strips with adjacency are fed to the GS and
1314 * - primitive restart is disabled (the rotation doesn't help
1315 * when the restart occurs after an odd number of triangles).
1316 */
1317 bool gs_tri_strip_adj_fix =
1318 !sctx->tes_shader.cso &&
1319 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1320 !info->primitive_restart;
1321
1322 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1323 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1324 sctx->do_update_shaders = true;
1325 }
1326 }
1327
1328 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1329 return;
1330
1331 if (index_size) {
1332 /* Translate or upload, if needed. */
1333 /* 8-bit indices are supported on VI. */
1334 if (sctx->chip_class <= CIK && index_size == 1) {
1335 unsigned start, count, start_offset, size, offset;
1336 void *ptr;
1337
1338 si_get_draw_start_count(sctx, info, &start, &count);
1339 start_offset = start * 2;
1340 size = count * 2;
1341
1342 indexbuf = NULL;
1343 u_upload_alloc(ctx->stream_uploader, start_offset,
1344 size,
1345 si_optimal_tcc_alignment(sctx, size),
1346 &offset, &indexbuf, &ptr);
1347 if (!indexbuf)
1348 return;
1349
1350 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1351 index_offset + start,
1352 count, ptr);
1353
1354 /* info->start will be added by the drawing code */
1355 index_offset = offset - start_offset;
1356 index_size = 2;
1357 } else if (info->has_user_indices) {
1358 unsigned start_offset;
1359
1360 assert(!info->indirect);
1361 start_offset = info->start * index_size;
1362
1363 indexbuf = NULL;
1364 u_upload_data(ctx->stream_uploader, start_offset,
1365 info->count * index_size,
1366 sctx->screen->info.tcc_cache_line_size,
1367 (char*)info->index.user + start_offset,
1368 &index_offset, &indexbuf);
1369 if (!indexbuf)
1370 return;
1371
1372 /* info->start will be added by the drawing code */
1373 index_offset -= start_offset;
1374 } else if (sctx->chip_class <= CIK &&
1375 r600_resource(indexbuf)->TC_L2_dirty) {
1376 /* VI reads index buffers through TC L2, so it doesn't
1377 * need this. */
1378 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1379 r600_resource(indexbuf)->TC_L2_dirty = false;
1380 }
1381 }
1382
1383 if (info->indirect) {
1384 struct pipe_draw_indirect_info *indirect = info->indirect;
1385
1386 /* Add the buffer size for memory checking in need_cs_space. */
1387 si_context_add_resource_size(sctx, indirect->buffer);
1388
1389 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1390 if (sctx->chip_class <= VI) {
1391 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1392 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1393 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1394 }
1395
1396 if (indirect->indirect_draw_count &&
1397 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1398 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1399 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1400 }
1401 }
1402 }
1403
1404 si_need_gfx_cs_space(sctx);
1405
1406 /* Since we've called si_context_add_resource_size for vertex buffers,
1407 * this must be called after si_need_cs_space, because we must let
1408 * need_cs_space flush before we add buffers to the buffer list.
1409 */
1410 if (!si_upload_vertex_buffer_descriptors(sctx))
1411 return;
1412
1413 /* Use optimal packet order based on whether we need to sync the pipeline. */
1414 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1415 SI_CONTEXT_FLUSH_AND_INV_DB |
1416 SI_CONTEXT_PS_PARTIAL_FLUSH |
1417 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1418 /* If we have to wait for idle, set all states first, so that all
1419 * SET packets are processed in parallel with previous draw calls.
1420 * Then draw and prefetch at the end. This ensures that the time
1421 * the CUs are idle is very short.
1422 */
1423 unsigned masked_atoms = 0;
1424
1425 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1426 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1427
1428 if (!si_upload_graphics_shader_descriptors(sctx))
1429 return;
1430
1431 /* Emit all states except possibly render condition. */
1432 si_emit_all_states(sctx, info, masked_atoms);
1433 si_emit_cache_flush(sctx);
1434 /* <-- CUs are idle here. */
1435
1436 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1437 sctx->atoms.s.render_cond.emit(sctx);
1438 sctx->dirty_atoms = 0;
1439
1440 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1441 /* <-- CUs are busy here. */
1442
1443 /* Start prefetches after the draw has been started. Both will run
1444 * in parallel, but starting the draw first is more important.
1445 */
1446 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1447 cik_emit_prefetch_L2(sctx, false);
1448 } else {
1449 /* If we don't wait for idle, start prefetches first, then set
1450 * states, and draw at the end.
1451 */
1452 if (sctx->flags)
1453 si_emit_cache_flush(sctx);
1454
1455 /* Only prefetch the API VS and VBO descriptors. */
1456 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1457 cik_emit_prefetch_L2(sctx, true);
1458
1459 if (!si_upload_graphics_shader_descriptors(sctx))
1460 return;
1461
1462 si_emit_all_states(sctx, info, 0);
1463 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1464
1465 /* Prefetch the remaining shaders after the draw has been
1466 * started. */
1467 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1468 cik_emit_prefetch_L2(sctx, false);
1469 }
1470
1471 if (unlikely(sctx->current_saved_cs)) {
1472 si_trace_emit(sctx);
1473 si_log_draw_state(sctx, sctx->log);
1474 }
1475
1476 /* Workaround for a VGT hang when streamout is enabled.
1477 * It must be done after drawing. */
1478 if ((sctx->family == CHIP_HAWAII ||
1479 sctx->family == CHIP_TONGA ||
1480 sctx->family == CHIP_FIJI) &&
1481 si_get_strmout_en(sctx)) {
1482 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1483 }
1484
1485 if (unlikely(sctx->decompression_enabled)) {
1486 sctx->num_decompress_calls++;
1487 } else {
1488 sctx->num_draw_calls++;
1489 if (sctx->framebuffer.state.nr_cbufs > 1)
1490 sctx->num_mrt_draw_calls++;
1491 if (info->primitive_restart)
1492 sctx->num_prim_restart_calls++;
1493 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1494 sctx->num_spill_draw_calls++;
1495 }
1496 if (index_size && indexbuf != info->index.resource)
1497 pipe_resource_reference(&indexbuf, NULL);
1498 }
1499
1500 void si_draw_rectangle(struct blitter_context *blitter,
1501 void *vertex_elements_cso,
1502 blitter_get_vs_func get_vs,
1503 int x1, int y1, int x2, int y2,
1504 float depth, unsigned num_instances,
1505 enum blitter_attrib_type type,
1506 const union blitter_attrib *attrib)
1507 {
1508 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1509 struct si_context *sctx = (struct si_context*)pipe;
1510
1511 /* Pack position coordinates as signed int16. */
1512 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1513 ((uint32_t)(y1 & 0xffff) << 16);
1514 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1515 ((uint32_t)(y2 & 0xffff) << 16);
1516 sctx->vs_blit_sh_data[2] = fui(depth);
1517
1518 switch (type) {
1519 case UTIL_BLITTER_ATTRIB_COLOR:
1520 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1521 sizeof(float)*4);
1522 break;
1523 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1524 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1525 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1526 sizeof(attrib->texcoord));
1527 break;
1528 case UTIL_BLITTER_ATTRIB_NONE:;
1529 }
1530
1531 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1532
1533 struct pipe_draw_info info = {};
1534 info.mode = SI_PRIM_RECTANGLE_LIST;
1535 info.count = 3;
1536 info.instance_count = num_instances;
1537
1538 /* Don't set per-stage shader pointers for VS. */
1539 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1540 sctx->vertex_buffer_pointer_dirty = false;
1541
1542 si_draw_vbo(pipe, &info);
1543 }
1544
1545 void si_trace_emit(struct si_context *sctx)
1546 {
1547 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1548 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1549 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1550
1551 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1552 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1553 S_370_WR_CONFIRM(1) |
1554 S_370_ENGINE_SEL(V_370_ME));
1555 radeon_emit(cs, va);
1556 radeon_emit(cs, va >> 32);
1557 radeon_emit(cs, trace_id);
1558 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1559 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1560
1561 if (sctx->log)
1562 u_log_flush(sctx->log);
1563 }