2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
39 static unsigned si_conv_pipe_prim(unsigned mode
)
41 static const unsigned prim_conv
[] = {
42 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
43 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
44 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
45 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
46 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
47 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
48 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
49 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
50 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
51 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
52 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
56 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
57 [SI_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
59 assert(mode
< ARRAY_SIZE(prim_conv
));
60 return prim_conv
[mode
];
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
70 static void si_emit_derived_tess_state(struct si_context
*sctx
,
71 const struct pipe_draw_info
*info
,
72 unsigned *num_patches
)
74 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
75 struct si_shader
*ls_current
;
76 struct si_shader_selector
*ls
;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector
*tcs
=
80 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
81 unsigned tess_uses_primid
= sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
;
82 bool has_primid_instancing_bug
= sctx
->chip_class
== GFX6
&&
83 sctx
->screen
->info
.max_se
== 1;
84 unsigned tes_sh_base
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_TESS_EVAL
];
85 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
86 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
87 unsigned num_tcs_patch_outputs
;
88 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
89 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
90 unsigned perpatch_output_offset
, lds_size
;
91 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
92 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx
->chip_class
>= GFX9
) {
96 if (sctx
->tcs_shader
.cso
)
97 ls_current
= sctx
->tcs_shader
.current
;
99 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
101 ls
= ls_current
->key
.part
.tcs
.ls
;
103 ls_current
= sctx
->vs_shader
.current
;
104 ls
= sctx
->vs_shader
.cso
;
107 if (sctx
->last_ls
== ls_current
&&
108 sctx
->last_tcs
== tcs
&&
109 sctx
->last_tes_sh_base
== tes_sh_base
&&
110 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
111 (!has_primid_instancing_bug
||
112 (sctx
->last_tess_uses_primid
== tess_uses_primid
))) {
113 *num_patches
= sctx
->last_num_patches
;
117 sctx
->last_ls
= ls_current
;
118 sctx
->last_tcs
= tcs
;
119 sctx
->last_tes_sh_base
= tes_sh_base
;
120 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
121 sctx
->last_tess_uses_primid
= tess_uses_primid
;
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
127 if (sctx
->tcs_shader
.cso
) {
128 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
129 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
130 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs
= num_tcs_inputs
;
134 num_tcs_output_cp
= num_tcs_input_cp
;
135 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
138 input_vertex_size
= ls
->lshs_vertex_stride
;
139 output_vertex_size
= num_tcs_outputs
* 16;
141 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
143 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
144 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
150 unsigned max_verts_per_patch
= MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
151 *num_patches
= 256 / max_verts_per_patch
;
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
160 hardware_lds_size
= 32768;
161 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches
= MIN2(*num_patches
,
166 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
173 *num_patches
= MIN2(*num_patches
, 63); /* triangles: 3 full waves except 3 lanes */
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
178 if (!sctx
->screen
->has_distributed_tess
&& sctx
->screen
->info
.max_se
> 1)
179 *num_patches
= MIN2(*num_patches
, 16); /* recommended */
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
185 unsigned temp_verts_per_tg
= *num_patches
* max_verts_per_patch
;
186 unsigned wave_size
= sctx
->screen
->ge_wave_size
;
188 if (temp_verts_per_tg
> wave_size
&& temp_verts_per_tg
% wave_size
< wave_size
*3/4)
189 *num_patches
= (temp_verts_per_tg
& ~(wave_size
- 1)) / max_verts_per_patch
;
191 if (sctx
->chip_class
== GFX6
) {
192 /* GFX6 bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
195 unsigned one_wave
= wave_size
/ max_verts_per_patch
;
196 *num_patches
= MIN2(*num_patches
, one_wave
);
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on GFX6 when there is no other
209 if (has_primid_instancing_bug
&& tess_uses_primid
)
212 sctx
->last_num_patches
= *num_patches
;
214 output_patch0_offset
= input_patch_size
* *num_patches
;
215 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
217 /* Compute userdata SGPRs. */
218 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
219 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
220 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
221 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
222 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
223 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
224 assert(num_tcs_input_cp
<= 32);
225 assert(num_tcs_output_cp
<= 32);
227 uint64_t ring_va
= si_resource(sctx
->tess_rings
)->gpu_address
;
228 assert((ring_va
& u_bit_consecutive(0, 19)) == 0);
230 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
231 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
232 tcs_out_layout
= (output_patch_size
/ 4) |
233 (num_tcs_input_cp
<< 13) |
235 tcs_out_offsets
= (output_patch0_offset
/ 16) |
236 ((perpatch_output_offset
/ 16) << 16);
237 offchip_layout
= *num_patches
|
238 (num_tcs_output_cp
<< 6) |
239 (pervertex_output_patch_size
* *num_patches
<< 12);
241 /* Compute the LDS size. */
242 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
244 if (sctx
->chip_class
>= GFX7
) {
245 assert(lds_size
<= 65536);
246 lds_size
= align(lds_size
, 512) / 512;
248 assert(lds_size
<= 32768);
249 lds_size
= align(lds_size
, 256) / 256;
252 /* Set SI_SGPR_VS_STATE_BITS. */
253 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
254 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
255 sctx
->current_vs_state
|= tcs_in_layout
;
257 /* We should be able to support in-shader LDS use with LLVM >= 9
258 * by just adding the lds_sizes together, but it has never
260 assert(ls_current
->config
.lds_size
== 0);
262 if (sctx
->chip_class
>= GFX9
) {
263 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
;
265 if (sctx
->chip_class
>= GFX10
)
266 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(lds_size
);
268 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(lds_size
);
270 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
272 /* Set userdata SGPRs for merged LS-HS. */
273 radeon_set_sh_reg_seq(cs
,
274 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
275 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
276 radeon_emit(cs
, offchip_layout
);
277 radeon_emit(cs
, tcs_out_offsets
);
278 radeon_emit(cs
, tcs_out_layout
);
280 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
282 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
283 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
285 /* Due to a hw bug, RSRC2_LS must be written twice with another
286 * LS register written in between. */
287 if (sctx
->chip_class
== GFX7
&& sctx
->family
!= CHIP_HAWAII
)
288 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
289 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
290 radeon_emit(cs
, ls_current
->config
.rsrc1
);
291 radeon_emit(cs
, ls_rsrc2
);
293 /* Set userdata SGPRs for TCS. */
294 radeon_set_sh_reg_seq(cs
,
295 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
296 radeon_emit(cs
, offchip_layout
);
297 radeon_emit(cs
, tcs_out_offsets
);
298 radeon_emit(cs
, tcs_out_layout
);
299 radeon_emit(cs
, tcs_in_layout
);
302 /* Set userdata SGPRs for TES. */
303 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
304 radeon_emit(cs
, offchip_layout
);
305 radeon_emit(cs
, ring_va
);
307 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
308 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
309 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
311 if (sctx
->last_ls_hs_config
!= ls_hs_config
) {
312 if (sctx
->chip_class
>= GFX7
) {
313 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
316 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
319 sctx
->last_ls_hs_config
= ls_hs_config
;
320 sctx
->context_roll
= true;
324 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
,
325 enum pipe_prim_type prim
)
328 case PIPE_PRIM_PATCHES
:
329 return info
->count
/ info
->vertices_per_patch
;
330 case PIPE_PRIM_POLYGON
:
331 return info
->count
>= 3;
332 case SI_PRIM_RECTANGLE_LIST
:
333 return info
->count
/ 3;
335 return u_decomposed_prims_for_vertices(prim
, info
->count
);
340 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
341 union si_vgt_param_key
*key
)
343 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
344 unsigned max_primgroup_in_wave
= 2;
346 /* SWITCH_ON_EOP(0) is always preferable. */
347 bool wd_switch_on_eop
= false;
348 bool ia_switch_on_eop
= false;
349 bool ia_switch_on_eoi
= false;
350 bool partial_vs_wave
= false;
351 bool partial_es_wave
= false;
353 if (key
->u
.uses_tess
) {
354 /* SWITCH_ON_EOI must be set if PrimID is used. */
355 if (key
->u
.tess_uses_prim_id
)
356 ia_switch_on_eoi
= true;
358 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
359 if ((sscreen
->info
.family
== CHIP_TAHITI
||
360 sscreen
->info
.family
== CHIP_PITCAIRN
||
361 sscreen
->info
.family
== CHIP_BONAIRE
) &&
363 partial_vs_wave
= true;
365 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
366 if (sscreen
->has_distributed_tess
) {
367 if (key
->u
.uses_gs
) {
368 if (sscreen
->info
.chip_class
== GFX8
)
369 partial_es_wave
= true;
371 partial_vs_wave
= true;
376 /* This is a hardware requirement. */
377 if (key
->u
.line_stipple_enabled
||
378 (sscreen
->debug_flags
& DBG(SWITCH_ON_EOP
))) {
379 ia_switch_on_eop
= true;
380 wd_switch_on_eop
= true;
383 if (sscreen
->info
.chip_class
>= GFX7
) {
384 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
385 * 4 shader engines. Set 1 to pass the assertion below.
386 * The other cases are hardware requirements.
388 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
389 * for points, line strips, and tri strips.
391 if (sscreen
->info
.max_se
<= 2 ||
392 key
->u
.prim
== PIPE_PRIM_POLYGON
||
393 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
394 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
395 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
396 (key
->u
.primitive_restart
&&
397 (sscreen
->info
.family
< CHIP_POLARIS10
||
398 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
399 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
400 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
401 key
->u
.count_from_stream_output
)
402 wd_switch_on_eop
= true;
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sscreen
->info
.family
== CHIP_HAWAII
&&
408 key
->u
.uses_instancing
)
409 wd_switch_on_eop
= true;
411 /* Performance recommendation for 4 SE Gfx7-8 parts if
412 * instances are smaller than a primgroup.
413 * Assume indirect draws always use small instances.
414 * This is needed for good VS wave utilization.
416 if (sscreen
->info
.chip_class
<= GFX8
&&
417 sscreen
->info
.max_se
== 4 &&
418 key
->u
.multi_instances_smaller_than_primgroup
)
419 wd_switch_on_eop
= true;
421 /* Required on GFX7 and later. */
422 if (sscreen
->info
.max_se
== 4 && !wd_switch_on_eop
)
423 ia_switch_on_eoi
= true;
425 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
426 * to work around a GS hang.
428 if (key
->u
.uses_gs
&&
429 (sscreen
->info
.family
== CHIP_TONGA
||
430 sscreen
->info
.family
== CHIP_FIJI
||
431 sscreen
->info
.family
== CHIP_POLARIS10
||
432 sscreen
->info
.family
== CHIP_POLARIS11
||
433 sscreen
->info
.family
== CHIP_POLARIS12
||
434 sscreen
->info
.family
== CHIP_VEGAM
))
435 partial_vs_wave
= true;
437 /* Required by Hawaii and, for some special cases, by GFX8. */
438 if (ia_switch_on_eoi
&&
439 (sscreen
->info
.family
== CHIP_HAWAII
||
440 (sscreen
->info
.chip_class
== GFX8
&&
441 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
442 partial_vs_wave
= true;
444 /* Instancing bug on Bonaire. */
445 if (sscreen
->info
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
446 key
->u
.uses_instancing
)
447 partial_vs_wave
= true;
449 /* This only applies to Polaris10 and later 4 SE chips.
450 * wd_switch_on_eop is already true on all other chips.
452 if (!wd_switch_on_eop
&& key
->u
.primitive_restart
)
453 partial_vs_wave
= true;
455 /* If the WD switch is false, the IA switch must be false too. */
456 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
459 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
460 if (sscreen
->info
.chip_class
<= GFX8
&& ia_switch_on_eoi
)
461 partial_es_wave
= true;
463 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
464 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
465 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
466 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
467 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->info
.chip_class
>= GFX7
? wd_switch_on_eop
: 0) |
468 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
469 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->info
.chip_class
== GFX8
?
470 max_primgroup_in_wave
: 0) |
471 S_030960_EN_INST_OPT_BASIC(sscreen
->info
.chip_class
>= GFX9
) |
472 S_030960_EN_INST_OPT_ADV(sscreen
->info
.chip_class
>= GFX9
);
475 static void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
477 for (int prim
= 0; prim
<= SI_PRIM_RECTANGLE_LIST
; prim
++)
478 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
479 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
480 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
481 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
482 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
483 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
484 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
485 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
486 union si_vgt_param_key key
;
490 key
.u
.uses_instancing
= uses_instancing
;
491 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
492 key
.u
.primitive_restart
= primitive_restart
;
493 key
.u
.count_from_stream_output
= count_from_so
;
494 key
.u
.line_stipple_enabled
= line_stipple
;
495 key
.u
.uses_tess
= uses_tess
;
496 key
.u
.tess_uses_prim_id
= tess_uses_primid
;
497 key
.u
.uses_gs
= uses_gs
;
499 sctx
->ia_multi_vgt_param
[key
.index
] =
500 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
504 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
505 const struct pipe_draw_info
*info
,
506 enum pipe_prim_type prim
,
507 unsigned num_patches
,
508 unsigned instance_count
,
509 bool primitive_restart
)
511 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
512 unsigned primgroup_size
;
513 unsigned ia_multi_vgt_param
;
515 if (sctx
->tes_shader
.cso
) {
516 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
517 } else if (sctx
->gs_shader
.cso
) {
518 primgroup_size
= 64; /* recommended with a GS */
520 primgroup_size
= 128; /* recommended without a GS and tess */
524 key
.u
.uses_instancing
= info
->indirect
|| instance_count
> 1;
525 key
.u
.multi_instances_smaller_than_primgroup
=
527 (instance_count
> 1 &&
528 (info
->count_from_stream_output
||
529 si_num_prims_for_vertices(info
, prim
) < primgroup_size
));
530 key
.u
.primitive_restart
= primitive_restart
;
531 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
533 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
534 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
536 if (sctx
->gs_shader
.cso
) {
537 /* GS requirement. */
538 if (sctx
->chip_class
<= GFX8
&&
539 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
540 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
542 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
543 * The hw doc says all multi-SE chips are affected, but Vulkan
544 * only applies it to Hawaii. Do what Vulkan does.
546 if (sctx
->family
== CHIP_HAWAII
&&
547 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
549 (instance_count
> 1 &&
550 (info
->count_from_stream_output
||
551 si_num_prims_for_vertices(info
, prim
) <= 1))))
552 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
555 return ia_multi_vgt_param
;
558 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
560 static const int prim_conv
[] = {
561 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
562 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
563 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
564 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
565 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
566 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
567 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
568 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
569 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
570 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
571 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
572 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
573 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
574 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
575 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
576 [SI_PRIM_RECTANGLE_LIST
] = V_028A6C_VGT_OUT_RECT_V0
,
578 assert(mode
< ARRAY_SIZE(prim_conv
));
580 return prim_conv
[mode
];
583 /* rast_prim is the primitive type after GS. */
584 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
586 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
587 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
588 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
590 if (likely(rast_prim
== sctx
->last_rast_prim
&&
591 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
&&
592 (sctx
->chip_class
<= GFX9
||
593 rs
->flatshade_first
== sctx
->last_flatshade_first
)))
596 if (util_prim_is_lines(rast_prim
)) {
597 /* For lines, reset the stipple pattern at each primitive. Otherwise,
598 * reset the stipple pattern at each packet (line strips, line loops).
600 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
601 rs
->pa_sc_line_stipple
|
602 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
603 sctx
->context_roll
= true;
606 unsigned gs_out
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
608 if (rast_prim
!= sctx
->last_rast_prim
&&
609 (sctx
->ngg
|| sctx
->gs_shader
.cso
)) {
610 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
611 sctx
->context_roll
= true;
613 if (sctx
->chip_class
>= GFX10
) {
614 sctx
->current_vs_state
&= C_VS_STATE_OUTPRIM
;
615 sctx
->current_vs_state
|= S_VS_STATE_OUTPRIM(gs_out
);
619 if (sctx
->chip_class
>= GFX10
) {
620 unsigned vtx_index
= rs
->flatshade_first
? 0 : gs_out
;
621 sctx
->current_vs_state
&= C_VS_STATE_PROVOKING_VTX_INDEX
;
622 sctx
->current_vs_state
|= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index
);
625 sctx
->last_rast_prim
= rast_prim
;
626 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
627 sctx
->last_flatshade_first
= rs
->flatshade_first
;
630 static void si_emit_vs_state(struct si_context
*sctx
,
631 const struct pipe_draw_info
*info
)
633 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
634 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->index_size
);
636 if (sctx
->num_vs_blit_sgprs
) {
637 /* Re-emit the state after we leave u_blitter. */
638 sctx
->last_vs_state
= ~0;
642 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
643 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
645 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
646 radeon_set_sh_reg(cs
,
647 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] +
648 SI_SGPR_VS_STATE_BITS
* 4,
649 sctx
->current_vs_state
);
651 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
652 * before the rasterizer.
654 * For TES or the GS copy shader without NGG:
656 if (sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] !=
657 R_00B130_SPI_SHADER_USER_DATA_VS_0
) {
658 radeon_set_sh_reg(cs
,
659 R_00B130_SPI_SHADER_USER_DATA_VS_0
+
660 SI_SGPR_VS_STATE_BITS
* 4,
661 sctx
->current_vs_state
);
665 if (sctx
->chip_class
>= GFX10
&&
666 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] !=
667 R_00B230_SPI_SHADER_USER_DATA_GS_0
) {
668 radeon_set_sh_reg(cs
,
669 R_00B230_SPI_SHADER_USER_DATA_GS_0
+
670 SI_SGPR_VS_STATE_BITS
* 4,
671 sctx
->current_vs_state
);
674 sctx
->last_vs_state
= sctx
->current_vs_state
;
678 static inline bool si_prim_restart_index_changed(struct si_context
*sctx
,
679 bool primitive_restart
,
680 unsigned restart_index
)
682 return primitive_restart
&&
683 (restart_index
!= sctx
->last_restart_index
||
684 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
);
687 static void si_emit_ia_multi_vgt_param(struct si_context
*sctx
,
688 const struct pipe_draw_info
*info
,
689 enum pipe_prim_type prim
,
690 unsigned num_patches
,
691 unsigned instance_count
,
692 bool primitive_restart
)
694 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
695 unsigned ia_multi_vgt_param
;
697 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, prim
, num_patches
,
698 instance_count
, primitive_restart
);
701 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
702 if (sctx
->chip_class
== GFX9
)
703 radeon_set_uconfig_reg_idx(cs
, sctx
->screen
,
704 R_030960_IA_MULTI_VGT_PARAM
, 4,
706 else if (sctx
->chip_class
>= GFX7
)
707 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
709 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
711 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
715 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
716 * We overload last_multi_vgt_param.
718 static void gfx10_emit_ge_cntl(struct si_context
*sctx
, unsigned num_patches
)
723 ge_cntl
= si_get_vs_state(sctx
)->ge_cntl
|
724 S_03096C_PACKET_TO_ONE_PA(sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
);
726 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
727 unsigned primgroup_size
;
728 unsigned vertgroup_size
;
730 if (sctx
->tes_shader
.cso
) {
731 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
733 } else if (sctx
->gs_shader
.cso
) {
734 unsigned vgt_gs_onchip_cntl
= sctx
->gs_shader
.current
->ctx_reg
.gs
.vgt_gs_onchip_cntl
;
735 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
736 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
738 primgroup_size
= 128; /* recommended without a GS and tess */
742 ge_cntl
= S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
743 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
744 S_03096C_BREAK_WAVE_AT_EOI(key
.u
.uses_tess
&& key
.u
.tess_uses_prim_id
) |
745 S_03096C_PACKET_TO_ONE_PA(key
.u
.line_stipple_enabled
);
748 if (ge_cntl
!= sctx
->last_multi_vgt_param
) {
749 radeon_set_uconfig_reg(sctx
->gfx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
750 sctx
->last_multi_vgt_param
= ge_cntl
;
754 static void si_emit_draw_registers(struct si_context
*sctx
,
755 const struct pipe_draw_info
*info
,
756 enum pipe_prim_type prim
,
757 unsigned num_patches
,
758 unsigned instance_count
,
759 bool primitive_restart
)
761 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
762 unsigned vgt_prim
= si_conv_pipe_prim(info
->mode
);
764 if (sctx
->chip_class
>= GFX10
)
765 gfx10_emit_ge_cntl(sctx
, num_patches
);
767 si_emit_ia_multi_vgt_param(sctx
, info
, prim
, num_patches
,
768 instance_count
, primitive_restart
);
770 if (vgt_prim
!= sctx
->last_prim
) {
771 if (sctx
->chip_class
>= GFX7
)
772 radeon_set_uconfig_reg_idx(cs
, sctx
->screen
,
773 R_030908_VGT_PRIMITIVE_TYPE
, 1, vgt_prim
);
775 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, vgt_prim
);
777 sctx
->last_prim
= vgt_prim
;
780 /* Primitive restart. */
781 if (primitive_restart
!= sctx
->last_primitive_restart_en
) {
782 if (sctx
->chip_class
>= GFX9
)
783 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
786 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
789 sctx
->last_primitive_restart_en
= primitive_restart
;
792 if (si_prim_restart_index_changed(sctx
, primitive_restart
, info
->restart_index
)) {
793 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
794 info
->restart_index
);
795 sctx
->last_restart_index
= info
->restart_index
;
796 sctx
->context_roll
= true;
800 static void si_emit_draw_packets(struct si_context
*sctx
,
801 const struct pipe_draw_info
*info
,
802 struct pipe_resource
*indexbuf
,
804 unsigned index_offset
,
805 unsigned instance_count
,
806 bool dispatch_prim_discard_cs
,
807 unsigned original_index_size
)
809 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
810 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
811 unsigned sh_base_reg
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
];
812 bool render_cond_bit
= sctx
->render_cond
&& !sctx
->render_cond_force_off
;
813 uint32_t index_max_size
= 0;
814 uint64_t index_va
= 0;
816 if (info
->count_from_stream_output
) {
817 struct si_streamout_target
*t
=
818 (struct si_streamout_target
*)info
->count_from_stream_output
;
820 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
822 si_cp_copy_data(sctx
, sctx
->gfx_cs
,
824 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2,
825 COPY_DATA_SRC_MEM
, t
->buf_filled_size
,
826 t
->buf_filled_size_offset
);
831 if (index_size
!= sctx
->last_index_size
) {
835 switch (index_size
) {
837 index_type
= V_028A7C_VGT_INDEX_8
;
840 index_type
= V_028A7C_VGT_INDEX_16
|
841 (SI_BIG_ENDIAN
&& sctx
->chip_class
<= GFX7
?
842 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
845 index_type
= V_028A7C_VGT_INDEX_32
|
846 (SI_BIG_ENDIAN
&& sctx
->chip_class
<= GFX7
?
847 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
850 assert(!"unreachable");
854 if (sctx
->chip_class
>= GFX9
) {
855 radeon_set_uconfig_reg_idx(cs
, sctx
->screen
,
856 R_03090C_VGT_INDEX_TYPE
, 2,
859 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
860 radeon_emit(cs
, index_type
);
863 sctx
->last_index_size
= index_size
;
866 if (original_index_size
) {
867 index_max_size
= (indexbuf
->width0
- index_offset
) /
869 index_va
= si_resource(indexbuf
)->gpu_address
+ index_offset
;
871 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
872 si_resource(indexbuf
),
873 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
876 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
877 * so the state must be re-emitted before the next indexed draw.
879 if (sctx
->chip_class
>= GFX7
)
880 sctx
->last_index_size
= -1;
884 uint64_t indirect_va
= si_resource(indirect
->buffer
)->gpu_address
;
886 assert(indirect_va
% 8 == 0);
888 si_invalidate_draw_sh_constants(sctx
);
890 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
892 radeon_emit(cs
, indirect_va
);
893 radeon_emit(cs
, indirect_va
>> 32);
895 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
896 si_resource(indirect
->buffer
),
897 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
899 unsigned di_src_sel
= index_size
? V_0287F0_DI_SRC_SEL_DMA
900 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
902 assert(indirect
->offset
% 4 == 0);
905 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
906 radeon_emit(cs
, index_va
);
907 radeon_emit(cs
, index_va
>> 32);
909 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
910 radeon_emit(cs
, index_max_size
);
913 if (!sctx
->screen
->has_draw_indirect_multi
) {
914 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT
915 : PKT3_DRAW_INDIRECT
,
916 3, render_cond_bit
));
917 radeon_emit(cs
, indirect
->offset
);
918 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
919 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
920 radeon_emit(cs
, di_src_sel
);
922 uint64_t count_va
= 0;
924 if (indirect
->indirect_draw_count
) {
925 struct si_resource
*params_buf
=
926 si_resource(indirect
->indirect_draw_count
);
928 radeon_add_to_buffer_list(
929 sctx
, sctx
->gfx_cs
, params_buf
,
930 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
932 count_va
= params_buf
->gpu_address
+ indirect
->indirect_draw_count_offset
;
935 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
936 PKT3_DRAW_INDIRECT_MULTI
,
937 8, render_cond_bit
));
938 radeon_emit(cs
, indirect
->offset
);
939 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
940 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
941 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
942 S_2C3_DRAW_INDEX_ENABLE(1) |
943 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect
->indirect_draw_count
));
944 radeon_emit(cs
, indirect
->draw_count
);
945 radeon_emit(cs
, count_va
);
946 radeon_emit(cs
, count_va
>> 32);
947 radeon_emit(cs
, indirect
->stride
);
948 radeon_emit(cs
, di_src_sel
);
953 if (sctx
->last_instance_count
== SI_INSTANCE_COUNT_UNKNOWN
||
954 sctx
->last_instance_count
!= instance_count
) {
955 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
956 radeon_emit(cs
, instance_count
);
957 sctx
->last_instance_count
= instance_count
;
960 /* Base vertex and start instance. */
961 base_vertex
= original_index_size
? info
->index_bias
: info
->start
;
963 if (sctx
->num_vs_blit_sgprs
) {
964 /* Re-emit draw constants after we leave u_blitter. */
965 si_invalidate_draw_sh_constants(sctx
);
967 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
968 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_VS_BLIT_DATA
* 4,
969 sctx
->num_vs_blit_sgprs
);
970 radeon_emit_array(cs
, sctx
->vs_blit_sh_data
,
971 sctx
->num_vs_blit_sgprs
);
972 } else if (base_vertex
!= sctx
->last_base_vertex
||
973 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
974 info
->start_instance
!= sctx
->last_start_instance
||
975 info
->drawid
!= sctx
->last_drawid
||
976 sh_base_reg
!= sctx
->last_sh_base_reg
) {
977 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
978 radeon_emit(cs
, base_vertex
);
979 radeon_emit(cs
, info
->start_instance
);
980 radeon_emit(cs
, info
->drawid
);
982 sctx
->last_base_vertex
= base_vertex
;
983 sctx
->last_start_instance
= info
->start_instance
;
984 sctx
->last_drawid
= info
->drawid
;
985 sctx
->last_sh_base_reg
= sh_base_reg
;
989 if (dispatch_prim_discard_cs
) {
990 index_va
+= info
->start
* original_index_size
;
991 index_max_size
= MIN2(index_max_size
, info
->count
);
993 si_dispatch_prim_discard_cs_and_draw(sctx
, info
,
996 index_va
, index_max_size
);
1000 index_va
+= info
->start
* index_size
;
1002 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
1003 radeon_emit(cs
, index_max_size
);
1004 radeon_emit(cs
, index_va
);
1005 radeon_emit(cs
, index_va
>> 32);
1006 radeon_emit(cs
, info
->count
);
1007 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1009 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
1010 radeon_emit(cs
, info
->count
);
1011 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1012 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
1017 void si_emit_surface_sync(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1018 unsigned cp_coher_cntl
)
1020 bool compute_ib
= !sctx
->has_graphics
||
1021 cs
== sctx
->prim_discard_compute_cs
;
1023 assert(sctx
->chip_class
<= GFX9
);
1025 if (sctx
->chip_class
== GFX9
|| compute_ib
) {
1026 /* Flush caches and wait for the caches to assert idle. */
1027 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
1028 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
1029 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1030 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1031 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1032 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1033 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1035 /* ACQUIRE_MEM is only required on a compute ring. */
1036 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
1037 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
1038 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1039 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1040 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1043 /* ACQUIRE_MEM has an implicit context roll if the current context
1046 sctx
->context_roll
= true;
1049 void si_prim_discard_signal_next_compute_ib_start(struct si_context
*sctx
)
1051 if (!si_compute_prim_discard_enabled(sctx
))
1054 if (!sctx
->barrier_buf
) {
1055 u_suballocator_alloc(sctx
->allocator_zeroed_memory
, 4, 4,
1056 &sctx
->barrier_buf_offset
,
1057 (struct pipe_resource
**)&sctx
->barrier_buf
);
1060 /* Emit a placeholder to signal the next compute IB to start.
1061 * See si_compute_prim_discard.c for explanation.
1063 uint32_t signal
= 1;
1064 si_cp_write_data(sctx
, sctx
->barrier_buf
, sctx
->barrier_buf_offset
,
1065 4, V_370_MEM
, V_370_ME
, &signal
);
1067 sctx
->last_pkt3_write_data
=
1068 &sctx
->gfx_cs
->current
.buf
[sctx
->gfx_cs
->current
.cdw
- 5];
1070 /* Only the last occurence of WRITE_DATA will be executed.
1071 * The packet will be enabled in si_flush_gfx_cs.
1073 *sctx
->last_pkt3_write_data
= PKT3(PKT3_NOP
, 3, 0);
1076 void gfx10_emit_cache_flush(struct si_context
*ctx
)
1078 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
1079 uint32_t gcr_cntl
= 0;
1080 unsigned cb_db_event
= 0;
1081 unsigned flags
= ctx
->flags
;
1083 if (!ctx
->has_graphics
) {
1084 /* Only process compute flags. */
1085 flags
&= SI_CONTEXT_INV_ICACHE
|
1086 SI_CONTEXT_INV_SCACHE
|
1087 SI_CONTEXT_INV_VCACHE
|
1090 SI_CONTEXT_INV_L2_METADATA
|
1091 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1094 /* We don't need these. */
1095 assert(!(flags
& (SI_CONTEXT_VGT_FLUSH
|
1096 SI_CONTEXT_VGT_STREAMOUT_SYNC
|
1097 SI_CONTEXT_FLUSH_AND_INV_DB_META
)));
1099 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
1100 ctx
->num_cb_cache_flushes
++;
1101 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
1102 ctx
->num_db_cache_flushes
++;
1104 if (flags
& SI_CONTEXT_INV_ICACHE
)
1105 gcr_cntl
|= S_586_GLI_INV(V_586_GLI_ALL
);
1106 if (flags
& SI_CONTEXT_INV_SCACHE
) {
1107 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1108 * to FORWARD when both L1 and L2 are written out (WB or INV).
1110 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1112 if (flags
& SI_CONTEXT_INV_VCACHE
)
1113 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1114 if (flags
& SI_CONTEXT_INV_L2
) {
1115 /* Writeback and invalidate everything in L2. */
1116 gcr_cntl
|= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1117 ctx
->num_L2_invalidates
++;
1118 } else if (flags
& SI_CONTEXT_WB_L2
) {
1119 /* Writeback but do not invalidate. */
1120 gcr_cntl
|= S_586_GL2_WB(1);
1122 if (flags
& SI_CONTEXT_INV_L2_METADATA
)
1123 gcr_cntl
|= S_586_GLM_INV(1);
1125 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_FLUSH_AND_INV_DB
)) {
1126 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1127 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1128 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1129 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) |
1132 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
1133 /* Flush HTILE. Will wait for idle later. */
1134 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1135 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) |
1139 /* First flush CB/DB, then L1/L2. */
1140 gcr_cntl
|= S_586_SEQ(V_586_SEQ_FORWARD
);
1142 if ((flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_FLUSH_AND_INV_DB
)) ==
1143 (SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_FLUSH_AND_INV_DB
)) {
1144 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1145 } else if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1146 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
1147 } else if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
1148 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
1153 /* Wait for graphics shaders to go idle if requested. */
1154 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
1155 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1156 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1157 /* Only count explicit shader flushes, not implicit ones. */
1158 ctx
->num_vs_flushes
++;
1159 ctx
->num_ps_flushes
++;
1160 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
1161 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1162 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1163 ctx
->num_vs_flushes
++;
1167 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&& ctx
->compute_is_busy
) {
1168 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1169 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
1170 ctx
->num_cs_flushes
++;
1171 ctx
->compute_is_busy
= false;
1175 /* CB/DB flush and invalidate (or possibly just a wait for a
1176 * meta flush) via RELEASE_MEM.
1178 * Combine this with other cache flushes when possible; this
1179 * requires affected shaders to be idle, so do it after the
1180 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1185 /* Do the flush (enqueue the event and wait for it). */
1186 va
= ctx
->wait_mem_scratch
->gpu_address
;
1187 ctx
->wait_mem_number
++;
1189 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1190 unsigned glm_wb
= G_586_GLM_WB(gcr_cntl
);
1191 unsigned glm_inv
= G_586_GLM_INV(gcr_cntl
);
1192 unsigned glv_inv
= G_586_GLV_INV(gcr_cntl
);
1193 unsigned gl1_inv
= G_586_GL1_INV(gcr_cntl
);
1194 assert(G_586_GL2_US(gcr_cntl
) == 0);
1195 assert(G_586_GL2_RANGE(gcr_cntl
) == 0);
1196 assert(G_586_GL2_DISCARD(gcr_cntl
) == 0);
1197 unsigned gl2_inv
= G_586_GL2_INV(gcr_cntl
);
1198 unsigned gl2_wb
= G_586_GL2_WB(gcr_cntl
);
1199 unsigned gcr_seq
= G_586_SEQ(gcr_cntl
);
1201 gcr_cntl
&= C_586_GLM_WB
&
1206 C_586_GL2_WB
; /* keep SEQ */
1208 si_cp_release_mem(ctx
, cs
, cb_db_event
,
1209 S_490_GLM_WB(glm_wb
) |
1210 S_490_GLM_INV(glm_inv
) |
1211 S_490_GLV_INV(glv_inv
) |
1212 S_490_GL1_INV(gl1_inv
) |
1213 S_490_GL2_INV(gl2_inv
) |
1214 S_490_GL2_WB(gl2_wb
) |
1217 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
,
1218 EOP_DATA_SEL_VALUE_32BIT
,
1219 ctx
->wait_mem_scratch
, va
,
1220 ctx
->wait_mem_number
, SI_NOT_QUERY
);
1221 si_cp_wait_mem(ctx
, ctx
->gfx_cs
, va
, ctx
->wait_mem_number
, 0xffffffff,
1222 WAIT_REG_MEM_EQUAL
);
1225 /* Ignore fields that only modify the behavior of other fields. */
1226 if (gcr_cntl
& C_586_GL1_RANGE
& C_586_GL2_RANGE
& C_586_SEQ
) {
1227 /* Flush caches and wait for the caches to assert idle.
1228 * The cache flush is executed in the ME, but the PFP waits
1231 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 6, 0));
1232 radeon_emit(cs
, 0); /* CP_COHER_CNTL */
1233 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1234 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1235 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1236 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1237 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1238 radeon_emit(cs
, gcr_cntl
); /* GCR_CNTL */
1239 } else if (cb_db_event
||
1240 (flags
& (SI_CONTEXT_VS_PARTIAL_FLUSH
|
1241 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1242 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
1243 /* We need to ensure that PFP waits as well. */
1244 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1248 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1249 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1250 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1252 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1253 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1254 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1261 void si_emit_cache_flush(struct si_context
*sctx
)
1263 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1264 uint32_t flags
= sctx
->flags
;
1266 if (!sctx
->has_graphics
) {
1267 /* Only process compute flags. */
1268 flags
&= SI_CONTEXT_INV_ICACHE
|
1269 SI_CONTEXT_INV_SCACHE
|
1270 SI_CONTEXT_INV_VCACHE
|
1273 SI_CONTEXT_INV_L2_METADATA
|
1274 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1277 uint32_t cp_coher_cntl
= 0;
1278 const uint32_t flush_cb_db
= flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
1279 SI_CONTEXT_FLUSH_AND_INV_DB
);
1280 const bool is_barrier
= flush_cb_db
||
1281 /* INV_ICACHE == beginning of gfx IB. Checking
1282 * INV_ICACHE fixes corruption for DeusExMD with
1283 * compute-based culling, but I don't know why.
1285 flags
& (SI_CONTEXT_INV_ICACHE
|
1286 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1287 SI_CONTEXT_VS_PARTIAL_FLUSH
) ||
1288 (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
1289 sctx
->compute_is_busy
);
1291 assert(sctx
->chip_class
<= GFX9
);
1293 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
1294 sctx
->num_cb_cache_flushes
++;
1295 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
1296 sctx
->num_db_cache_flushes
++;
1298 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1299 * bit is set. An alternative way is to write SQC_CACHES, but that
1300 * doesn't seem to work reliably. Since the bug doesn't affect
1301 * correctness (it only does more work than necessary) and
1302 * the performance impact is likely negligible, there is no plan
1303 * to add a workaround for it.
1306 if (flags
& SI_CONTEXT_INV_ICACHE
)
1307 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1308 if (flags
& SI_CONTEXT_INV_SCACHE
)
1309 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1311 if (sctx
->chip_class
<= GFX8
) {
1312 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1313 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
1314 S_0085F0_CB0_DEST_BASE_ENA(1) |
1315 S_0085F0_CB1_DEST_BASE_ENA(1) |
1316 S_0085F0_CB2_DEST_BASE_ENA(1) |
1317 S_0085F0_CB3_DEST_BASE_ENA(1) |
1318 S_0085F0_CB4_DEST_BASE_ENA(1) |
1319 S_0085F0_CB5_DEST_BASE_ENA(1) |
1320 S_0085F0_CB6_DEST_BASE_ENA(1) |
1321 S_0085F0_CB7_DEST_BASE_ENA(1);
1323 /* Necessary for DCC */
1324 if (sctx
->chip_class
== GFX8
)
1325 si_cp_release_mem(sctx
, cs
,
1326 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
1327 0, EOP_DST_SEL_MEM
, EOP_INT_SEL_NONE
,
1328 EOP_DATA_SEL_DISCARD
, NULL
,
1329 0, 0, SI_NOT_QUERY
);
1331 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
1332 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
1333 S_0085F0_DB_DEST_BASE_ENA(1);
1336 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
1337 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1338 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1339 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
1341 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_DB
|
1342 SI_CONTEXT_FLUSH_AND_INV_DB_META
)) {
1343 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1344 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1345 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
1348 /* Wait for shader engines to go idle.
1349 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1350 * for everything including CB/DB cache flushes.
1353 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
1354 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1355 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1356 /* Only count explicit shader flushes, not implicit ones
1357 * done by SURFACE_SYNC.
1359 sctx
->num_vs_flushes
++;
1360 sctx
->num_ps_flushes
++;
1361 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
1362 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1363 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1364 sctx
->num_vs_flushes
++;
1368 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
1369 sctx
->compute_is_busy
) {
1370 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1371 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1372 sctx
->num_cs_flushes
++;
1373 sctx
->compute_is_busy
= false;
1376 /* VGT state synchronization. */
1377 if (flags
& SI_CONTEXT_VGT_FLUSH
) {
1378 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1379 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1381 if (flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
1382 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1383 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
1386 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1387 * wait for idle on GFX9. We have to use a TS event.
1389 if (sctx
->chip_class
== GFX9
&& flush_cb_db
) {
1391 unsigned tc_flags
, cb_db_event
;
1393 /* Set the CB/DB flush event. */
1394 switch (flush_cb_db
) {
1395 case SI_CONTEXT_FLUSH_AND_INV_CB
:
1396 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
1398 case SI_CONTEXT_FLUSH_AND_INV_DB
:
1399 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
1403 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1406 /* These are the only allowed combinations. If you need to
1407 * do multiple operations at once, do them separately.
1408 * All operations that invalidate L2 also seem to invalidate
1409 * metadata. Volatile (VOL) and WC flushes are not listed here.
1411 * TC | TC_WB = writeback & invalidate L2 & L1
1412 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1413 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1414 * TC | TC_NC = invalidate L2 for MTYPE == NC
1415 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1416 * TCL1 = invalidate L1
1420 if (flags
& SI_CONTEXT_INV_L2_METADATA
) {
1421 tc_flags
= EVENT_TC_ACTION_ENA
|
1422 EVENT_TC_MD_ACTION_ENA
;
1425 /* Ideally flush TC together with CB/DB. */
1426 if (flags
& SI_CONTEXT_INV_L2
) {
1427 /* Writeback and invalidate everything in L2 & L1. */
1428 tc_flags
= EVENT_TC_ACTION_ENA
|
1429 EVENT_TC_WB_ACTION_ENA
;
1431 /* Clear the flags. */
1432 flags
&= ~(SI_CONTEXT_INV_L2
|
1434 SI_CONTEXT_INV_VCACHE
);
1435 sctx
->num_L2_invalidates
++;
1438 /* Do the flush (enqueue the event and wait for it). */
1439 va
= sctx
->wait_mem_scratch
->gpu_address
;
1440 sctx
->wait_mem_number
++;
1442 si_cp_release_mem(sctx
, cs
, cb_db_event
, tc_flags
,
1444 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
,
1445 EOP_DATA_SEL_VALUE_32BIT
,
1446 sctx
->wait_mem_scratch
, va
,
1447 sctx
->wait_mem_number
, SI_NOT_QUERY
);
1448 si_cp_wait_mem(sctx
, cs
, va
, sctx
->wait_mem_number
, 0xffffffff,
1449 WAIT_REG_MEM_EQUAL
);
1452 /* Make sure ME is idle (it executes most packets) before continuing.
1453 * This prevents read-after-write hazards between PFP and ME.
1455 if (sctx
->has_graphics
&&
1457 (flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
1458 SI_CONTEXT_INV_VCACHE
|
1460 SI_CONTEXT_WB_L2
)))) {
1461 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1466 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1467 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1469 * cp_coher_cntl should contain all necessary flags except TC flags
1472 * GFX6-GFX7 don't support L2 write-back.
1474 if (flags
& SI_CONTEXT_INV_L2
||
1475 (sctx
->chip_class
<= GFX7
&&
1476 (flags
& SI_CONTEXT_WB_L2
))) {
1477 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1478 * WB must be set on GFX8+ when TC_ACTION is set.
1480 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
|
1481 S_0085F0_TC_ACTION_ENA(1) |
1482 S_0085F0_TCL1_ACTION_ENA(1) |
1483 S_0301F0_TC_WB_ACTION_ENA(sctx
->chip_class
>= GFX8
));
1485 sctx
->num_L2_invalidates
++;
1487 /* L1 invalidation and L2 writeback must be done separately,
1488 * because both operations can't be done together.
1490 if (flags
& SI_CONTEXT_WB_L2
) {
1492 * NC = apply to non-coherent MTYPEs
1493 * (i.e. MTYPE <= 1, which is what we use everywhere)
1495 * WB doesn't work without NC.
1497 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
|
1498 S_0301F0_TC_WB_ACTION_ENA(1) |
1499 S_0301F0_TC_NC_ACTION_ENA(1));
1501 sctx
->num_L2_writebacks
++;
1503 if (flags
& SI_CONTEXT_INV_VCACHE
) {
1504 /* Invalidate per-CU VMEM L1. */
1505 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
|
1506 S_0085F0_TCL1_ACTION_ENA(1));
1511 /* If TC flushes haven't cleared this... */
1513 si_emit_surface_sync(sctx
, sctx
->gfx_cs
, cp_coher_cntl
);
1516 si_prim_discard_signal_next_compute_ib_start(sctx
);
1518 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1519 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1520 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1522 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1523 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1524 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1531 static void si_get_draw_start_count(struct si_context
*sctx
,
1532 const struct pipe_draw_info
*info
,
1533 unsigned *start
, unsigned *count
)
1535 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1538 unsigned indirect_count
;
1539 struct pipe_transfer
*transfer
;
1540 unsigned begin
, end
;
1544 if (indirect
->indirect_draw_count
) {
1545 data
= pipe_buffer_map_range(&sctx
->b
,
1546 indirect
->indirect_draw_count
,
1547 indirect
->indirect_draw_count_offset
,
1549 PIPE_TRANSFER_READ
, &transfer
);
1551 indirect_count
= *data
;
1553 pipe_buffer_unmap(&sctx
->b
, transfer
);
1555 indirect_count
= indirect
->draw_count
;
1558 if (!indirect_count
) {
1559 *start
= *count
= 0;
1563 map_size
= (indirect_count
- 1) * indirect
->stride
+ 3 * sizeof(unsigned);
1564 data
= pipe_buffer_map_range(&sctx
->b
, indirect
->buffer
,
1565 indirect
->offset
, map_size
,
1566 PIPE_TRANSFER_READ
, &transfer
);
1571 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1572 unsigned count
= data
[0];
1573 unsigned start
= data
[2];
1576 begin
= MIN2(begin
, start
);
1577 end
= MAX2(end
, start
+ count
);
1580 data
+= indirect
->stride
/ sizeof(unsigned);
1583 pipe_buffer_unmap(&sctx
->b
, transfer
);
1587 *count
= end
- begin
;
1589 *start
= *count
= 0;
1592 *start
= info
->start
;
1593 *count
= info
->count
;
1597 static void si_emit_all_states(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1598 enum pipe_prim_type prim
, unsigned instance_count
,
1599 bool primitive_restart
, unsigned skip_atom_mask
)
1601 unsigned num_patches
= 0;
1603 si_emit_rasterizer_prim_state(sctx
);
1604 if (sctx
->tes_shader
.cso
)
1605 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1607 /* Emit state atoms. */
1608 unsigned mask
= sctx
->dirty_atoms
& ~skip_atom_mask
;
1610 sctx
->atoms
.array
[u_bit_scan(&mask
)].emit(sctx
);
1612 sctx
->dirty_atoms
&= skip_atom_mask
;
1615 mask
= sctx
->dirty_states
;
1617 unsigned i
= u_bit_scan(&mask
);
1618 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1620 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1623 si_pm4_emit(sctx
, state
);
1624 sctx
->emitted
.array
[i
] = state
;
1626 sctx
->dirty_states
= 0;
1628 /* Emit draw states. */
1629 si_emit_vs_state(sctx
, info
);
1630 si_emit_draw_registers(sctx
, info
, prim
, num_patches
, instance_count
,
1635 si_all_vs_resources_read_only(struct si_context
*sctx
,
1636 struct pipe_resource
*indexbuf
)
1638 struct radeon_winsys
*ws
= sctx
->ws
;
1639 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1643 ws
->cs_is_buffer_referenced(cs
, si_resource(indexbuf
)->buf
,
1644 RADEON_USAGE_WRITE
))
1645 goto has_write_reference
;
1647 /* Vertex buffers. */
1648 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1649 unsigned num_velems
= velems
->count
;
1651 for (unsigned i
= 0; i
< num_velems
; i
++) {
1652 if (!((1 << i
) & velems
->first_vb_use_mask
))
1655 unsigned vb_index
= velems
->vertex_buffer_index
[i
];
1656 struct pipe_resource
*res
= sctx
->vertex_buffer
[vb_index
].buffer
.resource
;
1660 if (ws
->cs_is_buffer_referenced(cs
, si_resource(res
)->buf
,
1661 RADEON_USAGE_WRITE
))
1662 goto has_write_reference
;
1665 /* Constant and shader buffers. */
1666 struct si_descriptors
*buffers
=
1667 &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX
)];
1668 for (unsigned i
= 0; i
< buffers
->num_active_slots
; i
++) {
1669 unsigned index
= buffers
->first_active_slot
+ i
;
1670 struct pipe_resource
*res
=
1671 sctx
->const_and_shader_buffers
[PIPE_SHADER_VERTEX
].buffers
[index
];
1675 if (ws
->cs_is_buffer_referenced(cs
, si_resource(res
)->buf
,
1676 RADEON_USAGE_WRITE
))
1677 goto has_write_reference
;
1681 struct si_shader_selector
*vs
= sctx
->vs_shader
.cso
;
1682 if (vs
->info
.samplers_declared
) {
1683 unsigned num_samplers
= util_last_bit(vs
->info
.samplers_declared
);
1685 for (unsigned i
= 0; i
< num_samplers
; i
++) {
1686 struct pipe_sampler_view
*view
= sctx
->samplers
[PIPE_SHADER_VERTEX
].views
[i
];
1690 if (ws
->cs_is_buffer_referenced(cs
,
1691 si_resource(view
->texture
)->buf
,
1692 RADEON_USAGE_WRITE
))
1693 goto has_write_reference
;
1698 if (vs
->info
.images_declared
) {
1699 unsigned num_images
= util_last_bit(vs
->info
.images_declared
);
1701 for (unsigned i
= 0; i
< num_images
; i
++) {
1702 struct pipe_resource
*res
= sctx
->images
[PIPE_SHADER_VERTEX
].views
[i
].resource
;
1706 if (ws
->cs_is_buffer_referenced(cs
, si_resource(res
)->buf
,
1707 RADEON_USAGE_WRITE
))
1708 goto has_write_reference
;
1714 has_write_reference
:
1715 /* If the current gfx IB has enough packets, flush it to remove write
1716 * references to buffers.
1718 if (cs
->prev_dw
+ cs
->current
.cdw
> 2048) {
1719 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1720 assert(si_all_vs_resources_read_only(sctx
, indexbuf
));
1726 static ALWAYS_INLINE
bool pd_msg(const char *s
)
1728 if (SI_PRIM_DISCARD_DEBUG
)
1729 printf("PD failed: %s\n", s
);
1733 static void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1735 struct si_context
*sctx
= (struct si_context
*)ctx
;
1736 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1737 struct pipe_resource
*indexbuf
= info
->index
.resource
;
1738 unsigned dirty_tex_counter
, dirty_buf_counter
;
1739 enum pipe_prim_type rast_prim
, prim
= info
->mode
;
1740 unsigned index_size
= info
->index_size
;
1741 unsigned index_offset
= info
->indirect
? info
->start
* index_size
: 0;
1742 unsigned instance_count
= info
->instance_count
;
1743 bool primitive_restart
= info
->primitive_restart
&&
1744 (!sctx
->screen
->options
.prim_restart_tri_strips_only
||
1745 (prim
!= PIPE_PRIM_TRIANGLE_STRIP
&&
1746 prim
!= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
));
1748 if (likely(!info
->indirect
)) {
1749 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1750 * no workaround for indirect draws, but we can at least skip
1753 if (unlikely(!instance_count
))
1756 /* Handle count == 0. */
1757 if (unlikely(!info
->count
&&
1758 (index_size
|| !info
->count_from_stream_output
)))
1762 if (unlikely(!sctx
->vs_shader
.cso
||
1764 (!sctx
->ps_shader
.cso
&& !rs
->rasterizer_discard
) ||
1765 (!!sctx
->tes_shader
.cso
!= (prim
== PIPE_PRIM_PATCHES
)))) {
1770 /* Recompute and re-emit the texture resource states if needed. */
1771 dirty_tex_counter
= p_atomic_read(&sctx
->screen
->dirty_tex_counter
);
1772 if (unlikely(dirty_tex_counter
!= sctx
->last_dirty_tex_counter
)) {
1773 sctx
->last_dirty_tex_counter
= dirty_tex_counter
;
1774 sctx
->framebuffer
.dirty_cbufs
|=
1775 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1776 sctx
->framebuffer
.dirty_zsbuf
= true;
1777 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
1778 si_update_all_texture_descriptors(sctx
);
1781 dirty_buf_counter
= p_atomic_read(&sctx
->screen
->dirty_buf_counter
);
1782 if (unlikely(dirty_buf_counter
!= sctx
->last_dirty_buf_counter
)) {
1783 sctx
->last_dirty_buf_counter
= dirty_buf_counter
;
1784 /* Rebind all buffers unconditionally. */
1785 si_rebind_buffer(sctx
, NULL
);
1788 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
1790 /* Set the rasterization primitive type.
1792 * This must be done after si_decompress_textures, which can call
1793 * draw_vbo recursively, and before si_update_shaders, which uses
1794 * current_rast_prim for this draw_vbo call. */
1795 if (sctx
->gs_shader
.cso
) {
1796 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1797 rast_prim
= sctx
->gs_shader
.cso
->rast_prim
;
1798 } else if (sctx
->tes_shader
.cso
) {
1799 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1800 rast_prim
= sctx
->tes_shader
.cso
->rast_prim
;
1801 } else if (util_rast_prim_is_triangles(prim
)) {
1802 rast_prim
= PIPE_PRIM_TRIANGLES
;
1804 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1808 if (rast_prim
!= sctx
->current_rast_prim
) {
1809 if (util_prim_is_points_or_lines(sctx
->current_rast_prim
) !=
1810 util_prim_is_points_or_lines(rast_prim
))
1811 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1813 sctx
->current_rast_prim
= rast_prim
;
1814 sctx
->do_update_shaders
= true;
1817 if (sctx
->tes_shader
.cso
&&
1818 sctx
->screen
->has_ls_vgpr_init_bug
) {
1819 /* Determine whether the LS VGPR fix should be applied.
1821 * It is only required when num input CPs > num output CPs,
1822 * which cannot happen with the fixed function TCS. We should
1823 * also update this bit when switching from TCS to fixed
1826 struct si_shader_selector
*tcs
= sctx
->tcs_shader
.cso
;
1829 info
->vertices_per_patch
>
1830 tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
1832 if (ls_vgpr_fix
!= sctx
->ls_vgpr_fix
) {
1833 sctx
->ls_vgpr_fix
= ls_vgpr_fix
;
1834 sctx
->do_update_shaders
= true;
1838 if (sctx
->chip_class
<= GFX9
&& sctx
->gs_shader
.cso
) {
1839 /* Determine whether the GS triangle strip adjacency fix should
1840 * be applied. Rotate every other triangle if
1841 * - triangle strips with adjacency are fed to the GS and
1842 * - primitive restart is disabled (the rotation doesn't help
1843 * when the restart occurs after an odd number of triangles).
1845 bool gs_tri_strip_adj_fix
=
1846 !sctx
->tes_shader
.cso
&&
1847 prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1850 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1851 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1852 sctx
->do_update_shaders
= true;
1857 /* Translate or upload, if needed. */
1858 /* 8-bit indices are supported on GFX8. */
1859 if (sctx
->chip_class
<= GFX7
&& index_size
== 1) {
1860 unsigned start
, count
, start_offset
, size
, offset
;
1863 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1864 start_offset
= start
* 2;
1868 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1870 si_optimal_tcc_alignment(sctx
, size
),
1871 &offset
, &indexbuf
, &ptr
);
1875 util_shorten_ubyte_elts_to_userptr(&sctx
->b
, info
, 0, 0,
1876 index_offset
+ start
,
1879 /* info->start will be added by the drawing code */
1880 index_offset
= offset
- start_offset
;
1882 } else if (info
->has_user_indices
) {
1883 unsigned start_offset
;
1885 assert(!info
->indirect
);
1886 start_offset
= info
->start
* index_size
;
1889 u_upload_data(ctx
->stream_uploader
, start_offset
,
1890 info
->count
* index_size
,
1891 sctx
->screen
->info
.tcc_cache_line_size
,
1892 (char*)info
->index
.user
+ start_offset
,
1893 &index_offset
, &indexbuf
);
1897 /* info->start will be added by the drawing code */
1898 index_offset
-= start_offset
;
1899 } else if (sctx
->chip_class
<= GFX7
&&
1900 si_resource(indexbuf
)->TC_L2_dirty
) {
1901 /* GFX8 reads index buffers through TC L2, so it doesn't
1903 sctx
->flags
|= SI_CONTEXT_WB_L2
;
1904 si_resource(indexbuf
)->TC_L2_dirty
= false;
1908 bool dispatch_prim_discard_cs
= false;
1909 bool prim_discard_cs_instancing
= false;
1910 unsigned original_index_size
= index_size
;
1911 unsigned direct_count
= 0;
1913 if (info
->indirect
) {
1914 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1916 /* Add the buffer size for memory checking in need_cs_space. */
1917 si_context_add_resource_size(sctx
, indirect
->buffer
);
1919 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1920 if (sctx
->chip_class
<= GFX8
) {
1921 if (si_resource(indirect
->buffer
)->TC_L2_dirty
) {
1922 sctx
->flags
|= SI_CONTEXT_WB_L2
;
1923 si_resource(indirect
->buffer
)->TC_L2_dirty
= false;
1926 if (indirect
->indirect_draw_count
&&
1927 si_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
) {
1928 sctx
->flags
|= SI_CONTEXT_WB_L2
;
1929 si_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
= false;
1933 /* Multiply by 3 for strips and fans to get an approximate vertex
1934 * count as triangles. */
1935 direct_count
= info
->count
* instance_count
*
1936 (prim
== PIPE_PRIM_TRIANGLES
? 1 : 3);
1939 /* Determine if we can use the primitive discard compute shader. */
1940 if (si_compute_prim_discard_enabled(sctx
) &&
1941 (direct_count
> sctx
->prim_discard_vertex_count_threshold
?
1942 (sctx
->compute_num_verts_rejected
+= direct_count
, true) : /* Add, then return true. */
1943 (sctx
->compute_num_verts_ineligible
+= direct_count
, false)) && /* Add, then return false. */
1944 (!info
->count_from_stream_output
|| pd_msg("draw_opaque")) &&
1945 (primitive_restart
?
1946 /* Supported prim types with primitive restart: */
1947 (prim
== PIPE_PRIM_TRIANGLE_STRIP
|| pd_msg("bad prim type with primitive restart")) &&
1948 /* Disallow instancing with primitive restart: */
1949 (instance_count
== 1 || pd_msg("instance_count > 1 with primitive restart")) :
1950 /* Supported prim types without primitive restart + allow instancing: */
1951 (1 << prim
) & ((1 << PIPE_PRIM_TRIANGLES
) |
1952 (1 << PIPE_PRIM_TRIANGLE_STRIP
) |
1953 (1 << PIPE_PRIM_TRIANGLE_FAN
)) &&
1954 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1955 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1956 (instance_count
== 1 ||
1957 (instance_count
<= USHRT_MAX
&& index_size
&& index_size
<= 2) ||
1958 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1959 (info
->drawid
== 0 || !sctx
->vs_shader
.cso
->info
.uses_drawid
|| pd_msg("draw_id > 0")) &&
1960 (!sctx
->render_cond
|| pd_msg("render condition")) &&
1961 /* Forced enablement ignores pipeline statistics queries. */
1962 (sctx
->screen
->debug_flags
& (DBG(PD
) | DBG(ALWAYS_PD
)) ||
1963 (!sctx
->num_pipeline_stat_queries
&& !sctx
->streamout
.prims_gen_query_enabled
) ||
1964 pd_msg("pipestat or primgen query")) &&
1965 (!sctx
->vertex_elements
->instance_divisor_is_fetched
|| pd_msg("loads instance divisors")) &&
1966 (!sctx
->tes_shader
.cso
|| pd_msg("uses tess")) &&
1967 (!sctx
->gs_shader
.cso
|| pd_msg("uses GS")) &&
1968 (!sctx
->ps_shader
.cso
->info
.uses_primid
|| pd_msg("PS uses PrimID")) &&
1969 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1970 (!sctx
->vs_shader
.cso
->info
.uses_bindless_images
|| pd_msg("uses bindless images")) &&
1971 (!sctx
->vs_shader
.cso
->info
.uses_bindless_samplers
|| pd_msg("uses bindless samplers")) &&
1972 (!sctx
->vs_shader
.cso
->info
.writes_memory
|| pd_msg("writes memory")) &&
1973 (!sctx
->vs_shader
.cso
->info
.writes_viewport_index
|| pd_msg("writes viewport index")) &&
1974 !sctx
->vs_shader
.cso
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
1975 !sctx
->vs_shader
.cso
->so
.num_outputs
&&
1977 (sctx
->vs_shader
.cso
->prim_discard_cs_allowed
|| pd_msg("VS shader uses unsupported features")) &&
1979 /* Check that all buffers are used for read only, because compute
1980 * dispatches can run ahead. */
1981 (si_all_vs_resources_read_only(sctx
, index_size
? indexbuf
: NULL
) || pd_msg("write reference"))) {
1982 switch (si_prepare_prim_discard_or_split_draw(sctx
, info
, primitive_restart
)) {
1983 case SI_PRIM_DISCARD_ENABLED
:
1984 original_index_size
= index_size
;
1985 prim_discard_cs_instancing
= instance_count
> 1;
1986 dispatch_prim_discard_cs
= true;
1988 /* The compute shader changes/lowers the following: */
1989 prim
= PIPE_PRIM_TRIANGLES
;
1992 primitive_restart
= false;
1993 sctx
->compute_num_verts_rejected
-= direct_count
;
1994 sctx
->compute_num_verts_accepted
+= direct_count
;
1996 case SI_PRIM_DISCARD_DISABLED
:
1998 case SI_PRIM_DISCARD_DRAW_SPLIT
:
1999 sctx
->compute_num_verts_rejected
-= direct_count
;
2000 goto return_cleanup
;
2004 if (prim_discard_cs_instancing
!= sctx
->prim_discard_cs_instancing
) {
2005 sctx
->prim_discard_cs_instancing
= prim_discard_cs_instancing
;
2006 sctx
->do_update_shaders
= true;
2009 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
2010 goto return_cleanup
;
2012 si_need_gfx_cs_space(sctx
);
2014 if (sctx
->bo_list_add_all_gfx_resources
)
2015 si_gfx_resources_add_all_to_bo_list(sctx
);
2017 /* Since we've called si_context_add_resource_size for vertex buffers,
2018 * this must be called after si_need_cs_space, because we must let
2019 * need_cs_space flush before we add buffers to the buffer list.
2021 if (!si_upload_vertex_buffer_descriptors(sctx
))
2022 goto return_cleanup
;
2024 /* Vega10/Raven scissor bug workaround. When any context register is
2025 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2026 * registers must be written too.
2028 bool has_gfx9_scissor_bug
= sctx
->screen
->has_gfx9_scissor_bug
;
2029 unsigned masked_atoms
= 0;
2031 if (has_gfx9_scissor_bug
) {
2032 masked_atoms
|= si_get_atom_bit(sctx
, &sctx
->atoms
.s
.scissors
);
2034 if (info
->count_from_stream_output
||
2035 sctx
->dirty_atoms
& si_atoms_that_always_roll_context() ||
2036 sctx
->dirty_states
& si_states_that_always_roll_context())
2037 sctx
->context_roll
= true;
2040 /* Use optimal packet order based on whether we need to sync the pipeline. */
2041 if (unlikely(sctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
2042 SI_CONTEXT_FLUSH_AND_INV_DB
|
2043 SI_CONTEXT_PS_PARTIAL_FLUSH
|
2044 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
2045 /* If we have to wait for idle, set all states first, so that all
2046 * SET packets are processed in parallel with previous draw calls.
2047 * Then draw and prefetch at the end. This ensures that the time
2048 * the CUs are idle is very short.
2050 if (unlikely(sctx
->flags
& SI_CONTEXT_FLUSH_FOR_RENDER_COND
))
2051 masked_atoms
|= si_get_atom_bit(sctx
, &sctx
->atoms
.s
.render_cond
);
2053 if (!si_upload_graphics_shader_descriptors(sctx
))
2054 goto return_cleanup
;
2056 /* Emit all states except possibly render condition. */
2057 si_emit_all_states(sctx
, info
, prim
, instance_count
,
2058 primitive_restart
, masked_atoms
);
2059 sctx
->emit_cache_flush(sctx
);
2060 /* <-- CUs are idle here. */
2062 if (si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
))
2063 sctx
->atoms
.s
.render_cond
.emit(sctx
);
2065 if (has_gfx9_scissor_bug
&&
2066 (sctx
->context_roll
||
2067 si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
)))
2068 sctx
->atoms
.s
.scissors
.emit(sctx
);
2070 sctx
->dirty_atoms
= 0;
2072 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
,
2073 instance_count
, dispatch_prim_discard_cs
,
2074 original_index_size
);
2075 /* <-- CUs are busy here. */
2077 /* Start prefetches after the draw has been started. Both will run
2078 * in parallel, but starting the draw first is more important.
2080 if (sctx
->chip_class
>= GFX7
&& sctx
->prefetch_L2_mask
)
2081 cik_emit_prefetch_L2(sctx
, false);
2083 /* If we don't wait for idle, start prefetches first, then set
2084 * states, and draw at the end.
2087 sctx
->emit_cache_flush(sctx
);
2089 /* Only prefetch the API VS and VBO descriptors. */
2090 if (sctx
->chip_class
>= GFX7
&& sctx
->prefetch_L2_mask
)
2091 cik_emit_prefetch_L2(sctx
, true);
2093 if (!si_upload_graphics_shader_descriptors(sctx
))
2094 goto return_cleanup
;
2096 si_emit_all_states(sctx
, info
, prim
, instance_count
,
2097 primitive_restart
, masked_atoms
);
2099 if (has_gfx9_scissor_bug
&&
2100 (sctx
->context_roll
||
2101 si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
)))
2102 sctx
->atoms
.s
.scissors
.emit(sctx
);
2104 sctx
->dirty_atoms
= 0;
2106 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
,
2107 instance_count
, dispatch_prim_discard_cs
,
2108 original_index_size
);
2110 /* Prefetch the remaining shaders after the draw has been
2112 if (sctx
->chip_class
>= GFX7
&& sctx
->prefetch_L2_mask
)
2113 cik_emit_prefetch_L2(sctx
, false);
2116 /* Clear the context roll flag after the draw call. */
2117 sctx
->context_roll
= false;
2119 if (unlikely(sctx
->current_saved_cs
)) {
2120 si_trace_emit(sctx
);
2121 si_log_draw_state(sctx
, sctx
->log
);
2124 /* Workaround for a VGT hang when streamout is enabled.
2125 * It must be done after drawing. */
2126 if ((sctx
->family
== CHIP_HAWAII
||
2127 sctx
->family
== CHIP_TONGA
||
2128 sctx
->family
== CHIP_FIJI
) &&
2129 si_get_strmout_en(sctx
)) {
2130 sctx
->flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
2133 if (unlikely(sctx
->decompression_enabled
)) {
2134 sctx
->num_decompress_calls
++;
2136 sctx
->num_draw_calls
++;
2137 if (sctx
->framebuffer
.state
.nr_cbufs
> 1)
2138 sctx
->num_mrt_draw_calls
++;
2139 if (primitive_restart
)
2140 sctx
->num_prim_restart_calls
++;
2141 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
2142 sctx
->num_spill_draw_calls
++;
2146 if (index_size
&& indexbuf
!= info
->index
.resource
)
2147 pipe_resource_reference(&indexbuf
, NULL
);
2151 si_draw_rectangle(struct blitter_context
*blitter
,
2152 void *vertex_elements_cso
,
2153 blitter_get_vs_func get_vs
,
2154 int x1
, int y1
, int x2
, int y2
,
2155 float depth
, unsigned num_instances
,
2156 enum blitter_attrib_type type
,
2157 const union blitter_attrib
*attrib
)
2159 struct pipe_context
*pipe
= util_blitter_get_pipe(blitter
);
2160 struct si_context
*sctx
= (struct si_context
*)pipe
;
2162 /* Pack position coordinates as signed int16. */
2163 sctx
->vs_blit_sh_data
[0] = (uint32_t)(x1
& 0xffff) |
2164 ((uint32_t)(y1
& 0xffff) << 16);
2165 sctx
->vs_blit_sh_data
[1] = (uint32_t)(x2
& 0xffff) |
2166 ((uint32_t)(y2
& 0xffff) << 16);
2167 sctx
->vs_blit_sh_data
[2] = fui(depth
);
2170 case UTIL_BLITTER_ATTRIB_COLOR
:
2171 memcpy(&sctx
->vs_blit_sh_data
[3], attrib
->color
,
2174 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
2175 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
2176 memcpy(&sctx
->vs_blit_sh_data
[3], &attrib
->texcoord
,
2177 sizeof(attrib
->texcoord
));
2179 case UTIL_BLITTER_ATTRIB_NONE
:;
2182 pipe
->bind_vs_state(pipe
, si_get_blitter_vs(sctx
, type
, num_instances
));
2184 struct pipe_draw_info info
= {};
2185 info
.mode
= SI_PRIM_RECTANGLE_LIST
;
2187 info
.instance_count
= num_instances
;
2189 /* Don't set per-stage shader pointers for VS. */
2190 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(VERTEX
);
2191 sctx
->vertex_buffer_pointer_dirty
= false;
2193 si_draw_vbo(pipe
, &info
);
2196 void si_trace_emit(struct si_context
*sctx
)
2198 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2199 uint32_t trace_id
= ++sctx
->current_saved_cs
->trace_id
;
2201 si_cp_write_data(sctx
, sctx
->current_saved_cs
->trace_buf
,
2202 0, 4, V_370_MEM
, V_370_ME
, &trace_id
);
2204 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2205 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(trace_id
));
2208 u_log_flush(sctx
->log
);
2211 void si_init_draw_functions(struct si_context
*sctx
)
2213 sctx
->b
.draw_vbo
= si_draw_vbo
;
2215 sctx
->blitter
->draw_rectangle
= si_draw_rectangle
;
2217 si_init_ia_multi_vgt_param_table(sctx
);