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radeonsi: add a cs parameter into si_cp_release_mem
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static void si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_cmdbuf *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = ls->lshs_vertex_stride;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance.
169 * The hardware can do more, but the radeonsi shader constant is
170 * limited to 6 bits.
171 */
172 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
173
174 /* When distributed tessellation is unsupported, switch between SEs
175 * at a higher frequency to compensate for it.
176 */
177 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
178 *num_patches = MIN2(*num_patches, 16); /* recommended */
179
180 /* Make sure that vector lanes are reasonably occupied. It probably
181 * doesn't matter much because this is LS-HS, and TES is likely to
182 * occupy significantly more CUs.
183 */
184 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
185 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
186 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
187
188 if (sctx->chip_class == GFX6) {
189 /* GFX6 bug workaround, related to power management. Limit LS-HS
190 * threadgroups to only one wave.
191 */
192 unsigned one_wave = 64 / max_verts_per_patch;
193 *num_patches = MIN2(*num_patches, one_wave);
194 }
195
196 /* The VGT HS block increments the patch ID unconditionally
197 * within a single threadgroup. This results in incorrect
198 * patch IDs when instanced draws are used.
199 *
200 * The intended solution is to restrict threadgroups to
201 * a single instance by setting SWITCH_ON_EOI, which
202 * should cause IA to split instances up. However, this
203 * doesn't work correctly on GFX6 when there is no other
204 * SE to switch to.
205 */
206 if (has_primid_instancing_bug && tess_uses_primid)
207 *num_patches = 1;
208
209 sctx->last_num_patches = *num_patches;
210
211 output_patch0_offset = input_patch_size * *num_patches;
212 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
213
214 /* Compute userdata SGPRs. */
215 assert(((input_vertex_size / 4) & ~0xff) == 0);
216 assert(((output_vertex_size / 4) & ~0xff) == 0);
217 assert(((input_patch_size / 4) & ~0x1fff) == 0);
218 assert(((output_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
220 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
221 assert(num_tcs_input_cp <= 32);
222 assert(num_tcs_output_cp <= 32);
223
224 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
225 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
226
227 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
228 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
229 tcs_out_layout = (output_patch_size / 4) |
230 (num_tcs_input_cp << 13) |
231 ring_va;
232 tcs_out_offsets = (output_patch0_offset / 16) |
233 ((perpatch_output_offset / 16) << 16);
234 offchip_layout = *num_patches |
235 (num_tcs_output_cp << 6) |
236 (pervertex_output_patch_size * *num_patches << 12);
237
238 /* Compute the LDS size. */
239 lds_size = output_patch0_offset + output_patch_size * *num_patches;
240
241 if (sctx->chip_class >= GFX7) {
242 assert(lds_size <= 65536);
243 lds_size = align(lds_size, 512) / 512;
244 } else {
245 assert(lds_size <= 32768);
246 lds_size = align(lds_size, 256) / 256;
247 }
248
249 /* Set SI_SGPR_VS_STATE_BITS. */
250 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
251 C_VS_STATE_LS_OUT_VERTEX_SIZE;
252 sctx->current_vs_state |= tcs_in_layout;
253
254 if (sctx->chip_class >= GFX9) {
255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
256 S_00B42C_LDS_SIZE(lds_size);
257
258 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
259
260 /* Set userdata SGPRs for merged LS-HS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
263 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout);
267 } else {
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
269
270 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
271 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
272
273 /* Due to a hw bug, RSRC2_LS must be written twice with another
274 * LS register written in between. */
275 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
276 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
280
281 /* Set userdata SGPRs for TCS. */
282 radeon_set_sh_reg_seq(cs,
283 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout);
287 radeon_emit(cs, tcs_in_layout);
288 }
289
290 /* Set userdata SGPRs for TES. */
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
292 radeon_emit(cs, offchip_layout);
293 radeon_emit(cs, ring_va);
294
295 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
296 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
297 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
298
299 if (sctx->last_ls_hs_config != ls_hs_config) {
300 if (sctx->chip_class >= GFX7) {
301 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
302 ls_hs_config);
303 } else {
304 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
305 ls_hs_config);
306 }
307 sctx->last_ls_hs_config = ls_hs_config;
308 sctx->context_roll = true;
309 }
310 }
311
312 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
313 {
314 switch (info->mode) {
315 case PIPE_PRIM_PATCHES:
316 return info->count / info->vertices_per_patch;
317 case PIPE_PRIM_POLYGON:
318 return info->count >= 3;
319 case SI_PRIM_RECTANGLE_LIST:
320 return info->count / 3;
321 default:
322 return u_decomposed_prims_for_vertices(info->mode, info->count);
323 }
324 }
325
326 static unsigned
327 si_get_init_multi_vgt_param(struct si_screen *sscreen,
328 union si_vgt_param_key *key)
329 {
330 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
331 unsigned max_primgroup_in_wave = 2;
332
333 /* SWITCH_ON_EOP(0) is always preferable. */
334 bool wd_switch_on_eop = false;
335 bool ia_switch_on_eop = false;
336 bool ia_switch_on_eoi = false;
337 bool partial_vs_wave = false;
338 bool partial_es_wave = false;
339
340 if (key->u.uses_tess) {
341 /* SWITCH_ON_EOI must be set if PrimID is used. */
342 if (key->u.tess_uses_prim_id)
343 ia_switch_on_eoi = true;
344
345 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
346 if ((sscreen->info.family == CHIP_TAHITI ||
347 sscreen->info.family == CHIP_PITCAIRN ||
348 sscreen->info.family == CHIP_BONAIRE) &&
349 key->u.uses_gs)
350 partial_vs_wave = true;
351
352 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
353 if (sscreen->has_distributed_tess) {
354 if (key->u.uses_gs) {
355 if (sscreen->info.chip_class == GFX8)
356 partial_es_wave = true;
357 } else {
358 partial_vs_wave = true;
359 }
360 }
361 }
362
363 /* This is a hardware requirement. */
364 if (key->u.line_stipple_enabled ||
365 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
366 ia_switch_on_eop = true;
367 wd_switch_on_eop = true;
368 }
369
370 if (sscreen->info.chip_class >= GFX7) {
371 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
372 * 4 shader engines. Set 1 to pass the assertion below.
373 * The other cases are hardware requirements.
374 *
375 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
376 * for points, line strips, and tri strips.
377 */
378 if (sscreen->info.max_se <= 2 ||
379 key->u.prim == PIPE_PRIM_POLYGON ||
380 key->u.prim == PIPE_PRIM_LINE_LOOP ||
381 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
382 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
383 (key->u.primitive_restart &&
384 (sscreen->info.family < CHIP_POLARIS10 ||
385 (key->u.prim != PIPE_PRIM_POINTS &&
386 key->u.prim != PIPE_PRIM_LINE_STRIP &&
387 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
388 key->u.count_from_stream_output)
389 wd_switch_on_eop = true;
390
391 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
392 * We don't know that for indirect drawing, so treat it as
393 * always problematic. */
394 if (sscreen->info.family == CHIP_HAWAII &&
395 key->u.uses_instancing)
396 wd_switch_on_eop = true;
397
398 /* Performance recommendation for 4 SE Gfx7-8 parts if
399 * instances are smaller than a primgroup.
400 * Assume indirect draws always use small instances.
401 * This is needed for good VS wave utilization.
402 */
403 if (sscreen->info.chip_class <= GFX8 &&
404 sscreen->info.max_se == 4 &&
405 key->u.multi_instances_smaller_than_primgroup)
406 wd_switch_on_eop = true;
407
408 /* Required on GFX7 and later. */
409 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
410 ia_switch_on_eoi = true;
411
412 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
413 * to work around a GS hang.
414 */
415 if (key->u.uses_gs &&
416 (sscreen->info.family == CHIP_TONGA ||
417 sscreen->info.family == CHIP_FIJI ||
418 sscreen->info.family == CHIP_POLARIS10 ||
419 sscreen->info.family == CHIP_POLARIS11 ||
420 sscreen->info.family == CHIP_POLARIS12 ||
421 sscreen->info.family == CHIP_VEGAM))
422 partial_vs_wave = true;
423
424 /* Required by Hawaii and, for some special cases, by GFX8. */
425 if (ia_switch_on_eoi &&
426 (sscreen->info.family == CHIP_HAWAII ||
427 (sscreen->info.chip_class == GFX8 &&
428 (key->u.uses_gs || max_primgroup_in_wave != 2))))
429 partial_vs_wave = true;
430
431 /* Instancing bug on Bonaire. */
432 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
433 key->u.uses_instancing)
434 partial_vs_wave = true;
435
436 /* This only applies to Polaris10 and later 4 SE chips.
437 * wd_switch_on_eop is already true on all other chips.
438 */
439 if (!wd_switch_on_eop && key->u.primitive_restart)
440 partial_vs_wave = true;
441
442 /* If the WD switch is false, the IA switch must be false too. */
443 assert(wd_switch_on_eop || !ia_switch_on_eop);
444 }
445
446 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
447 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
448 partial_es_wave = true;
449
450 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
451 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
452 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
453 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
454 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
455 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
456 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
457 max_primgroup_in_wave : 0) |
458 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
459 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
460 }
461
462 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
463 {
464 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
465 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
466 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
467 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
468 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
469 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
470 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
471 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
472 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
473 union si_vgt_param_key key;
474
475 key.index = 0;
476 key.u.prim = prim;
477 key.u.uses_instancing = uses_instancing;
478 key.u.multi_instances_smaller_than_primgroup = multi_instances;
479 key.u.primitive_restart = primitive_restart;
480 key.u.count_from_stream_output = count_from_so;
481 key.u.line_stipple_enabled = line_stipple;
482 key.u.uses_tess = uses_tess;
483 key.u.tess_uses_prim_id = tess_uses_primid;
484 key.u.uses_gs = uses_gs;
485
486 sctx->ia_multi_vgt_param[key.index] =
487 si_get_init_multi_vgt_param(sctx->screen, &key);
488 }
489 }
490
491 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
492 const struct pipe_draw_info *info,
493 unsigned num_patches)
494 {
495 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
496 unsigned primgroup_size;
497 unsigned ia_multi_vgt_param;
498
499 if (sctx->tes_shader.cso) {
500 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
501 } else if (sctx->gs_shader.cso) {
502 primgroup_size = 64; /* recommended with a GS */
503 } else {
504 primgroup_size = 128; /* recommended without a GS and tess */
505 }
506
507 key.u.prim = info->mode;
508 key.u.uses_instancing = info->indirect || info->instance_count > 1;
509 key.u.multi_instances_smaller_than_primgroup =
510 info->indirect ||
511 (info->instance_count > 1 &&
512 (info->count_from_stream_output ||
513 si_num_prims_for_vertices(info) < primgroup_size));
514 key.u.primitive_restart = info->primitive_restart;
515 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
516
517 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
518 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
519
520 if (sctx->gs_shader.cso) {
521 /* GS requirement. */
522 if (sctx->chip_class <= GFX8 &&
523 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
524 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
525
526 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
527 * The hw doc says all multi-SE chips are affected, but Vulkan
528 * only applies it to Hawaii. Do what Vulkan does.
529 */
530 if (sctx->family == CHIP_HAWAII &&
531 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
532 (info->indirect ||
533 (info->instance_count > 1 &&
534 (info->count_from_stream_output ||
535 si_num_prims_for_vertices(info) <= 1))))
536 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
537 }
538
539 return ia_multi_vgt_param;
540 }
541
542 /* rast_prim is the primitive type after GS. */
543 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
544 {
545 struct radeon_cmdbuf *cs = sctx->gfx_cs;
546 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
547 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
548
549 /* Skip this if not rendering lines. */
550 if (!util_prim_is_lines(rast_prim))
551 return;
552
553 if (rast_prim == sctx->last_rast_prim &&
554 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
555 return;
556
557 /* For lines, reset the stipple pattern at each primitive. Otherwise,
558 * reset the stipple pattern at each packet (line strips, line loops).
559 */
560 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
561 rs->pa_sc_line_stipple |
562 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
563
564 sctx->last_rast_prim = rast_prim;
565 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
566 sctx->context_roll = true;
567 }
568
569 static void si_emit_vs_state(struct si_context *sctx,
570 const struct pipe_draw_info *info)
571 {
572 sctx->current_vs_state &= C_VS_STATE_INDEXED;
573 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
574
575 if (sctx->num_vs_blit_sgprs) {
576 /* Re-emit the state after we leave u_blitter. */
577 sctx->last_vs_state = ~0;
578 return;
579 }
580
581 if (sctx->current_vs_state != sctx->last_vs_state) {
582 struct radeon_cmdbuf *cs = sctx->gfx_cs;
583
584 /* For the API vertex shader (VS_STATE_INDEXED). */
585 radeon_set_sh_reg(cs,
586 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
587 SI_SGPR_VS_STATE_BITS * 4,
588 sctx->current_vs_state);
589
590 /* For vertex color clamping, which is done in the last stage
591 * before the rasterizer. */
592 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
593 /* GS copy shader or TES if GS is missing. */
594 radeon_set_sh_reg(cs,
595 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
596 SI_SGPR_VS_STATE_BITS * 4,
597 sctx->current_vs_state);
598 }
599
600 sctx->last_vs_state = sctx->current_vs_state;
601 }
602 }
603
604 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
605 const struct pipe_draw_info *info)
606 {
607 return info->primitive_restart &&
608 (info->restart_index != sctx->last_restart_index ||
609 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
610 }
611
612 static void si_emit_draw_registers(struct si_context *sctx,
613 const struct pipe_draw_info *info,
614 unsigned num_patches)
615 {
616 struct radeon_cmdbuf *cs = sctx->gfx_cs;
617 unsigned prim = si_conv_pipe_prim(info->mode);
618 unsigned ia_multi_vgt_param;
619
620 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
621
622 /* Draw state. */
623 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
624 if (sctx->chip_class >= GFX9)
625 radeon_set_uconfig_reg_idx(cs, sctx->screen,
626 R_030960_IA_MULTI_VGT_PARAM, 4,
627 ia_multi_vgt_param);
628 else if (sctx->chip_class >= GFX7)
629 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
630 else
631 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
632
633 sctx->last_multi_vgt_param = ia_multi_vgt_param;
634 }
635 if (prim != sctx->last_prim) {
636 if (sctx->chip_class >= GFX7)
637 radeon_set_uconfig_reg_idx(cs, sctx->screen,
638 R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
639 else
640 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
641
642 sctx->last_prim = prim;
643 }
644
645 /* Primitive restart. */
646 if (info->primitive_restart != sctx->last_primitive_restart_en) {
647 if (sctx->chip_class >= GFX9)
648 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
649 info->primitive_restart);
650 else
651 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
652 info->primitive_restart);
653
654 sctx->last_primitive_restart_en = info->primitive_restart;
655
656 }
657 if (si_prim_restart_index_changed(sctx, info)) {
658 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
659 info->restart_index);
660 sctx->last_restart_index = info->restart_index;
661 sctx->context_roll = true;
662 }
663 }
664
665 static void si_emit_draw_packets(struct si_context *sctx,
666 const struct pipe_draw_info *info,
667 struct pipe_resource *indexbuf,
668 unsigned index_size,
669 unsigned index_offset)
670 {
671 struct pipe_draw_indirect_info *indirect = info->indirect;
672 struct radeon_cmdbuf *cs = sctx->gfx_cs;
673 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
674 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
675 uint32_t index_max_size = 0;
676 uint64_t index_va = 0;
677
678 if (info->count_from_stream_output) {
679 struct si_streamout_target *t =
680 (struct si_streamout_target*)info->count_from_stream_output;
681
682 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
683 t->stride_in_dw);
684 si_cp_copy_data(sctx,
685 COPY_DATA_REG, NULL,
686 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
687 COPY_DATA_SRC_MEM, t->buf_filled_size,
688 t->buf_filled_size_offset);
689 }
690
691 /* draw packet */
692 if (index_size) {
693 if (index_size != sctx->last_index_size) {
694 unsigned index_type;
695
696 /* index type */
697 switch (index_size) {
698 case 1:
699 index_type = V_028A7C_VGT_INDEX_8;
700 break;
701 case 2:
702 index_type = V_028A7C_VGT_INDEX_16 |
703 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
704 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
705 break;
706 case 4:
707 index_type = V_028A7C_VGT_INDEX_32 |
708 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
709 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
710 break;
711 default:
712 assert(!"unreachable");
713 return;
714 }
715
716 if (sctx->chip_class >= GFX9) {
717 radeon_set_uconfig_reg_idx(cs, sctx->screen,
718 R_03090C_VGT_INDEX_TYPE, 2,
719 index_type);
720 } else {
721 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
722 radeon_emit(cs, index_type);
723 }
724
725 sctx->last_index_size = index_size;
726 }
727
728 index_max_size = (indexbuf->width0 - index_offset) /
729 index_size;
730 index_va = si_resource(indexbuf)->gpu_address + index_offset;
731
732 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
733 si_resource(indexbuf),
734 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
735 } else {
736 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
737 * so the state must be re-emitted before the next indexed draw.
738 */
739 if (sctx->chip_class >= GFX7)
740 sctx->last_index_size = -1;
741 }
742
743 if (indirect) {
744 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
745
746 assert(indirect_va % 8 == 0);
747
748 si_invalidate_draw_sh_constants(sctx);
749
750 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
751 radeon_emit(cs, 1);
752 radeon_emit(cs, indirect_va);
753 radeon_emit(cs, indirect_va >> 32);
754
755 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
756 si_resource(indirect->buffer),
757 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
758
759 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
760 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
761
762 assert(indirect->offset % 4 == 0);
763
764 if (index_size) {
765 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
766 radeon_emit(cs, index_va);
767 radeon_emit(cs, index_va >> 32);
768
769 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
770 radeon_emit(cs, index_max_size);
771 }
772
773 if (!sctx->screen->has_draw_indirect_multi) {
774 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
775 : PKT3_DRAW_INDIRECT,
776 3, render_cond_bit));
777 radeon_emit(cs, indirect->offset);
778 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
779 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
780 radeon_emit(cs, di_src_sel);
781 } else {
782 uint64_t count_va = 0;
783
784 if (indirect->indirect_draw_count) {
785 struct si_resource *params_buf =
786 si_resource(indirect->indirect_draw_count);
787
788 radeon_add_to_buffer_list(
789 sctx, sctx->gfx_cs, params_buf,
790 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
791
792 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
793 }
794
795 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
796 PKT3_DRAW_INDIRECT_MULTI,
797 8, render_cond_bit));
798 radeon_emit(cs, indirect->offset);
799 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
800 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
801 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
802 S_2C3_DRAW_INDEX_ENABLE(1) |
803 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
804 radeon_emit(cs, indirect->draw_count);
805 radeon_emit(cs, count_va);
806 radeon_emit(cs, count_va >> 32);
807 radeon_emit(cs, indirect->stride);
808 radeon_emit(cs, di_src_sel);
809 }
810 } else {
811 unsigned instance_count = info->instance_count;
812 int base_vertex;
813
814 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
815 sctx->last_instance_count != instance_count) {
816 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
817 radeon_emit(cs, instance_count);
818 sctx->last_instance_count = instance_count;
819 }
820
821 /* Base vertex and start instance. */
822 base_vertex = index_size ? info->index_bias : info->start;
823
824 if (sctx->num_vs_blit_sgprs) {
825 /* Re-emit draw constants after we leave u_blitter. */
826 si_invalidate_draw_sh_constants(sctx);
827
828 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
829 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
830 sctx->num_vs_blit_sgprs);
831 radeon_emit_array(cs, sctx->vs_blit_sh_data,
832 sctx->num_vs_blit_sgprs);
833 } else if (base_vertex != sctx->last_base_vertex ||
834 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
835 info->start_instance != sctx->last_start_instance ||
836 info->drawid != sctx->last_drawid ||
837 sh_base_reg != sctx->last_sh_base_reg) {
838 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
839 radeon_emit(cs, base_vertex);
840 radeon_emit(cs, info->start_instance);
841 radeon_emit(cs, info->drawid);
842
843 sctx->last_base_vertex = base_vertex;
844 sctx->last_start_instance = info->start_instance;
845 sctx->last_drawid = info->drawid;
846 sctx->last_sh_base_reg = sh_base_reg;
847 }
848
849 if (index_size) {
850 index_va += info->start * index_size;
851
852 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
853 radeon_emit(cs, index_max_size);
854 radeon_emit(cs, index_va);
855 radeon_emit(cs, index_va >> 32);
856 radeon_emit(cs, info->count);
857 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
858 } else {
859 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
860 radeon_emit(cs, info->count);
861 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
862 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
863 }
864 }
865 }
866
867 static void si_emit_surface_sync(struct si_context *sctx,
868 unsigned cp_coher_cntl)
869 {
870 struct radeon_cmdbuf *cs = sctx->gfx_cs;
871
872 if (sctx->chip_class >= GFX9 || !sctx->has_graphics) {
873 /* Flush caches and wait for the caches to assert idle. */
874 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
875 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
876 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
877 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
878 radeon_emit(cs, 0); /* CP_COHER_BASE */
879 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
880 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
881 } else {
882 /* ACQUIRE_MEM is only required on a compute ring. */
883 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
884 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
885 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
886 radeon_emit(cs, 0); /* CP_COHER_BASE */
887 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
888 }
889
890 /* ACQUIRE_MEM has an implicit context roll if the current context
891 * is busy. */
892 if (sctx->has_graphics)
893 sctx->context_roll = true;
894 }
895
896 void si_emit_cache_flush(struct si_context *sctx)
897 {
898 struct radeon_cmdbuf *cs = sctx->gfx_cs;
899 uint32_t flags = sctx->flags;
900
901 if (!sctx->has_graphics) {
902 /* Only process compute flags. */
903 flags &= SI_CONTEXT_INV_ICACHE |
904 SI_CONTEXT_INV_SMEM_L1 |
905 SI_CONTEXT_INV_VMEM_L1 |
906 SI_CONTEXT_INV_GLOBAL_L2 |
907 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
908 SI_CONTEXT_INV_L2_METADATA |
909 SI_CONTEXT_CS_PARTIAL_FLUSH;
910 }
911
912 uint32_t cp_coher_cntl = 0;
913 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
914 SI_CONTEXT_FLUSH_AND_INV_DB);
915
916 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
917 sctx->num_cb_cache_flushes++;
918 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
919 sctx->num_db_cache_flushes++;
920
921 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
922 * bit is set. An alternative way is to write SQC_CACHES, but that
923 * doesn't seem to work reliably. Since the bug doesn't affect
924 * correctness (it only does more work than necessary) and
925 * the performance impact is likely negligible, there is no plan
926 * to add a workaround for it.
927 */
928
929 if (flags & SI_CONTEXT_INV_ICACHE)
930 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
931 if (flags & SI_CONTEXT_INV_SMEM_L1)
932 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
933
934 if (sctx->chip_class <= GFX8) {
935 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
936 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
937 S_0085F0_CB0_DEST_BASE_ENA(1) |
938 S_0085F0_CB1_DEST_BASE_ENA(1) |
939 S_0085F0_CB2_DEST_BASE_ENA(1) |
940 S_0085F0_CB3_DEST_BASE_ENA(1) |
941 S_0085F0_CB4_DEST_BASE_ENA(1) |
942 S_0085F0_CB5_DEST_BASE_ENA(1) |
943 S_0085F0_CB6_DEST_BASE_ENA(1) |
944 S_0085F0_CB7_DEST_BASE_ENA(1);
945
946 /* Necessary for DCC */
947 if (sctx->chip_class == GFX8)
948 si_cp_release_mem(sctx, cs,
949 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
950 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
951 EOP_DATA_SEL_DISCARD, NULL,
952 0, 0, SI_NOT_QUERY);
953 }
954 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
955 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
956 S_0085F0_DB_DEST_BASE_ENA(1);
957 }
958
959 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
960 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
961 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
962 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
963 }
964 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
965 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
966 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
967 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
968 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
969 }
970
971 /* Wait for shader engines to go idle.
972 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
973 * for everything including CB/DB cache flushes.
974 */
975 if (!flush_cb_db) {
976 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
977 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
978 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
979 /* Only count explicit shader flushes, not implicit ones
980 * done by SURFACE_SYNC.
981 */
982 sctx->num_vs_flushes++;
983 sctx->num_ps_flushes++;
984 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
985 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
986 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
987 sctx->num_vs_flushes++;
988 }
989 }
990
991 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
992 sctx->compute_is_busy) {
993 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
994 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
995 sctx->num_cs_flushes++;
996 sctx->compute_is_busy = false;
997 }
998
999 /* VGT state synchronization. */
1000 if (flags & SI_CONTEXT_VGT_FLUSH) {
1001 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1002 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1003 }
1004 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1005 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1006 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1007 }
1008
1009 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1010 * wait for idle on GFX9. We have to use a TS event.
1011 */
1012 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1013 uint64_t va;
1014 unsigned tc_flags, cb_db_event;
1015
1016 /* Set the CB/DB flush event. */
1017 switch (flush_cb_db) {
1018 case SI_CONTEXT_FLUSH_AND_INV_CB:
1019 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1020 break;
1021 case SI_CONTEXT_FLUSH_AND_INV_DB:
1022 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1023 break;
1024 default:
1025 /* both CB & DB */
1026 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1027 }
1028
1029 /* These are the only allowed combinations. If you need to
1030 * do multiple operations at once, do them separately.
1031 * All operations that invalidate L2 also seem to invalidate
1032 * metadata. Volatile (VOL) and WC flushes are not listed here.
1033 *
1034 * TC | TC_WB = writeback & invalidate L2 & L1
1035 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1036 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1037 * TC | TC_NC = invalidate L2 for MTYPE == NC
1038 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1039 * TCL1 = invalidate L1
1040 */
1041 tc_flags = 0;
1042
1043 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1044 tc_flags = EVENT_TC_ACTION_ENA |
1045 EVENT_TC_MD_ACTION_ENA;
1046 }
1047
1048 /* Ideally flush TC together with CB/DB. */
1049 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1050 /* Writeback and invalidate everything in L2 & L1. */
1051 tc_flags = EVENT_TC_ACTION_ENA |
1052 EVENT_TC_WB_ACTION_ENA;
1053
1054 /* Clear the flags. */
1055 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1056 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1057 SI_CONTEXT_INV_VMEM_L1);
1058 sctx->num_L2_invalidates++;
1059 }
1060
1061 /* Do the flush (enqueue the event and wait for it). */
1062 va = sctx->wait_mem_scratch->gpu_address;
1063 sctx->wait_mem_number++;
1064
1065 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1066 EOP_DST_SEL_MEM,
1067 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1068 EOP_DATA_SEL_VALUE_32BIT,
1069 sctx->wait_mem_scratch, va,
1070 sctx->wait_mem_number, SI_NOT_QUERY);
1071 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1072 WAIT_REG_MEM_EQUAL);
1073 }
1074
1075 /* Make sure ME is idle (it executes most packets) before continuing.
1076 * This prevents read-after-write hazards between PFP and ME.
1077 */
1078 if (sctx->has_graphics &&
1079 (cp_coher_cntl ||
1080 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1081 SI_CONTEXT_INV_VMEM_L1 |
1082 SI_CONTEXT_INV_GLOBAL_L2 |
1083 SI_CONTEXT_WRITEBACK_GLOBAL_L2)))) {
1084 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1085 radeon_emit(cs, 0);
1086 }
1087
1088 /* GFX6-GFX8 only:
1089 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1090 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1091 *
1092 * cp_coher_cntl should contain all necessary flags except TC flags
1093 * at this point.
1094 *
1095 * GFX6-GFX7 don't support L2 write-back.
1096 */
1097 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1098 (sctx->chip_class <= GFX7 &&
1099 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1100 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1101 * WB must be set on GFX8+ when TC_ACTION is set.
1102 */
1103 si_emit_surface_sync(sctx, cp_coher_cntl |
1104 S_0085F0_TC_ACTION_ENA(1) |
1105 S_0085F0_TCL1_ACTION_ENA(1) |
1106 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1107 cp_coher_cntl = 0;
1108 sctx->num_L2_invalidates++;
1109 } else {
1110 /* L1 invalidation and L2 writeback must be done separately,
1111 * because both operations can't be done together.
1112 */
1113 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1114 /* WB = write-back
1115 * NC = apply to non-coherent MTYPEs
1116 * (i.e. MTYPE <= 1, which is what we use everywhere)
1117 *
1118 * WB doesn't work without NC.
1119 */
1120 si_emit_surface_sync(sctx, cp_coher_cntl |
1121 S_0301F0_TC_WB_ACTION_ENA(1) |
1122 S_0301F0_TC_NC_ACTION_ENA(1));
1123 cp_coher_cntl = 0;
1124 sctx->num_L2_writebacks++;
1125 }
1126 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1127 /* Invalidate per-CU VMEM L1. */
1128 si_emit_surface_sync(sctx, cp_coher_cntl |
1129 S_0085F0_TCL1_ACTION_ENA(1));
1130 cp_coher_cntl = 0;
1131 }
1132 }
1133
1134 /* If TC flushes haven't cleared this... */
1135 if (cp_coher_cntl)
1136 si_emit_surface_sync(sctx, cp_coher_cntl);
1137
1138 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1139 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1140 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1141 EVENT_INDEX(0));
1142 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1143 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1144 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1145 EVENT_INDEX(0));
1146 }
1147
1148 sctx->flags = 0;
1149 }
1150
1151 static void si_get_draw_start_count(struct si_context *sctx,
1152 const struct pipe_draw_info *info,
1153 unsigned *start, unsigned *count)
1154 {
1155 struct pipe_draw_indirect_info *indirect = info->indirect;
1156
1157 if (indirect) {
1158 unsigned indirect_count;
1159 struct pipe_transfer *transfer;
1160 unsigned begin, end;
1161 unsigned map_size;
1162 unsigned *data;
1163
1164 if (indirect->indirect_draw_count) {
1165 data = pipe_buffer_map_range(&sctx->b,
1166 indirect->indirect_draw_count,
1167 indirect->indirect_draw_count_offset,
1168 sizeof(unsigned),
1169 PIPE_TRANSFER_READ, &transfer);
1170
1171 indirect_count = *data;
1172
1173 pipe_buffer_unmap(&sctx->b, transfer);
1174 } else {
1175 indirect_count = indirect->draw_count;
1176 }
1177
1178 if (!indirect_count) {
1179 *start = *count = 0;
1180 return;
1181 }
1182
1183 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1184 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1185 indirect->offset, map_size,
1186 PIPE_TRANSFER_READ, &transfer);
1187
1188 begin = UINT_MAX;
1189 end = 0;
1190
1191 for (unsigned i = 0; i < indirect_count; ++i) {
1192 unsigned count = data[0];
1193 unsigned start = data[2];
1194
1195 if (count > 0) {
1196 begin = MIN2(begin, start);
1197 end = MAX2(end, start + count);
1198 }
1199
1200 data += indirect->stride / sizeof(unsigned);
1201 }
1202
1203 pipe_buffer_unmap(&sctx->b, transfer);
1204
1205 if (begin < end) {
1206 *start = begin;
1207 *count = end - begin;
1208 } else {
1209 *start = *count = 0;
1210 }
1211 } else {
1212 *start = info->start;
1213 *count = info->count;
1214 }
1215 }
1216
1217 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1218 unsigned skip_atom_mask)
1219 {
1220 unsigned num_patches = 0;
1221
1222 si_emit_rasterizer_prim_state(sctx);
1223 if (sctx->tes_shader.cso)
1224 si_emit_derived_tess_state(sctx, info, &num_patches);
1225
1226 /* Emit state atoms. */
1227 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1228 while (mask)
1229 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1230
1231 sctx->dirty_atoms &= skip_atom_mask;
1232
1233 /* Emit states. */
1234 mask = sctx->dirty_states;
1235 while (mask) {
1236 unsigned i = u_bit_scan(&mask);
1237 struct si_pm4_state *state = sctx->queued.array[i];
1238
1239 if (!state || sctx->emitted.array[i] == state)
1240 continue;
1241
1242 si_pm4_emit(sctx, state);
1243 sctx->emitted.array[i] = state;
1244 }
1245 sctx->dirty_states = 0;
1246
1247 /* Emit draw states. */
1248 si_emit_vs_state(sctx, info);
1249 si_emit_draw_registers(sctx, info, num_patches);
1250 }
1251
1252 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1253 {
1254 struct si_context *sctx = (struct si_context *)ctx;
1255 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1256 struct pipe_resource *indexbuf = info->index.resource;
1257 unsigned dirty_tex_counter;
1258 enum pipe_prim_type rast_prim;
1259 unsigned index_size = info->index_size;
1260 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1261
1262 if (likely(!info->indirect)) {
1263 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1264 * no workaround for indirect draws, but we can at least skip
1265 * direct draws.
1266 */
1267 if (unlikely(!info->instance_count))
1268 return;
1269
1270 /* Handle count == 0. */
1271 if (unlikely(!info->count &&
1272 (index_size || !info->count_from_stream_output)))
1273 return;
1274 }
1275
1276 if (unlikely(!sctx->vs_shader.cso ||
1277 !rs ||
1278 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1279 (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
1280 assert(0);
1281 return;
1282 }
1283
1284 /* Recompute and re-emit the texture resource states if needed. */
1285 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1286 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1287 sctx->last_dirty_tex_counter = dirty_tex_counter;
1288 sctx->framebuffer.dirty_cbufs |=
1289 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1290 sctx->framebuffer.dirty_zsbuf = true;
1291 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1292 si_update_all_texture_descriptors(sctx);
1293 }
1294
1295 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1296
1297 /* Set the rasterization primitive type.
1298 *
1299 * This must be done after si_decompress_textures, which can call
1300 * draw_vbo recursively, and before si_update_shaders, which uses
1301 * current_rast_prim for this draw_vbo call. */
1302 if (sctx->gs_shader.cso)
1303 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1304 else if (sctx->tes_shader.cso) {
1305 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1306 rast_prim = PIPE_PRIM_POINTS;
1307 else
1308 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1309 } else
1310 rast_prim = info->mode;
1311
1312 if (rast_prim != sctx->current_rast_prim) {
1313 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1314 util_prim_is_points_or_lines(rast_prim))
1315 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1316
1317 sctx->current_rast_prim = rast_prim;
1318 sctx->do_update_shaders = true;
1319 }
1320
1321 if (sctx->tes_shader.cso &&
1322 sctx->screen->has_ls_vgpr_init_bug) {
1323 /* Determine whether the LS VGPR fix should be applied.
1324 *
1325 * It is only required when num input CPs > num output CPs,
1326 * which cannot happen with the fixed function TCS. We should
1327 * also update this bit when switching from TCS to fixed
1328 * function TCS.
1329 */
1330 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1331 bool ls_vgpr_fix =
1332 tcs &&
1333 info->vertices_per_patch >
1334 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1335
1336 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1337 sctx->ls_vgpr_fix = ls_vgpr_fix;
1338 sctx->do_update_shaders = true;
1339 }
1340 }
1341
1342 if (sctx->gs_shader.cso) {
1343 /* Determine whether the GS triangle strip adjacency fix should
1344 * be applied. Rotate every other triangle if
1345 * - triangle strips with adjacency are fed to the GS and
1346 * - primitive restart is disabled (the rotation doesn't help
1347 * when the restart occurs after an odd number of triangles).
1348 */
1349 bool gs_tri_strip_adj_fix =
1350 !sctx->tes_shader.cso &&
1351 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1352 !info->primitive_restart;
1353
1354 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1355 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1356 sctx->do_update_shaders = true;
1357 }
1358 }
1359
1360 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1361 goto return_cleanup;
1362
1363 if (index_size) {
1364 /* Translate or upload, if needed. */
1365 /* 8-bit indices are supported on GFX8. */
1366 if (sctx->chip_class <= GFX7 && index_size == 1) {
1367 unsigned start, count, start_offset, size, offset;
1368 void *ptr;
1369
1370 si_get_draw_start_count(sctx, info, &start, &count);
1371 start_offset = start * 2;
1372 size = count * 2;
1373
1374 indexbuf = NULL;
1375 u_upload_alloc(ctx->stream_uploader, start_offset,
1376 size,
1377 si_optimal_tcc_alignment(sctx, size),
1378 &offset, &indexbuf, &ptr);
1379 if (!indexbuf)
1380 return;
1381
1382 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1383 index_offset + start,
1384 count, ptr);
1385
1386 /* info->start will be added by the drawing code */
1387 index_offset = offset - start_offset;
1388 index_size = 2;
1389 } else if (info->has_user_indices) {
1390 unsigned start_offset;
1391
1392 assert(!info->indirect);
1393 start_offset = info->start * index_size;
1394
1395 indexbuf = NULL;
1396 u_upload_data(ctx->stream_uploader, start_offset,
1397 info->count * index_size,
1398 sctx->screen->info.tcc_cache_line_size,
1399 (char*)info->index.user + start_offset,
1400 &index_offset, &indexbuf);
1401 if (!indexbuf)
1402 return;
1403
1404 /* info->start will be added by the drawing code */
1405 index_offset -= start_offset;
1406 } else if (sctx->chip_class <= GFX7 &&
1407 si_resource(indexbuf)->TC_L2_dirty) {
1408 /* GFX8 reads index buffers through TC L2, so it doesn't
1409 * need this. */
1410 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1411 si_resource(indexbuf)->TC_L2_dirty = false;
1412 }
1413 }
1414
1415 if (info->indirect) {
1416 struct pipe_draw_indirect_info *indirect = info->indirect;
1417
1418 /* Add the buffer size for memory checking in need_cs_space. */
1419 si_context_add_resource_size(sctx, indirect->buffer);
1420
1421 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1422 if (sctx->chip_class <= GFX8) {
1423 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1424 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1425 si_resource(indirect->buffer)->TC_L2_dirty = false;
1426 }
1427
1428 if (indirect->indirect_draw_count &&
1429 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1430 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1431 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1432 }
1433 }
1434 }
1435
1436 si_need_gfx_cs_space(sctx);
1437
1438 if (sctx->bo_list_add_all_gfx_resources)
1439 si_gfx_resources_add_all_to_bo_list(sctx);
1440
1441 /* Since we've called si_context_add_resource_size for vertex buffers,
1442 * this must be called after si_need_cs_space, because we must let
1443 * need_cs_space flush before we add buffers to the buffer list.
1444 */
1445 if (!si_upload_vertex_buffer_descriptors(sctx))
1446 goto return_cleanup;
1447
1448 /* Vega10/Raven scissor bug workaround. When any context register is
1449 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1450 * registers must be written too.
1451 */
1452 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1453 unsigned masked_atoms = 0;
1454
1455 if (has_gfx9_scissor_bug) {
1456 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
1457
1458 if (info->count_from_stream_output ||
1459 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1460 sctx->dirty_states & si_states_that_always_roll_context())
1461 sctx->context_roll = true;
1462 }
1463
1464 /* Use optimal packet order based on whether we need to sync the pipeline. */
1465 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1466 SI_CONTEXT_FLUSH_AND_INV_DB |
1467 SI_CONTEXT_PS_PARTIAL_FLUSH |
1468 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1469 /* If we have to wait for idle, set all states first, so that all
1470 * SET packets are processed in parallel with previous draw calls.
1471 * Then draw and prefetch at the end. This ensures that the time
1472 * the CUs are idle is very short.
1473 */
1474 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1475 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1476
1477 if (!si_upload_graphics_shader_descriptors(sctx))
1478 goto return_cleanup;
1479
1480 /* Emit all states except possibly render condition. */
1481 si_emit_all_states(sctx, info, masked_atoms);
1482 si_emit_cache_flush(sctx);
1483 /* <-- CUs are idle here. */
1484
1485 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1486 sctx->atoms.s.render_cond.emit(sctx);
1487
1488 if (has_gfx9_scissor_bug &&
1489 (sctx->context_roll ||
1490 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1491 sctx->atoms.s.scissors.emit(sctx);
1492
1493 sctx->dirty_atoms = 0;
1494
1495 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1496 /* <-- CUs are busy here. */
1497
1498 /* Start prefetches after the draw has been started. Both will run
1499 * in parallel, but starting the draw first is more important.
1500 */
1501 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1502 cik_emit_prefetch_L2(sctx, false);
1503 } else {
1504 /* If we don't wait for idle, start prefetches first, then set
1505 * states, and draw at the end.
1506 */
1507 if (sctx->flags)
1508 si_emit_cache_flush(sctx);
1509
1510 /* Only prefetch the API VS and VBO descriptors. */
1511 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1512 cik_emit_prefetch_L2(sctx, true);
1513
1514 if (!si_upload_graphics_shader_descriptors(sctx))
1515 return;
1516
1517 si_emit_all_states(sctx, info, masked_atoms);
1518
1519 if (has_gfx9_scissor_bug &&
1520 (sctx->context_roll ||
1521 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1522 sctx->atoms.s.scissors.emit(sctx);
1523
1524 sctx->dirty_atoms = 0;
1525
1526 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1527
1528 /* Prefetch the remaining shaders after the draw has been
1529 * started. */
1530 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1531 cik_emit_prefetch_L2(sctx, false);
1532 }
1533
1534 /* Clear the context roll flag after the draw call. */
1535 sctx->context_roll = false;
1536
1537 if (unlikely(sctx->current_saved_cs)) {
1538 si_trace_emit(sctx);
1539 si_log_draw_state(sctx, sctx->log);
1540 }
1541
1542 /* Workaround for a VGT hang when streamout is enabled.
1543 * It must be done after drawing. */
1544 if ((sctx->family == CHIP_HAWAII ||
1545 sctx->family == CHIP_TONGA ||
1546 sctx->family == CHIP_FIJI) &&
1547 si_get_strmout_en(sctx)) {
1548 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1549 }
1550
1551 if (unlikely(sctx->decompression_enabled)) {
1552 sctx->num_decompress_calls++;
1553 } else {
1554 sctx->num_draw_calls++;
1555 if (sctx->framebuffer.state.nr_cbufs > 1)
1556 sctx->num_mrt_draw_calls++;
1557 if (info->primitive_restart)
1558 sctx->num_prim_restart_calls++;
1559 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1560 sctx->num_spill_draw_calls++;
1561 }
1562
1563 return_cleanup:
1564 if (index_size && indexbuf != info->index.resource)
1565 pipe_resource_reference(&indexbuf, NULL);
1566 }
1567
1568 static void
1569 si_draw_rectangle(struct blitter_context *blitter,
1570 void *vertex_elements_cso,
1571 blitter_get_vs_func get_vs,
1572 int x1, int y1, int x2, int y2,
1573 float depth, unsigned num_instances,
1574 enum blitter_attrib_type type,
1575 const union blitter_attrib *attrib)
1576 {
1577 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1578 struct si_context *sctx = (struct si_context*)pipe;
1579
1580 /* Pack position coordinates as signed int16. */
1581 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1582 ((uint32_t)(y1 & 0xffff) << 16);
1583 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1584 ((uint32_t)(y2 & 0xffff) << 16);
1585 sctx->vs_blit_sh_data[2] = fui(depth);
1586
1587 switch (type) {
1588 case UTIL_BLITTER_ATTRIB_COLOR:
1589 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1590 sizeof(float)*4);
1591 break;
1592 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1593 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1594 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1595 sizeof(attrib->texcoord));
1596 break;
1597 case UTIL_BLITTER_ATTRIB_NONE:;
1598 }
1599
1600 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
1601
1602 struct pipe_draw_info info = {};
1603 info.mode = SI_PRIM_RECTANGLE_LIST;
1604 info.count = 3;
1605 info.instance_count = num_instances;
1606
1607 /* Don't set per-stage shader pointers for VS. */
1608 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1609 sctx->vertex_buffer_pointer_dirty = false;
1610
1611 si_draw_vbo(pipe, &info);
1612 }
1613
1614 void si_trace_emit(struct si_context *sctx)
1615 {
1616 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1617 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1618
1619 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
1620 0, 4, V_370_MEM, V_370_ME, &trace_id);
1621
1622 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1623 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1624
1625 if (sctx->log)
1626 u_log_flush(sctx->log);
1627 }
1628
1629 void si_init_draw_functions(struct si_context *sctx)
1630 {
1631 sctx->b.draw_vbo = si_draw_vbo;
1632
1633 sctx->blitter->draw_rectangle = si_draw_rectangle;
1634
1635 si_init_ia_multi_vgt_param_table(sctx);
1636 }