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radeonsi: properly compute an LS-HS thread group size limit
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static bool si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_winsys_cs *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return false;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = num_tcs_inputs * 16;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While CIK can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance. The
169 * specific value is taken from the proprietary driver.
170 */
171 *num_patches = MIN2(*num_patches, 40);
172
173 if (sctx->chip_class == SI) {
174 /* SI bug workaround, related to power management. Limit LS-HS
175 * threadgroups to only one wave.
176 */
177 unsigned one_wave = 64 / max_verts_per_patch;
178 *num_patches = MIN2(*num_patches, one_wave);
179 }
180
181 /* The VGT HS block increments the patch ID unconditionally
182 * within a single threadgroup. This results in incorrect
183 * patch IDs when instanced draws are used.
184 *
185 * The intended solution is to restrict threadgroups to
186 * a single instance by setting SWITCH_ON_EOI, which
187 * should cause IA to split instances up. However, this
188 * doesn't work correctly on SI when there is no other
189 * SE to switch to.
190 */
191 if (has_primid_instancing_bug && tess_uses_primid)
192 *num_patches = 1;
193
194 sctx->last_num_patches = *num_patches;
195
196 output_patch0_offset = input_patch_size * *num_patches;
197 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
198
199 /* Compute userdata SGPRs. */
200 assert(((input_vertex_size / 4) & ~0xff) == 0);
201 assert(((output_vertex_size / 4) & ~0xff) == 0);
202 assert(((input_patch_size / 4) & ~0x1fff) == 0);
203 assert(((output_patch_size / 4) & ~0x1fff) == 0);
204 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
205 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
206 assert(num_tcs_input_cp <= 32);
207 assert(num_tcs_output_cp <= 32);
208
209 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
210 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
211
212 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
213 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
214 tcs_out_layout = (output_patch_size / 4) |
215 (num_tcs_input_cp << 13) |
216 ring_va;
217 tcs_out_offsets = (output_patch0_offset / 16) |
218 ((perpatch_output_offset / 16) << 16);
219 offchip_layout = *num_patches |
220 (num_tcs_output_cp << 6) |
221 (pervertex_output_patch_size * *num_patches << 12);
222
223 /* Compute the LDS size. */
224 lds_size = output_patch0_offset + output_patch_size * *num_patches;
225
226 if (sctx->chip_class >= CIK) {
227 assert(lds_size <= 65536);
228 lds_size = align(lds_size, 512) / 512;
229 } else {
230 assert(lds_size <= 32768);
231 lds_size = align(lds_size, 256) / 256;
232 }
233
234 /* Set SI_SGPR_VS_STATE_BITS. */
235 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
236 C_VS_STATE_LS_OUT_VERTEX_SIZE;
237 sctx->current_vs_state |= tcs_in_layout;
238
239 if (sctx->chip_class >= GFX9) {
240 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
241 S_00B42C_LDS_SIZE(lds_size);
242
243 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
244
245 /* Set userdata SGPRs for merged LS-HS. */
246 radeon_set_sh_reg_seq(cs,
247 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
248 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
249 radeon_emit(cs, offchip_layout);
250 radeon_emit(cs, tcs_out_offsets);
251 radeon_emit(cs, tcs_out_layout);
252 } else {
253 unsigned ls_rsrc2 = ls_current->config.rsrc2;
254
255 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
256 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
257
258 /* Due to a hw bug, RSRC2_LS must be written twice with another
259 * LS register written in between. */
260 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
261 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
262 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
263 radeon_emit(cs, ls_current->config.rsrc1);
264 radeon_emit(cs, ls_rsrc2);
265
266 /* Set userdata SGPRs for TCS. */
267 radeon_set_sh_reg_seq(cs,
268 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
269 radeon_emit(cs, offchip_layout);
270 radeon_emit(cs, tcs_out_offsets);
271 radeon_emit(cs, tcs_out_layout);
272 radeon_emit(cs, tcs_in_layout);
273 }
274
275 /* Set userdata SGPRs for TES. */
276 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
277 radeon_emit(cs, offchip_layout);
278 radeon_emit(cs, ring_va);
279
280 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
281 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
282 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
283
284 if (sctx->last_ls_hs_config != ls_hs_config) {
285 if (sctx->chip_class >= CIK) {
286 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
287 ls_hs_config);
288 } else {
289 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
290 ls_hs_config);
291 }
292 sctx->last_ls_hs_config = ls_hs_config;
293 return true; /* true if the context rolls */
294 }
295 return false;
296 }
297
298 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
299 {
300 switch (info->mode) {
301 case PIPE_PRIM_PATCHES:
302 return info->count / info->vertices_per_patch;
303 case SI_PRIM_RECTANGLE_LIST:
304 return info->count / 3;
305 default:
306 return u_prims_for_vertices(info->mode, info->count);
307 }
308 }
309
310 static unsigned
311 si_get_init_multi_vgt_param(struct si_screen *sscreen,
312 union si_vgt_param_key *key)
313 {
314 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
315 unsigned max_primgroup_in_wave = 2;
316
317 /* SWITCH_ON_EOP(0) is always preferable. */
318 bool wd_switch_on_eop = false;
319 bool ia_switch_on_eop = false;
320 bool ia_switch_on_eoi = false;
321 bool partial_vs_wave = false;
322 bool partial_es_wave = false;
323
324 if (key->u.uses_tess) {
325 /* SWITCH_ON_EOI must be set if PrimID is used. */
326 if (key->u.tess_uses_prim_id)
327 ia_switch_on_eoi = true;
328
329 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
330 if ((sscreen->info.family == CHIP_TAHITI ||
331 sscreen->info.family == CHIP_PITCAIRN ||
332 sscreen->info.family == CHIP_BONAIRE) &&
333 key->u.uses_gs)
334 partial_vs_wave = true;
335
336 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
337 if (sscreen->has_distributed_tess) {
338 if (key->u.uses_gs) {
339 if (sscreen->info.chip_class <= VI)
340 partial_es_wave = true;
341
342 /* GPU hang workaround. */
343 if (sscreen->info.family == CHIP_TONGA ||
344 sscreen->info.family == CHIP_FIJI ||
345 sscreen->info.family == CHIP_POLARIS10 ||
346 sscreen->info.family == CHIP_POLARIS11 ||
347 sscreen->info.family == CHIP_POLARIS12 ||
348 sscreen->info.family == CHIP_VEGAM)
349 partial_vs_wave = true;
350 } else {
351 partial_vs_wave = true;
352 }
353 }
354 }
355
356 /* This is a hardware requirement. */
357 if (key->u.line_stipple_enabled ||
358 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
359 ia_switch_on_eop = true;
360 wd_switch_on_eop = true;
361 }
362
363 if (sscreen->info.chip_class >= CIK) {
364 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
365 * 4 shader engines. Set 1 to pass the assertion below.
366 * The other cases are hardware requirements.
367 *
368 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
369 * for points, line strips, and tri strips.
370 */
371 if (sscreen->info.max_se < 4 ||
372 key->u.prim == PIPE_PRIM_POLYGON ||
373 key->u.prim == PIPE_PRIM_LINE_LOOP ||
374 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
375 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
376 (key->u.primitive_restart &&
377 (sscreen->info.family < CHIP_POLARIS10 ||
378 (key->u.prim != PIPE_PRIM_POINTS &&
379 key->u.prim != PIPE_PRIM_LINE_STRIP &&
380 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
381 key->u.count_from_stream_output)
382 wd_switch_on_eop = true;
383
384 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
385 * We don't know that for indirect drawing, so treat it as
386 * always problematic. */
387 if (sscreen->info.family == CHIP_HAWAII &&
388 key->u.uses_instancing)
389 wd_switch_on_eop = true;
390
391 /* Performance recommendation for 4 SE Gfx7-8 parts if
392 * instances are smaller than a primgroup.
393 * Assume indirect draws always use small instances.
394 * This is needed for good VS wave utilization.
395 */
396 if (sscreen->info.chip_class <= VI &&
397 sscreen->info.max_se == 4 &&
398 key->u.multi_instances_smaller_than_primgroup)
399 wd_switch_on_eop = true;
400
401 /* Required on CIK and later. */
402 if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
403 ia_switch_on_eoi = true;
404
405 /* Required by Hawaii and, for some special cases, by VI. */
406 if (ia_switch_on_eoi &&
407 (sscreen->info.family == CHIP_HAWAII ||
408 (sscreen->info.chip_class == VI &&
409 (key->u.uses_gs || max_primgroup_in_wave != 2))))
410 partial_vs_wave = true;
411
412 /* Instancing bug on Bonaire. */
413 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
414 key->u.uses_instancing)
415 partial_vs_wave = true;
416
417 /* If the WD switch is false, the IA switch must be false too. */
418 assert(wd_switch_on_eop || !ia_switch_on_eop);
419 }
420
421 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
422 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
423 partial_es_wave = true;
424
425 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
426 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
427 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
428 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
429 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
430 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
431 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
432 max_primgroup_in_wave : 0) |
433 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
434 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
435 }
436
437 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
438 {
439 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
440 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
441 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
442 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
443 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
444 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
445 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
446 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
447 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
448 union si_vgt_param_key key;
449
450 key.index = 0;
451 key.u.prim = prim;
452 key.u.uses_instancing = uses_instancing;
453 key.u.multi_instances_smaller_than_primgroup = multi_instances;
454 key.u.primitive_restart = primitive_restart;
455 key.u.count_from_stream_output = count_from_so;
456 key.u.line_stipple_enabled = line_stipple;
457 key.u.uses_tess = uses_tess;
458 key.u.tess_uses_prim_id = tess_uses_primid;
459 key.u.uses_gs = uses_gs;
460
461 sctx->ia_multi_vgt_param[key.index] =
462 si_get_init_multi_vgt_param(sctx->screen, &key);
463 }
464 }
465
466 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
467 const struct pipe_draw_info *info,
468 unsigned num_patches)
469 {
470 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
471 unsigned primgroup_size;
472 unsigned ia_multi_vgt_param;
473
474 if (sctx->tes_shader.cso) {
475 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
476 } else if (sctx->gs_shader.cso) {
477 primgroup_size = 64; /* recommended with a GS */
478 } else {
479 primgroup_size = 128; /* recommended without a GS and tess */
480 }
481
482 key.u.prim = info->mode;
483 key.u.uses_instancing = info->indirect || info->instance_count > 1;
484 key.u.multi_instances_smaller_than_primgroup =
485 info->indirect ||
486 (info->instance_count > 1 &&
487 (info->count_from_stream_output ||
488 si_num_prims_for_vertices(info) < primgroup_size));
489 key.u.primitive_restart = info->primitive_restart;
490 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
491
492 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
493 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
494
495 if (sctx->gs_shader.cso) {
496 /* GS requirement. */
497 if (sctx->chip_class <= VI &&
498 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
499 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
500
501 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
502 * The hw doc says all multi-SE chips are affected, but Vulkan
503 * only applies it to Hawaii. Do what Vulkan does.
504 */
505 if (sctx->family == CHIP_HAWAII &&
506 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
507 (info->indirect ||
508 (info->instance_count > 1 &&
509 (info->count_from_stream_output ||
510 si_num_prims_for_vertices(info) <= 1))))
511 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
512 }
513
514 return ia_multi_vgt_param;
515 }
516
517 /* rast_prim is the primitive type after GS. */
518 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
519 {
520 struct radeon_winsys_cs *cs = sctx->gfx_cs;
521 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
522 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
523
524 /* Skip this if not rendering lines. */
525 if (!util_prim_is_lines(rast_prim))
526 return false;
527
528 if (rast_prim == sctx->last_rast_prim &&
529 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
530 return false;
531
532 /* For lines, reset the stipple pattern at each primitive. Otherwise,
533 * reset the stipple pattern at each packet (line strips, line loops).
534 */
535 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
536 rs->pa_sc_line_stipple |
537 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
538
539 sctx->last_rast_prim = rast_prim;
540 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
541 return true; /* true if the context rolls */
542 }
543
544 static void si_emit_vs_state(struct si_context *sctx,
545 const struct pipe_draw_info *info)
546 {
547 sctx->current_vs_state &= C_VS_STATE_INDEXED;
548 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
549
550 if (sctx->num_vs_blit_sgprs) {
551 /* Re-emit the state after we leave u_blitter. */
552 sctx->last_vs_state = ~0;
553 return;
554 }
555
556 if (sctx->current_vs_state != sctx->last_vs_state) {
557 struct radeon_winsys_cs *cs = sctx->gfx_cs;
558
559 radeon_set_sh_reg(cs,
560 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
561 SI_SGPR_VS_STATE_BITS * 4,
562 sctx->current_vs_state);
563
564 sctx->last_vs_state = sctx->current_vs_state;
565 }
566 }
567
568 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
569 const struct pipe_draw_info *info)
570 {
571 return info->primitive_restart &&
572 (info->restart_index != sctx->last_restart_index ||
573 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
574 }
575
576 static void si_emit_draw_registers(struct si_context *sctx,
577 const struct pipe_draw_info *info,
578 unsigned num_patches)
579 {
580 struct radeon_winsys_cs *cs = sctx->gfx_cs;
581 unsigned prim = si_conv_pipe_prim(info->mode);
582 unsigned ia_multi_vgt_param;
583
584 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
585
586 /* Draw state. */
587 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
588 if (sctx->chip_class >= GFX9)
589 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
590 else if (sctx->chip_class >= CIK)
591 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
592 else
593 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
594
595 sctx->last_multi_vgt_param = ia_multi_vgt_param;
596 }
597 if (prim != sctx->last_prim) {
598 if (sctx->chip_class >= CIK)
599 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
600 else
601 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
602
603 sctx->last_prim = prim;
604 }
605
606 /* Primitive restart. */
607 if (info->primitive_restart != sctx->last_primitive_restart_en) {
608 if (sctx->chip_class >= GFX9)
609 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
610 info->primitive_restart);
611 else
612 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
613 info->primitive_restart);
614
615 sctx->last_primitive_restart_en = info->primitive_restart;
616
617 }
618 if (si_prim_restart_index_changed(sctx, info)) {
619 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
620 info->restart_index);
621 sctx->last_restart_index = info->restart_index;
622 }
623 }
624
625 static void si_emit_draw_packets(struct si_context *sctx,
626 const struct pipe_draw_info *info,
627 struct pipe_resource *indexbuf,
628 unsigned index_size,
629 unsigned index_offset)
630 {
631 struct pipe_draw_indirect_info *indirect = info->indirect;
632 struct radeon_winsys_cs *cs = sctx->gfx_cs;
633 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
634 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
635 uint32_t index_max_size = 0;
636 uint64_t index_va = 0;
637
638 if (info->count_from_stream_output) {
639 struct si_streamout_target *t =
640 (struct si_streamout_target*)info->count_from_stream_output;
641 uint64_t va = t->buf_filled_size->gpu_address +
642 t->buf_filled_size_offset;
643
644 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
645 t->stride_in_dw);
646
647 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
648 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
649 COPY_DATA_DST_SEL(COPY_DATA_REG) |
650 COPY_DATA_WR_CONFIRM);
651 radeon_emit(cs, va); /* src address lo */
652 radeon_emit(cs, va >> 32); /* src address hi */
653 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
654 radeon_emit(cs, 0); /* unused */
655
656 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
657 t->buf_filled_size, RADEON_USAGE_READ,
658 RADEON_PRIO_SO_FILLED_SIZE);
659 }
660
661 /* draw packet */
662 if (index_size) {
663 if (index_size != sctx->last_index_size) {
664 unsigned index_type;
665
666 /* index type */
667 switch (index_size) {
668 case 1:
669 index_type = V_028A7C_VGT_INDEX_8;
670 break;
671 case 2:
672 index_type = V_028A7C_VGT_INDEX_16 |
673 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
674 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
675 break;
676 case 4:
677 index_type = V_028A7C_VGT_INDEX_32 |
678 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
679 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
680 break;
681 default:
682 assert(!"unreachable");
683 return;
684 }
685
686 if (sctx->chip_class >= GFX9) {
687 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
688 2, index_type);
689 } else {
690 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
691 radeon_emit(cs, index_type);
692 }
693
694 sctx->last_index_size = index_size;
695 }
696
697 index_max_size = (indexbuf->width0 - index_offset) /
698 index_size;
699 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
700
701 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
702 r600_resource(indexbuf),
703 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
704 } else {
705 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
706 * so the state must be re-emitted before the next indexed draw.
707 */
708 if (sctx->chip_class >= CIK)
709 sctx->last_index_size = -1;
710 }
711
712 if (indirect) {
713 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
714
715 assert(indirect_va % 8 == 0);
716
717 si_invalidate_draw_sh_constants(sctx);
718
719 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
720 radeon_emit(cs, 1);
721 radeon_emit(cs, indirect_va);
722 radeon_emit(cs, indirect_va >> 32);
723
724 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
725 r600_resource(indirect->buffer),
726 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
727
728 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
729 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
730
731 assert(indirect->offset % 4 == 0);
732
733 if (index_size) {
734 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
735 radeon_emit(cs, index_va);
736 radeon_emit(cs, index_va >> 32);
737
738 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
739 radeon_emit(cs, index_max_size);
740 }
741
742 if (!sctx->screen->has_draw_indirect_multi) {
743 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
744 : PKT3_DRAW_INDIRECT,
745 3, render_cond_bit));
746 radeon_emit(cs, indirect->offset);
747 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
748 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
749 radeon_emit(cs, di_src_sel);
750 } else {
751 uint64_t count_va = 0;
752
753 if (indirect->indirect_draw_count) {
754 struct r600_resource *params_buf =
755 r600_resource(indirect->indirect_draw_count);
756
757 radeon_add_to_buffer_list(
758 sctx, sctx->gfx_cs, params_buf,
759 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
760
761 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
762 }
763
764 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
765 PKT3_DRAW_INDIRECT_MULTI,
766 8, render_cond_bit));
767 radeon_emit(cs, indirect->offset);
768 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
769 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
770 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
771 S_2C3_DRAW_INDEX_ENABLE(1) |
772 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
773 radeon_emit(cs, indirect->draw_count);
774 radeon_emit(cs, count_va);
775 radeon_emit(cs, count_va >> 32);
776 radeon_emit(cs, indirect->stride);
777 radeon_emit(cs, di_src_sel);
778 }
779 } else {
780 int base_vertex;
781
782 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
783 radeon_emit(cs, info->instance_count);
784
785 /* Base vertex and start instance. */
786 base_vertex = index_size ? info->index_bias : info->start;
787
788 if (sctx->num_vs_blit_sgprs) {
789 /* Re-emit draw constants after we leave u_blitter. */
790 si_invalidate_draw_sh_constants(sctx);
791
792 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
793 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
794 sctx->num_vs_blit_sgprs);
795 radeon_emit_array(cs, sctx->vs_blit_sh_data,
796 sctx->num_vs_blit_sgprs);
797 } else if (base_vertex != sctx->last_base_vertex ||
798 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
799 info->start_instance != sctx->last_start_instance ||
800 info->drawid != sctx->last_drawid ||
801 sh_base_reg != sctx->last_sh_base_reg) {
802 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
803 radeon_emit(cs, base_vertex);
804 radeon_emit(cs, info->start_instance);
805 radeon_emit(cs, info->drawid);
806
807 sctx->last_base_vertex = base_vertex;
808 sctx->last_start_instance = info->start_instance;
809 sctx->last_drawid = info->drawid;
810 sctx->last_sh_base_reg = sh_base_reg;
811 }
812
813 if (index_size) {
814 index_va += info->start * index_size;
815
816 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
817 radeon_emit(cs, index_max_size);
818 radeon_emit(cs, index_va);
819 radeon_emit(cs, index_va >> 32);
820 radeon_emit(cs, info->count);
821 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
822 } else {
823 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
824 radeon_emit(cs, info->count);
825 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
826 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
827 }
828 }
829 }
830
831 static void si_emit_surface_sync(struct si_context *sctx,
832 unsigned cp_coher_cntl)
833 {
834 struct radeon_winsys_cs *cs = sctx->gfx_cs;
835
836 if (sctx->chip_class >= GFX9) {
837 /* Flush caches and wait for the caches to assert idle. */
838 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
839 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
840 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
841 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
842 radeon_emit(cs, 0); /* CP_COHER_BASE */
843 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
844 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
845 } else {
846 /* ACQUIRE_MEM is only required on a compute ring. */
847 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
848 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
849 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
850 radeon_emit(cs, 0); /* CP_COHER_BASE */
851 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
852 }
853 }
854
855 void si_emit_cache_flush(struct si_context *sctx)
856 {
857 struct radeon_winsys_cs *cs = sctx->gfx_cs;
858 uint32_t flags = sctx->flags;
859 uint32_t cp_coher_cntl = 0;
860 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
861 SI_CONTEXT_FLUSH_AND_INV_DB);
862
863 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
864 sctx->num_cb_cache_flushes++;
865 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
866 sctx->num_db_cache_flushes++;
867
868 /* SI has a bug that it always flushes ICACHE and KCACHE if either
869 * bit is set. An alternative way is to write SQC_CACHES, but that
870 * doesn't seem to work reliably. Since the bug doesn't affect
871 * correctness (it only does more work than necessary) and
872 * the performance impact is likely negligible, there is no plan
873 * to add a workaround for it.
874 */
875
876 if (flags & SI_CONTEXT_INV_ICACHE)
877 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
878 if (flags & SI_CONTEXT_INV_SMEM_L1)
879 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
880
881 if (sctx->chip_class <= VI) {
882 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
883 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
884 S_0085F0_CB0_DEST_BASE_ENA(1) |
885 S_0085F0_CB1_DEST_BASE_ENA(1) |
886 S_0085F0_CB2_DEST_BASE_ENA(1) |
887 S_0085F0_CB3_DEST_BASE_ENA(1) |
888 S_0085F0_CB4_DEST_BASE_ENA(1) |
889 S_0085F0_CB5_DEST_BASE_ENA(1) |
890 S_0085F0_CB6_DEST_BASE_ENA(1) |
891 S_0085F0_CB7_DEST_BASE_ENA(1);
892
893 /* Necessary for DCC */
894 if (sctx->chip_class == VI)
895 si_gfx_write_event_eop(sctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
896 0, EOP_DATA_SEL_DISCARD, NULL,
897 0, 0, SI_NOT_QUERY);
898 }
899 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
900 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
901 S_0085F0_DB_DEST_BASE_ENA(1);
902 }
903
904 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
905 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
906 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
907 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
908 }
909 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
910 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
911 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
912 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
913 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
914 }
915
916 /* Wait for shader engines to go idle.
917 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
918 * for everything including CB/DB cache flushes.
919 */
920 if (!flush_cb_db) {
921 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
922 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
923 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
924 /* Only count explicit shader flushes, not implicit ones
925 * done by SURFACE_SYNC.
926 */
927 sctx->num_vs_flushes++;
928 sctx->num_ps_flushes++;
929 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
930 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
931 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
932 sctx->num_vs_flushes++;
933 }
934 }
935
936 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
937 sctx->compute_is_busy) {
938 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
939 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
940 sctx->num_cs_flushes++;
941 sctx->compute_is_busy = false;
942 }
943
944 /* VGT state synchronization. */
945 if (flags & SI_CONTEXT_VGT_FLUSH) {
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
947 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
948 }
949 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
950 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
951 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
952 }
953
954 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
955 * wait for idle on GFX9. We have to use a TS event.
956 */
957 if (sctx->chip_class >= GFX9 && flush_cb_db) {
958 uint64_t va;
959 unsigned tc_flags, cb_db_event;
960
961 /* Set the CB/DB flush event. */
962 switch (flush_cb_db) {
963 case SI_CONTEXT_FLUSH_AND_INV_CB:
964 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
965 break;
966 case SI_CONTEXT_FLUSH_AND_INV_DB:
967 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
968 break;
969 default:
970 /* both CB & DB */
971 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
972 }
973
974 /* These are the only allowed combinations. If you need to
975 * do multiple operations at once, do them separately.
976 * All operations that invalidate L2 also seem to invalidate
977 * metadata. Volatile (VOL) and WC flushes are not listed here.
978 *
979 * TC | TC_WB = writeback & invalidate L2 & L1
980 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
981 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
982 * TC | TC_NC = invalidate L2 for MTYPE == NC
983 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
984 * TCL1 = invalidate L1
985 */
986 tc_flags = 0;
987
988 if (flags & SI_CONTEXT_INV_L2_METADATA) {
989 tc_flags = EVENT_TC_ACTION_ENA |
990 EVENT_TC_MD_ACTION_ENA;
991 }
992
993 /* Ideally flush TC together with CB/DB. */
994 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
995 /* Writeback and invalidate everything in L2 & L1. */
996 tc_flags = EVENT_TC_ACTION_ENA |
997 EVENT_TC_WB_ACTION_ENA;
998
999 /* Clear the flags. */
1000 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1001 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1002 SI_CONTEXT_INV_VMEM_L1);
1003 sctx->num_L2_invalidates++;
1004 }
1005
1006 /* Do the flush (enqueue the event and wait for it). */
1007 va = sctx->wait_mem_scratch->gpu_address;
1008 sctx->wait_mem_number++;
1009
1010 si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
1011 EOP_DATA_SEL_VALUE_32BIT,
1012 sctx->wait_mem_scratch, va,
1013 sctx->wait_mem_number, SI_NOT_QUERY);
1014 si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
1015 }
1016
1017 /* Make sure ME is idle (it executes most packets) before continuing.
1018 * This prevents read-after-write hazards between PFP and ME.
1019 */
1020 if (cp_coher_cntl ||
1021 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1022 SI_CONTEXT_INV_VMEM_L1 |
1023 SI_CONTEXT_INV_GLOBAL_L2 |
1024 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1025 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1026 radeon_emit(cs, 0);
1027 }
1028
1029 /* SI-CI-VI only:
1030 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1031 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1032 *
1033 * cp_coher_cntl should contain all necessary flags except TC flags
1034 * at this point.
1035 *
1036 * SI-CIK don't support L2 write-back.
1037 */
1038 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1039 (sctx->chip_class <= CIK &&
1040 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1041 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1042 * WB must be set on VI+ when TC_ACTION is set.
1043 */
1044 si_emit_surface_sync(sctx, cp_coher_cntl |
1045 S_0085F0_TC_ACTION_ENA(1) |
1046 S_0085F0_TCL1_ACTION_ENA(1) |
1047 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1048 cp_coher_cntl = 0;
1049 sctx->num_L2_invalidates++;
1050 } else {
1051 /* L1 invalidation and L2 writeback must be done separately,
1052 * because both operations can't be done together.
1053 */
1054 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1055 /* WB = write-back
1056 * NC = apply to non-coherent MTYPEs
1057 * (i.e. MTYPE <= 1, which is what we use everywhere)
1058 *
1059 * WB doesn't work without NC.
1060 */
1061 si_emit_surface_sync(sctx, cp_coher_cntl |
1062 S_0301F0_TC_WB_ACTION_ENA(1) |
1063 S_0301F0_TC_NC_ACTION_ENA(1));
1064 cp_coher_cntl = 0;
1065 sctx->num_L2_writebacks++;
1066 }
1067 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1068 /* Invalidate per-CU VMEM L1. */
1069 si_emit_surface_sync(sctx, cp_coher_cntl |
1070 S_0085F0_TCL1_ACTION_ENA(1));
1071 cp_coher_cntl = 0;
1072 }
1073 }
1074
1075 /* If TC flushes haven't cleared this... */
1076 if (cp_coher_cntl)
1077 si_emit_surface_sync(sctx, cp_coher_cntl);
1078
1079 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1080 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1081 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1082 EVENT_INDEX(0));
1083 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1084 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1085 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1086 EVENT_INDEX(0));
1087 }
1088
1089 sctx->flags = 0;
1090 }
1091
1092 static void si_get_draw_start_count(struct si_context *sctx,
1093 const struct pipe_draw_info *info,
1094 unsigned *start, unsigned *count)
1095 {
1096 struct pipe_draw_indirect_info *indirect = info->indirect;
1097
1098 if (indirect) {
1099 unsigned indirect_count;
1100 struct pipe_transfer *transfer;
1101 unsigned begin, end;
1102 unsigned map_size;
1103 unsigned *data;
1104
1105 if (indirect->indirect_draw_count) {
1106 data = pipe_buffer_map_range(&sctx->b,
1107 indirect->indirect_draw_count,
1108 indirect->indirect_draw_count_offset,
1109 sizeof(unsigned),
1110 PIPE_TRANSFER_READ, &transfer);
1111
1112 indirect_count = *data;
1113
1114 pipe_buffer_unmap(&sctx->b, transfer);
1115 } else {
1116 indirect_count = indirect->draw_count;
1117 }
1118
1119 if (!indirect_count) {
1120 *start = *count = 0;
1121 return;
1122 }
1123
1124 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1125 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1126 indirect->offset, map_size,
1127 PIPE_TRANSFER_READ, &transfer);
1128
1129 begin = UINT_MAX;
1130 end = 0;
1131
1132 for (unsigned i = 0; i < indirect_count; ++i) {
1133 unsigned count = data[0];
1134 unsigned start = data[2];
1135
1136 if (count > 0) {
1137 begin = MIN2(begin, start);
1138 end = MAX2(end, start + count);
1139 }
1140
1141 data += indirect->stride / sizeof(unsigned);
1142 }
1143
1144 pipe_buffer_unmap(&sctx->b, transfer);
1145
1146 if (begin < end) {
1147 *start = begin;
1148 *count = end - begin;
1149 } else {
1150 *start = *count = 0;
1151 }
1152 } else {
1153 *start = info->start;
1154 *count = info->count;
1155 }
1156 }
1157
1158 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1159 unsigned skip_atom_mask)
1160 {
1161 unsigned num_patches = 0;
1162 bool context_roll = false; /* set correctly for GFX9 only */
1163
1164 context_roll |= si_emit_rasterizer_prim_state(sctx);
1165 if (sctx->tes_shader.cso)
1166 context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
1167 if (info->count_from_stream_output)
1168 context_roll = true;
1169
1170 /* Vega10/Raven scissor bug workaround. When any context register is
1171 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1172 * registers must be written too.
1173 */
1174 if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1175 (context_roll ||
1176 sctx->dirty_atoms & si_atoms_that_roll_context() ||
1177 sctx->dirty_states & si_states_that_roll_context() ||
1178 si_prim_restart_index_changed(sctx, info))) {
1179 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1180 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1181 }
1182
1183 /* Emit state atoms. */
1184 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1185 while (mask)
1186 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1187
1188 sctx->dirty_atoms &= skip_atom_mask;
1189
1190 /* Emit states. */
1191 mask = sctx->dirty_states;
1192 while (mask) {
1193 unsigned i = u_bit_scan(&mask);
1194 struct si_pm4_state *state = sctx->queued.array[i];
1195
1196 if (!state || sctx->emitted.array[i] == state)
1197 continue;
1198
1199 si_pm4_emit(sctx, state);
1200 sctx->emitted.array[i] = state;
1201 }
1202 sctx->dirty_states = 0;
1203
1204 /* Emit draw states. */
1205 si_emit_vs_state(sctx, info);
1206 si_emit_draw_registers(sctx, info, num_patches);
1207 }
1208
1209 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1210 {
1211 struct si_context *sctx = (struct si_context *)ctx;
1212 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1213 struct pipe_resource *indexbuf = info->index.resource;
1214 unsigned dirty_tex_counter;
1215 enum pipe_prim_type rast_prim;
1216 unsigned index_size = info->index_size;
1217 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1218
1219 if (likely(!info->indirect)) {
1220 /* SI-CI treat instance_count==0 as instance_count==1. There is
1221 * no workaround for indirect draws, but we can at least skip
1222 * direct draws.
1223 */
1224 if (unlikely(!info->instance_count))
1225 return;
1226
1227 /* Handle count == 0. */
1228 if (unlikely(!info->count &&
1229 (index_size || !info->count_from_stream_output)))
1230 return;
1231 }
1232
1233 if (unlikely(!sctx->vs_shader.cso ||
1234 !rs ||
1235 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1236 (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
1237 assert(0);
1238 return;
1239 }
1240
1241 /* Recompute and re-emit the texture resource states if needed. */
1242 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1243 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1244 sctx->last_dirty_tex_counter = dirty_tex_counter;
1245 sctx->framebuffer.dirty_cbufs |=
1246 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1247 sctx->framebuffer.dirty_zsbuf = true;
1248 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1249 si_update_all_texture_descriptors(sctx);
1250 }
1251
1252 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1253
1254 /* Set the rasterization primitive type.
1255 *
1256 * This must be done after si_decompress_textures, which can call
1257 * draw_vbo recursively, and before si_update_shaders, which uses
1258 * current_rast_prim for this draw_vbo call. */
1259 if (sctx->gs_shader.cso)
1260 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1261 else if (sctx->tes_shader.cso) {
1262 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1263 rast_prim = PIPE_PRIM_POINTS;
1264 else
1265 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1266 } else
1267 rast_prim = info->mode;
1268
1269 if (rast_prim != sctx->current_rast_prim) {
1270 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1271 util_prim_is_points_or_lines(rast_prim))
1272 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1273
1274 sctx->current_rast_prim = rast_prim;
1275 sctx->do_update_shaders = true;
1276 }
1277
1278 if (sctx->tes_shader.cso &&
1279 sctx->screen->has_ls_vgpr_init_bug) {
1280 /* Determine whether the LS VGPR fix should be applied.
1281 *
1282 * It is only required when num input CPs > num output CPs,
1283 * which cannot happen with the fixed function TCS. We should
1284 * also update this bit when switching from TCS to fixed
1285 * function TCS.
1286 */
1287 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1288 bool ls_vgpr_fix =
1289 tcs &&
1290 info->vertices_per_patch >
1291 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1292
1293 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1294 sctx->ls_vgpr_fix = ls_vgpr_fix;
1295 sctx->do_update_shaders = true;
1296 }
1297 }
1298
1299 if (sctx->gs_shader.cso) {
1300 /* Determine whether the GS triangle strip adjacency fix should
1301 * be applied. Rotate every other triangle if
1302 * - triangle strips with adjacency are fed to the GS and
1303 * - primitive restart is disabled (the rotation doesn't help
1304 * when the restart occurs after an odd number of triangles).
1305 */
1306 bool gs_tri_strip_adj_fix =
1307 !sctx->tes_shader.cso &&
1308 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1309 !info->primitive_restart;
1310
1311 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1312 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1313 sctx->do_update_shaders = true;
1314 }
1315 }
1316
1317 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1318 return;
1319
1320 if (index_size) {
1321 /* Translate or upload, if needed. */
1322 /* 8-bit indices are supported on VI. */
1323 if (sctx->chip_class <= CIK && index_size == 1) {
1324 unsigned start, count, start_offset, size, offset;
1325 void *ptr;
1326
1327 si_get_draw_start_count(sctx, info, &start, &count);
1328 start_offset = start * 2;
1329 size = count * 2;
1330
1331 indexbuf = NULL;
1332 u_upload_alloc(ctx->stream_uploader, start_offset,
1333 size,
1334 si_optimal_tcc_alignment(sctx, size),
1335 &offset, &indexbuf, &ptr);
1336 if (!indexbuf)
1337 return;
1338
1339 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1340 index_offset + start,
1341 count, ptr);
1342
1343 /* info->start will be added by the drawing code */
1344 index_offset = offset - start_offset;
1345 index_size = 2;
1346 } else if (info->has_user_indices) {
1347 unsigned start_offset;
1348
1349 assert(!info->indirect);
1350 start_offset = info->start * index_size;
1351
1352 indexbuf = NULL;
1353 u_upload_data(ctx->stream_uploader, start_offset,
1354 info->count * index_size,
1355 sctx->screen->info.tcc_cache_line_size,
1356 (char*)info->index.user + start_offset,
1357 &index_offset, &indexbuf);
1358 if (!indexbuf)
1359 return;
1360
1361 /* info->start will be added by the drawing code */
1362 index_offset -= start_offset;
1363 } else if (sctx->chip_class <= CIK &&
1364 r600_resource(indexbuf)->TC_L2_dirty) {
1365 /* VI reads index buffers through TC L2, so it doesn't
1366 * need this. */
1367 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1368 r600_resource(indexbuf)->TC_L2_dirty = false;
1369 }
1370 }
1371
1372 if (info->indirect) {
1373 struct pipe_draw_indirect_info *indirect = info->indirect;
1374
1375 /* Add the buffer size for memory checking in need_cs_space. */
1376 si_context_add_resource_size(sctx, indirect->buffer);
1377
1378 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1379 if (sctx->chip_class <= VI) {
1380 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1381 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1382 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1383 }
1384
1385 if (indirect->indirect_draw_count &&
1386 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1387 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1388 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1389 }
1390 }
1391 }
1392
1393 si_need_gfx_cs_space(sctx);
1394
1395 /* Since we've called si_context_add_resource_size for vertex buffers,
1396 * this must be called after si_need_cs_space, because we must let
1397 * need_cs_space flush before we add buffers to the buffer list.
1398 */
1399 if (!si_upload_vertex_buffer_descriptors(sctx))
1400 return;
1401
1402 /* Use optimal packet order based on whether we need to sync the pipeline. */
1403 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1404 SI_CONTEXT_FLUSH_AND_INV_DB |
1405 SI_CONTEXT_PS_PARTIAL_FLUSH |
1406 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1407 /* If we have to wait for idle, set all states first, so that all
1408 * SET packets are processed in parallel with previous draw calls.
1409 * Then draw and prefetch at the end. This ensures that the time
1410 * the CUs are idle is very short.
1411 */
1412 unsigned masked_atoms = 0;
1413
1414 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1415 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1416
1417 if (!si_upload_graphics_shader_descriptors(sctx))
1418 return;
1419
1420 /* Emit all states except possibly render condition. */
1421 si_emit_all_states(sctx, info, masked_atoms);
1422 si_emit_cache_flush(sctx);
1423 /* <-- CUs are idle here. */
1424
1425 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1426 sctx->atoms.s.render_cond.emit(sctx);
1427 sctx->dirty_atoms = 0;
1428
1429 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1430 /* <-- CUs are busy here. */
1431
1432 /* Start prefetches after the draw has been started. Both will run
1433 * in parallel, but starting the draw first is more important.
1434 */
1435 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1436 cik_emit_prefetch_L2(sctx, false);
1437 } else {
1438 /* If we don't wait for idle, start prefetches first, then set
1439 * states, and draw at the end.
1440 */
1441 if (sctx->flags)
1442 si_emit_cache_flush(sctx);
1443
1444 /* Only prefetch the API VS and VBO descriptors. */
1445 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1446 cik_emit_prefetch_L2(sctx, true);
1447
1448 if (!si_upload_graphics_shader_descriptors(sctx))
1449 return;
1450
1451 si_emit_all_states(sctx, info, 0);
1452 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1453
1454 /* Prefetch the remaining shaders after the draw has been
1455 * started. */
1456 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1457 cik_emit_prefetch_L2(sctx, false);
1458 }
1459
1460 if (unlikely(sctx->current_saved_cs)) {
1461 si_trace_emit(sctx);
1462 si_log_draw_state(sctx, sctx->log);
1463 }
1464
1465 /* Workaround for a VGT hang when streamout is enabled.
1466 * It must be done after drawing. */
1467 if ((sctx->family == CHIP_HAWAII ||
1468 sctx->family == CHIP_TONGA ||
1469 sctx->family == CHIP_FIJI) &&
1470 si_get_strmout_en(sctx)) {
1471 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1472 }
1473
1474 if (unlikely(sctx->decompression_enabled)) {
1475 sctx->num_decompress_calls++;
1476 } else {
1477 sctx->num_draw_calls++;
1478 if (sctx->framebuffer.state.nr_cbufs > 1)
1479 sctx->num_mrt_draw_calls++;
1480 if (info->primitive_restart)
1481 sctx->num_prim_restart_calls++;
1482 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1483 sctx->num_spill_draw_calls++;
1484 }
1485 if (index_size && indexbuf != info->index.resource)
1486 pipe_resource_reference(&indexbuf, NULL);
1487 }
1488
1489 void si_draw_rectangle(struct blitter_context *blitter,
1490 void *vertex_elements_cso,
1491 blitter_get_vs_func get_vs,
1492 int x1, int y1, int x2, int y2,
1493 float depth, unsigned num_instances,
1494 enum blitter_attrib_type type,
1495 const union blitter_attrib *attrib)
1496 {
1497 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1498 struct si_context *sctx = (struct si_context*)pipe;
1499
1500 /* Pack position coordinates as signed int16. */
1501 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1502 ((uint32_t)(y1 & 0xffff) << 16);
1503 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1504 ((uint32_t)(y2 & 0xffff) << 16);
1505 sctx->vs_blit_sh_data[2] = fui(depth);
1506
1507 switch (type) {
1508 case UTIL_BLITTER_ATTRIB_COLOR:
1509 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1510 sizeof(float)*4);
1511 break;
1512 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1513 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1514 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1515 sizeof(attrib->texcoord));
1516 break;
1517 case UTIL_BLITTER_ATTRIB_NONE:;
1518 }
1519
1520 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1521
1522 struct pipe_draw_info info = {};
1523 info.mode = SI_PRIM_RECTANGLE_LIST;
1524 info.count = 3;
1525 info.instance_count = num_instances;
1526
1527 /* Don't set per-stage shader pointers for VS. */
1528 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1529 sctx->vertex_buffer_pointer_dirty = false;
1530
1531 si_draw_vbo(pipe, &info);
1532 }
1533
1534 void si_trace_emit(struct si_context *sctx)
1535 {
1536 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1537 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1538 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1539
1540 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1541 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1542 S_370_WR_CONFIRM(1) |
1543 S_370_ENGINE_SEL(V_370_ME));
1544 radeon_emit(cs, va);
1545 radeon_emit(cs, va >> 32);
1546 radeon_emit(cs, trace_id);
1547 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1548 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1549
1550 if (sctx->log)
1551 u_log_flush(sctx->log);
1552 }