2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
131 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
133 /* Refuse to allocate overly large buffers and guard against integer
135 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
136 llvm_ir_size
> UINT_MAX
/ 4)
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.elf_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
159 assert((char *)ptr
- (char *)buffer
== size
);
162 ptr
= (uint32_t*)buffer
;
164 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
169 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
171 uint32_t *ptr
= (uint32_t*)binary
;
172 uint32_t size
= *ptr
++;
173 uint32_t crc32
= *ptr
++;
177 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
178 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
182 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
183 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
184 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
186 shader
->binary
.elf_size
= elf_size
;
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
196 * Returns false on failure, in which case the ir_binary should be freed.
198 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
199 struct si_shader
*shader
,
200 bool insert_into_disk_cache
)
203 struct hash_entry
*entry
;
204 uint8_t key
[CACHE_KEY_SIZE
];
206 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
208 return false; /* already added */
210 hw_binary
= si_get_shader_binary(shader
);
214 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
215 hw_binary
) == NULL
) {
220 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
221 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
222 *((uint32_t *)ir_binary
), key
);
223 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
224 *((uint32_t *) hw_binary
), NULL
);
230 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
231 struct si_shader
*shader
)
233 struct hash_entry
*entry
=
234 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
236 if (sscreen
->disk_shader_cache
) {
237 unsigned char sha1
[CACHE_KEY_SIZE
];
238 size_t tg_size
= *((uint32_t *) ir_binary
);
240 disk_cache_compute_key(sscreen
->disk_shader_cache
,
241 ir_binary
, tg_size
, sha1
);
245 disk_cache_get(sscreen
->disk_shader_cache
,
250 if (binary_size
< sizeof(uint32_t) ||
251 *((uint32_t*)buffer
) != binary_size
) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
256 assert(!"Invalid radeonsi shader disk cache "
259 disk_cache_remove(sscreen
->disk_shader_cache
,
266 if (!si_load_shader_binary(shader
, buffer
)) {
272 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
279 if (si_load_shader_binary(shader
, entry
->data
))
284 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
288 static uint32_t si_shader_cache_key_hash(const void *key
)
290 /* The first dword is the key size. */
291 return util_hash_crc32(key
, *(uint32_t*)key
);
294 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 uint32_t *keya
= (uint32_t*)a
;
297 uint32_t *keyb
= (uint32_t*)b
;
299 /* The first dword is the key size. */
303 return memcmp(keya
, keyb
, *keya
) == 0;
306 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
308 FREE((void*)entry
->key
);
312 bool si_init_shader_cache(struct si_screen
*sscreen
)
314 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
315 sscreen
->shader_cache
=
316 _mesa_hash_table_create(NULL
,
317 si_shader_cache_key_hash
,
318 si_shader_cache_key_equals
);
320 return sscreen
->shader_cache
!= NULL
;
323 void si_destroy_shader_cache(struct si_screen
*sscreen
)
325 if (sscreen
->shader_cache
)
326 _mesa_hash_table_destroy(sscreen
->shader_cache
,
327 si_destroy_shader_cache_entry
);
328 mtx_destroy(&sscreen
->shader_cache_mutex
);
333 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
334 const struct si_shader_selector
*tes
,
335 struct si_pm4_state
*pm4
)
337 const struct tgsi_shader_info
*info
= &tes
->info
;
338 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
339 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
340 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
341 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
342 unsigned type
, partitioning
, topology
, distribution_mode
;
344 switch (tes_prim_mode
) {
345 case PIPE_PRIM_LINES
:
346 type
= V_028B6C_TESS_ISOLINE
;
348 case PIPE_PRIM_TRIANGLES
:
349 type
= V_028B6C_TESS_TRIANGLE
;
351 case PIPE_PRIM_QUADS
:
352 type
= V_028B6C_TESS_QUAD
;
359 switch (tes_spacing
) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
361 partitioning
= V_028B6C_PART_FRAC_ODD
;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
364 partitioning
= V_028B6C_PART_FRAC_EVEN
;
366 case PIPE_TESS_SPACING_EQUAL
:
367 partitioning
= V_028B6C_PART_INTEGER
;
375 topology
= V_028B6C_OUTPUT_POINT
;
376 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
377 topology
= V_028B6C_OUTPUT_LINE
;
378 else if (tes_vertex_order_cw
)
379 /* for some reason, this must be the other way around */
380 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
382 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
384 if (sscreen
->has_distributed_tess
) {
385 if (sscreen
->info
.family
== CHIP_FIJI
||
386 sscreen
->info
.family
>= CHIP_POLARIS10
)
387 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
389 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
391 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
394 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
395 S_028B6C_PARTITIONING(partitioning
) |
396 S_028B6C_TOPOLOGY(topology
) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
403 * Possible VGT configurations and which state should set the register:
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
415 struct si_shader_selector
*sel
,
416 struct si_shader
*shader
,
417 struct si_pm4_state
*pm4
)
419 unsigned type
= sel
->type
;
421 if (sscreen
->info
.family
< CHIP_POLARIS10
)
424 /* VS as VS, or VS as ES: */
425 if ((type
== PIPE_SHADER_VERTEX
&&
427 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
428 /* TES as VS, or TES as ES: */
429 type
== PIPE_SHADER_TESS_EVAL
) {
430 unsigned vtx_reuse_depth
= 30;
432 if (type
== PIPE_SHADER_TESS_EVAL
&&
433 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
435 vtx_reuse_depth
= 14;
438 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
442 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
445 si_pm4_clear_state(shader
->pm4
);
447 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
450 shader
->pm4
->shader
= shader
;
453 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs
+ 1;
464 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
466 struct si_pm4_state
*pm4
;
467 unsigned vgpr_comp_cnt
;
470 assert(sscreen
->info
.chip_class
<= GFX8
);
472 pm4
= si_get_shader_pm4_state(shader
);
476 va
= shader
->bo
->gpu_address
;
477 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
485 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
486 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
488 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
489 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
493 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
494 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
497 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
499 struct si_pm4_state
*pm4
;
501 unsigned ls_vgpr_comp_cnt
= 0;
503 pm4
= si_get_shader_pm4_state(shader
);
507 va
= shader
->bo
->gpu_address
;
508 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
510 if (sscreen
->info
.chip_class
>= GFX9
) {
511 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
512 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
518 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
520 unsigned num_user_sgprs
=
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
523 shader
->config
.rsrc2
=
524 S_00B42C_USER_SGPR(num_user_sgprs
) |
525 S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5) |
526 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
528 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
529 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
531 shader
->config
.rsrc2
=
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
537 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
538 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
539 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
544 if (sscreen
->info
.chip_class
<= GFX8
) {
545 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
546 shader
->config
.rsrc2
);
550 static void si_emit_shader_es(struct si_context
*sctx
)
552 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
553 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
558 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
560 shader
->selector
->esgs_itemsize
/ 4);
562 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
563 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
564 SI_TRACKED_VGT_TF_PARAM
,
565 shader
->vgt_tf_param
);
567 if (shader
->vgt_vertex_reuse_block_cntl
)
568 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
570 shader
->vgt_vertex_reuse_block_cntl
);
572 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
573 sctx
->context_roll
= true;
576 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
578 struct si_pm4_state
*pm4
;
579 unsigned num_user_sgprs
;
580 unsigned vgpr_comp_cnt
;
584 assert(sscreen
->info
.chip_class
<= GFX8
);
586 pm4
= si_get_shader_pm4_state(shader
);
590 pm4
->atom
.emit
= si_emit_shader_es
;
591 va
= shader
->bo
->gpu_address
;
592 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
594 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
597 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
598 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
599 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
600 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
602 unreachable("invalid shader selector type");
604 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
606 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
607 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
608 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
609 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
610 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
614 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
615 S_00B32C_USER_SGPR(num_user_sgprs
) |
616 S_00B32C_OC_LDS_EN(oc_lds_en
) |
617 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
619 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
620 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
622 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
625 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
627 static const int prim_conv
[] = {
628 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
629 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
630 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
631 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
632 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
633 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
634 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
635 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
636 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
637 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
638 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
639 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
640 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
641 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
642 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
644 assert(mode
< ARRAY_SIZE(prim_conv
));
646 return prim_conv
[mode
];
649 void gfx9_get_gs_info(struct si_shader_selector
*es
,
650 struct si_shader_selector
*gs
,
651 struct gfx9_gs_info
*out
)
653 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
654 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
655 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
656 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
658 /* All these are in dwords: */
659 /* We can't allow using the whole LDS, because GS waves compete with
660 * other shader stages for LDS space. */
661 const unsigned max_lds_size
= 8 * 1024;
662 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
663 unsigned esgs_lds_size
;
665 /* All these are per subgroup: */
666 const unsigned max_out_prims
= 32 * 1024;
667 const unsigned max_es_verts
= 255;
668 const unsigned ideal_gs_prims
= 64;
669 unsigned max_gs_prims
, gs_prims
;
670 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
672 if (uses_adjacency
|| gs_num_invocations
> 1)
673 max_gs_prims
= 127 / gs_num_invocations
;
677 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
678 * Make sure we don't go over the maximum value.
680 if (gs
->gs_max_out_vertices
> 0) {
681 max_gs_prims
= MIN2(max_gs_prims
,
683 (gs
->gs_max_out_vertices
* gs_num_invocations
));
685 assert(max_gs_prims
> 0);
687 /* If the primitive has adjacency, halve the number of vertices
688 * that will be reused in multiple primitives.
690 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
692 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
693 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
695 /* Compute ESGS LDS size based on the worst case number of ES vertices
696 * needed to create the target number of GS prims per subgroup.
698 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
700 /* If total LDS usage is too big, refactor partitions based on ratio
701 * of ESGS item sizes.
703 if (esgs_lds_size
> max_lds_size
) {
704 /* Our target GS Prims Per Subgroup was too large. Calculate
705 * the maximum number of GS Prims Per Subgroup that will fit
706 * into LDS, capped by the maximum that the hardware can support.
708 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
710 assert(gs_prims
> 0);
711 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
714 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
715 assert(esgs_lds_size
<= max_lds_size
);
718 /* Now calculate remaining ESGS information. */
720 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
722 es_verts
= max_es_verts
;
724 /* Vertices for adjacency primitives are not always reused, so restore
725 * it for ES_VERTS_PER_SUBGRP.
727 min_es_verts
= gs
->gs_input_verts_per_prim
;
729 /* For normal primitives, the VGT only checks if they are past the ES
730 * verts per subgroup after allocating a full GS primitive and if they
731 * are, kick off a new subgroup. But if those additional ES verts are
732 * unique (e.g. not reused) we need to make sure there is enough LDS
733 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
735 es_verts
-= min_es_verts
- 1;
737 out
->es_verts_per_subgroup
= es_verts
;
738 out
->gs_prims_per_subgroup
= gs_prims
;
739 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
740 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
741 gs
->gs_max_out_vertices
;
742 out
->esgs_ring_size
= 4 * esgs_lds_size
;
744 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
747 static void si_emit_shader_gs(struct si_context
*sctx
)
749 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
750 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
755 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
756 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
757 radeon_opt_set_context_reg4(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
758 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
759 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
760 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
761 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
,
762 shader
->ctx_reg
.gs
.vgt_gs_out_prim_type
);
765 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
766 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
767 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
768 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
770 /* R_028B38_VGT_GS_MAX_VERT_OUT */
771 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
772 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
773 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
775 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
776 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
777 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
778 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
779 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
780 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
781 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
782 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
784 /* R_028B90_VGT_GS_INSTANCE_CNT */
785 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
786 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
787 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
789 if (sctx
->chip_class
>= GFX9
) {
790 /* R_028A44_VGT_GS_ONCHIP_CNTL */
791 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
792 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
793 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
794 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
795 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
796 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
797 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
798 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
799 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
800 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
801 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
803 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
804 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
805 SI_TRACKED_VGT_TF_PARAM
,
806 shader
->vgt_tf_param
);
807 if (shader
->vgt_vertex_reuse_block_cntl
)
808 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
809 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
810 shader
->vgt_vertex_reuse_block_cntl
);
813 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
814 sctx
->context_roll
= true;
817 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
819 struct si_shader_selector
*sel
= shader
->selector
;
820 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
821 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
822 struct si_pm4_state
*pm4
;
824 unsigned max_stream
= sel
->max_gs_stream
;
827 pm4
= si_get_shader_pm4_state(shader
);
831 pm4
->atom
.emit
= si_emit_shader_gs
;
833 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
834 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
837 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
838 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
841 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
842 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
844 shader
->ctx_reg
.gs
.vgt_gs_out_prim_type
=
845 si_conv_prim_to_gs_out(sel
->gs_output_prim
);
848 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
849 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
851 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
852 assert(offset
< (1 << 15));
854 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
856 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
857 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
858 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
859 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
861 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
862 S_028B90_ENABLE(gs_num_invocations
> 0);
864 va
= shader
->bo
->gpu_address
;
865 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
867 if (sscreen
->info
.chip_class
>= GFX9
) {
868 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
869 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
870 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
872 if (es_type
== PIPE_SHADER_VERTEX
)
873 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
874 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
875 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
876 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
878 unreachable("invalid shader selector type");
880 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
881 * VGPR[0:4] are always loaded.
883 if (sel
->info
.uses_invocationid
)
884 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
885 else if (sel
->info
.uses_primid
)
886 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
887 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
888 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
890 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
892 unsigned num_user_sgprs
;
893 if (es_type
== PIPE_SHADER_VERTEX
)
894 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
896 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
898 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
899 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
901 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
902 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
903 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
904 S_00B228_DX10_CLAMP(1) |
905 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
907 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
908 S_00B22C_USER_SGPR(num_user_sgprs
) |
909 S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5) |
910 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
911 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
912 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
913 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
915 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
916 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
917 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
918 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
919 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
920 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
921 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
922 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
924 if (es_type
== PIPE_SHADER_TESS_EVAL
)
925 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
927 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
930 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
931 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
933 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
934 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
935 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
936 S_00B228_DX10_CLAMP(1) |
937 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
938 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
939 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
940 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
944 /* Common tail code for NGG primitive shaders. */
945 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
946 struct si_shader
*shader
,
947 unsigned initial_cdw
)
949 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
950 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
951 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
952 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
953 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
954 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
955 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
956 SI_TRACKED_VGT_PRIMITIVEID_EN
,
957 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
958 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
959 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
960 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
961 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
962 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
963 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
964 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
965 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
966 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
967 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
968 SI_TRACKED_VGT_REUSE_OFF
,
969 shader
->ctx_reg
.ngg
.vgt_reuse_off
);
970 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
971 SI_TRACKED_SPI_VS_OUT_CONFIG
,
972 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
973 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
974 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
975 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
976 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
977 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
978 SI_TRACKED_PA_CL_VTE_CNTL
,
979 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
981 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
982 sctx
->context_roll
= true;
984 if (shader
->ge_cntl
!= sctx
->last_multi_vgt_param
) {
985 radeon_set_uconfig_reg(sctx
->gfx_cs
, R_03096C_GE_CNTL
, shader
->ge_cntl
);
986 sctx
->last_multi_vgt_param
= shader
->ge_cntl
;
990 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
992 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
993 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
998 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1001 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1003 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1004 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1009 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1010 SI_TRACKED_VGT_TF_PARAM
,
1011 shader
->vgt_tf_param
);
1013 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1017 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1020 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1022 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1023 enum pipe_shader_type es_type
= shader
->selector
->type
;
1024 unsigned num_user_sgprs
;
1025 unsigned nparams
, es_vgpr_comp_cnt
;
1027 unsigned window_space
=
1028 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1029 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1030 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1034 pm4
->atom
.emit
= es_type
== PIPE_SHADER_TESS_EVAL
? gfx10_emit_shader_ngg_tess_nogs
1035 : gfx10_emit_shader_ngg_notess_nogs
;
1037 va
= shader
->bo
->gpu_address
;
1038 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1040 if (es_type
== PIPE_SHADER_VERTEX
) {
1041 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1042 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1044 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1045 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1046 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1048 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1051 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1052 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1053 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1056 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1057 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1058 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1059 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1060 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1061 S_00B228_DX10_CLAMP(1) |
1062 S_00B228_GS_VGPR_COMP_CNT(3));
1063 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1064 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1065 S_00B22C_USER_SGPR(num_user_sgprs
) |
1066 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1067 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5));
1069 /* TODO: Use NO_PC_EXPORT when applicable. */
1070 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1071 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1072 S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1074 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1075 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1076 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1077 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1078 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1079 V_02870C_SPI_SHADER_4COMP
:
1080 V_02870C_SPI_SHADER_NONE
) |
1081 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1082 V_02870C_SPI_SHADER_4COMP
:
1083 V_02870C_SPI_SHADER_NONE
) |
1084 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1085 V_02870C_SPI_SHADER_4COMP
:
1086 V_02870C_SPI_SHADER_NONE
);
1088 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1089 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1090 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1092 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1094 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1095 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1097 uint32_t es_verts_per_subgrp
= 252;
1098 uint32_t gs_prims_per_subgrp
= 255;
1099 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1100 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgrp
) |
1101 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgrp
) |
1102 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_prims_per_subgrp
);
1103 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1104 S_0287FC_MAX_VERTS_PER_SUBGROUP(es_verts_per_subgrp
);
1105 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1106 S_028B4C_PRIM_AMP_FACTOR(1) |
1107 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1109 S_03096C_PRIM_GRP_SIZE(gs_prims_per_subgrp
) |
1110 S_03096C_VERT_GRP_SIZE(es_verts_per_subgrp
);
1113 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1114 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1116 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1117 S_028818_VTX_W0_FMT(1) |
1118 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1119 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1120 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1123 shader
->ctx_reg
.ngg
.vgt_reuse_off
=
1124 S_028AB4_REUSE_OFF(sscreen
->info
.family
== CHIP_NAVI10
&&
1125 sscreen
->info
.chip_external_rev
== 0x1 &&
1126 es_type
== PIPE_SHADER_TESS_EVAL
);
1129 static void si_emit_shader_vs(struct si_context
*sctx
)
1131 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1132 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1137 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1138 SI_TRACKED_VGT_GS_MODE
,
1139 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1140 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1141 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1142 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1144 if (sctx
->chip_class
<= GFX8
) {
1145 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1146 SI_TRACKED_VGT_REUSE_OFF
,
1147 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1150 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1151 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1152 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1154 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1155 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1156 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1158 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1159 SI_TRACKED_PA_CL_VTE_CNTL
,
1160 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1162 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1163 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1164 SI_TRACKED_VGT_TF_PARAM
,
1165 shader
->vgt_tf_param
);
1167 if (shader
->vgt_vertex_reuse_block_cntl
)
1168 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1169 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1170 shader
->vgt_vertex_reuse_block_cntl
);
1172 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1173 sctx
->context_roll
= true;
1177 * Compute the state for \p shader, which will run as a vertex shader on the
1180 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1181 * is the copy shader.
1183 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1184 struct si_shader_selector
*gs
)
1186 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1187 struct si_pm4_state
*pm4
;
1188 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1190 unsigned nparams
, oc_lds_en
;
1191 unsigned window_space
=
1192 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1193 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1195 pm4
= si_get_shader_pm4_state(shader
);
1199 pm4
->atom
.emit
= si_emit_shader_vs
;
1201 /* We always write VGT_GS_MODE in the VS state, because every switch
1202 * between different shader pipelines involving a different GS or no
1203 * GS at all involves a switch of the VS (different GS use different
1204 * copy shaders). On the other hand, when the API switches from a GS to
1205 * no GS and then back to the same GS used originally, the GS state is
1209 unsigned mode
= V_028A40_GS_OFF
;
1211 /* PrimID needs GS scenario A. */
1213 mode
= V_028A40_GS_SCENARIO_A
;
1215 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1216 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1218 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1219 sscreen
->info
.chip_class
);
1220 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1223 if (sscreen
->info
.chip_class
<= GFX8
) {
1224 /* Reuse needs to be set off if we write oViewport. */
1225 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1226 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1229 va
= shader
->bo
->gpu_address
;
1230 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1233 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1234 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1235 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1236 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1237 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1238 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1240 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1242 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1243 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1244 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1246 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1248 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1249 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1250 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1252 unreachable("invalid shader selector type");
1254 /* VS is required to export at least one param. */
1255 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1256 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1258 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1259 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1260 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1261 V_02870C_SPI_SHADER_4COMP
:
1262 V_02870C_SPI_SHADER_NONE
) |
1263 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1264 V_02870C_SPI_SHADER_4COMP
:
1265 V_02870C_SPI_SHADER_NONE
) |
1266 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1267 V_02870C_SPI_SHADER_4COMP
:
1268 V_02870C_SPI_SHADER_NONE
);
1270 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1272 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1273 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1274 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
1275 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1276 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1277 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1278 S_00B128_DX10_CLAMP(1) |
1279 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
1280 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
1281 S_00B12C_USER_SGPR(num_user_sgprs
) |
1282 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1283 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1284 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1285 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1286 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1287 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
1288 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1291 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1292 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1294 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1295 S_028818_VTX_W0_FMT(1) |
1296 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1297 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1298 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1300 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1301 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1303 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1306 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1308 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1309 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1310 !!(info
->colors_read
& 0xf0);
1311 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1312 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1314 assert(num_interp
<= 32);
1315 return MIN2(num_interp
, 32);
1318 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1320 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1321 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1323 /* If the i-th target format is set, all previous target formats must
1324 * be non-zero to avoid hangs.
1326 for (i
= 0; i
< num_targets
; i
++)
1327 if (!(value
& (0xf << (i
* 4))))
1328 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1333 static void si_emit_shader_ps(struct si_context
*sctx
)
1335 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1336 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1341 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1342 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1343 SI_TRACKED_SPI_PS_INPUT_ENA
,
1344 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1345 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1347 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1348 SI_TRACKED_SPI_BARYC_CNTL
,
1349 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1350 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1351 SI_TRACKED_SPI_PS_IN_CONTROL
,
1352 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1354 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1355 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1356 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1357 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1358 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1360 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1361 SI_TRACKED_CB_SHADER_MASK
,
1362 shader
->ctx_reg
.ps
.cb_shader_mask
);
1364 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1365 sctx
->context_roll
= true;
1368 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1370 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1371 struct si_pm4_state
*pm4
;
1372 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1373 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1375 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1377 /* we need to enable at least one of them, otherwise we hang the GPU */
1378 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1379 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1380 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1381 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1382 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1383 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1384 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1385 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1386 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1387 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1388 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1389 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1390 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1391 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1393 /* Validate interpolation optimization flags (read as implications). */
1394 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1395 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1396 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1397 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1398 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1399 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1400 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1401 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1402 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1403 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1404 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1405 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1406 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1407 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1408 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1409 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1410 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1411 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1413 /* Validate cases when the optimizations are off (read as implications). */
1414 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1415 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1416 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1417 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1418 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1419 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1421 pm4
= si_get_shader_pm4_state(shader
);
1425 pm4
->atom
.emit
= si_emit_shader_ps
;
1427 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1429 * 0 -> Position = pixel center
1430 * 1 -> Position = pixel centroid
1431 * 2 -> Position = at sample position
1433 * From GLSL 4.5 specification, section 7.1:
1434 * "The variable gl_FragCoord is available as an input variable from
1435 * within fragment shaders and it holds the window relative coordinates
1436 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1437 * value can be for any location within the pixel, or one of the
1438 * fragment samples. The use of centroid does not further restrict
1439 * this value to be inside the current primitive."
1441 * Meaning that centroid has no effect and we can return anything within
1442 * the pixel. Thus, return the value at sample position, because that's
1443 * the most accurate one shaders can get.
1445 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1447 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1448 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1449 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1451 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1452 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1454 /* Ensure that some export memory is always allocated, for two reasons:
1456 * 1) Correctness: The hardware ignores the EXEC mask if no export
1457 * memory is allocated, so KILL and alpha test do not work correctly
1459 * 2) Performance: Every shader needs at least a NULL export, even when
1460 * it writes no color/depth output. The NULL export instruction
1461 * stalls without this setting.
1463 * Don't add this to CB_SHADER_MASK.
1465 if (!spi_shader_col_format
&&
1466 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1467 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1469 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1470 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1472 /* Set interpolation controls. */
1473 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1475 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1476 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1477 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1478 ac_get_spi_shader_z_format(info
->writes_z
,
1479 info
->writes_stencil
,
1480 info
->writes_samplemask
);
1481 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1482 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1484 va
= shader
->bo
->gpu_address
;
1485 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1486 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1487 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1490 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1491 S_00B028_DX10_CLAMP(1) |
1492 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1493 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1495 if (sscreen
->info
.chip_class
< GFX10
) {
1496 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1499 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1500 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1501 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1502 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1503 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1506 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1507 struct si_shader
*shader
)
1509 switch (shader
->selector
->type
) {
1510 case PIPE_SHADER_VERTEX
:
1511 if (shader
->key
.as_ls
)
1512 si_shader_ls(sscreen
, shader
);
1513 else if (shader
->key
.as_es
)
1514 si_shader_es(sscreen
, shader
);
1515 else if (shader
->key
.as_ngg
)
1516 gfx10_shader_ngg(sscreen
, shader
);
1518 si_shader_vs(sscreen
, shader
, NULL
);
1520 case PIPE_SHADER_TESS_CTRL
:
1521 si_shader_hs(sscreen
, shader
);
1523 case PIPE_SHADER_TESS_EVAL
:
1524 if (shader
->key
.as_es
)
1525 si_shader_es(sscreen
, shader
);
1526 else if (shader
->key
.as_ngg
)
1527 gfx10_shader_ngg(sscreen
, shader
);
1529 si_shader_vs(sscreen
, shader
, NULL
);
1531 case PIPE_SHADER_GEOMETRY
:
1532 si_shader_gs(sscreen
, shader
);
1534 case PIPE_SHADER_FRAGMENT
:
1535 si_shader_ps(sscreen
, shader
);
1542 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1544 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1545 if (sctx
->queued
.named
.dsa
)
1546 return sctx
->queued
.named
.dsa
->alpha_func
;
1548 return PIPE_FUNC_ALWAYS
;
1551 void si_shader_selector_key_vs(struct si_context
*sctx
,
1552 struct si_shader_selector
*vs
,
1553 struct si_shader_key
*key
,
1554 struct si_vs_prolog_bits
*prolog_key
)
1556 if (!sctx
->vertex_elements
||
1557 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1560 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1562 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1563 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1564 prolog_key
->unpack_instance_id_from_vertex_id
=
1565 sctx
->prim_discard_cs_instancing
;
1567 /* Prefer a monolithic shader to allow scheduling divisions around
1569 if (prolog_key
->instance_divisor_is_fetched
)
1570 key
->opt
.prefer_mono
= 1;
1572 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1573 unsigned count_mask
= (1 << count
) - 1;
1574 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1575 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1577 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1578 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1580 unsigned i
= u_bit_scan(&mask
);
1581 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1582 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1583 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1584 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1585 if (vb
->buffer_offset
& align_mask
||
1586 vb
->stride
& align_mask
) {
1594 unsigned i
= u_bit_scan(&fix
);
1595 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1597 key
->mono
.vs_fetch_opencode
= opencode
;
1600 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1601 struct si_shader_selector
*vs
,
1602 struct si_shader_key
*key
)
1604 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1606 key
->opt
.clip_disable
=
1607 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1608 (vs
->info
.clipdist_writemask
||
1609 vs
->info
.writes_clipvertex
) &&
1610 !vs
->info
.culldist_writemask
;
1612 /* Find out if PS is disabled. */
1613 bool ps_disabled
= true;
1615 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1616 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1617 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1618 ps
->info
.writes_z
||
1619 ps
->info
.writes_stencil
||
1620 ps
->info
.writes_samplemask
||
1621 alpha_to_coverage
||
1622 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1623 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1625 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1628 !ps
->info
.writes_memory
);
1631 /* Find out which VS outputs aren't used by the PS. */
1632 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1633 uint64_t inputs_read
= 0;
1635 /* Ignore outputs that are not passed from VS to PS. */
1636 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1637 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1638 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1641 inputs_read
= ps
->inputs_read
;
1644 uint64_t linked
= outputs_written
& inputs_read
;
1646 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1649 /* Compute the key for the hw shader variant */
1650 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1651 struct si_shader_selector
*sel
,
1652 union si_vgt_stages_key stages_key
,
1653 struct si_shader_key
*key
)
1655 struct si_context
*sctx
= (struct si_context
*)ctx
;
1657 memset(key
, 0, sizeof(*key
));
1659 switch (sel
->type
) {
1660 case PIPE_SHADER_VERTEX
:
1661 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1663 if (sctx
->tes_shader
.cso
)
1665 else if (sctx
->gs_shader
.cso
)
1668 key
->as_ngg
= stages_key
.u
.ngg
;
1669 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1671 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1672 key
->mono
.u
.vs_export_prim_id
= 1;
1675 case PIPE_SHADER_TESS_CTRL
:
1676 if (sctx
->chip_class
>= GFX9
) {
1677 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1678 key
, &key
->part
.tcs
.ls_prolog
);
1679 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1681 /* When the LS VGPR fix is needed, monolithic shaders
1683 * - avoid initializing EXEC in both the LS prolog
1684 * and the LS main part when !vs_needs_prolog
1685 * - remove the fixup for unused input VGPRs
1687 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1689 /* The LS output / HS input layout can be communicated
1690 * directly instead of via user SGPRs for merged LS-HS.
1691 * The LS VGPR fix prefers this too.
1693 key
->opt
.prefer_mono
= 1;
1696 key
->part
.tcs
.epilog
.prim_mode
=
1697 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1698 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1699 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1700 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1701 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1703 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1704 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1706 case PIPE_SHADER_TESS_EVAL
:
1707 if (sctx
->gs_shader
.cso
)
1710 key
->as_ngg
= stages_key
.u
.ngg
;
1711 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1713 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1714 key
->mono
.u
.vs_export_prim_id
= 1;
1717 case PIPE_SHADER_GEOMETRY
:
1718 if (sctx
->chip_class
>= GFX9
) {
1719 if (sctx
->tes_shader
.cso
) {
1720 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1722 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1723 key
, &key
->part
.gs
.vs_prolog
);
1724 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1725 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1728 key
->as_ngg
= stages_key
.u
.ngg
;
1730 /* Merged ES-GS can have unbalanced wave usage.
1732 * ES threads are per-vertex, while GS threads are
1733 * per-primitive. So without any amplification, there
1734 * are fewer GS threads than ES threads, which can result
1735 * in empty (no-op) GS waves. With too much amplification,
1736 * there are more GS threads than ES threads, which
1737 * can result in empty (no-op) ES waves.
1739 * Non-monolithic shaders are implemented by setting EXEC
1740 * at the beginning of shader parts, and don't jump to
1741 * the end if EXEC is 0.
1743 * Monolithic shaders use conditional blocks, so they can
1744 * jump and skip empty waves of ES or GS. So set this to
1745 * always use optimized variants, which are monolithic.
1747 key
->opt
.prefer_mono
= 1;
1749 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1751 case PIPE_SHADER_FRAGMENT
: {
1752 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1753 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1755 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1756 sel
->info
.colors_written
== 0x1)
1757 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1760 /* Select the shader color format based on whether
1761 * blending or alpha are needed.
1763 key
->part
.ps
.epilog
.spi_shader_col_format
=
1764 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1765 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1766 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1767 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1768 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1769 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1770 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1771 sctx
->framebuffer
.spi_shader_col_format
);
1772 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1774 /* The output for dual source blending should have
1775 * the same format as the first output.
1777 if (blend
->dual_src_blend
)
1778 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1779 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1781 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1783 /* If alpha-to-coverage is enabled, we have to export alpha
1784 * even if there is no color buffer.
1786 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1787 blend
&& blend
->alpha_to_coverage
)
1788 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1790 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1791 * to the range supported by the type if a channel has less
1792 * than 16 bits and the export format is 16_ABGR.
1794 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1795 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1796 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1799 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1800 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1801 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1802 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1803 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1806 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1807 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1809 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1810 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1812 if (sctx
->queued
.named
.blend
) {
1813 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1814 rs
->multisample_enable
;
1817 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1818 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1819 (is_line
&& rs
->line_smooth
)) &&
1820 sctx
->framebuffer
.nr_samples
<= 1;
1821 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1823 if (sctx
->ps_iter_samples
> 1 &&
1824 sel
->info
.reads_samplemask
) {
1825 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1826 util_logbase2(sctx
->ps_iter_samples
);
1829 if (rs
->force_persample_interp
&&
1830 rs
->multisample_enable
&&
1831 sctx
->framebuffer
.nr_samples
> 1 &&
1832 sctx
->ps_iter_samples
> 1) {
1833 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1834 sel
->info
.uses_persp_center
||
1835 sel
->info
.uses_persp_centroid
;
1837 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1838 sel
->info
.uses_linear_center
||
1839 sel
->info
.uses_linear_centroid
;
1840 } else if (rs
->multisample_enable
&&
1841 sctx
->framebuffer
.nr_samples
> 1) {
1842 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1843 sel
->info
.uses_persp_center
&&
1844 sel
->info
.uses_persp_centroid
;
1845 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1846 sel
->info
.uses_linear_center
&&
1847 sel
->info
.uses_linear_centroid
;
1849 /* Make sure SPI doesn't compute more than 1 pair
1850 * of (i,j), which is the optimization here. */
1851 key
->part
.ps
.prolog
.force_persp_center_interp
=
1852 sel
->info
.uses_persp_center
+
1853 sel
->info
.uses_persp_centroid
+
1854 sel
->info
.uses_persp_sample
> 1;
1856 key
->part
.ps
.prolog
.force_linear_center_interp
=
1857 sel
->info
.uses_linear_center
+
1858 sel
->info
.uses_linear_centroid
+
1859 sel
->info
.uses_linear_sample
> 1;
1861 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1862 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1865 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1867 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1868 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
1869 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1870 struct pipe_resource
*tex
= cb0
->texture
;
1872 /* 1D textures are allocated and used as 2D on GFX9. */
1873 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1874 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1875 (tex
->target
== PIPE_TEXTURE_1D
||
1876 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1877 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1878 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1879 tex
->target
== PIPE_TEXTURE_CUBE
||
1880 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1881 tex
->target
== PIPE_TEXTURE_3D
;
1889 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1890 memset(&key
->opt
, 0, sizeof(key
->opt
));
1893 static void si_build_shader_variant(struct si_shader
*shader
,
1897 struct si_shader_selector
*sel
= shader
->selector
;
1898 struct si_screen
*sscreen
= sel
->screen
;
1899 struct ac_llvm_compiler
*compiler
;
1900 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1902 if (thread_index
>= 0) {
1904 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1905 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1907 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1908 compiler
= &sscreen
->compiler
[thread_index
];
1913 assert(!low_priority
);
1914 compiler
= shader
->compiler_ctx_state
.compiler
;
1917 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
1918 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1920 shader
->compilation_failed
= true;
1924 if (shader
->compiler_ctx_state
.is_debug_context
) {
1925 FILE *f
= open_memstream(&shader
->shader_log
,
1926 &shader
->shader_log_size
);
1928 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1933 si_shader_init_pm4_state(sscreen
, shader
);
1936 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1938 struct si_shader
*shader
= (struct si_shader
*)job
;
1940 assert(thread_index
>= 0);
1942 si_build_shader_variant(shader
, thread_index
, true);
1945 static const struct si_shader_key zeroed
;
1947 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1948 struct si_shader_selector
*sel
,
1949 struct si_compiler_ctx_state
*compiler_state
,
1950 struct si_shader_key
*key
)
1952 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1955 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1960 /* We can leave the fence as permanently signaled because the
1961 * main part becomes visible globally only after it has been
1963 util_queue_fence_init(&main_part
->ready
);
1965 main_part
->selector
= sel
;
1966 main_part
->key
.as_es
= key
->as_es
;
1967 main_part
->key
.as_ls
= key
->as_ls
;
1968 main_part
->key
.as_ngg
= key
->as_ngg
;
1969 main_part
->is_monolithic
= false;
1971 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1972 main_part
, &compiler_state
->debug
) != 0) {
1982 * Select a shader variant according to the shader key.
1984 * \param optimized_or_none If the key describes an optimized shader variant and
1985 * the compilation isn't finished, don't select any
1986 * shader and return an error.
1988 int si_shader_select_with_key(struct si_screen
*sscreen
,
1989 struct si_shader_ctx_state
*state
,
1990 struct si_compiler_ctx_state
*compiler_state
,
1991 struct si_shader_key
*key
,
1993 bool optimized_or_none
)
1995 struct si_shader_selector
*sel
= state
->cso
;
1996 struct si_shader_selector
*previous_stage_sel
= NULL
;
1997 struct si_shader
*current
= state
->current
;
1998 struct si_shader
*iter
, *shader
= NULL
;
2001 /* Check if we don't need to change anything.
2002 * This path is also used for most shaders that don't need multiple
2003 * variants, it will cost just a computation of the key and this
2005 if (likely(current
&&
2006 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2007 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2008 if (current
->is_optimized
) {
2009 if (optimized_or_none
)
2012 memset(&key
->opt
, 0, sizeof(key
->opt
));
2013 goto current_not_ready
;
2016 util_queue_fence_wait(¤t
->ready
);
2019 return current
->compilation_failed
? -1 : 0;
2023 /* This must be done before the mutex is locked, because async GS
2024 * compilation calls this function too, and therefore must enter
2027 * Only wait if we are in a draw call. Don't wait if we are
2028 * in a compiler thread.
2030 if (thread_index
< 0)
2031 util_queue_fence_wait(&sel
->ready
);
2033 mtx_lock(&sel
->mutex
);
2035 /* Find the shader variant. */
2036 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2037 /* Don't check the "current" shader. We checked it above. */
2038 if (current
!= iter
&&
2039 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2040 mtx_unlock(&sel
->mutex
);
2042 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2043 /* If it's an optimized shader and its compilation has
2044 * been started but isn't done, use the unoptimized
2045 * shader so as not to cause a stall due to compilation.
2047 if (iter
->is_optimized
) {
2048 if (optimized_or_none
)
2050 memset(&key
->opt
, 0, sizeof(key
->opt
));
2054 util_queue_fence_wait(&iter
->ready
);
2057 if (iter
->compilation_failed
) {
2058 return -1; /* skip the draw call */
2061 state
->current
= iter
;
2066 /* Build a new shader. */
2067 shader
= CALLOC_STRUCT(si_shader
);
2069 mtx_unlock(&sel
->mutex
);
2073 util_queue_fence_init(&shader
->ready
);
2075 shader
->selector
= sel
;
2077 shader
->compiler_ctx_state
= *compiler_state
;
2079 /* If this is a merged shader, get the first shader's selector. */
2080 if (sscreen
->info
.chip_class
>= GFX9
) {
2081 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2082 previous_stage_sel
= key
->part
.tcs
.ls
;
2083 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2084 previous_stage_sel
= key
->part
.gs
.es
;
2086 /* We need to wait for the previous shader. */
2087 if (previous_stage_sel
&& thread_index
< 0)
2088 util_queue_fence_wait(&previous_stage_sel
->ready
);
2091 bool is_pure_monolithic
=
2092 sscreen
->use_monolithic_shaders
||
2093 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2095 /* Compile the main shader part if it doesn't exist. This can happen
2096 * if the initial guess was wrong.
2098 * The prim discard CS doesn't need the main shader part.
2100 if (!is_pure_monolithic
&&
2101 !key
->opt
.vs_as_prim_discard_cs
) {
2104 /* Make sure the main shader part is present. This is needed
2105 * for shaders that can be compiled as VS, LS, or ES, and only
2106 * one of them is compiled at creation.
2108 * It is also needed for GS, which can be compiled as non-NGG
2111 * For merged shaders, check that the starting shader's main
2114 if (previous_stage_sel
) {
2115 struct si_shader_key shader1_key
= zeroed
;
2117 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2118 shader1_key
.as_ls
= 1;
2119 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2120 shader1_key
.as_es
= 1;
2124 mtx_lock(&previous_stage_sel
->mutex
);
2125 ok
= si_check_missing_main_part(sscreen
,
2127 compiler_state
, &shader1_key
);
2128 mtx_unlock(&previous_stage_sel
->mutex
);
2132 ok
= si_check_missing_main_part(sscreen
, sel
,
2133 compiler_state
, key
);
2138 mtx_unlock(&sel
->mutex
);
2139 return -ENOMEM
; /* skip the draw call */
2143 /* Keep the reference to the 1st shader of merged shaders, so that
2144 * Gallium can't destroy it before we destroy the 2nd shader.
2146 * Set sctx = NULL, because it's unused if we're not releasing
2147 * the shader, and we don't have any sctx here.
2149 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2150 previous_stage_sel
);
2152 /* Monolithic-only shaders don't make a distinction between optimized
2153 * and unoptimized. */
2154 shader
->is_monolithic
=
2155 is_pure_monolithic
||
2156 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2158 /* The prim discard CS is always optimized. */
2159 shader
->is_optimized
=
2160 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2161 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2163 /* If it's an optimized shader, compile it asynchronously. */
2164 if (shader
->is_optimized
&& thread_index
< 0) {
2165 /* Compile it asynchronously. */
2166 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2167 shader
, &shader
->ready
,
2168 si_build_shader_variant_low_priority
, NULL
);
2170 /* Add only after the ready fence was reset, to guard against a
2171 * race with si_bind_XX_shader. */
2172 if (!sel
->last_variant
) {
2173 sel
->first_variant
= shader
;
2174 sel
->last_variant
= shader
;
2176 sel
->last_variant
->next_variant
= shader
;
2177 sel
->last_variant
= shader
;
2180 /* Use the default (unoptimized) shader for now. */
2181 memset(&key
->opt
, 0, sizeof(key
->opt
));
2182 mtx_unlock(&sel
->mutex
);
2184 if (sscreen
->options
.sync_compile
)
2185 util_queue_fence_wait(&shader
->ready
);
2187 if (optimized_or_none
)
2192 /* Reset the fence before adding to the variant list. */
2193 util_queue_fence_reset(&shader
->ready
);
2195 if (!sel
->last_variant
) {
2196 sel
->first_variant
= shader
;
2197 sel
->last_variant
= shader
;
2199 sel
->last_variant
->next_variant
= shader
;
2200 sel
->last_variant
= shader
;
2203 mtx_unlock(&sel
->mutex
);
2205 assert(!shader
->is_optimized
);
2206 si_build_shader_variant(shader
, thread_index
, false);
2208 util_queue_fence_signal(&shader
->ready
);
2210 if (!shader
->compilation_failed
)
2211 state
->current
= shader
;
2213 return shader
->compilation_failed
? -1 : 0;
2216 static int si_shader_select(struct pipe_context
*ctx
,
2217 struct si_shader_ctx_state
*state
,
2218 union si_vgt_stages_key stages_key
,
2219 struct si_compiler_ctx_state
*compiler_state
)
2221 struct si_context
*sctx
= (struct si_context
*)ctx
;
2222 struct si_shader_key key
;
2224 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2225 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2229 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2231 struct si_shader_key
*key
)
2233 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2235 switch (info
->processor
) {
2236 case PIPE_SHADER_VERTEX
:
2237 switch (next_shader
) {
2238 case PIPE_SHADER_GEOMETRY
:
2241 case PIPE_SHADER_TESS_CTRL
:
2242 case PIPE_SHADER_TESS_EVAL
:
2246 /* If POSITION isn't written, it can only be a HW VS
2247 * if streamout is used. If streamout isn't used,
2248 * assume that it's a HW LS. (the next shader is TCS)
2249 * This heuristic is needed for separate shader objects.
2251 if (!info
->writes_position
&& !streamout
)
2256 case PIPE_SHADER_TESS_EVAL
:
2257 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2258 !info
->writes_position
)
2265 * Compile the main shader part or the monolithic shader as part of
2266 * si_shader_selector initialization. Since it can be done asynchronously,
2267 * there is no way to report compile failures to applications.
2269 static void si_init_shader_selector_async(void *job
, int thread_index
)
2271 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2272 struct si_screen
*sscreen
= sel
->screen
;
2273 struct ac_llvm_compiler
*compiler
;
2274 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2276 assert(!debug
->debug_message
|| debug
->async
);
2277 assert(thread_index
>= 0);
2278 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2279 compiler
= &sscreen
->compiler
[thread_index
];
2284 /* Compile the main shader part for use with a prolog and/or epilog.
2285 * If this fails, the driver will try to compile a monolithic shader
2288 if (!sscreen
->use_monolithic_shaders
) {
2289 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2290 void *ir_binary
= NULL
;
2293 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2297 /* We can leave the fence signaled because use of the default
2298 * main part is guarded by the selector's ready fence. */
2299 util_queue_fence_init(&shader
->ready
);
2301 shader
->selector
= sel
;
2302 shader
->is_monolithic
= false;
2303 si_parse_next_shader_property(&sel
->info
,
2304 sel
->so
.num_outputs
!= 0,
2306 if (sscreen
->info
.chip_class
>= GFX10
&&
2307 !sscreen
->options
.disable_ngg
&&
2308 (((sel
->type
== PIPE_SHADER_VERTEX
||
2309 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2310 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2311 sel
->type
== PIPE_SHADER_GEOMETRY
))
2312 shader
->key
.as_ngg
= 1;
2314 if (sel
->tokens
|| sel
->nir
)
2315 ir_binary
= si_get_ir_binary(sel
);
2317 /* Try to load the shader from the shader cache. */
2318 mtx_lock(&sscreen
->shader_cache_mutex
);
2321 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2322 mtx_unlock(&sscreen
->shader_cache_mutex
);
2323 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2325 mtx_unlock(&sscreen
->shader_cache_mutex
);
2327 /* Compile the shader if it hasn't been loaded from the cache. */
2328 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2332 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2337 mtx_lock(&sscreen
->shader_cache_mutex
);
2338 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2340 mtx_unlock(&sscreen
->shader_cache_mutex
);
2344 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2346 /* Unset "outputs_written" flags for outputs converted to
2347 * DEFAULT_VAL, so that later inter-shader optimizations don't
2348 * try to eliminate outputs that don't exist in the final
2351 * This is only done if non-monolithic shaders are enabled.
2353 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2354 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2355 !shader
->key
.as_ls
&&
2356 !shader
->key
.as_es
) {
2359 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2360 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2362 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2365 unsigned name
= sel
->info
.output_semantic_name
[i
];
2366 unsigned index
= sel
->info
.output_semantic_index
[i
];
2370 case TGSI_SEMANTIC_GENERIC
:
2371 /* don't process indices the function can't handle */
2372 if (index
>= SI_MAX_IO_GENERIC
)
2376 id
= si_shader_io_get_unique_index(name
, index
, true);
2377 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2379 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2380 case TGSI_SEMANTIC_PSIZE
:
2381 case TGSI_SEMANTIC_CLIPVERTEX
:
2382 case TGSI_SEMANTIC_EDGEFLAG
:
2389 /* The GS copy shader is always pre-compiled. */
2390 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2391 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2392 if (!sel
->gs_copy_shader
) {
2393 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2397 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2401 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2402 struct util_queue_fence
*ready_fence
,
2403 struct si_compiler_ctx_state
*compiler_ctx_state
,
2404 void *job
, util_queue_execute_func execute
)
2406 util_queue_fence_init(ready_fence
);
2408 struct util_async_debug_callback async_debug
;
2410 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2412 si_can_dump_shader(sctx
->screen
, processor
);
2415 u_async_debug_init(&async_debug
);
2416 compiler_ctx_state
->debug
= async_debug
.base
;
2419 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2420 ready_fence
, execute
, NULL
);
2423 util_queue_fence_wait(ready_fence
);
2424 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2425 u_async_debug_cleanup(&async_debug
);
2428 if (sctx
->screen
->options
.sync_compile
)
2429 util_queue_fence_wait(ready_fence
);
2432 /* Return descriptor slot usage masks from the given shader info. */
2433 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2434 uint32_t *const_and_shader_buffers
,
2435 uint64_t *samplers_and_images
)
2437 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2439 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2440 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2441 /* two 8-byte images share one 16-byte slot */
2442 num_images
= align(util_last_bit(info
->images_declared
), 2);
2443 num_samplers
= util_last_bit(info
->samplers_declared
);
2445 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2446 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2447 *const_and_shader_buffers
=
2448 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2450 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2451 start
= si_get_image_slot(num_images
- 1) / 2;
2452 *samplers_and_images
=
2453 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2456 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2457 const struct pipe_shader_state
*state
)
2459 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2460 struct si_context
*sctx
= (struct si_context
*)ctx
;
2461 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2467 pipe_reference_init(&sel
->reference
, 1);
2468 sel
->screen
= sscreen
;
2469 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2470 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2472 sel
->so
= state
->stream_output
;
2474 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2475 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2481 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2482 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2484 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2486 sel
->nir
= state
->ir
.nir
;
2488 si_nir_opts(sel
->nir
);
2489 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2490 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2493 sel
->type
= sel
->info
.processor
;
2494 p_atomic_inc(&sscreen
->num_shaders_created
);
2495 si_get_active_slot_masks(&sel
->info
,
2496 &sel
->active_const_and_shader_buffers
,
2497 &sel
->active_samplers_and_images
);
2499 /* Record which streamout buffers are enabled. */
2500 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2501 sel
->enabled_streamout_buffer_mask
|=
2502 (1 << sel
->so
.output
[i
].output_buffer
) <<
2503 (sel
->so
.output
[i
].stream
* 4);
2506 /* The prolog is a no-op if there are no inputs. */
2507 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2508 sel
->info
.num_inputs
&&
2509 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2511 sel
->force_correct_derivs_after_kill
=
2512 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2513 sel
->info
.uses_derivatives
&&
2514 sel
->info
.uses_kill
&&
2515 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2517 sel
->prim_discard_cs_allowed
=
2518 sel
->type
== PIPE_SHADER_VERTEX
&&
2519 !sel
->info
.uses_bindless_images
&&
2520 !sel
->info
.uses_bindless_samplers
&&
2521 !sel
->info
.writes_memory
&&
2522 !sel
->info
.writes_viewport_index
&&
2523 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2524 !sel
->so
.num_outputs
;
2526 /* Set which opcode uses which (i,j) pair. */
2527 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2528 sel
->info
.uses_persp_centroid
= true;
2530 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2531 sel
->info
.uses_linear_centroid
= true;
2533 if (sel
->info
.uses_persp_opcode_interp_offset
||
2534 sel
->info
.uses_persp_opcode_interp_sample
)
2535 sel
->info
.uses_persp_center
= true;
2537 if (sel
->info
.uses_linear_opcode_interp_offset
||
2538 sel
->info
.uses_linear_opcode_interp_sample
)
2539 sel
->info
.uses_linear_center
= true;
2541 switch (sel
->type
) {
2542 case PIPE_SHADER_GEOMETRY
:
2543 sel
->gs_output_prim
=
2544 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2545 sel
->gs_max_out_vertices
=
2546 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2547 sel
->gs_num_invocations
=
2548 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2549 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2550 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2551 sel
->gs_max_out_vertices
;
2553 sel
->max_gs_stream
= 0;
2554 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2555 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2556 sel
->so
.output
[i
].stream
);
2558 sel
->gs_input_verts_per_prim
=
2559 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2562 case PIPE_SHADER_TESS_CTRL
:
2563 /* Always reserve space for these. */
2564 sel
->patch_outputs_written
|=
2565 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2566 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2568 case PIPE_SHADER_VERTEX
:
2569 case PIPE_SHADER_TESS_EVAL
:
2570 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2571 unsigned name
= sel
->info
.output_semantic_name
[i
];
2572 unsigned index
= sel
->info
.output_semantic_index
[i
];
2575 case TGSI_SEMANTIC_TESSINNER
:
2576 case TGSI_SEMANTIC_TESSOUTER
:
2577 case TGSI_SEMANTIC_PATCH
:
2578 sel
->patch_outputs_written
|=
2579 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2582 case TGSI_SEMANTIC_GENERIC
:
2583 /* don't process indices the function can't handle */
2584 if (index
>= SI_MAX_IO_GENERIC
)
2588 sel
->outputs_written
|=
2589 1ull << si_shader_io_get_unique_index(name
, index
, false);
2590 sel
->outputs_written_before_ps
|=
2591 1ull << si_shader_io_get_unique_index(name
, index
, true);
2593 case TGSI_SEMANTIC_EDGEFLAG
:
2597 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2598 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2600 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2601 * will start on a different bank. (except for the maximum 32*16).
2603 if (sel
->lshs_vertex_stride
< 32*16)
2604 sel
->lshs_vertex_stride
+= 4;
2606 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2607 * conflicts, i.e. each vertex will start at a different bank.
2609 if (sctx
->chip_class
>= GFX9
)
2610 sel
->esgs_itemsize
+= 4;
2612 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2615 case PIPE_SHADER_FRAGMENT
:
2616 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2617 unsigned name
= sel
->info
.input_semantic_name
[i
];
2618 unsigned index
= sel
->info
.input_semantic_index
[i
];
2621 case TGSI_SEMANTIC_GENERIC
:
2622 /* don't process indices the function can't handle */
2623 if (index
>= SI_MAX_IO_GENERIC
)
2628 1ull << si_shader_io_get_unique_index(name
, index
, true);
2630 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2635 for (i
= 0; i
< 8; i
++)
2636 if (sel
->info
.colors_written
& (1 << i
))
2637 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2639 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2640 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2641 int index
= sel
->info
.input_semantic_index
[i
];
2642 sel
->color_attr_index
[index
] = i
;
2648 /* PA_CL_VS_OUT_CNTL */
2650 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2651 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2652 sel
->pa_cl_vs_out_cntl
=
2653 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2654 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2655 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2656 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2657 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2658 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2659 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2660 SIX_BITS
: sel
->info
.clipdist_writemask
;
2661 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2662 sel
->info
.num_written_clipdistance
;
2664 /* DB_SHADER_CONTROL */
2665 sel
->db_shader_control
=
2666 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2667 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2668 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2669 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2671 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2672 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2673 sel
->db_shader_control
|=
2674 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2676 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2677 sel
->db_shader_control
|=
2678 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2682 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2684 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2685 * --|-----------|------------|------------|--------------------|-------------------|-------------
2686 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2687 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2688 * 2 | false | true | n/a | LateZ | 1 | 0
2689 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2690 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2692 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2693 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2695 * Don't use ReZ without profiling !!!
2697 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2700 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2702 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2703 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2704 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2705 } else if (sel
->info
.writes_memory
) {
2707 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2708 S_02880C_EXEC_ON_HIER_FAIL(1);
2711 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2714 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2716 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2717 &sel
->compiler_ctx_state
, sel
,
2718 si_init_shader_selector_async
);
2722 static void si_update_streamout_state(struct si_context
*sctx
)
2724 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2726 if (!shader_with_so
)
2729 sctx
->streamout
.enabled_stream_buffers_mask
=
2730 shader_with_so
->enabled_streamout_buffer_mask
;
2731 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2734 static void si_update_clip_regs(struct si_context
*sctx
,
2735 struct si_shader_selector
*old_hw_vs
,
2736 struct si_shader
*old_hw_vs_variant
,
2737 struct si_shader_selector
*next_hw_vs
,
2738 struct si_shader
*next_hw_vs_variant
)
2742 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2743 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2744 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2745 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2746 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2747 !old_hw_vs_variant
||
2748 !next_hw_vs_variant
||
2749 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2750 next_hw_vs_variant
->key
.opt
.clip_disable
))
2751 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2754 static void si_update_common_shader_state(struct si_context
*sctx
)
2756 sctx
->uses_bindless_samplers
=
2757 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2758 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2759 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2760 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2761 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2762 sctx
->uses_bindless_images
=
2763 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2764 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2765 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2766 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2767 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2768 sctx
->do_update_shaders
= true;
2771 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2773 struct si_context
*sctx
= (struct si_context
*)ctx
;
2774 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2775 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2776 struct si_shader_selector
*sel
= state
;
2778 if (sctx
->vs_shader
.cso
== sel
)
2781 sctx
->vs_shader
.cso
= sel
;
2782 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2783 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2785 si_update_common_shader_state(sctx
);
2786 si_update_vs_viewport_state(sctx
);
2787 si_set_active_descriptors_for_shader(sctx
, sel
);
2788 si_update_streamout_state(sctx
);
2789 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2790 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2793 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2795 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2796 (sctx
->tes_shader
.cso
&&
2797 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2798 (sctx
->tcs_shader
.cso
&&
2799 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2800 (sctx
->gs_shader
.cso
&&
2801 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2802 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2803 sctx
->ps_shader
.cso
->info
.uses_primid
);
2806 static bool si_update_ngg(struct si_context
*sctx
)
2808 if (sctx
->chip_class
<= GFX9
||
2809 sctx
->screen
->options
.disable_ngg
)
2812 bool new_ngg
= true;
2814 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2815 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
2816 sctx
->gs_shader
.cso
->gs_num_invocations
* sctx
->gs_shader
.cso
->gs_max_out_vertices
> 256)
2819 if (new_ngg
!= sctx
->ngg
) {
2820 sctx
->ngg
= new_ngg
;
2821 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2827 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2829 struct si_context
*sctx
= (struct si_context
*)ctx
;
2830 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2831 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2832 struct si_shader_selector
*sel
= state
;
2833 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2836 if (sctx
->gs_shader
.cso
== sel
)
2839 sctx
->gs_shader
.cso
= sel
;
2840 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2841 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2843 si_update_common_shader_state(sctx
);
2844 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2846 ngg_changed
= si_update_ngg(sctx
);
2847 if (ngg_changed
|| enable_changed
)
2848 si_shader_change_notify(sctx
);
2849 if (enable_changed
) {
2850 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2851 si_update_tess_uses_prim_id(sctx
);
2853 si_update_vs_viewport_state(sctx
);
2854 si_set_active_descriptors_for_shader(sctx
, sel
);
2855 si_update_streamout_state(sctx
);
2856 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2857 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2860 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2862 struct si_context
*sctx
= (struct si_context
*)ctx
;
2863 struct si_shader_selector
*sel
= state
;
2864 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2866 if (sctx
->tcs_shader
.cso
== sel
)
2869 sctx
->tcs_shader
.cso
= sel
;
2870 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2871 si_update_tess_uses_prim_id(sctx
);
2873 si_update_common_shader_state(sctx
);
2876 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2878 si_set_active_descriptors_for_shader(sctx
, sel
);
2881 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2883 struct si_context
*sctx
= (struct si_context
*)ctx
;
2884 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2885 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2886 struct si_shader_selector
*sel
= state
;
2887 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2889 if (sctx
->tes_shader
.cso
== sel
)
2892 sctx
->tes_shader
.cso
= sel
;
2893 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2894 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2895 si_update_tess_uses_prim_id(sctx
);
2897 si_update_common_shader_state(sctx
);
2898 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2900 if (enable_changed
) {
2901 si_update_ngg(sctx
);
2902 si_shader_change_notify(sctx
);
2903 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2905 si_update_vs_viewport_state(sctx
);
2906 si_set_active_descriptors_for_shader(sctx
, sel
);
2907 si_update_streamout_state(sctx
);
2908 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2909 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2912 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2914 struct si_context
*sctx
= (struct si_context
*)ctx
;
2915 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2916 struct si_shader_selector
*sel
= state
;
2918 /* skip if supplied shader is one already in use */
2922 sctx
->ps_shader
.cso
= sel
;
2923 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2925 si_update_common_shader_state(sctx
);
2927 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2928 si_update_tess_uses_prim_id(sctx
);
2931 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2932 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2934 if (sctx
->screen
->has_out_of_order_rast
&&
2936 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2937 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2938 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2939 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2941 si_set_active_descriptors_for_shader(sctx
, sel
);
2942 si_update_ps_colorbuf0_slot(sctx
);
2945 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2947 if (shader
->is_optimized
) {
2948 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2952 util_queue_fence_destroy(&shader
->ready
);
2955 switch (shader
->selector
->type
) {
2956 case PIPE_SHADER_VERTEX
:
2957 if (shader
->key
.as_ls
) {
2958 assert(sctx
->chip_class
<= GFX8
);
2959 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2960 } else if (shader
->key
.as_es
) {
2961 assert(sctx
->chip_class
<= GFX8
);
2962 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2964 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2967 case PIPE_SHADER_TESS_CTRL
:
2968 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2970 case PIPE_SHADER_TESS_EVAL
:
2971 if (shader
->key
.as_es
) {
2972 assert(sctx
->chip_class
<= GFX8
);
2973 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2975 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2978 case PIPE_SHADER_GEOMETRY
:
2979 if (shader
->is_gs_copy_shader
)
2980 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2982 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2984 case PIPE_SHADER_FRAGMENT
:
2985 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2990 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2991 si_shader_destroy(shader
);
2995 void si_destroy_shader_selector(struct si_context
*sctx
,
2996 struct si_shader_selector
*sel
)
2998 struct si_shader
*p
= sel
->first_variant
, *c
;
2999 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3000 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3001 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3002 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3003 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3004 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3007 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3009 if (current_shader
[sel
->type
]->cso
== sel
) {
3010 current_shader
[sel
->type
]->cso
= NULL
;
3011 current_shader
[sel
->type
]->current
= NULL
;
3015 c
= p
->next_variant
;
3016 si_delete_shader(sctx
, p
);
3020 if (sel
->main_shader_part
)
3021 si_delete_shader(sctx
, sel
->main_shader_part
);
3022 if (sel
->main_shader_part_ls
)
3023 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3024 if (sel
->main_shader_part_es
)
3025 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3026 if (sel
->main_shader_part_ngg
)
3027 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3028 if (sel
->gs_copy_shader
)
3029 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3031 util_queue_fence_destroy(&sel
->ready
);
3032 mtx_destroy(&sel
->mutex
);
3034 ralloc_free(sel
->nir
);
3038 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3040 struct si_context
*sctx
= (struct si_context
*)ctx
;
3041 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3043 si_shader_selector_reference(sctx
, &sel
, NULL
);
3046 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3047 struct si_shader
*vs
, unsigned name
,
3048 unsigned index
, unsigned interpolate
)
3050 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3051 unsigned j
, offset
, ps_input_cntl
= 0;
3053 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3054 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3055 name
== TGSI_SEMANTIC_PRIMID
)
3056 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3058 if (name
== TGSI_SEMANTIC_PCOORD
||
3059 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3060 sctx
->sprite_coord_enable
& (1 << index
))) {
3061 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3064 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3065 if (name
== vsinfo
->output_semantic_name
[j
] &&
3066 index
== vsinfo
->output_semantic_index
[j
]) {
3067 offset
= vs
->info
.vs_output_param_offset
[j
];
3069 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3070 /* The input is loaded from parameter memory. */
3071 ps_input_cntl
|= S_028644_OFFSET(offset
);
3072 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3073 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3074 /* This can happen with depth-only rendering. */
3077 /* The input is a DEFAULT_VAL constant. */
3078 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3079 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3080 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3083 ps_input_cntl
= S_028644_OFFSET(0x20) |
3084 S_028644_DEFAULT_VAL(offset
);
3090 if (name
== TGSI_SEMANTIC_PRIMID
)
3091 /* PrimID is written after the last output. */
3092 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3093 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3094 /* No corresponding output found, load defaults into input.
3095 * Don't set any other bits.
3096 * (FLAT_SHADE=1 completely changes behavior) */
3097 ps_input_cntl
= S_028644_OFFSET(0x20);
3098 /* D3D 9 behaviour. GL is undefined */
3099 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3100 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3102 return ps_input_cntl
;
3105 static void si_emit_spi_map(struct si_context
*sctx
)
3107 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3108 struct si_shader
*vs
= si_get_vs_state(sctx
);
3109 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3110 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3111 unsigned spi_ps_input_cntl
[32];
3113 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3116 num_interp
= si_get_ps_num_interp(ps
);
3117 assert(num_interp
> 0);
3119 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3120 unsigned name
= psinfo
->input_semantic_name
[i
];
3121 unsigned index
= psinfo
->input_semantic_index
[i
];
3122 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3124 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3125 index
, interpolate
);
3127 if (name
== TGSI_SEMANTIC_COLOR
) {
3128 assert(index
< ARRAY_SIZE(bcol_interp
));
3129 bcol_interp
[index
] = interpolate
;
3133 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3134 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3136 for (i
= 0; i
< 2; i
++) {
3137 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3140 spi_ps_input_cntl
[num_written
++] =
3141 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3145 assert(num_interp
== num_written
);
3147 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3148 /* Dota 2: Only ~16% of SPI map updates set different values. */
3149 /* Talos: Only ~9% of SPI map updates set different values. */
3150 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3151 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3153 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3155 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3156 sctx
->context_roll
= true;
3160 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3162 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3164 if (sctx
->init_config_has_vgt_flush
)
3167 /* Done by Vulkan before VGT_FLUSH. */
3168 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3169 si_pm4_cmd_add(sctx
->init_config
,
3170 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3171 si_pm4_cmd_end(sctx
->init_config
, false);
3173 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3174 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3175 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3176 si_pm4_cmd_end(sctx
->init_config
, false);
3177 sctx
->init_config_has_vgt_flush
= true;
3180 /* Initialize state related to ESGS / GSVS ring buffers */
3181 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3183 struct si_shader_selector
*es
=
3184 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3185 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3186 struct si_pm4_state
*pm4
;
3188 /* Chip constants. */
3189 unsigned num_se
= sctx
->screen
->info
.max_se
;
3190 unsigned wave_size
= 64;
3191 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3192 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3193 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3195 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3196 unsigned alignment
= 256 * num_se
;
3197 /* The maximum size is 63.999 MB per SE. */
3198 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3200 /* Calculate the minimum size. */
3201 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3202 wave_size
, alignment
);
3204 /* These are recommended sizes, not minimum sizes. */
3205 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3206 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3207 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3208 gs
->max_gsvs_emit_size
;
3210 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3211 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3212 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3214 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3215 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3217 /* Some rings don't have to be allocated if shaders don't use them.
3218 * (e.g. no varyings between ES and GS or GS and VS)
3220 * GFX9 doesn't have the ESGS ring.
3222 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3224 (!sctx
->esgs_ring
||
3225 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3226 bool update_gsvs
= gsvs_ring_size
&&
3227 (!sctx
->gsvs_ring
||
3228 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3230 if (!update_esgs
&& !update_gsvs
)
3234 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3236 pipe_aligned_buffer_create(sctx
->b
.screen
,
3237 SI_RESOURCE_FLAG_UNMAPPABLE
,
3239 esgs_ring_size
, alignment
);
3240 if (!sctx
->esgs_ring
)
3245 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3247 pipe_aligned_buffer_create(sctx
->b
.screen
,
3248 SI_RESOURCE_FLAG_UNMAPPABLE
,
3250 gsvs_ring_size
, alignment
);
3251 if (!sctx
->gsvs_ring
)
3255 /* Create the "init_config_gs_rings" state. */
3256 pm4
= CALLOC_STRUCT(si_pm4_state
);
3260 if (sctx
->chip_class
>= GFX7
) {
3261 if (sctx
->esgs_ring
) {
3262 assert(sctx
->chip_class
<= GFX8
);
3263 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3264 sctx
->esgs_ring
->width0
/ 256);
3266 if (sctx
->gsvs_ring
)
3267 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3268 sctx
->gsvs_ring
->width0
/ 256);
3270 if (sctx
->esgs_ring
)
3271 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3272 sctx
->esgs_ring
->width0
/ 256);
3273 if (sctx
->gsvs_ring
)
3274 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3275 sctx
->gsvs_ring
->width0
/ 256);
3278 /* Set the state. */
3279 if (sctx
->init_config_gs_rings
)
3280 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3281 sctx
->init_config_gs_rings
= pm4
;
3283 if (!sctx
->init_config_has_vgt_flush
) {
3284 si_init_config_add_vgt_flush(sctx
);
3285 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3288 /* Flush the context to re-emit both init_config states. */
3289 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3290 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3292 /* Set ring bindings. */
3293 if (sctx
->esgs_ring
) {
3294 assert(sctx
->chip_class
<= GFX8
);
3295 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3296 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3297 true, true, 4, 64, 0);
3298 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3299 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3300 false, false, 0, 0, 0);
3302 if (sctx
->gsvs_ring
) {
3303 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3304 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3305 false, false, 0, 0, 0);
3311 static void si_shader_lock(struct si_shader
*shader
)
3313 mtx_lock(&shader
->selector
->mutex
);
3314 if (shader
->previous_stage_sel
) {
3315 assert(shader
->previous_stage_sel
!= shader
->selector
);
3316 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3320 static void si_shader_unlock(struct si_shader
*shader
)
3322 if (shader
->previous_stage_sel
)
3323 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3324 mtx_unlock(&shader
->selector
->mutex
);
3328 * @returns 1 if \p sel has been updated to use a new scratch buffer
3330 * < 0 if there was a failure
3332 static int si_update_scratch_buffer(struct si_context
*sctx
,
3333 struct si_shader
*shader
)
3335 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3340 /* This shader doesn't need a scratch buffer */
3341 if (shader
->config
.scratch_bytes_per_wave
== 0)
3344 /* Prevent race conditions when updating:
3345 * - si_shader::scratch_bo
3346 * - si_shader::binary::code
3347 * - si_shader::previous_stage::binary::code.
3349 si_shader_lock(shader
);
3351 /* This shader is already configured to use the current
3352 * scratch buffer. */
3353 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3354 si_shader_unlock(shader
);
3358 assert(sctx
->scratch_buffer
);
3360 /* Replace the shader bo with a new bo that has the relocs applied. */
3361 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3362 si_shader_unlock(shader
);
3366 /* Update the shader state to use the new shader bo. */
3367 si_shader_init_pm4_state(sctx
->screen
, shader
);
3369 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3371 si_shader_unlock(shader
);
3375 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3377 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3380 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3382 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3385 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3387 if (!sctx
->tes_shader
.cso
)
3388 return NULL
; /* tessellation disabled */
3390 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3391 sctx
->fixed_func_tcs_shader
.current
;
3394 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3398 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3399 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3400 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3401 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3403 if (sctx
->tes_shader
.cso
) {
3404 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3406 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3411 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3413 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3416 /* Update the shaders, so that they are using the latest scratch.
3417 * The scratch buffer may have been changed since these shaders were
3418 * last used, so we still need to try to update them, even if they
3419 * require scratch buffers smaller than the current size.
3421 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3425 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3427 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3431 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3433 r
= si_update_scratch_buffer(sctx
, tcs
);
3437 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3439 /* VS can be bound as LS, ES, or VS. */
3440 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3444 if (sctx
->tes_shader
.current
)
3445 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3446 else if (sctx
->gs_shader
.current
)
3447 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3449 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3452 /* TES can be bound as ES or VS. */
3453 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3457 if (sctx
->gs_shader
.current
)
3458 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3460 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3466 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3468 unsigned current_scratch_buffer_size
=
3469 si_get_current_scratch_buffer_size(sctx
);
3470 unsigned scratch_bytes_per_wave
=
3471 si_get_max_scratch_bytes_per_wave(sctx
);
3472 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3473 sctx
->scratch_waves
;
3474 unsigned spi_tmpring_size
;
3476 if (scratch_needed_size
> 0) {
3477 if (scratch_needed_size
> current_scratch_buffer_size
) {
3478 /* Create a bigger scratch buffer */
3479 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3481 sctx
->scratch_buffer
=
3482 si_aligned_buffer_create(&sctx
->screen
->b
,
3483 SI_RESOURCE_FLAG_UNMAPPABLE
,
3485 scratch_needed_size
, 256);
3486 if (!sctx
->scratch_buffer
)
3489 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3490 si_context_add_resource_size(sctx
,
3491 &sctx
->scratch_buffer
->b
.b
);
3494 if (!si_update_scratch_relocs(sctx
))
3498 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3499 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3500 "scratch size should already be aligned correctly.");
3502 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3503 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3504 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3505 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3506 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3511 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3513 assert(!sctx
->tess_rings
);
3515 /* The address must be aligned to 2^19, because the shader only
3516 * receives the high 13 bits.
3518 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3519 SI_RESOURCE_FLAG_32BIT
,
3521 sctx
->screen
->tess_offchip_ring_size
+
3522 sctx
->screen
->tess_factor_ring_size
,
3524 if (!sctx
->tess_rings
)
3527 si_init_config_add_vgt_flush(sctx
);
3529 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3530 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3532 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3533 sctx
->screen
->tess_offchip_ring_size
;
3535 /* Append these registers to the init config state. */
3536 if (sctx
->chip_class
>= GFX7
) {
3537 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3538 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3539 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3541 if (sctx
->chip_class
>= GFX9
)
3542 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3543 S_030944_BASE_HI(factor_va
>> 40));
3544 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3545 sctx
->screen
->vgt_hs_offchip_param
);
3547 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3548 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3549 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3551 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3552 sctx
->screen
->vgt_hs_offchip_param
);
3555 /* Flush the context to re-emit the init_config state.
3556 * This is done only once in a lifetime of a context.
3558 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3559 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3560 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3563 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3564 union si_vgt_stages_key key
)
3566 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3567 uint32_t stages
= 0;
3570 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3571 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3574 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3577 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3579 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3580 } else if (key
.u
.gs
) {
3581 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3583 } else if (key
.u
.ngg
) {
3584 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3588 stages
|= S_028B54_PRIMGEN_EN(1);
3589 if (key
.u
.streamout
)
3590 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3591 } else if (key
.u
.gs
)
3592 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3594 if (screen
->info
.chip_class
>= GFX9
)
3595 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3597 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3601 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3602 union si_vgt_stages_key key
)
3604 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3606 if (unlikely(!*pm4
))
3607 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3608 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3611 bool si_update_shaders(struct si_context
*sctx
)
3613 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3614 struct si_compiler_ctx_state compiler_state
;
3615 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3616 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3617 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3618 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3619 union si_vgt_stages_key key
;
3620 unsigned old_spi_shader_col_format
=
3621 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3624 compiler_state
.compiler
= &sctx
->compiler
;
3625 compiler_state
.debug
= sctx
->debug
;
3626 compiler_state
.is_debug_context
= sctx
->is_debug
;
3630 if (sctx
->tes_shader
.cso
)
3632 if (sctx
->gs_shader
.cso
)
3635 if (sctx
->chip_class
>= GFX10
) {
3636 key
.u
.ngg
= sctx
->ngg
;
3638 if (sctx
->gs_shader
.cso
)
3639 key
.u
.streamout
= !!sctx
->gs_shader
.cso
->so
.num_outputs
;
3640 else if (sctx
->tes_shader
.cso
)
3641 key
.u
.streamout
= !!sctx
->tes_shader
.cso
->so
.num_outputs
;
3643 key
.u
.streamout
= !!sctx
->vs_shader
.cso
->so
.num_outputs
;
3646 /* Update TCS and TES. */
3647 if (sctx
->tes_shader
.cso
) {
3648 if (!sctx
->tess_rings
) {
3649 si_init_tess_factor_ring(sctx
);
3650 if (!sctx
->tess_rings
)
3654 if (sctx
->tcs_shader
.cso
) {
3655 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3659 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3661 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3662 sctx
->fixed_func_tcs_shader
.cso
=
3663 si_create_fixed_func_tcs(sctx
);
3664 if (!sctx
->fixed_func_tcs_shader
.cso
)
3668 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3669 key
, &compiler_state
);
3672 si_pm4_bind_state(sctx
, hs
,
3673 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3676 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3677 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3681 if (sctx
->gs_shader
.cso
) {
3683 assert(sctx
->chip_class
<= GFX8
);
3684 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3685 } else if (key
.u
.ngg
) {
3686 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3688 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3692 if (sctx
->chip_class
<= GFX8
)
3693 si_pm4_bind_state(sctx
, ls
, NULL
);
3694 si_pm4_bind_state(sctx
, hs
, NULL
);
3698 if (sctx
->gs_shader
.cso
) {
3699 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3702 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3704 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3706 if (!si_update_gs_ring_buffers(sctx
))
3709 si_pm4_bind_state(sctx
, vs
, NULL
);
3713 si_pm4_bind_state(sctx
, gs
, NULL
);
3714 if (sctx
->chip_class
<= GFX8
)
3715 si_pm4_bind_state(sctx
, es
, NULL
);
3720 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3721 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3725 if (!key
.u
.tess
&& !key
.u
.gs
) {
3727 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3728 si_pm4_bind_state(sctx
, vs
, NULL
);
3730 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3732 } else if (sctx
->tes_shader
.cso
) {
3733 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3735 assert(sctx
->gs_shader
.cso
);
3736 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3740 si_update_vgt_shader_config(sctx
, key
);
3742 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3743 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3745 if (sctx
->ps_shader
.cso
) {
3746 unsigned db_shader_control
;
3748 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3751 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3754 sctx
->ps_shader
.cso
->db_shader_control
|
3755 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3757 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3758 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3759 sctx
->flatshade
!= rs
->flatshade
) {
3760 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3761 sctx
->flatshade
= rs
->flatshade
;
3762 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3765 if (sctx
->screen
->rbplus_allowed
&&
3766 si_pm4_state_changed(sctx
, ps
) &&
3768 old_spi_shader_col_format
!=
3769 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3770 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3772 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3773 sctx
->ps_db_shader_control
= db_shader_control
;
3774 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3775 if (sctx
->screen
->dpbb_allowed
)
3776 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3779 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3780 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3781 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3783 if (sctx
->chip_class
== GFX6
)
3784 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3786 if (sctx
->framebuffer
.nr_samples
<= 1)
3787 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3791 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3792 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3793 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3794 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3795 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3796 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3797 if (!si_update_spi_tmpring_size(sctx
))
3801 if (sctx
->chip_class
>= GFX7
) {
3802 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3803 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3804 else if (!sctx
->queued
.named
.ls
)
3805 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3807 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3808 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3809 else if (!sctx
->queued
.named
.hs
)
3810 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3812 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3813 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3814 else if (!sctx
->queued
.named
.es
)
3815 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3817 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3818 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3819 else if (!sctx
->queued
.named
.gs
)
3820 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3822 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3823 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3824 else if (!sctx
->queued
.named
.vs
)
3825 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3827 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3828 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3829 else if (!sctx
->queued
.named
.ps
)
3830 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3833 sctx
->do_update_shaders
= false;
3837 static void si_emit_scratch_state(struct si_context
*sctx
)
3839 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3841 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3842 sctx
->spi_tmpring_size
);
3844 if (sctx
->scratch_buffer
) {
3845 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3846 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3847 RADEON_PRIO_SCRATCH_BUFFER
);
3851 void si_init_shader_functions(struct si_context
*sctx
)
3853 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3854 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3856 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3857 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3858 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3859 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3860 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3862 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3863 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3864 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3865 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3866 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3868 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3869 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3870 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3871 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3872 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;