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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10 ||
422 sscreen->info.chip_class >= GFX10)
423 return;
424
425 /* VS as VS, or VS as ES: */
426 if ((type == PIPE_SHADER_VERTEX &&
427 (!shader ||
428 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
429 /* TES as VS, or TES as ES: */
430 type == PIPE_SHADER_TESS_EVAL) {
431 unsigned vtx_reuse_depth = 30;
432
433 if (type == PIPE_SHADER_TESS_EVAL &&
434 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD)
436 vtx_reuse_depth = 14;
437
438 assert(pm4->shader);
439 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
440 }
441 }
442
443 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
444 {
445 if (shader->pm4)
446 si_pm4_clear_state(shader->pm4);
447 else
448 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
449
450 if (shader->pm4) {
451 shader->pm4->shader = shader;
452 return shader->pm4;
453 } else {
454 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
455 return NULL;
456 }
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs + 1;
463 }
464
465 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
466 {
467 struct si_pm4_state *pm4;
468 unsigned vgpr_comp_cnt;
469 uint64_t va;
470
471 assert(sscreen->info.chip_class <= GFX8);
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 */
484 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
485
486 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
487 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
488
489 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
490 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader->config.float_mode);
494 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
495 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
496 }
497
498 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
499 {
500 struct si_pm4_state *pm4;
501 uint64_t va;
502 unsigned ls_vgpr_comp_cnt = 0;
503
504 pm4 = si_get_shader_pm4_state(shader);
505 if (!pm4)
506 return;
507
508 va = shader->bo->gpu_address;
509 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 if (sscreen->info.chip_class >= GFX9) {
512 if (sscreen->info.chip_class >= GFX10) {
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515 } else {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518 }
519
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
524 * be loaded.
525 */
526 ls_vgpr_comp_cnt = 1;
527 if (shader->info.uses_instanceid) {
528 if (sscreen->info.chip_class >= GFX10)
529 ls_vgpr_comp_cnt = 3;
530 else
531 ls_vgpr_comp_cnt = 2;
532 }
533
534 unsigned num_user_sgprs =
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(num_user_sgprs) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540
541 if (sscreen->info.chip_class >= GFX10)
542 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
543 else
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
545 } else {
546 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
553 }
554
555 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
556 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
557 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
558 (sscreen->info.chip_class <= GFX9 ?
559 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
560 S_00B428_DX10_CLAMP(1) |
561 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
562 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
563 S_00B428_FLOAT_MODE(shader->config.float_mode) |
564 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
565
566 if (sscreen->info.chip_class <= GFX8) {
567 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
568 shader->config.rsrc2);
569 }
570 }
571
572 static void si_emit_shader_es(struct si_context *sctx)
573 {
574 struct si_shader *shader = sctx->queued.named.es->shader;
575 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
576
577 if (!shader)
578 return;
579
580 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
581 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
582 shader->selector->esgs_itemsize / 4);
583
584 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
585 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
586 SI_TRACKED_VGT_TF_PARAM,
587 shader->vgt_tf_param);
588
589 if (shader->vgt_vertex_reuse_block_cntl)
590 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
591 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 shader->vgt_vertex_reuse_block_cntl);
593
594 if (initial_cdw != sctx->gfx_cs->current.cdw)
595 sctx->context_roll = true;
596 }
597
598 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
599 {
600 struct si_pm4_state *pm4;
601 unsigned num_user_sgprs;
602 unsigned vgpr_comp_cnt;
603 uint64_t va;
604 unsigned oc_lds_en;
605
606 assert(sscreen->info.chip_class <= GFX8);
607
608 pm4 = si_get_shader_pm4_state(shader);
609 if (!pm4)
610 return;
611
612 pm4->atom.emit = si_emit_shader_es;
613 va = shader->bo->gpu_address;
614 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
615
616 if (shader->selector->type == PIPE_SHADER_VERTEX) {
617 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
618 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
619 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
620 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
621 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
622 num_user_sgprs = SI_TES_NUM_USER_SGPR;
623 } else
624 unreachable("invalid shader selector type");
625
626 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
627
628 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
629 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
630 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
631 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
632 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
633 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
634 S_00B328_DX10_CLAMP(1) |
635 S_00B328_FLOAT_MODE(shader->config.float_mode));
636 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
637 S_00B32C_USER_SGPR(num_user_sgprs) |
638 S_00B32C_OC_LDS_EN(oc_lds_en) |
639 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
640
641 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
642 si_set_tesseval_regs(sscreen, shader->selector, pm4);
643
644 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
645 }
646
647 void gfx9_get_gs_info(struct si_shader_selector *es,
648 struct si_shader_selector *gs,
649 struct gfx9_gs_info *out)
650 {
651 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
652 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
653 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
654 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
655
656 /* All these are in dwords: */
657 /* We can't allow using the whole LDS, because GS waves compete with
658 * other shader stages for LDS space. */
659 const unsigned max_lds_size = 8 * 1024;
660 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
661 unsigned esgs_lds_size;
662
663 /* All these are per subgroup: */
664 const unsigned max_out_prims = 32 * 1024;
665 const unsigned max_es_verts = 255;
666 const unsigned ideal_gs_prims = 64;
667 unsigned max_gs_prims, gs_prims;
668 unsigned min_es_verts, es_verts, worst_case_es_verts;
669
670 if (uses_adjacency || gs_num_invocations > 1)
671 max_gs_prims = 127 / gs_num_invocations;
672 else
673 max_gs_prims = 255;
674
675 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
676 * Make sure we don't go over the maximum value.
677 */
678 if (gs->gs_max_out_vertices > 0) {
679 max_gs_prims = MIN2(max_gs_prims,
680 max_out_prims /
681 (gs->gs_max_out_vertices * gs_num_invocations));
682 }
683 assert(max_gs_prims > 0);
684
685 /* If the primitive has adjacency, halve the number of vertices
686 * that will be reused in multiple primitives.
687 */
688 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
689
690 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
691 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
692
693 /* Compute ESGS LDS size based on the worst case number of ES vertices
694 * needed to create the target number of GS prims per subgroup.
695 */
696 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
697
698 /* If total LDS usage is too big, refactor partitions based on ratio
699 * of ESGS item sizes.
700 */
701 if (esgs_lds_size > max_lds_size) {
702 /* Our target GS Prims Per Subgroup was too large. Calculate
703 * the maximum number of GS Prims Per Subgroup that will fit
704 * into LDS, capped by the maximum that the hardware can support.
705 */
706 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
707 max_gs_prims);
708 assert(gs_prims > 0);
709 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
710 max_es_verts);
711
712 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
713 assert(esgs_lds_size <= max_lds_size);
714 }
715
716 /* Now calculate remaining ESGS information. */
717 if (esgs_lds_size)
718 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
719 else
720 es_verts = max_es_verts;
721
722 /* Vertices for adjacency primitives are not always reused, so restore
723 * it for ES_VERTS_PER_SUBGRP.
724 */
725 min_es_verts = gs->gs_input_verts_per_prim;
726
727 /* For normal primitives, the VGT only checks if they are past the ES
728 * verts per subgroup after allocating a full GS primitive and if they
729 * are, kick off a new subgroup. But if those additional ES verts are
730 * unique (e.g. not reused) we need to make sure there is enough LDS
731 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
732 */
733 es_verts -= min_es_verts - 1;
734
735 out->es_verts_per_subgroup = es_verts;
736 out->gs_prims_per_subgroup = gs_prims;
737 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
738 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
739 gs->gs_max_out_vertices;
740 out->esgs_ring_size = 4 * esgs_lds_size;
741
742 assert(out->max_prims_per_subgroup <= max_out_prims);
743 }
744
745 static void si_emit_shader_gs(struct si_context *sctx)
746 {
747 struct si_shader *shader = sctx->queued.named.gs->shader;
748 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
749
750 if (!shader)
751 return;
752
753 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
754 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
755 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
756 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
757 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
760
761 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
762 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
763 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
764 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
765
766 /* R_028B38_VGT_GS_MAX_VERT_OUT */
767 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
768 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
769 shader->ctx_reg.gs.vgt_gs_max_vert_out);
770
771 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
772 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
773 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
774 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
779
780 /* R_028B90_VGT_GS_INSTANCE_CNT */
781 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
782 SI_TRACKED_VGT_GS_INSTANCE_CNT,
783 shader->ctx_reg.gs.vgt_gs_instance_cnt);
784
785 if (sctx->chip_class >= GFX9) {
786 /* R_028A44_VGT_GS_ONCHIP_CNTL */
787 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
788 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
789 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
790 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
791 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
792 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
794 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
795 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
796 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
797 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
798
799 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
800 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
801 SI_TRACKED_VGT_TF_PARAM,
802 shader->vgt_tf_param);
803 if (shader->vgt_vertex_reuse_block_cntl)
804 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
805 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 shader->vgt_vertex_reuse_block_cntl);
807 }
808
809 if (initial_cdw != sctx->gfx_cs->current.cdw)
810 sctx->context_roll = true;
811 }
812
813 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
814 {
815 struct si_shader_selector *sel = shader->selector;
816 const ubyte *num_components = sel->info.num_stream_output_components;
817 unsigned gs_num_invocations = sel->gs_num_invocations;
818 struct si_pm4_state *pm4;
819 uint64_t va;
820 unsigned max_stream = sel->max_gs_stream;
821 unsigned offset;
822
823 pm4 = si_get_shader_pm4_state(shader);
824 if (!pm4)
825 return;
826
827 pm4->atom.emit = si_emit_shader_gs;
828
829 offset = num_components[0] * sel->gs_max_out_vertices;
830 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
831
832 if (max_stream >= 1)
833 offset += num_components[1] * sel->gs_max_out_vertices;
834 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
835
836 if (max_stream >= 2)
837 offset += num_components[2] * sel->gs_max_out_vertices;
838 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
839
840 if (max_stream >= 3)
841 offset += num_components[3] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
843
844 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
845 assert(offset < (1 << 15));
846
847 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
848
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
853
854 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
855 S_028B90_ENABLE(gs_num_invocations > 0);
856
857 va = shader->bo->gpu_address;
858 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
859
860 if (sscreen->info.chip_class >= GFX9) {
861 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
862 unsigned es_type = shader->key.part.gs.es->type;
863 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
864
865 if (es_type == PIPE_SHADER_VERTEX)
866 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
867 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
868 else if (es_type == PIPE_SHADER_TESS_EVAL)
869 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
870 else
871 unreachable("invalid shader selector type");
872
873 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
874 * VGPR[0:4] are always loaded.
875 */
876 if (sel->info.uses_invocationid)
877 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
878 else if (sel->info.uses_primid)
879 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
880 else if (input_prim >= PIPE_PRIM_TRIANGLES)
881 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
882 else
883 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
884
885 unsigned num_user_sgprs;
886 if (es_type == PIPE_SHADER_VERTEX)
887 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
888 else
889 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
890
891 if (sscreen->info.chip_class >= GFX10) {
892 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
893 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
894 } else {
895 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
896 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
897 }
898
899 uint32_t rsrc1 =
900 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
901 S_00B228_DX10_CLAMP(1) |
902 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
903 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
904 S_00B228_FLOAT_MODE(shader->config.float_mode) |
905 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
906 uint32_t rsrc2 =
907 S_00B22C_USER_SGPR(num_user_sgprs) |
908 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
909 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
910 S_00B22C_LDS_SIZE(shader->config.lds_size) |
911 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
912
913 if (sscreen->info.chip_class >= GFX10) {
914 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
915 } else {
916 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
917 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
918 }
919
920 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
921 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
922
923 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
924 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
925 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
926 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
927 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
928 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
929 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
930 shader->key.part.gs.es->esgs_itemsize / 4;
931
932 if (es_type == PIPE_SHADER_TESS_EVAL)
933 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
934
935 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
936 NULL, pm4);
937 } else {
938 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
939 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
940
941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
942 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
943 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
944 S_00B228_DX10_CLAMP(1) |
945 S_00B228_FLOAT_MODE(shader->config.float_mode));
946 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
947 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
948 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
949 }
950 }
951
952 /* Common tail code for NGG primitive shaders. */
953 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
954 struct si_shader *shader,
955 unsigned initial_cdw)
956 {
957 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
958 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
959 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
960 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
961 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
962 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
963 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
964 SI_TRACKED_VGT_PRIMITIVEID_EN,
965 shader->ctx_reg.ngg.vgt_primitiveid_en);
966 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
967 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
968 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
969 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
970 SI_TRACKED_VGT_GS_INSTANCE_CNT,
971 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
972 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
973 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
974 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
975 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
976 SI_TRACKED_VGT_REUSE_OFF,
977 shader->ctx_reg.ngg.vgt_reuse_off);
978 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
979 SI_TRACKED_SPI_VS_OUT_CONFIG,
980 shader->ctx_reg.ngg.spi_vs_out_config);
981 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
982 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
983 shader->ctx_reg.ngg.spi_shader_idx_format,
984 shader->ctx_reg.ngg.spi_shader_pos_format);
985 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
986 SI_TRACKED_PA_CL_VTE_CNTL,
987 shader->ctx_reg.ngg.pa_cl_vte_cntl);
988 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
989 SI_TRACKED_PA_CL_NGG_CNTL,
990 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
991
992 if (initial_cdw != sctx->gfx_cs->current.cdw)
993 sctx->context_roll = true;
994 }
995
996 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
997 {
998 struct si_shader *shader = sctx->queued.named.gs->shader;
999 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1000
1001 if (!shader)
1002 return;
1003
1004 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1005 }
1006
1007 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1008 {
1009 struct si_shader *shader = sctx->queued.named.gs->shader;
1010 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1011
1012 if (!shader)
1013 return;
1014
1015 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1016 SI_TRACKED_VGT_TF_PARAM,
1017 shader->vgt_tf_param);
1018
1019 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1020 }
1021
1022 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1023 {
1024 struct si_shader *shader = sctx->queued.named.gs->shader;
1025 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1026
1027 if (!shader)
1028 return;
1029
1030 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1031 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1032 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1033
1034 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1035 }
1036
1037 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1038 {
1039 struct si_shader *shader = sctx->queued.named.gs->shader;
1040 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1041
1042 if (!shader)
1043 return;
1044
1045 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1046 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1047 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1048 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1049 SI_TRACKED_VGT_TF_PARAM,
1050 shader->vgt_tf_param);
1051
1052 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1053 }
1054
1055 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1056 struct si_pm4_state *pm4, bool culling)
1057 {
1058 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1059 S_030980_OVERSUB_EN(1) |
1060 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1061 }
1062
1063 unsigned si_get_input_prim(const struct si_shader_selector *gs,
1064 unsigned default_worst_case)
1065 {
1066 if (gs->type == PIPE_SHADER_GEOMETRY)
1067 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1068
1069 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1070 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1071 return PIPE_PRIM_POINTS;
1072 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1073 return PIPE_PRIM_LINES;
1074 return PIPE_PRIM_TRIANGLES;
1075 }
1076
1077 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1078 return default_worst_case;
1079 }
1080
1081 /**
1082 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1083 * in NGG mode.
1084 */
1085 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1086 {
1087 const struct si_shader_selector *gs_sel = shader->selector;
1088 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1089 enum pipe_shader_type gs_type = shader->selector->type;
1090 const struct si_shader_selector *es_sel =
1091 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1092 const struct tgsi_shader_info *es_info = &es_sel->info;
1093 enum pipe_shader_type es_type = es_sel->type;
1094 unsigned num_user_sgprs;
1095 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1096 uint64_t va;
1097 unsigned window_space =
1098 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1099 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1100 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1101 /* Anything above TRIANGLES has the same effect as TRIANGLES here. */
1102 unsigned input_prim = si_get_input_prim(gs_sel, PIPE_PRIM_TRIANGLES);
1103 bool break_wave_at_eoi = false;
1104 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1105 if (!pm4)
1106 return;
1107
1108 if (es_type == PIPE_SHADER_TESS_EVAL) {
1109 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1110 : gfx10_emit_shader_ngg_tess_nogs;
1111 } else {
1112 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1113 : gfx10_emit_shader_ngg_notess_nogs;
1114 }
1115
1116 va = shader->bo->gpu_address;
1117 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1118
1119 if (es_type == PIPE_SHADER_VERTEX) {
1120 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1121 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1122
1123 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1124 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1125 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1126 } else {
1127 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1128 }
1129 } else {
1130 assert(es_type == PIPE_SHADER_TESS_EVAL);
1131 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1132 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1133
1134 if (es_enable_prim_id || gs_info->uses_primid)
1135 break_wave_at_eoi = true;
1136 }
1137
1138 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1139 * VGPR[0:4] are always loaded.
1140 *
1141 * Vertex shaders always need to load VGPR3, because they need to
1142 * pass edge flags for decomposed primitives (such as quads) to the PA
1143 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1144 */
1145 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1146 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1147 else if (gs_info->uses_primid)
1148 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1149 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1150 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1151 else
1152 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1153
1154 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1155 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1156 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1157 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1158 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1159 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1160 S_00B228_DX10_CLAMP(1) |
1161 S_00B228_MEM_ORDERED(1) |
1162 S_00B228_WGP_MODE(1) |
1163 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1164 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1165 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1166 S_00B22C_USER_SGPR(num_user_sgprs) |
1167 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1168 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1169 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1170 S_00B22C_LDS_SIZE(shader->config.lds_size));
1171 si_set_ge_pc_alloc(sscreen, pm4, false);
1172
1173 nparams = MAX2(shader->info.nr_param_exports, 1);
1174 shader->ctx_reg.ngg.spi_vs_out_config =
1175 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1176 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1177
1178 shader->ctx_reg.ngg.spi_shader_idx_format =
1179 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1180 shader->ctx_reg.ngg.spi_shader_pos_format =
1181 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1182 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1183 V_02870C_SPI_SHADER_4COMP :
1184 V_02870C_SPI_SHADER_NONE) |
1185 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1186 V_02870C_SPI_SHADER_4COMP :
1187 V_02870C_SPI_SHADER_NONE) |
1188 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1189 V_02870C_SPI_SHADER_4COMP :
1190 V_02870C_SPI_SHADER_NONE);
1191
1192 shader->ctx_reg.ngg.vgt_primitiveid_en =
1193 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1194 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1195
1196 if (gs_type == PIPE_SHADER_GEOMETRY) {
1197 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1198 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1199 } else {
1200 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1201 }
1202
1203 if (es_type == PIPE_SHADER_TESS_EVAL)
1204 si_set_tesseval_regs(sscreen, es_sel, pm4);
1205
1206 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1207 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1208 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1209 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1210 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1211 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1212 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1213 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1214 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1215 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1216 S_028B90_CNT(gs_num_invocations) |
1217 S_028B90_ENABLE(gs_num_invocations > 1) |
1218 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1219 shader->ngg.max_vert_out_per_gs_instance);
1220
1221 /* Always output hw-generated edge flags and pass them via the prim
1222 * export to prevent drawing lines on internal edges of decomposed
1223 * primitives (such as quads) with polygon mode = lines. Only VS needs
1224 * this.
1225 */
1226 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1227 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1228
1229 shader->ge_cntl =
1230 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1231 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1232 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1233
1234 if (window_space) {
1235 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1236 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1237 } else {
1238 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1239 S_028818_VTX_W0_FMT(1) |
1240 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1241 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1242 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1243 }
1244
1245 shader->ctx_reg.ngg.vgt_reuse_off =
1246 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1247 sscreen->info.chip_external_rev == 0x1 &&
1248 es_type == PIPE_SHADER_TESS_EVAL);
1249 }
1250
1251 static void si_emit_shader_vs(struct si_context *sctx)
1252 {
1253 struct si_shader *shader = sctx->queued.named.vs->shader;
1254 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1255
1256 if (!shader)
1257 return;
1258
1259 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1260 SI_TRACKED_VGT_GS_MODE,
1261 shader->ctx_reg.vs.vgt_gs_mode);
1262 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1263 SI_TRACKED_VGT_PRIMITIVEID_EN,
1264 shader->ctx_reg.vs.vgt_primitiveid_en);
1265
1266 if (sctx->chip_class <= GFX8) {
1267 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1268 SI_TRACKED_VGT_REUSE_OFF,
1269 shader->ctx_reg.vs.vgt_reuse_off);
1270 }
1271
1272 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1273 SI_TRACKED_SPI_VS_OUT_CONFIG,
1274 shader->ctx_reg.vs.spi_vs_out_config);
1275
1276 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1277 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1278 shader->ctx_reg.vs.spi_shader_pos_format);
1279
1280 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1281 SI_TRACKED_PA_CL_VTE_CNTL,
1282 shader->ctx_reg.vs.pa_cl_vte_cntl);
1283
1284 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1285 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1286 SI_TRACKED_VGT_TF_PARAM,
1287 shader->vgt_tf_param);
1288
1289 if (shader->vgt_vertex_reuse_block_cntl)
1290 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1291 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1292 shader->vgt_vertex_reuse_block_cntl);
1293
1294 if (initial_cdw != sctx->gfx_cs->current.cdw)
1295 sctx->context_roll = true;
1296 }
1297
1298 /**
1299 * Compute the state for \p shader, which will run as a vertex shader on the
1300 * hardware.
1301 *
1302 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1303 * is the copy shader.
1304 */
1305 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1306 struct si_shader_selector *gs)
1307 {
1308 const struct tgsi_shader_info *info = &shader->selector->info;
1309 struct si_pm4_state *pm4;
1310 unsigned num_user_sgprs, vgpr_comp_cnt;
1311 uint64_t va;
1312 unsigned nparams, oc_lds_en;
1313 unsigned window_space =
1314 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1315 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1316
1317 pm4 = si_get_shader_pm4_state(shader);
1318 if (!pm4)
1319 return;
1320
1321 pm4->atom.emit = si_emit_shader_vs;
1322
1323 /* We always write VGT_GS_MODE in the VS state, because every switch
1324 * between different shader pipelines involving a different GS or no
1325 * GS at all involves a switch of the VS (different GS use different
1326 * copy shaders). On the other hand, when the API switches from a GS to
1327 * no GS and then back to the same GS used originally, the GS state is
1328 * not sent again.
1329 */
1330 if (!gs) {
1331 unsigned mode = V_028A40_GS_OFF;
1332
1333 /* PrimID needs GS scenario A. */
1334 if (enable_prim_id)
1335 mode = V_028A40_GS_SCENARIO_A;
1336
1337 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1338 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1339 } else {
1340 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1341 sscreen->info.chip_class);
1342 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1343 }
1344
1345 if (sscreen->info.chip_class <= GFX8) {
1346 /* Reuse needs to be set off if we write oViewport. */
1347 shader->ctx_reg.vs.vgt_reuse_off =
1348 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1349 }
1350
1351 va = shader->bo->gpu_address;
1352 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1353
1354 if (gs) {
1355 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1356 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1357 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1358 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1359 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1360 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1361 */
1362 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1363
1364 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1365 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1366 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1367 } else {
1368 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1369 }
1370 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1371 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1372 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1373 } else
1374 unreachable("invalid shader selector type");
1375
1376 /* VS is required to export at least one param. */
1377 nparams = MAX2(shader->info.nr_param_exports, 1);
1378 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1379
1380 if (sscreen->info.chip_class >= GFX10) {
1381 shader->ctx_reg.vs.spi_vs_out_config |=
1382 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1383 }
1384
1385 shader->ctx_reg.vs.spi_shader_pos_format =
1386 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1387 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1388 V_02870C_SPI_SHADER_4COMP :
1389 V_02870C_SPI_SHADER_NONE) |
1390 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1391 V_02870C_SPI_SHADER_4COMP :
1392 V_02870C_SPI_SHADER_NONE) |
1393 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1394 V_02870C_SPI_SHADER_4COMP :
1395 V_02870C_SPI_SHADER_NONE);
1396
1397 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1398
1399 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1400 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1401 if (sscreen->info.chip_class >= GFX10)
1402 si_set_ge_pc_alloc(sscreen, pm4, false);
1403
1404 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1405 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1406 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1407 S_00B128_DX10_CLAMP(1) |
1408 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1409 S_00B128_FLOAT_MODE(shader->config.float_mode);
1410 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1411 S_00B12C_OC_LDS_EN(oc_lds_en) |
1412 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1413
1414 if (sscreen->info.chip_class <= GFX9) {
1415 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1416 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1417 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1418 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1419 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1420 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1421 }
1422
1423 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1424 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1425
1426 if (window_space)
1427 shader->ctx_reg.vs.pa_cl_vte_cntl =
1428 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1429 else
1430 shader->ctx_reg.vs.pa_cl_vte_cntl =
1431 S_028818_VTX_W0_FMT(1) |
1432 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1433 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1434 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1435
1436 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1437 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1438
1439 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1440 }
1441
1442 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1443 {
1444 struct tgsi_shader_info *info = &ps->selector->info;
1445 unsigned num_colors = !!(info->colors_read & 0x0f) +
1446 !!(info->colors_read & 0xf0);
1447 unsigned num_interp = ps->selector->info.num_inputs +
1448 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1449
1450 assert(num_interp <= 32);
1451 return MIN2(num_interp, 32);
1452 }
1453
1454 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1455 {
1456 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1457 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1458
1459 /* If the i-th target format is set, all previous target formats must
1460 * be non-zero to avoid hangs.
1461 */
1462 for (i = 0; i < num_targets; i++)
1463 if (!(value & (0xf << (i * 4))))
1464 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1465
1466 return value;
1467 }
1468
1469 static void si_emit_shader_ps(struct si_context *sctx)
1470 {
1471 struct si_shader *shader = sctx->queued.named.ps->shader;
1472 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1473
1474 if (!shader)
1475 return;
1476
1477 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1478 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1479 SI_TRACKED_SPI_PS_INPUT_ENA,
1480 shader->ctx_reg.ps.spi_ps_input_ena,
1481 shader->ctx_reg.ps.spi_ps_input_addr);
1482
1483 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1484 SI_TRACKED_SPI_BARYC_CNTL,
1485 shader->ctx_reg.ps.spi_baryc_cntl);
1486 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1487 SI_TRACKED_SPI_PS_IN_CONTROL,
1488 shader->ctx_reg.ps.spi_ps_in_control);
1489
1490 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1491 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1492 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1493 shader->ctx_reg.ps.spi_shader_z_format,
1494 shader->ctx_reg.ps.spi_shader_col_format);
1495
1496 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1497 SI_TRACKED_CB_SHADER_MASK,
1498 shader->ctx_reg.ps.cb_shader_mask);
1499
1500 if (initial_cdw != sctx->gfx_cs->current.cdw)
1501 sctx->context_roll = true;
1502 }
1503
1504 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1505 {
1506 struct tgsi_shader_info *info = &shader->selector->info;
1507 struct si_pm4_state *pm4;
1508 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1509 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1510 uint64_t va;
1511 unsigned input_ena = shader->config.spi_ps_input_ena;
1512
1513 /* we need to enable at least one of them, otherwise we hang the GPU */
1514 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1515 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1516 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1517 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1518 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1519 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1520 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1521 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1522 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1523 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1524 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1525 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1526 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1527 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1528
1529 /* Validate interpolation optimization flags (read as implications). */
1530 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1531 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1532 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1533 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1534 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1535 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1536 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1537 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1538 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1539 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1540 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1541 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1542 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1543 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1544 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1545 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1546 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1547 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1548
1549 /* Validate cases when the optimizations are off (read as implications). */
1550 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1551 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1552 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1553 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1554 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1555 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1556
1557 pm4 = si_get_shader_pm4_state(shader);
1558 if (!pm4)
1559 return;
1560
1561 pm4->atom.emit = si_emit_shader_ps;
1562
1563 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1564 * Possible vaules:
1565 * 0 -> Position = pixel center
1566 * 1 -> Position = pixel centroid
1567 * 2 -> Position = at sample position
1568 *
1569 * From GLSL 4.5 specification, section 7.1:
1570 * "The variable gl_FragCoord is available as an input variable from
1571 * within fragment shaders and it holds the window relative coordinates
1572 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1573 * value can be for any location within the pixel, or one of the
1574 * fragment samples. The use of centroid does not further restrict
1575 * this value to be inside the current primitive."
1576 *
1577 * Meaning that centroid has no effect and we can return anything within
1578 * the pixel. Thus, return the value at sample position, because that's
1579 * the most accurate one shaders can get.
1580 */
1581 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1582
1583 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1584 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1585 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1586
1587 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1588 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1589
1590 /* Ensure that some export memory is always allocated, for two reasons:
1591 *
1592 * 1) Correctness: The hardware ignores the EXEC mask if no export
1593 * memory is allocated, so KILL and alpha test do not work correctly
1594 * without this.
1595 * 2) Performance: Every shader needs at least a NULL export, even when
1596 * it writes no color/depth output. The NULL export instruction
1597 * stalls without this setting.
1598 *
1599 * Don't add this to CB_SHADER_MASK.
1600 *
1601 * GFX10 supports pixel shaders without exports by setting both
1602 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1603 * instructions if any are present.
1604 */
1605 if ((sscreen->info.chip_class <= GFX9 ||
1606 info->uses_kill ||
1607 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1608 !spi_shader_col_format &&
1609 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1610 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1611
1612 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1613 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1614
1615 /* Set interpolation controls. */
1616 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1617 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1618
1619 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1620 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1621 shader->ctx_reg.ps.spi_shader_z_format =
1622 ac_get_spi_shader_z_format(info->writes_z,
1623 info->writes_stencil,
1624 info->writes_samplemask);
1625 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1626 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1627
1628 va = shader->bo->gpu_address;
1629 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1630 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1631 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1632
1633 uint32_t rsrc1 =
1634 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1635 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1636 S_00B028_DX10_CLAMP(1) |
1637 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1638 S_00B028_FLOAT_MODE(shader->config.float_mode);
1639
1640 if (sscreen->info.chip_class < GFX10) {
1641 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1642 }
1643
1644 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1645 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1646 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1647 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1648 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1649 }
1650
1651 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1652 struct si_shader *shader)
1653 {
1654 switch (shader->selector->type) {
1655 case PIPE_SHADER_VERTEX:
1656 if (shader->key.as_ls)
1657 si_shader_ls(sscreen, shader);
1658 else if (shader->key.as_es)
1659 si_shader_es(sscreen, shader);
1660 else if (shader->key.as_ngg)
1661 gfx10_shader_ngg(sscreen, shader);
1662 else
1663 si_shader_vs(sscreen, shader, NULL);
1664 break;
1665 case PIPE_SHADER_TESS_CTRL:
1666 si_shader_hs(sscreen, shader);
1667 break;
1668 case PIPE_SHADER_TESS_EVAL:
1669 if (shader->key.as_es)
1670 si_shader_es(sscreen, shader);
1671 else if (shader->key.as_ngg)
1672 gfx10_shader_ngg(sscreen, shader);
1673 else
1674 si_shader_vs(sscreen, shader, NULL);
1675 break;
1676 case PIPE_SHADER_GEOMETRY:
1677 if (shader->key.as_ngg)
1678 gfx10_shader_ngg(sscreen, shader);
1679 else
1680 si_shader_gs(sscreen, shader);
1681 break;
1682 case PIPE_SHADER_FRAGMENT:
1683 si_shader_ps(sscreen, shader);
1684 break;
1685 default:
1686 assert(0);
1687 }
1688 }
1689
1690 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1691 {
1692 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1693 if (sctx->queued.named.dsa)
1694 return sctx->queued.named.dsa->alpha_func;
1695
1696 return PIPE_FUNC_ALWAYS;
1697 }
1698
1699 void si_shader_selector_key_vs(struct si_context *sctx,
1700 struct si_shader_selector *vs,
1701 struct si_shader_key *key,
1702 struct si_vs_prolog_bits *prolog_key)
1703 {
1704 if (!sctx->vertex_elements ||
1705 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1706 return;
1707
1708 struct si_vertex_elements *elts = sctx->vertex_elements;
1709
1710 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1711 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1712 prolog_key->unpack_instance_id_from_vertex_id =
1713 sctx->prim_discard_cs_instancing;
1714
1715 /* Prefer a monolithic shader to allow scheduling divisions around
1716 * VBO loads. */
1717 if (prolog_key->instance_divisor_is_fetched)
1718 key->opt.prefer_mono = 1;
1719
1720 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1721 unsigned count_mask = (1 << count) - 1;
1722 unsigned fix = elts->fix_fetch_always & count_mask;
1723 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1724
1725 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1726 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1727 while (mask) {
1728 unsigned i = u_bit_scan(&mask);
1729 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1730 unsigned vbidx = elts->vertex_buffer_index[i];
1731 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1732 unsigned align_mask = (1 << log_hw_load_size) - 1;
1733 if (vb->buffer_offset & align_mask ||
1734 vb->stride & align_mask) {
1735 fix |= 1 << i;
1736 opencode |= 1 << i;
1737 }
1738 }
1739 }
1740
1741 while (fix) {
1742 unsigned i = u_bit_scan(&fix);
1743 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1744 }
1745 key->mono.vs_fetch_opencode = opencode;
1746 }
1747
1748 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1749 struct si_shader_selector *vs,
1750 struct si_shader_key *key)
1751 {
1752 struct si_shader_selector *ps = sctx->ps_shader.cso;
1753
1754 key->opt.clip_disable =
1755 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1756 (vs->info.clipdist_writemask ||
1757 vs->info.writes_clipvertex) &&
1758 !vs->info.culldist_writemask;
1759
1760 /* Find out if PS is disabled. */
1761 bool ps_disabled = true;
1762 if (ps) {
1763 const struct si_state_blend *blend = sctx->queued.named.blend;
1764 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1765 bool ps_modifies_zs = ps->info.uses_kill ||
1766 ps->info.writes_z ||
1767 ps->info.writes_stencil ||
1768 ps->info.writes_samplemask ||
1769 alpha_to_coverage ||
1770 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1771 unsigned ps_colormask = si_get_total_colormask(sctx);
1772
1773 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1774 (!ps_colormask &&
1775 !ps_modifies_zs &&
1776 !ps->info.writes_memory);
1777 }
1778
1779 /* Find out which VS outputs aren't used by the PS. */
1780 uint64_t outputs_written = vs->outputs_written_before_ps;
1781 uint64_t inputs_read = 0;
1782
1783 /* Ignore outputs that are not passed from VS to PS. */
1784 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1785 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1786 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1787
1788 if (!ps_disabled) {
1789 inputs_read = ps->inputs_read;
1790 }
1791
1792 uint64_t linked = outputs_written & inputs_read;
1793
1794 key->opt.kill_outputs = ~linked & outputs_written;
1795 }
1796
1797 /* Compute the key for the hw shader variant */
1798 static inline void si_shader_selector_key(struct pipe_context *ctx,
1799 struct si_shader_selector *sel,
1800 union si_vgt_stages_key stages_key,
1801 struct si_shader_key *key)
1802 {
1803 struct si_context *sctx = (struct si_context *)ctx;
1804
1805 memset(key, 0, sizeof(*key));
1806
1807 switch (sel->type) {
1808 case PIPE_SHADER_VERTEX:
1809 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1810
1811 if (sctx->tes_shader.cso)
1812 key->as_ls = 1;
1813 else if (sctx->gs_shader.cso)
1814 key->as_es = 1;
1815 else {
1816 key->as_ngg = stages_key.u.ngg;
1817 si_shader_selector_key_hw_vs(sctx, sel, key);
1818
1819 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1820 key->mono.u.vs_export_prim_id = 1;
1821 }
1822 break;
1823 case PIPE_SHADER_TESS_CTRL:
1824 if (sctx->chip_class >= GFX9) {
1825 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1826 key, &key->part.tcs.ls_prolog);
1827 key->part.tcs.ls = sctx->vs_shader.cso;
1828
1829 /* When the LS VGPR fix is needed, monolithic shaders
1830 * can:
1831 * - avoid initializing EXEC in both the LS prolog
1832 * and the LS main part when !vs_needs_prolog
1833 * - remove the fixup for unused input VGPRs
1834 */
1835 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1836
1837 /* The LS output / HS input layout can be communicated
1838 * directly instead of via user SGPRs for merged LS-HS.
1839 * The LS VGPR fix prefers this too.
1840 */
1841 key->opt.prefer_mono = 1;
1842 }
1843
1844 key->part.tcs.epilog.prim_mode =
1845 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1846 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1847 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1848 key->part.tcs.epilog.tes_reads_tess_factors =
1849 sctx->tes_shader.cso->info.reads_tess_factors;
1850
1851 if (sel == sctx->fixed_func_tcs_shader.cso)
1852 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1853 break;
1854 case PIPE_SHADER_TESS_EVAL:
1855 key->as_ngg = stages_key.u.ngg;
1856
1857 if (sctx->gs_shader.cso)
1858 key->as_es = 1;
1859 else {
1860 si_shader_selector_key_hw_vs(sctx, sel, key);
1861
1862 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1863 key->mono.u.vs_export_prim_id = 1;
1864 }
1865 break;
1866 case PIPE_SHADER_GEOMETRY:
1867 if (sctx->chip_class >= GFX9) {
1868 if (sctx->tes_shader.cso) {
1869 key->part.gs.es = sctx->tes_shader.cso;
1870 } else {
1871 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1872 key, &key->part.gs.vs_prolog);
1873 key->part.gs.es = sctx->vs_shader.cso;
1874 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1875 }
1876
1877 key->as_ngg = stages_key.u.ngg;
1878
1879 /* Merged ES-GS can have unbalanced wave usage.
1880 *
1881 * ES threads are per-vertex, while GS threads are
1882 * per-primitive. So without any amplification, there
1883 * are fewer GS threads than ES threads, which can result
1884 * in empty (no-op) GS waves. With too much amplification,
1885 * there are more GS threads than ES threads, which
1886 * can result in empty (no-op) ES waves.
1887 *
1888 * Non-monolithic shaders are implemented by setting EXEC
1889 * at the beginning of shader parts, and don't jump to
1890 * the end if EXEC is 0.
1891 *
1892 * Monolithic shaders use conditional blocks, so they can
1893 * jump and skip empty waves of ES or GS. So set this to
1894 * always use optimized variants, which are monolithic.
1895 */
1896 key->opt.prefer_mono = 1;
1897 }
1898 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1899 break;
1900 case PIPE_SHADER_FRAGMENT: {
1901 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1902 struct si_state_blend *blend = sctx->queued.named.blend;
1903
1904 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1905 sel->info.colors_written == 0x1)
1906 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1907
1908 if (blend) {
1909 /* Select the shader color format based on whether
1910 * blending or alpha are needed.
1911 */
1912 key->part.ps.epilog.spi_shader_col_format =
1913 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1914 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1915 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1916 sctx->framebuffer.spi_shader_col_format_blend) |
1917 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1918 sctx->framebuffer.spi_shader_col_format_alpha) |
1919 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1920 sctx->framebuffer.spi_shader_col_format);
1921 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1922
1923 /* The output for dual source blending should have
1924 * the same format as the first output.
1925 */
1926 if (blend->dual_src_blend)
1927 key->part.ps.epilog.spi_shader_col_format |=
1928 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1929 } else
1930 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1931
1932 /* If alpha-to-coverage is enabled, we have to export alpha
1933 * even if there is no color buffer.
1934 */
1935 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1936 blend && blend->alpha_to_coverage)
1937 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1938
1939 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1940 * to the range supported by the type if a channel has less
1941 * than 16 bits and the export format is 16_ABGR.
1942 */
1943 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1944 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1945 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1946 }
1947
1948 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1949 if (!key->part.ps.epilog.last_cbuf) {
1950 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1951 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1952 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1953 }
1954
1955 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1956 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1957
1958 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1959 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1960
1961 if (sctx->queued.named.blend) {
1962 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1963 rs->multisample_enable;
1964 }
1965
1966 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1967 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1968 (is_line && rs->line_smooth)) &&
1969 sctx->framebuffer.nr_samples <= 1;
1970 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1971
1972 if (sctx->ps_iter_samples > 1 &&
1973 sel->info.reads_samplemask) {
1974 key->part.ps.prolog.samplemask_log_ps_iter =
1975 util_logbase2(sctx->ps_iter_samples);
1976 }
1977
1978 if (rs->force_persample_interp &&
1979 rs->multisample_enable &&
1980 sctx->framebuffer.nr_samples > 1 &&
1981 sctx->ps_iter_samples > 1) {
1982 key->part.ps.prolog.force_persp_sample_interp =
1983 sel->info.uses_persp_center ||
1984 sel->info.uses_persp_centroid;
1985
1986 key->part.ps.prolog.force_linear_sample_interp =
1987 sel->info.uses_linear_center ||
1988 sel->info.uses_linear_centroid;
1989 } else if (rs->multisample_enable &&
1990 sctx->framebuffer.nr_samples > 1) {
1991 key->part.ps.prolog.bc_optimize_for_persp =
1992 sel->info.uses_persp_center &&
1993 sel->info.uses_persp_centroid;
1994 key->part.ps.prolog.bc_optimize_for_linear =
1995 sel->info.uses_linear_center &&
1996 sel->info.uses_linear_centroid;
1997 } else {
1998 /* Make sure SPI doesn't compute more than 1 pair
1999 * of (i,j), which is the optimization here. */
2000 key->part.ps.prolog.force_persp_center_interp =
2001 sel->info.uses_persp_center +
2002 sel->info.uses_persp_centroid +
2003 sel->info.uses_persp_sample > 1;
2004
2005 key->part.ps.prolog.force_linear_center_interp =
2006 sel->info.uses_linear_center +
2007 sel->info.uses_linear_centroid +
2008 sel->info.uses_linear_sample > 1;
2009
2010 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
2011 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2012 }
2013
2014 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2015
2016 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2017 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2018 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2019 struct pipe_resource *tex = cb0->texture;
2020
2021 /* 1D textures are allocated and used as 2D on GFX9. */
2022 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2023 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2024 (tex->target == PIPE_TEXTURE_1D ||
2025 tex->target == PIPE_TEXTURE_1D_ARRAY);
2026 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2027 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2028 tex->target == PIPE_TEXTURE_CUBE ||
2029 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2030 tex->target == PIPE_TEXTURE_3D;
2031 }
2032 break;
2033 }
2034 default:
2035 assert(0);
2036 }
2037
2038 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2039 memset(&key->opt, 0, sizeof(key->opt));
2040 }
2041
2042 static void si_build_shader_variant(struct si_shader *shader,
2043 int thread_index,
2044 bool low_priority)
2045 {
2046 struct si_shader_selector *sel = shader->selector;
2047 struct si_screen *sscreen = sel->screen;
2048 struct ac_llvm_compiler *compiler;
2049 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2050
2051 if (thread_index >= 0) {
2052 if (low_priority) {
2053 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2054 compiler = &sscreen->compiler_lowp[thread_index];
2055 } else {
2056 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2057 compiler = &sscreen->compiler[thread_index];
2058 }
2059 if (!debug->async)
2060 debug = NULL;
2061 } else {
2062 assert(!low_priority);
2063 compiler = shader->compiler_ctx_state.compiler;
2064 }
2065
2066 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2067 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2068 sel->type);
2069 shader->compilation_failed = true;
2070 return;
2071 }
2072
2073 if (shader->compiler_ctx_state.is_debug_context) {
2074 FILE *f = open_memstream(&shader->shader_log,
2075 &shader->shader_log_size);
2076 if (f) {
2077 si_shader_dump(sscreen, shader, NULL, f, false);
2078 fclose(f);
2079 }
2080 }
2081
2082 si_shader_init_pm4_state(sscreen, shader);
2083 }
2084
2085 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2086 {
2087 struct si_shader *shader = (struct si_shader *)job;
2088
2089 assert(thread_index >= 0);
2090
2091 si_build_shader_variant(shader, thread_index, true);
2092 }
2093
2094 static const struct si_shader_key zeroed;
2095
2096 static bool si_check_missing_main_part(struct si_screen *sscreen,
2097 struct si_shader_selector *sel,
2098 struct si_compiler_ctx_state *compiler_state,
2099 struct si_shader_key *key)
2100 {
2101 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2102
2103 if (!*mainp) {
2104 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2105
2106 if (!main_part)
2107 return false;
2108
2109 /* We can leave the fence as permanently signaled because the
2110 * main part becomes visible globally only after it has been
2111 * compiled. */
2112 util_queue_fence_init(&main_part->ready);
2113
2114 main_part->selector = sel;
2115 main_part->key.as_es = key->as_es;
2116 main_part->key.as_ls = key->as_ls;
2117 main_part->key.as_ngg = key->as_ngg;
2118 main_part->is_monolithic = false;
2119
2120 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2121 main_part, &compiler_state->debug) != 0) {
2122 FREE(main_part);
2123 return false;
2124 }
2125 *mainp = main_part;
2126 }
2127 return true;
2128 }
2129
2130 /**
2131 * Select a shader variant according to the shader key.
2132 *
2133 * \param optimized_or_none If the key describes an optimized shader variant and
2134 * the compilation isn't finished, don't select any
2135 * shader and return an error.
2136 */
2137 int si_shader_select_with_key(struct si_screen *sscreen,
2138 struct si_shader_ctx_state *state,
2139 struct si_compiler_ctx_state *compiler_state,
2140 struct si_shader_key *key,
2141 int thread_index,
2142 bool optimized_or_none)
2143 {
2144 struct si_shader_selector *sel = state->cso;
2145 struct si_shader_selector *previous_stage_sel = NULL;
2146 struct si_shader *current = state->current;
2147 struct si_shader *iter, *shader = NULL;
2148
2149 again:
2150 /* Check if we don't need to change anything.
2151 * This path is also used for most shaders that don't need multiple
2152 * variants, it will cost just a computation of the key and this
2153 * test. */
2154 if (likely(current &&
2155 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2156 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2157 if (current->is_optimized) {
2158 if (optimized_or_none)
2159 return -1;
2160
2161 memset(&key->opt, 0, sizeof(key->opt));
2162 goto current_not_ready;
2163 }
2164
2165 util_queue_fence_wait(&current->ready);
2166 }
2167
2168 return current->compilation_failed ? -1 : 0;
2169 }
2170 current_not_ready:
2171
2172 /* This must be done before the mutex is locked, because async GS
2173 * compilation calls this function too, and therefore must enter
2174 * the mutex first.
2175 *
2176 * Only wait if we are in a draw call. Don't wait if we are
2177 * in a compiler thread.
2178 */
2179 if (thread_index < 0)
2180 util_queue_fence_wait(&sel->ready);
2181
2182 mtx_lock(&sel->mutex);
2183
2184 /* Find the shader variant. */
2185 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2186 /* Don't check the "current" shader. We checked it above. */
2187 if (current != iter &&
2188 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2189 mtx_unlock(&sel->mutex);
2190
2191 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2192 /* If it's an optimized shader and its compilation has
2193 * been started but isn't done, use the unoptimized
2194 * shader so as not to cause a stall due to compilation.
2195 */
2196 if (iter->is_optimized) {
2197 if (optimized_or_none)
2198 return -1;
2199 memset(&key->opt, 0, sizeof(key->opt));
2200 goto again;
2201 }
2202
2203 util_queue_fence_wait(&iter->ready);
2204 }
2205
2206 if (iter->compilation_failed) {
2207 return -1; /* skip the draw call */
2208 }
2209
2210 state->current = iter;
2211 return 0;
2212 }
2213 }
2214
2215 /* Build a new shader. */
2216 shader = CALLOC_STRUCT(si_shader);
2217 if (!shader) {
2218 mtx_unlock(&sel->mutex);
2219 return -ENOMEM;
2220 }
2221
2222 util_queue_fence_init(&shader->ready);
2223
2224 shader->selector = sel;
2225 shader->key = *key;
2226 shader->compiler_ctx_state = *compiler_state;
2227
2228 /* If this is a merged shader, get the first shader's selector. */
2229 if (sscreen->info.chip_class >= GFX9) {
2230 if (sel->type == PIPE_SHADER_TESS_CTRL)
2231 previous_stage_sel = key->part.tcs.ls;
2232 else if (sel->type == PIPE_SHADER_GEOMETRY)
2233 previous_stage_sel = key->part.gs.es;
2234
2235 /* We need to wait for the previous shader. */
2236 if (previous_stage_sel && thread_index < 0)
2237 util_queue_fence_wait(&previous_stage_sel->ready);
2238 }
2239
2240 bool is_pure_monolithic =
2241 sscreen->use_monolithic_shaders ||
2242 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2243
2244 /* Compile the main shader part if it doesn't exist. This can happen
2245 * if the initial guess was wrong.
2246 *
2247 * The prim discard CS doesn't need the main shader part.
2248 */
2249 if (!is_pure_monolithic &&
2250 !key->opt.vs_as_prim_discard_cs) {
2251 bool ok = true;
2252
2253 /* Make sure the main shader part is present. This is needed
2254 * for shaders that can be compiled as VS, LS, or ES, and only
2255 * one of them is compiled at creation.
2256 *
2257 * It is also needed for GS, which can be compiled as non-NGG
2258 * and NGG.
2259 *
2260 * For merged shaders, check that the starting shader's main
2261 * part is present.
2262 */
2263 if (previous_stage_sel) {
2264 struct si_shader_key shader1_key = zeroed;
2265
2266 if (sel->type == PIPE_SHADER_TESS_CTRL)
2267 shader1_key.as_ls = 1;
2268 else if (sel->type == PIPE_SHADER_GEOMETRY)
2269 shader1_key.as_es = 1;
2270 else
2271 assert(0);
2272
2273 if (sel->type == PIPE_SHADER_GEOMETRY &&
2274 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2275 shader1_key.as_ngg = key->as_ngg;
2276
2277 mtx_lock(&previous_stage_sel->mutex);
2278 ok = si_check_missing_main_part(sscreen,
2279 previous_stage_sel,
2280 compiler_state, &shader1_key);
2281 mtx_unlock(&previous_stage_sel->mutex);
2282 }
2283
2284 if (ok) {
2285 ok = si_check_missing_main_part(sscreen, sel,
2286 compiler_state, key);
2287 }
2288
2289 if (!ok) {
2290 FREE(shader);
2291 mtx_unlock(&sel->mutex);
2292 return -ENOMEM; /* skip the draw call */
2293 }
2294 }
2295
2296 /* Keep the reference to the 1st shader of merged shaders, so that
2297 * Gallium can't destroy it before we destroy the 2nd shader.
2298 *
2299 * Set sctx = NULL, because it's unused if we're not releasing
2300 * the shader, and we don't have any sctx here.
2301 */
2302 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2303 previous_stage_sel);
2304
2305 /* Monolithic-only shaders don't make a distinction between optimized
2306 * and unoptimized. */
2307 shader->is_monolithic =
2308 is_pure_monolithic ||
2309 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2310
2311 /* The prim discard CS is always optimized. */
2312 shader->is_optimized =
2313 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2314 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2315
2316 /* If it's an optimized shader, compile it asynchronously. */
2317 if (shader->is_optimized && thread_index < 0) {
2318 /* Compile it asynchronously. */
2319 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2320 shader, &shader->ready,
2321 si_build_shader_variant_low_priority, NULL);
2322
2323 /* Add only after the ready fence was reset, to guard against a
2324 * race with si_bind_XX_shader. */
2325 if (!sel->last_variant) {
2326 sel->first_variant = shader;
2327 sel->last_variant = shader;
2328 } else {
2329 sel->last_variant->next_variant = shader;
2330 sel->last_variant = shader;
2331 }
2332
2333 /* Use the default (unoptimized) shader for now. */
2334 memset(&key->opt, 0, sizeof(key->opt));
2335 mtx_unlock(&sel->mutex);
2336
2337 if (sscreen->options.sync_compile)
2338 util_queue_fence_wait(&shader->ready);
2339
2340 if (optimized_or_none)
2341 return -1;
2342 goto again;
2343 }
2344
2345 /* Reset the fence before adding to the variant list. */
2346 util_queue_fence_reset(&shader->ready);
2347
2348 if (!sel->last_variant) {
2349 sel->first_variant = shader;
2350 sel->last_variant = shader;
2351 } else {
2352 sel->last_variant->next_variant = shader;
2353 sel->last_variant = shader;
2354 }
2355
2356 mtx_unlock(&sel->mutex);
2357
2358 assert(!shader->is_optimized);
2359 si_build_shader_variant(shader, thread_index, false);
2360
2361 util_queue_fence_signal(&shader->ready);
2362
2363 if (!shader->compilation_failed)
2364 state->current = shader;
2365
2366 return shader->compilation_failed ? -1 : 0;
2367 }
2368
2369 static int si_shader_select(struct pipe_context *ctx,
2370 struct si_shader_ctx_state *state,
2371 union si_vgt_stages_key stages_key,
2372 struct si_compiler_ctx_state *compiler_state)
2373 {
2374 struct si_context *sctx = (struct si_context *)ctx;
2375 struct si_shader_key key;
2376
2377 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2378 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2379 &key, -1, false);
2380 }
2381
2382 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2383 bool streamout,
2384 struct si_shader_key *key)
2385 {
2386 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2387
2388 switch (info->processor) {
2389 case PIPE_SHADER_VERTEX:
2390 switch (next_shader) {
2391 case PIPE_SHADER_GEOMETRY:
2392 key->as_es = 1;
2393 break;
2394 case PIPE_SHADER_TESS_CTRL:
2395 case PIPE_SHADER_TESS_EVAL:
2396 key->as_ls = 1;
2397 break;
2398 default:
2399 /* If POSITION isn't written, it can only be a HW VS
2400 * if streamout is used. If streamout isn't used,
2401 * assume that it's a HW LS. (the next shader is TCS)
2402 * This heuristic is needed for separate shader objects.
2403 */
2404 if (!info->writes_position && !streamout)
2405 key->as_ls = 1;
2406 }
2407 break;
2408
2409 case PIPE_SHADER_TESS_EVAL:
2410 if (next_shader == PIPE_SHADER_GEOMETRY ||
2411 !info->writes_position)
2412 key->as_es = 1;
2413 break;
2414 }
2415 }
2416
2417 /**
2418 * Compile the main shader part or the monolithic shader as part of
2419 * si_shader_selector initialization. Since it can be done asynchronously,
2420 * there is no way to report compile failures to applications.
2421 */
2422 static void si_init_shader_selector_async(void *job, int thread_index)
2423 {
2424 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2425 struct si_screen *sscreen = sel->screen;
2426 struct ac_llvm_compiler *compiler;
2427 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2428
2429 assert(!debug->debug_message || debug->async);
2430 assert(thread_index >= 0);
2431 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2432 compiler = &sscreen->compiler[thread_index];
2433
2434 if (sel->nir) {
2435 /* TODO: GS always sets wave size = default. Legacy GS will have
2436 * incorrect subgroup_size and ballot_bit_size. */
2437 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2438 }
2439
2440 /* Compile the main shader part for use with a prolog and/or epilog.
2441 * If this fails, the driver will try to compile a monolithic shader
2442 * on demand.
2443 */
2444 if (!sscreen->use_monolithic_shaders) {
2445 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2446 void *ir_binary = NULL;
2447
2448 if (!shader) {
2449 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2450 return;
2451 }
2452
2453 /* We can leave the fence signaled because use of the default
2454 * main part is guarded by the selector's ready fence. */
2455 util_queue_fence_init(&shader->ready);
2456
2457 shader->selector = sel;
2458 shader->is_monolithic = false;
2459 si_parse_next_shader_property(&sel->info,
2460 sel->so.num_outputs != 0,
2461 &shader->key);
2462 if (sscreen->info.chip_class >= GFX10 &&
2463 ((sel->type == PIPE_SHADER_VERTEX &&
2464 !shader->key.as_ls && !shader->key.as_es) ||
2465 sel->type == PIPE_SHADER_TESS_EVAL ||
2466 sel->type == PIPE_SHADER_GEOMETRY))
2467 shader->key.as_ngg = 1;
2468
2469 if (sel->tokens || sel->nir)
2470 ir_binary = si_get_ir_binary(sel);
2471
2472 /* Try to load the shader from the shader cache. */
2473 mtx_lock(&sscreen->shader_cache_mutex);
2474
2475 if (ir_binary &&
2476 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2477 mtx_unlock(&sscreen->shader_cache_mutex);
2478 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2479 } else {
2480 mtx_unlock(&sscreen->shader_cache_mutex);
2481
2482 /* Compile the shader if it hasn't been loaded from the cache. */
2483 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2484 debug) != 0) {
2485 FREE(shader);
2486 FREE(ir_binary);
2487 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2488 return;
2489 }
2490
2491 if (ir_binary) {
2492 mtx_lock(&sscreen->shader_cache_mutex);
2493 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2494 FREE(ir_binary);
2495 mtx_unlock(&sscreen->shader_cache_mutex);
2496 }
2497 }
2498
2499 *si_get_main_shader_part(sel, &shader->key) = shader;
2500
2501 /* Unset "outputs_written" flags for outputs converted to
2502 * DEFAULT_VAL, so that later inter-shader optimizations don't
2503 * try to eliminate outputs that don't exist in the final
2504 * shader.
2505 *
2506 * This is only done if non-monolithic shaders are enabled.
2507 */
2508 if ((sel->type == PIPE_SHADER_VERTEX ||
2509 sel->type == PIPE_SHADER_TESS_EVAL) &&
2510 !shader->key.as_ls &&
2511 !shader->key.as_es) {
2512 unsigned i;
2513
2514 for (i = 0; i < sel->info.num_outputs; i++) {
2515 unsigned offset = shader->info.vs_output_param_offset[i];
2516
2517 if (offset <= AC_EXP_PARAM_OFFSET_31)
2518 continue;
2519
2520 unsigned name = sel->info.output_semantic_name[i];
2521 unsigned index = sel->info.output_semantic_index[i];
2522 unsigned id;
2523
2524 switch (name) {
2525 case TGSI_SEMANTIC_GENERIC:
2526 /* don't process indices the function can't handle */
2527 if (index >= SI_MAX_IO_GENERIC)
2528 break;
2529 /* fall through */
2530 default:
2531 id = si_shader_io_get_unique_index(name, index, true);
2532 sel->outputs_written_before_ps &= ~(1ull << id);
2533 break;
2534 case TGSI_SEMANTIC_POSITION: /* ignore these */
2535 case TGSI_SEMANTIC_PSIZE:
2536 case TGSI_SEMANTIC_CLIPVERTEX:
2537 case TGSI_SEMANTIC_EDGEFLAG:
2538 break;
2539 }
2540 }
2541 }
2542 }
2543
2544 /* The GS copy shader is always pre-compiled. */
2545 if (sel->type == PIPE_SHADER_GEOMETRY &&
2546 (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
2547 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2548 if (!sel->gs_copy_shader) {
2549 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2550 return;
2551 }
2552
2553 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2554 }
2555 }
2556
2557 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2558 struct util_queue_fence *ready_fence,
2559 struct si_compiler_ctx_state *compiler_ctx_state,
2560 void *job, util_queue_execute_func execute)
2561 {
2562 util_queue_fence_init(ready_fence);
2563
2564 struct util_async_debug_callback async_debug;
2565 bool debug =
2566 (sctx->debug.debug_message && !sctx->debug.async) ||
2567 sctx->is_debug ||
2568 si_can_dump_shader(sctx->screen, processor);
2569
2570 if (debug) {
2571 u_async_debug_init(&async_debug);
2572 compiler_ctx_state->debug = async_debug.base;
2573 }
2574
2575 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2576 ready_fence, execute, NULL);
2577
2578 if (debug) {
2579 util_queue_fence_wait(ready_fence);
2580 u_async_debug_drain(&async_debug, &sctx->debug);
2581 u_async_debug_cleanup(&async_debug);
2582 }
2583
2584 if (sctx->screen->options.sync_compile)
2585 util_queue_fence_wait(ready_fence);
2586 }
2587
2588 /* Return descriptor slot usage masks from the given shader info. */
2589 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2590 uint32_t *const_and_shader_buffers,
2591 uint64_t *samplers_and_images)
2592 {
2593 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2594
2595 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2596 num_constbufs = util_last_bit(info->const_buffers_declared);
2597 /* two 8-byte images share one 16-byte slot */
2598 num_images = align(util_last_bit(info->images_declared), 2);
2599 num_samplers = util_last_bit(info->samplers_declared);
2600
2601 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2602 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2603 *const_and_shader_buffers =
2604 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2605
2606 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2607 start = si_get_image_slot(num_images - 1) / 2;
2608 *samplers_and_images =
2609 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2610 }
2611
2612 static void *si_create_shader_selector(struct pipe_context *ctx,
2613 const struct pipe_shader_state *state)
2614 {
2615 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2616 struct si_context *sctx = (struct si_context*)ctx;
2617 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2618 int i;
2619
2620 if (!sel)
2621 return NULL;
2622
2623 pipe_reference_init(&sel->reference, 1);
2624 sel->screen = sscreen;
2625 sel->compiler_ctx_state.debug = sctx->debug;
2626 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2627
2628 sel->so = state->stream_output;
2629
2630 if (state->type == PIPE_SHADER_IR_TGSI) {
2631 sel->tokens = tgsi_dup_tokens(state->tokens);
2632 if (!sel->tokens) {
2633 FREE(sel);
2634 return NULL;
2635 }
2636
2637 tgsi_scan_shader(state->tokens, &sel->info);
2638 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2639 } else {
2640 assert(state->type == PIPE_SHADER_IR_NIR);
2641
2642 sel->nir = state->ir.nir;
2643
2644 si_nir_opts(sel->nir);
2645 si_nir_scan_shader(sel->nir, &sel->info);
2646 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2647 }
2648
2649 sel->type = sel->info.processor;
2650 p_atomic_inc(&sscreen->num_shaders_created);
2651 si_get_active_slot_masks(&sel->info,
2652 &sel->active_const_and_shader_buffers,
2653 &sel->active_samplers_and_images);
2654
2655 /* Record which streamout buffers are enabled. */
2656 for (i = 0; i < sel->so.num_outputs; i++) {
2657 sel->enabled_streamout_buffer_mask |=
2658 (1 << sel->so.output[i].output_buffer) <<
2659 (sel->so.output[i].stream * 4);
2660 }
2661
2662 /* The prolog is a no-op if there are no inputs. */
2663 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2664 sel->info.num_inputs &&
2665 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2666
2667 sel->force_correct_derivs_after_kill =
2668 sel->type == PIPE_SHADER_FRAGMENT &&
2669 sel->info.uses_derivatives &&
2670 sel->info.uses_kill &&
2671 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2672
2673 sel->prim_discard_cs_allowed =
2674 sel->type == PIPE_SHADER_VERTEX &&
2675 !sel->info.uses_bindless_images &&
2676 !sel->info.uses_bindless_samplers &&
2677 !sel->info.writes_memory &&
2678 !sel->info.writes_viewport_index &&
2679 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2680 !sel->so.num_outputs;
2681
2682 if (sel->type == PIPE_SHADER_VERTEX &&
2683 sel->info.writes_edgeflag) {
2684 if (sscreen->info.chip_class >= GFX10)
2685 sel->ngg_writes_edgeflag = true;
2686 else
2687 sel->pos_writes_edgeflag = true;
2688 }
2689
2690 /* Set which opcode uses which (i,j) pair. */
2691 if (sel->info.uses_persp_opcode_interp_centroid)
2692 sel->info.uses_persp_centroid = true;
2693
2694 if (sel->info.uses_linear_opcode_interp_centroid)
2695 sel->info.uses_linear_centroid = true;
2696
2697 if (sel->info.uses_persp_opcode_interp_offset ||
2698 sel->info.uses_persp_opcode_interp_sample)
2699 sel->info.uses_persp_center = true;
2700
2701 if (sel->info.uses_linear_opcode_interp_offset ||
2702 sel->info.uses_linear_opcode_interp_sample)
2703 sel->info.uses_linear_center = true;
2704
2705 switch (sel->type) {
2706 case PIPE_SHADER_GEOMETRY:
2707 sel->gs_output_prim =
2708 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2709
2710 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2711 sel->rast_prim = sel->gs_output_prim;
2712 if (util_rast_prim_is_triangles(sel->rast_prim))
2713 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2714
2715 sel->gs_max_out_vertices =
2716 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2717 sel->gs_num_invocations =
2718 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2719 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2720 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2721 sel->gs_max_out_vertices;
2722
2723 sel->max_gs_stream = 0;
2724 for (i = 0; i < sel->so.num_outputs; i++)
2725 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2726 sel->so.output[i].stream);
2727
2728 sel->gs_input_verts_per_prim =
2729 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2730
2731 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2732 sel->tess_turns_off_ngg =
2733 (sscreen->info.family == CHIP_NAVI10 ||
2734 sscreen->info.family == CHIP_NAVI12 ||
2735 sscreen->info.family == CHIP_NAVI14) &&
2736 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2737 break;
2738
2739 case PIPE_SHADER_TESS_CTRL:
2740 /* Always reserve space for these. */
2741 sel->patch_outputs_written |=
2742 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2743 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2744 /* fall through */
2745 case PIPE_SHADER_VERTEX:
2746 case PIPE_SHADER_TESS_EVAL:
2747 for (i = 0; i < sel->info.num_outputs; i++) {
2748 unsigned name = sel->info.output_semantic_name[i];
2749 unsigned index = sel->info.output_semantic_index[i];
2750
2751 switch (name) {
2752 case TGSI_SEMANTIC_TESSINNER:
2753 case TGSI_SEMANTIC_TESSOUTER:
2754 case TGSI_SEMANTIC_PATCH:
2755 sel->patch_outputs_written |=
2756 1ull << si_shader_io_get_unique_index_patch(name, index);
2757 break;
2758
2759 case TGSI_SEMANTIC_GENERIC:
2760 /* don't process indices the function can't handle */
2761 if (index >= SI_MAX_IO_GENERIC)
2762 break;
2763 /* fall through */
2764 default:
2765 sel->outputs_written |=
2766 1ull << si_shader_io_get_unique_index(name, index, false);
2767 sel->outputs_written_before_ps |=
2768 1ull << si_shader_io_get_unique_index(name, index, true);
2769 break;
2770 case TGSI_SEMANTIC_EDGEFLAG:
2771 break;
2772 }
2773 }
2774 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2775 sel->lshs_vertex_stride = sel->esgs_itemsize;
2776
2777 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2778 * will start on a different bank. (except for the maximum 32*16).
2779 */
2780 if (sel->lshs_vertex_stride < 32*16)
2781 sel->lshs_vertex_stride += 4;
2782
2783 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2784 * conflicts, i.e. each vertex will start at a different bank.
2785 */
2786 if (sctx->chip_class >= GFX9)
2787 sel->esgs_itemsize += 4;
2788
2789 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2790
2791 /* Only for TES: */
2792 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2793 sel->rast_prim = PIPE_PRIM_POINTS;
2794 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2795 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2796 else
2797 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2798 break;
2799
2800 case PIPE_SHADER_FRAGMENT:
2801 for (i = 0; i < sel->info.num_inputs; i++) {
2802 unsigned name = sel->info.input_semantic_name[i];
2803 unsigned index = sel->info.input_semantic_index[i];
2804
2805 switch (name) {
2806 case TGSI_SEMANTIC_GENERIC:
2807 /* don't process indices the function can't handle */
2808 if (index >= SI_MAX_IO_GENERIC)
2809 break;
2810 /* fall through */
2811 default:
2812 sel->inputs_read |=
2813 1ull << si_shader_io_get_unique_index(name, index, true);
2814 break;
2815 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2816 break;
2817 }
2818 }
2819
2820 for (i = 0; i < 8; i++)
2821 if (sel->info.colors_written & (1 << i))
2822 sel->colors_written_4bit |= 0xf << (4 * i);
2823
2824 for (i = 0; i < sel->info.num_inputs; i++) {
2825 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2826 int index = sel->info.input_semantic_index[i];
2827 sel->color_attr_index[index] = i;
2828 }
2829 }
2830 break;
2831 default:;
2832 }
2833
2834 /* PA_CL_VS_OUT_CNTL */
2835 bool misc_vec_ena =
2836 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2837 sel->info.writes_layer || sel->info.writes_viewport_index;
2838 sel->pa_cl_vs_out_cntl =
2839 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2840 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2841 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2842 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2843 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2844 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2845 sel->clipdist_mask = sel->info.writes_clipvertex ?
2846 SIX_BITS : sel->info.clipdist_writemask;
2847 sel->culldist_mask = sel->info.culldist_writemask <<
2848 sel->info.num_written_clipdistance;
2849
2850 /* DB_SHADER_CONTROL */
2851 sel->db_shader_control =
2852 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2853 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2854 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2855 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2856
2857 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2858 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2859 sel->db_shader_control |=
2860 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2861 break;
2862 case TGSI_FS_DEPTH_LAYOUT_LESS:
2863 sel->db_shader_control |=
2864 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2865 break;
2866 }
2867
2868 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2869 *
2870 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2871 * --|-----------|------------|------------|--------------------|-------------------|-------------
2872 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2873 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2874 * 2 | false | true | n/a | LateZ | 1 | 0
2875 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2876 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2877 *
2878 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2879 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2880 *
2881 * Don't use ReZ without profiling !!!
2882 *
2883 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2884 * shaders.
2885 */
2886 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2887 /* Cases 3, 4. */
2888 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2889 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2890 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2891 } else if (sel->info.writes_memory) {
2892 /* Case 2. */
2893 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2894 S_02880C_EXEC_ON_HIER_FAIL(1);
2895 } else {
2896 /* Case 1. */
2897 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2898 }
2899
2900 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2901 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2902
2903 (void) mtx_init(&sel->mutex, mtx_plain);
2904
2905 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2906 &sel->compiler_ctx_state, sel,
2907 si_init_shader_selector_async);
2908 return sel;
2909 }
2910
2911 static void si_update_streamout_state(struct si_context *sctx)
2912 {
2913 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2914
2915 if (!shader_with_so)
2916 return;
2917
2918 sctx->streamout.enabled_stream_buffers_mask =
2919 shader_with_so->enabled_streamout_buffer_mask;
2920 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2921 }
2922
2923 static void si_update_clip_regs(struct si_context *sctx,
2924 struct si_shader_selector *old_hw_vs,
2925 struct si_shader *old_hw_vs_variant,
2926 struct si_shader_selector *next_hw_vs,
2927 struct si_shader *next_hw_vs_variant)
2928 {
2929 if (next_hw_vs &&
2930 (!old_hw_vs ||
2931 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2932 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2933 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2934 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2935 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2936 !old_hw_vs_variant ||
2937 !next_hw_vs_variant ||
2938 old_hw_vs_variant->key.opt.clip_disable !=
2939 next_hw_vs_variant->key.opt.clip_disable))
2940 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2941 }
2942
2943 static void si_update_common_shader_state(struct si_context *sctx)
2944 {
2945 sctx->uses_bindless_samplers =
2946 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2947 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2948 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2949 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2950 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2951 sctx->uses_bindless_images =
2952 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2953 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2954 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2955 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2956 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2957 sctx->do_update_shaders = true;
2958 }
2959
2960 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2961 {
2962 struct si_context *sctx = (struct si_context *)ctx;
2963 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2964 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2965 struct si_shader_selector *sel = state;
2966
2967 if (sctx->vs_shader.cso == sel)
2968 return;
2969
2970 sctx->vs_shader.cso = sel;
2971 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2972 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2973
2974 si_update_common_shader_state(sctx);
2975 si_update_vs_viewport_state(sctx);
2976 si_set_active_descriptors_for_shader(sctx, sel);
2977 si_update_streamout_state(sctx);
2978 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2979 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2980 }
2981
2982 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2983 {
2984 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2985 (sctx->tes_shader.cso &&
2986 sctx->tes_shader.cso->info.uses_primid) ||
2987 (sctx->tcs_shader.cso &&
2988 sctx->tcs_shader.cso->info.uses_primid) ||
2989 (sctx->gs_shader.cso &&
2990 sctx->gs_shader.cso->info.uses_primid) ||
2991 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2992 sctx->ps_shader.cso->info.uses_primid);
2993 }
2994
2995 static bool si_update_ngg(struct si_context *sctx)
2996 {
2997 if (sctx->chip_class <= GFX9)
2998 return false;
2999
3000 bool new_ngg = true;
3001
3002 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3003 sctx->gs_shader.cso->tess_turns_off_ngg)
3004 new_ngg = false;
3005
3006 if (new_ngg != sctx->ngg) {
3007 sctx->ngg = new_ngg;
3008 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3009 return true;
3010 }
3011 return false;
3012 }
3013
3014 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3015 {
3016 struct si_context *sctx = (struct si_context *)ctx;
3017 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3018 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3019 struct si_shader_selector *sel = state;
3020 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3021 bool ngg_changed;
3022
3023 if (sctx->gs_shader.cso == sel)
3024 return;
3025
3026 sctx->gs_shader.cso = sel;
3027 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3028 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3029
3030 si_update_common_shader_state(sctx);
3031 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3032
3033 ngg_changed = si_update_ngg(sctx);
3034 if (ngg_changed || enable_changed)
3035 si_shader_change_notify(sctx);
3036 if (enable_changed) {
3037 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3038 si_update_tess_uses_prim_id(sctx);
3039 }
3040 si_update_vs_viewport_state(sctx);
3041 si_set_active_descriptors_for_shader(sctx, sel);
3042 si_update_streamout_state(sctx);
3043 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3044 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3045 }
3046
3047 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3048 {
3049 struct si_context *sctx = (struct si_context *)ctx;
3050 struct si_shader_selector *sel = state;
3051 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3052
3053 if (sctx->tcs_shader.cso == sel)
3054 return;
3055
3056 sctx->tcs_shader.cso = sel;
3057 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3058 si_update_tess_uses_prim_id(sctx);
3059
3060 si_update_common_shader_state(sctx);
3061
3062 if (enable_changed)
3063 sctx->last_tcs = NULL; /* invalidate derived tess state */
3064
3065 si_set_active_descriptors_for_shader(sctx, sel);
3066 }
3067
3068 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3069 {
3070 struct si_context *sctx = (struct si_context *)ctx;
3071 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3072 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3073 struct si_shader_selector *sel = state;
3074 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3075
3076 if (sctx->tes_shader.cso == sel)
3077 return;
3078
3079 sctx->tes_shader.cso = sel;
3080 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3081 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3082 si_update_tess_uses_prim_id(sctx);
3083
3084 si_update_common_shader_state(sctx);
3085 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3086
3087 if (enable_changed) {
3088 si_update_ngg(sctx);
3089 si_shader_change_notify(sctx);
3090 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3091 }
3092 si_update_vs_viewport_state(sctx);
3093 si_set_active_descriptors_for_shader(sctx, sel);
3094 si_update_streamout_state(sctx);
3095 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3096 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3097 }
3098
3099 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3100 {
3101 struct si_context *sctx = (struct si_context *)ctx;
3102 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3103 struct si_shader_selector *sel = state;
3104
3105 /* skip if supplied shader is one already in use */
3106 if (old_sel == sel)
3107 return;
3108
3109 sctx->ps_shader.cso = sel;
3110 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3111
3112 si_update_common_shader_state(sctx);
3113 if (sel) {
3114 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3115 si_update_tess_uses_prim_id(sctx);
3116
3117 if (!old_sel ||
3118 old_sel->info.colors_written != sel->info.colors_written)
3119 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3120
3121 if (sctx->screen->has_out_of_order_rast &&
3122 (!old_sel ||
3123 old_sel->info.writes_memory != sel->info.writes_memory ||
3124 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3125 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3126 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3127 }
3128 si_set_active_descriptors_for_shader(sctx, sel);
3129 si_update_ps_colorbuf0_slot(sctx);
3130 }
3131
3132 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3133 {
3134 if (shader->is_optimized) {
3135 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3136 &shader->ready);
3137 }
3138
3139 util_queue_fence_destroy(&shader->ready);
3140
3141 if (shader->pm4) {
3142 /* If destroyed shaders were not unbound, the next compiled
3143 * shader variant could get the same pointer address and so
3144 * binding it to the same shader stage would be considered
3145 * a no-op, causing random behavior.
3146 */
3147 switch (shader->selector->type) {
3148 case PIPE_SHADER_VERTEX:
3149 if (shader->key.as_ls) {
3150 assert(sctx->chip_class <= GFX8);
3151 si_pm4_delete_state(sctx, ls, shader->pm4);
3152 } else if (shader->key.as_es) {
3153 assert(sctx->chip_class <= GFX8);
3154 si_pm4_delete_state(sctx, es, shader->pm4);
3155 } else if (shader->key.as_ngg) {
3156 si_pm4_delete_state(sctx, gs, shader->pm4);
3157 } else {
3158 si_pm4_delete_state(sctx, vs, shader->pm4);
3159 }
3160 break;
3161 case PIPE_SHADER_TESS_CTRL:
3162 si_pm4_delete_state(sctx, hs, shader->pm4);
3163 break;
3164 case PIPE_SHADER_TESS_EVAL:
3165 if (shader->key.as_es) {
3166 assert(sctx->chip_class <= GFX8);
3167 si_pm4_delete_state(sctx, es, shader->pm4);
3168 } else if (shader->key.as_ngg) {
3169 si_pm4_delete_state(sctx, gs, shader->pm4);
3170 } else {
3171 si_pm4_delete_state(sctx, vs, shader->pm4);
3172 }
3173 break;
3174 case PIPE_SHADER_GEOMETRY:
3175 if (shader->is_gs_copy_shader)
3176 si_pm4_delete_state(sctx, vs, shader->pm4);
3177 else
3178 si_pm4_delete_state(sctx, gs, shader->pm4);
3179 break;
3180 case PIPE_SHADER_FRAGMENT:
3181 si_pm4_delete_state(sctx, ps, shader->pm4);
3182 break;
3183 default:;
3184 }
3185 }
3186
3187 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3188 si_shader_destroy(shader);
3189 free(shader);
3190 }
3191
3192 void si_destroy_shader_selector(struct si_context *sctx,
3193 struct si_shader_selector *sel)
3194 {
3195 struct si_shader *p = sel->first_variant, *c;
3196 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3197 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3198 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3199 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3200 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3201 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3202 };
3203
3204 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3205
3206 if (current_shader[sel->type]->cso == sel) {
3207 current_shader[sel->type]->cso = NULL;
3208 current_shader[sel->type]->current = NULL;
3209 }
3210
3211 while (p) {
3212 c = p->next_variant;
3213 si_delete_shader(sctx, p);
3214 p = c;
3215 }
3216
3217 if (sel->main_shader_part)
3218 si_delete_shader(sctx, sel->main_shader_part);
3219 if (sel->main_shader_part_ls)
3220 si_delete_shader(sctx, sel->main_shader_part_ls);
3221 if (sel->main_shader_part_es)
3222 si_delete_shader(sctx, sel->main_shader_part_es);
3223 if (sel->main_shader_part_ngg)
3224 si_delete_shader(sctx, sel->main_shader_part_ngg);
3225 if (sel->gs_copy_shader)
3226 si_delete_shader(sctx, sel->gs_copy_shader);
3227
3228 util_queue_fence_destroy(&sel->ready);
3229 mtx_destroy(&sel->mutex);
3230 free(sel->tokens);
3231 ralloc_free(sel->nir);
3232 free(sel);
3233 }
3234
3235 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3236 {
3237 struct si_context *sctx = (struct si_context *)ctx;
3238 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3239
3240 si_shader_selector_reference(sctx, &sel, NULL);
3241 }
3242
3243 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3244 struct si_shader *vs, unsigned name,
3245 unsigned index, unsigned interpolate)
3246 {
3247 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3248 unsigned j, offset, ps_input_cntl = 0;
3249
3250 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3251 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3252 name == TGSI_SEMANTIC_PRIMID)
3253 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3254
3255 if (name == TGSI_SEMANTIC_PCOORD ||
3256 (name == TGSI_SEMANTIC_TEXCOORD &&
3257 sctx->sprite_coord_enable & (1 << index))) {
3258 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3259 }
3260
3261 for (j = 0; j < vsinfo->num_outputs; j++) {
3262 if (name == vsinfo->output_semantic_name[j] &&
3263 index == vsinfo->output_semantic_index[j]) {
3264 offset = vs->info.vs_output_param_offset[j];
3265
3266 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3267 /* The input is loaded from parameter memory. */
3268 ps_input_cntl |= S_028644_OFFSET(offset);
3269 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3270 if (offset == AC_EXP_PARAM_UNDEFINED) {
3271 /* This can happen with depth-only rendering. */
3272 offset = 0;
3273 } else {
3274 /* The input is a DEFAULT_VAL constant. */
3275 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3276 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3277 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3278 }
3279
3280 ps_input_cntl = S_028644_OFFSET(0x20) |
3281 S_028644_DEFAULT_VAL(offset);
3282 }
3283 break;
3284 }
3285 }
3286
3287 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3288 /* PrimID is written after the last output when HW VS is used. */
3289 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3290 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3291 /* No corresponding output found, load defaults into input.
3292 * Don't set any other bits.
3293 * (FLAT_SHADE=1 completely changes behavior) */
3294 ps_input_cntl = S_028644_OFFSET(0x20);
3295 /* D3D 9 behaviour. GL is undefined */
3296 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3297 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3298 }
3299 return ps_input_cntl;
3300 }
3301
3302 static void si_emit_spi_map(struct si_context *sctx)
3303 {
3304 struct si_shader *ps = sctx->ps_shader.current;
3305 struct si_shader *vs = si_get_vs_state(sctx);
3306 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3307 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3308 unsigned spi_ps_input_cntl[32];
3309
3310 if (!ps || !ps->selector->info.num_inputs)
3311 return;
3312
3313 num_interp = si_get_ps_num_interp(ps);
3314 assert(num_interp > 0);
3315
3316 for (i = 0; i < psinfo->num_inputs; i++) {
3317 unsigned name = psinfo->input_semantic_name[i];
3318 unsigned index = psinfo->input_semantic_index[i];
3319 unsigned interpolate = psinfo->input_interpolate[i];
3320
3321 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3322 index, interpolate);
3323
3324 if (name == TGSI_SEMANTIC_COLOR) {
3325 assert(index < ARRAY_SIZE(bcol_interp));
3326 bcol_interp[index] = interpolate;
3327 }
3328 }
3329
3330 if (ps->key.part.ps.prolog.color_two_side) {
3331 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3332
3333 for (i = 0; i < 2; i++) {
3334 if (!(psinfo->colors_read & (0xf << (i * 4))))
3335 continue;
3336
3337 spi_ps_input_cntl[num_written++] =
3338 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3339
3340 }
3341 }
3342 assert(num_interp == num_written);
3343
3344 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3345 /* Dota 2: Only ~16% of SPI map updates set different values. */
3346 /* Talos: Only ~9% of SPI map updates set different values. */
3347 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3348 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3349 spi_ps_input_cntl,
3350 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3351
3352 if (initial_cdw != sctx->gfx_cs->current.cdw)
3353 sctx->context_roll = true;
3354 }
3355
3356 /**
3357 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3358 */
3359 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3360 {
3361 if (sctx->init_config_has_vgt_flush)
3362 return;
3363
3364 /* Done by Vulkan before VGT_FLUSH. */
3365 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3366 si_pm4_cmd_add(sctx->init_config,
3367 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3368 si_pm4_cmd_end(sctx->init_config, false);
3369
3370 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3371 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3372 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3373 si_pm4_cmd_end(sctx->init_config, false);
3374 sctx->init_config_has_vgt_flush = true;
3375 }
3376
3377 /* Initialize state related to ESGS / GSVS ring buffers */
3378 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3379 {
3380 struct si_shader_selector *es =
3381 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3382 struct si_shader_selector *gs = sctx->gs_shader.cso;
3383 struct si_pm4_state *pm4;
3384
3385 /* Chip constants. */
3386 unsigned num_se = sctx->screen->info.max_se;
3387 unsigned wave_size = 64;
3388 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3389 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3390 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3391 */
3392 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3393 unsigned alignment = 256 * num_se;
3394 /* The maximum size is 63.999 MB per SE. */
3395 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3396
3397 /* Calculate the minimum size. */
3398 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3399 wave_size, alignment);
3400
3401 /* These are recommended sizes, not minimum sizes. */
3402 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3403 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3404 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3405 gs->max_gsvs_emit_size;
3406
3407 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3408 esgs_ring_size = align(esgs_ring_size, alignment);
3409 gsvs_ring_size = align(gsvs_ring_size, alignment);
3410
3411 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3412 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3413
3414 /* Some rings don't have to be allocated if shaders don't use them.
3415 * (e.g. no varyings between ES and GS or GS and VS)
3416 *
3417 * GFX9 doesn't have the ESGS ring.
3418 */
3419 bool update_esgs = sctx->chip_class <= GFX8 &&
3420 esgs_ring_size &&
3421 (!sctx->esgs_ring ||
3422 sctx->esgs_ring->width0 < esgs_ring_size);
3423 bool update_gsvs = gsvs_ring_size &&
3424 (!sctx->gsvs_ring ||
3425 sctx->gsvs_ring->width0 < gsvs_ring_size);
3426
3427 if (!update_esgs && !update_gsvs)
3428 return true;
3429
3430 if (update_esgs) {
3431 pipe_resource_reference(&sctx->esgs_ring, NULL);
3432 sctx->esgs_ring =
3433 pipe_aligned_buffer_create(sctx->b.screen,
3434 SI_RESOURCE_FLAG_UNMAPPABLE,
3435 PIPE_USAGE_DEFAULT,
3436 esgs_ring_size, alignment);
3437 if (!sctx->esgs_ring)
3438 return false;
3439 }
3440
3441 if (update_gsvs) {
3442 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3443 sctx->gsvs_ring =
3444 pipe_aligned_buffer_create(sctx->b.screen,
3445 SI_RESOURCE_FLAG_UNMAPPABLE,
3446 PIPE_USAGE_DEFAULT,
3447 gsvs_ring_size, alignment);
3448 if (!sctx->gsvs_ring)
3449 return false;
3450 }
3451
3452 /* Create the "init_config_gs_rings" state. */
3453 pm4 = CALLOC_STRUCT(si_pm4_state);
3454 if (!pm4)
3455 return false;
3456
3457 if (sctx->chip_class >= GFX7) {
3458 if (sctx->esgs_ring) {
3459 assert(sctx->chip_class <= GFX8);
3460 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3461 sctx->esgs_ring->width0 / 256);
3462 }
3463 if (sctx->gsvs_ring)
3464 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3465 sctx->gsvs_ring->width0 / 256);
3466 } else {
3467 if (sctx->esgs_ring)
3468 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3469 sctx->esgs_ring->width0 / 256);
3470 if (sctx->gsvs_ring)
3471 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3472 sctx->gsvs_ring->width0 / 256);
3473 }
3474
3475 /* Set the state. */
3476 if (sctx->init_config_gs_rings)
3477 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3478 sctx->init_config_gs_rings = pm4;
3479
3480 if (!sctx->init_config_has_vgt_flush) {
3481 si_init_config_add_vgt_flush(sctx);
3482 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3483 }
3484
3485 /* Flush the context to re-emit both init_config states. */
3486 sctx->initial_gfx_cs_size = 0; /* force flush */
3487 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3488
3489 /* Set ring bindings. */
3490 if (sctx->esgs_ring) {
3491 assert(sctx->chip_class <= GFX8);
3492 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3493 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3494 true, true, 4, 64, 0);
3495 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3496 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3497 false, false, 0, 0, 0);
3498 }
3499 if (sctx->gsvs_ring) {
3500 si_set_ring_buffer(sctx, SI_RING_GSVS,
3501 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3502 false, false, 0, 0, 0);
3503 }
3504
3505 return true;
3506 }
3507
3508 static void si_shader_lock(struct si_shader *shader)
3509 {
3510 mtx_lock(&shader->selector->mutex);
3511 if (shader->previous_stage_sel) {
3512 assert(shader->previous_stage_sel != shader->selector);
3513 mtx_lock(&shader->previous_stage_sel->mutex);
3514 }
3515 }
3516
3517 static void si_shader_unlock(struct si_shader *shader)
3518 {
3519 if (shader->previous_stage_sel)
3520 mtx_unlock(&shader->previous_stage_sel->mutex);
3521 mtx_unlock(&shader->selector->mutex);
3522 }
3523
3524 /**
3525 * @returns 1 if \p sel has been updated to use a new scratch buffer
3526 * 0 if not
3527 * < 0 if there was a failure
3528 */
3529 static int si_update_scratch_buffer(struct si_context *sctx,
3530 struct si_shader *shader)
3531 {
3532 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3533
3534 if (!shader)
3535 return 0;
3536
3537 /* This shader doesn't need a scratch buffer */
3538 if (shader->config.scratch_bytes_per_wave == 0)
3539 return 0;
3540
3541 /* Prevent race conditions when updating:
3542 * - si_shader::scratch_bo
3543 * - si_shader::binary::code
3544 * - si_shader::previous_stage::binary::code.
3545 */
3546 si_shader_lock(shader);
3547
3548 /* This shader is already configured to use the current
3549 * scratch buffer. */
3550 if (shader->scratch_bo == sctx->scratch_buffer) {
3551 si_shader_unlock(shader);
3552 return 0;
3553 }
3554
3555 assert(sctx->scratch_buffer);
3556
3557 /* Replace the shader bo with a new bo that has the relocs applied. */
3558 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3559 si_shader_unlock(shader);
3560 return -1;
3561 }
3562
3563 /* Update the shader state to use the new shader bo. */
3564 si_shader_init_pm4_state(sctx->screen, shader);
3565
3566 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3567
3568 si_shader_unlock(shader);
3569 return 1;
3570 }
3571
3572 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3573 {
3574 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3575 }
3576
3577 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3578 {
3579 return shader ? shader->config.scratch_bytes_per_wave : 0;
3580 }
3581
3582 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3583 {
3584 if (!sctx->tes_shader.cso)
3585 return NULL; /* tessellation disabled */
3586
3587 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3588 sctx->fixed_func_tcs_shader.current;
3589 }
3590
3591 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3592 {
3593 unsigned bytes = 0;
3594
3595 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3596 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3597 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3598 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3599
3600 if (sctx->tes_shader.cso) {
3601 struct si_shader *tcs = si_get_tcs_current(sctx);
3602
3603 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3604 }
3605 return bytes;
3606 }
3607
3608 static bool si_update_scratch_relocs(struct si_context *sctx)
3609 {
3610 struct si_shader *tcs = si_get_tcs_current(sctx);
3611 int r;
3612
3613 /* Update the shaders, so that they are using the latest scratch.
3614 * The scratch buffer may have been changed since these shaders were
3615 * last used, so we still need to try to update them, even if they
3616 * require scratch buffers smaller than the current size.
3617 */
3618 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3619 if (r < 0)
3620 return false;
3621 if (r == 1)
3622 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3623
3624 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3625 if (r < 0)
3626 return false;
3627 if (r == 1)
3628 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3629
3630 r = si_update_scratch_buffer(sctx, tcs);
3631 if (r < 0)
3632 return false;
3633 if (r == 1)
3634 si_pm4_bind_state(sctx, hs, tcs->pm4);
3635
3636 /* VS can be bound as LS, ES, or VS. */
3637 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3638 if (r < 0)
3639 return false;
3640 if (r == 1) {
3641 if (sctx->vs_shader.current->key.as_ls)
3642 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3643 else if (sctx->vs_shader.current->key.as_es)
3644 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3645 else if (sctx->vs_shader.current->key.as_ngg)
3646 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3647 else
3648 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3649 }
3650
3651 /* TES can be bound as ES or VS. */
3652 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3653 if (r < 0)
3654 return false;
3655 if (r == 1) {
3656 if (sctx->tes_shader.current->key.as_es)
3657 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3658 else if (sctx->tes_shader.current->key.as_ngg)
3659 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3660 else
3661 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3662 }
3663
3664 return true;
3665 }
3666
3667 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3668 {
3669 unsigned current_scratch_buffer_size =
3670 si_get_current_scratch_buffer_size(sctx);
3671 unsigned scratch_bytes_per_wave =
3672 si_get_max_scratch_bytes_per_wave(sctx);
3673 unsigned scratch_needed_size = scratch_bytes_per_wave *
3674 sctx->scratch_waves;
3675 unsigned spi_tmpring_size;
3676
3677 if (scratch_needed_size > 0) {
3678 if (scratch_needed_size > current_scratch_buffer_size) {
3679 /* Create a bigger scratch buffer */
3680 si_resource_reference(&sctx->scratch_buffer, NULL);
3681
3682 sctx->scratch_buffer =
3683 si_aligned_buffer_create(&sctx->screen->b,
3684 SI_RESOURCE_FLAG_UNMAPPABLE,
3685 PIPE_USAGE_DEFAULT,
3686 scratch_needed_size, 256);
3687 if (!sctx->scratch_buffer)
3688 return false;
3689
3690 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3691 si_context_add_resource_size(sctx,
3692 &sctx->scratch_buffer->b.b);
3693 }
3694
3695 if (!si_update_scratch_relocs(sctx))
3696 return false;
3697 }
3698
3699 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3700 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3701 "scratch size should already be aligned correctly.");
3702
3703 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3704 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3705 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3706 sctx->spi_tmpring_size = spi_tmpring_size;
3707 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3708 }
3709 return true;
3710 }
3711
3712 static void si_init_tess_factor_ring(struct si_context *sctx)
3713 {
3714 assert(!sctx->tess_rings);
3715
3716 /* The address must be aligned to 2^19, because the shader only
3717 * receives the high 13 bits.
3718 */
3719 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3720 SI_RESOURCE_FLAG_32BIT,
3721 PIPE_USAGE_DEFAULT,
3722 sctx->screen->tess_offchip_ring_size +
3723 sctx->screen->tess_factor_ring_size,
3724 1 << 19);
3725 if (!sctx->tess_rings)
3726 return;
3727
3728 si_init_config_add_vgt_flush(sctx);
3729
3730 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3731 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3732
3733 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3734 sctx->screen->tess_offchip_ring_size;
3735
3736 /* Append these registers to the init config state. */
3737 if (sctx->chip_class >= GFX7) {
3738 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3739 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3740 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3741 factor_va >> 8);
3742 if (sctx->chip_class >= GFX10)
3743 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3744 S_030984_BASE_HI(factor_va >> 40));
3745 else if (sctx->chip_class == GFX9)
3746 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3747 S_030944_BASE_HI(factor_va >> 40));
3748 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3749 sctx->screen->vgt_hs_offchip_param);
3750 } else {
3751 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3752 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3753 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3754 factor_va >> 8);
3755 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3756 sctx->screen->vgt_hs_offchip_param);
3757 }
3758
3759 /* Flush the context to re-emit the init_config state.
3760 * This is done only once in a lifetime of a context.
3761 */
3762 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3763 sctx->initial_gfx_cs_size = 0; /* force flush */
3764 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3765 }
3766
3767 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3768 union si_vgt_stages_key key)
3769 {
3770 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3771 uint32_t stages = 0;
3772
3773 if (key.u.tess) {
3774 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3775 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3776
3777 if (key.u.gs)
3778 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3779 S_028B54_GS_EN(1);
3780 else if (key.u.ngg)
3781 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3782 else
3783 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3784 } else if (key.u.gs) {
3785 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3786 S_028B54_GS_EN(1);
3787 } else if (key.u.ngg) {
3788 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3789 }
3790
3791 if (key.u.ngg) {
3792 stages |= S_028B54_PRIMGEN_EN(1);
3793 if (key.u.streamout)
3794 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3795 } else if (key.u.gs)
3796 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3797
3798 if (screen->info.chip_class >= GFX9)
3799 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3800
3801 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3802 stages |= S_028B54_HS_W32_EN(1) |
3803 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3804 S_028B54_VS_W32_EN(1);
3805 }
3806
3807 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3808 return pm4;
3809 }
3810
3811 static void si_update_vgt_shader_config(struct si_context *sctx,
3812 union si_vgt_stages_key key)
3813 {
3814 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3815
3816 if (unlikely(!*pm4))
3817 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3818 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3819 }
3820
3821 bool si_update_shaders(struct si_context *sctx)
3822 {
3823 struct pipe_context *ctx = (struct pipe_context*)sctx;
3824 struct si_compiler_ctx_state compiler_state;
3825 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3826 struct si_shader *old_vs = si_get_vs_state(sctx);
3827 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3828 struct si_shader *old_ps = sctx->ps_shader.current;
3829 union si_vgt_stages_key key;
3830 unsigned old_spi_shader_col_format =
3831 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3832 int r;
3833
3834 compiler_state.compiler = &sctx->compiler;
3835 compiler_state.debug = sctx->debug;
3836 compiler_state.is_debug_context = sctx->is_debug;
3837
3838 key.index = 0;
3839
3840 if (sctx->tes_shader.cso)
3841 key.u.tess = 1;
3842 if (sctx->gs_shader.cso)
3843 key.u.gs = 1;
3844
3845 if (sctx->chip_class >= GFX10) {
3846 key.u.ngg = sctx->ngg;
3847
3848 if (sctx->gs_shader.cso)
3849 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3850 else if (sctx->tes_shader.cso)
3851 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3852 else
3853 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3854 }
3855
3856 /* Update TCS and TES. */
3857 if (sctx->tes_shader.cso) {
3858 if (!sctx->tess_rings) {
3859 si_init_tess_factor_ring(sctx);
3860 if (!sctx->tess_rings)
3861 return false;
3862 }
3863
3864 if (sctx->tcs_shader.cso) {
3865 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3866 &compiler_state);
3867 if (r)
3868 return false;
3869 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3870 } else {
3871 if (!sctx->fixed_func_tcs_shader.cso) {
3872 sctx->fixed_func_tcs_shader.cso =
3873 si_create_fixed_func_tcs(sctx);
3874 if (!sctx->fixed_func_tcs_shader.cso)
3875 return false;
3876 }
3877
3878 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3879 key, &compiler_state);
3880 if (r)
3881 return false;
3882 si_pm4_bind_state(sctx, hs,
3883 sctx->fixed_func_tcs_shader.current->pm4);
3884 }
3885
3886 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3887 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3888 if (r)
3889 return false;
3890
3891 if (sctx->gs_shader.cso) {
3892 /* TES as ES */
3893 assert(sctx->chip_class <= GFX8);
3894 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3895 } else if (key.u.ngg) {
3896 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3897 } else {
3898 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3899 }
3900 }
3901 } else {
3902 if (sctx->chip_class <= GFX8)
3903 si_pm4_bind_state(sctx, ls, NULL);
3904 si_pm4_bind_state(sctx, hs, NULL);
3905 }
3906
3907 /* Update GS. */
3908 if (sctx->gs_shader.cso) {
3909 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3910 if (r)
3911 return false;
3912 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3913 if (!key.u.ngg) {
3914 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3915
3916 if (!si_update_gs_ring_buffers(sctx))
3917 return false;
3918 } else {
3919 si_pm4_bind_state(sctx, vs, NULL);
3920 }
3921 } else {
3922 if (!key.u.ngg) {
3923 si_pm4_bind_state(sctx, gs, NULL);
3924 if (sctx->chip_class <= GFX8)
3925 si_pm4_bind_state(sctx, es, NULL);
3926 }
3927 }
3928
3929 /* Update VS. */
3930 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3931 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3932 if (r)
3933 return false;
3934
3935 if (!key.u.tess && !key.u.gs) {
3936 if (key.u.ngg) {
3937 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3938 si_pm4_bind_state(sctx, vs, NULL);
3939 } else {
3940 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3941 }
3942 } else if (sctx->tes_shader.cso) {
3943 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3944 } else {
3945 assert(sctx->gs_shader.cso);
3946 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3947 }
3948 }
3949
3950 si_update_vgt_shader_config(sctx, key);
3951
3952 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3953 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3954
3955 if (sctx->ps_shader.cso) {
3956 unsigned db_shader_control;
3957
3958 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3959 if (r)
3960 return false;
3961 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3962
3963 db_shader_control =
3964 sctx->ps_shader.cso->db_shader_control |
3965 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3966
3967 if (si_pm4_state_changed(sctx, ps) ||
3968 si_pm4_state_changed(sctx, vs) ||
3969 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3970 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3971 sctx->flatshade != rs->flatshade) {
3972 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3973 sctx->flatshade = rs->flatshade;
3974 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3975 }
3976
3977 if (sctx->screen->rbplus_allowed &&
3978 si_pm4_state_changed(sctx, ps) &&
3979 (!old_ps ||
3980 old_spi_shader_col_format !=
3981 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3982 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3983
3984 if (sctx->ps_db_shader_control != db_shader_control) {
3985 sctx->ps_db_shader_control = db_shader_control;
3986 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3987 if (sctx->screen->dpbb_allowed)
3988 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3989 }
3990
3991 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3992 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3993 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3994
3995 if (sctx->chip_class == GFX6)
3996 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3997
3998 if (sctx->framebuffer.nr_samples <= 1)
3999 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4000 }
4001 }
4002
4003 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4004 si_pm4_state_enabled_and_changed(sctx, hs) ||
4005 si_pm4_state_enabled_and_changed(sctx, es) ||
4006 si_pm4_state_enabled_and_changed(sctx, gs) ||
4007 si_pm4_state_enabled_and_changed(sctx, vs) ||
4008 si_pm4_state_enabled_and_changed(sctx, ps)) {
4009 if (!si_update_spi_tmpring_size(sctx))
4010 return false;
4011 }
4012
4013 if (sctx->chip_class >= GFX7) {
4014 if (si_pm4_state_enabled_and_changed(sctx, ls))
4015 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4016 else if (!sctx->queued.named.ls)
4017 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4018
4019 if (si_pm4_state_enabled_and_changed(sctx, hs))
4020 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4021 else if (!sctx->queued.named.hs)
4022 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4023
4024 if (si_pm4_state_enabled_and_changed(sctx, es))
4025 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4026 else if (!sctx->queued.named.es)
4027 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4028
4029 if (si_pm4_state_enabled_and_changed(sctx, gs))
4030 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4031 else if (!sctx->queued.named.gs)
4032 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4033
4034 if (si_pm4_state_enabled_and_changed(sctx, vs))
4035 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4036 else if (!sctx->queued.named.vs)
4037 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4038
4039 if (si_pm4_state_enabled_and_changed(sctx, ps))
4040 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4041 else if (!sctx->queued.named.ps)
4042 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4043 }
4044
4045 sctx->do_update_shaders = false;
4046 return true;
4047 }
4048
4049 static void si_emit_scratch_state(struct si_context *sctx)
4050 {
4051 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4052
4053 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4054 sctx->spi_tmpring_size);
4055
4056 if (sctx->scratch_buffer) {
4057 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4058 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4059 RADEON_PRIO_SCRATCH_BUFFER);
4060 }
4061 }
4062
4063 void si_init_shader_functions(struct si_context *sctx)
4064 {
4065 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4066 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4067
4068 sctx->b.create_vs_state = si_create_shader_selector;
4069 sctx->b.create_tcs_state = si_create_shader_selector;
4070 sctx->b.create_tes_state = si_create_shader_selector;
4071 sctx->b.create_gs_state = si_create_shader_selector;
4072 sctx->b.create_fs_state = si_create_shader_selector;
4073
4074 sctx->b.bind_vs_state = si_bind_vs_shader;
4075 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4076 sctx->b.bind_tes_state = si_bind_tes_shader;
4077 sctx->b.bind_gs_state = si_bind_gs_shader;
4078 sctx->b.bind_fs_state = si_bind_ps_shader;
4079
4080 sctx->b.delete_vs_state = si_delete_shader_selector;
4081 sctx->b.delete_tcs_state = si_delete_shader_selector;
4082 sctx->b.delete_tes_state = si_delete_shader_selector;
4083 sctx->b.delete_gs_state = si_delete_shader_selector;
4084 sctx->b.delete_fs_state = si_delete_shader_selector;
4085 }