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radeonsi: compile non-GS middle parts of shaders immediately if enabled
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (!pm4)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->config.num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(1) |
128 S_00B528_FLOAT_MODE(shader->config.float_mode);
129 shader->config.rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
130 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
131 }
132
133 static void si_shader_hs(struct si_shader *shader)
134 {
135 struct si_pm4_state *pm4;
136 unsigned num_sgprs, num_user_sgprs;
137 uint64_t va;
138
139 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
140 if (!pm4)
141 return;
142
143 va = shader->bo->gpu_address;
144 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
145
146 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
147 num_sgprs = shader->config.num_sgprs;
148 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
149 * buffer offset. */
150 if ((num_user_sgprs + 1) > num_sgprs) {
151 /* Last 2 reserved SGPRs are used for VCC */
152 num_sgprs = num_user_sgprs + 1 + 2;
153 }
154 assert(num_sgprs <= 104);
155
156 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
157 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
158 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
159 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
160 S_00B428_SGPRS((num_sgprs - 1) / 8) |
161 S_00B428_DX10_CLAMP(1) |
162 S_00B428_FLOAT_MODE(shader->config.float_mode));
163 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
164 S_00B42C_USER_SGPR(num_user_sgprs) |
165 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
166 }
167
168 static void si_shader_es(struct si_shader *shader)
169 {
170 struct si_pm4_state *pm4;
171 unsigned num_sgprs, num_user_sgprs;
172 unsigned vgpr_comp_cnt;
173 uint64_t va;
174
175 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
176
177 if (!pm4)
178 return;
179
180 va = shader->bo->gpu_address;
181 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
182
183 if (shader->selector->type == PIPE_SHADER_VERTEX) {
184 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
185 num_user_sgprs = SI_ES_NUM_USER_SGPR;
186 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
187 vgpr_comp_cnt = 3; /* all components are needed for TES */
188 num_user_sgprs = SI_TES_NUM_USER_SGPR;
189 } else
190 unreachable("invalid shader selector type");
191
192 num_sgprs = shader->config.num_sgprs;
193 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
194 if ((num_user_sgprs + 1) > num_sgprs) {
195 /* Last 2 reserved SGPRs are used for VCC */
196 num_sgprs = num_user_sgprs + 1 + 2;
197 }
198 assert(num_sgprs <= 104);
199
200 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
201 shader->selector->esgs_itemsize / 4);
202 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
203 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
204 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
205 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
206 S_00B328_SGPRS((num_sgprs - 1) / 8) |
207 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
208 S_00B328_DX10_CLAMP(1) |
209 S_00B328_FLOAT_MODE(shader->config.float_mode));
210 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
211 S_00B32C_USER_SGPR(num_user_sgprs) |
212 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
213
214 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
215 si_set_tesseval_regs(shader, pm4);
216 }
217
218 /**
219 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
220 * geometry shader.
221 */
222 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
223 {
224 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
225 unsigned cut_mode;
226
227 if (gs_max_vert_out <= 128) {
228 cut_mode = V_028A40_GS_CUT_128;
229 } else if (gs_max_vert_out <= 256) {
230 cut_mode = V_028A40_GS_CUT_256;
231 } else if (gs_max_vert_out <= 512) {
232 cut_mode = V_028A40_GS_CUT_512;
233 } else {
234 assert(gs_max_vert_out <= 1024);
235 cut_mode = V_028A40_GS_CUT_1024;
236 }
237
238 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
239 S_028A40_CUT_MODE(cut_mode)|
240 S_028A40_ES_WRITE_OPTIMIZE(1) |
241 S_028A40_GS_WRITE_OPTIMIZE(1);
242 }
243
244 static void si_shader_gs(struct si_shader *shader)
245 {
246 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
247 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
248 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
249 struct si_pm4_state *pm4;
250 unsigned num_sgprs, num_user_sgprs;
251 uint64_t va;
252 unsigned max_stream = shader->selector->max_gs_stream;
253
254 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
255 assert(gsvs_itemsize < (1 << 15));
256
257 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
258
259 if (!pm4)
260 return;
261
262 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
263
264 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
265 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
266 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
267
268 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
269
270 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
271
272 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
273 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
274 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
275 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
276
277 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
278 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
279 S_028B90_ENABLE(gs_num_invocations > 0));
280
281 va = shader->bo->gpu_address;
282 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
283 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
284 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
285
286 num_user_sgprs = SI_GS_NUM_USER_SGPR;
287 num_sgprs = shader->config.num_sgprs;
288 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
289 if ((num_user_sgprs + 2) > num_sgprs) {
290 /* Last 2 reserved SGPRs are used for VCC */
291 num_sgprs = num_user_sgprs + 2 + 2;
292 }
293 assert(num_sgprs <= 104);
294
295 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
296 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
297 S_00B228_SGPRS((num_sgprs - 1) / 8) |
298 S_00B228_DX10_CLAMP(1) |
299 S_00B228_FLOAT_MODE(shader->config.float_mode));
300 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
301 S_00B22C_USER_SGPR(num_user_sgprs) |
302 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
303 }
304
305 /**
306 * Compute the state for \p shader, which will run as a vertex shader on the
307 * hardware.
308 *
309 * If \p gs is non-NULL, it points to the geometry shader for which this shader
310 * is the copy shader.
311 */
312 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
313 {
314 struct si_pm4_state *pm4;
315 unsigned num_sgprs, num_user_sgprs;
316 unsigned nparams, vgpr_comp_cnt;
317 uint64_t va;
318 unsigned window_space =
319 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
320 bool enable_prim_id = si_vs_exports_prim_id(shader);
321
322 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
323
324 if (!pm4)
325 return;
326
327 /* We always write VGT_GS_MODE in the VS state, because every switch
328 * between different shader pipelines involving a different GS or no
329 * GS at all involves a switch of the VS (different GS use different
330 * copy shaders). On the other hand, when the API switches from a GS to
331 * no GS and then back to the same GS used originally, the GS state is
332 * not sent again.
333 */
334 if (!gs) {
335 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
336 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
337 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
338 } else {
339 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
340 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
341 }
342
343 va = shader->bo->gpu_address;
344 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
345
346 if (gs) {
347 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
348 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
349 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
350 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
351 num_user_sgprs = SI_VS_NUM_USER_SGPR;
352 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
353 vgpr_comp_cnt = 3; /* all components are needed for TES */
354 num_user_sgprs = SI_TES_NUM_USER_SGPR;
355 } else
356 unreachable("invalid shader selector type");
357
358 num_sgprs = shader->config.num_sgprs;
359 if (num_user_sgprs > num_sgprs) {
360 /* Last 2 reserved SGPRs are used for VCC */
361 num_sgprs = num_user_sgprs + 2;
362 }
363 assert(num_sgprs <= 104);
364
365 /* VS is required to export at least one param. */
366 nparams = MAX2(shader->nr_param_exports, 1);
367 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
368 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
369
370 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
371 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
372 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
373 V_02870C_SPI_SHADER_4COMP :
374 V_02870C_SPI_SHADER_NONE) |
375 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
376 V_02870C_SPI_SHADER_4COMP :
377 V_02870C_SPI_SHADER_NONE) |
378 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
379 V_02870C_SPI_SHADER_4COMP :
380 V_02870C_SPI_SHADER_NONE));
381
382 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
383 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
384 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
385 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
386 S_00B128_SGPRS((num_sgprs - 1) / 8) |
387 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
388 S_00B128_DX10_CLAMP(1) |
389 S_00B128_FLOAT_MODE(shader->config.float_mode));
390 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
391 S_00B12C_USER_SGPR(num_user_sgprs) |
392 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
393 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
394 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
395 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
396 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
397 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
398 if (window_space)
399 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
400 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
401 else
402 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
403 S_028818_VTX_W0_FMT(1) |
404 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
405 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
406 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
407
408 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
409 si_set_tesseval_regs(shader, pm4);
410 }
411
412 static unsigned si_get_ps_num_interp(struct si_shader *ps)
413 {
414 struct tgsi_shader_info *info = &ps->selector->info;
415 unsigned num_colors = !!(info->colors_read & 0x0f) +
416 !!(info->colors_read & 0xf0);
417 unsigned num_interp = ps->selector->info.num_inputs +
418 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
419
420 assert(num_interp <= 32);
421 return MIN2(num_interp, 32);
422 }
423
424 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
425 {
426 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
427 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
428
429 /* If the i-th target format is set, all previous target formats must
430 * be non-zero to avoid hangs.
431 */
432 for (i = 0; i < num_targets; i++)
433 if (!(value & (0xf << (i * 4))))
434 value |= V_028714_SPI_SHADER_32_R << (i * 4);
435
436 return value;
437 }
438
439 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
440 {
441 unsigned i, cb_shader_mask = 0;
442
443 for (i = 0; i < 8; i++) {
444 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
445 case V_028714_SPI_SHADER_ZERO:
446 break;
447 case V_028714_SPI_SHADER_32_R:
448 cb_shader_mask |= 0x1 << (i * 4);
449 break;
450 case V_028714_SPI_SHADER_32_GR:
451 cb_shader_mask |= 0x3 << (i * 4);
452 break;
453 case V_028714_SPI_SHADER_32_AR:
454 cb_shader_mask |= 0x9 << (i * 4);
455 break;
456 case V_028714_SPI_SHADER_FP16_ABGR:
457 case V_028714_SPI_SHADER_UNORM16_ABGR:
458 case V_028714_SPI_SHADER_SNORM16_ABGR:
459 case V_028714_SPI_SHADER_UINT16_ABGR:
460 case V_028714_SPI_SHADER_SINT16_ABGR:
461 case V_028714_SPI_SHADER_32_ABGR:
462 cb_shader_mask |= 0xf << (i * 4);
463 break;
464 default:
465 assert(0);
466 }
467 }
468 return cb_shader_mask;
469 }
470
471 static void si_shader_ps(struct si_shader *shader)
472 {
473 struct tgsi_shader_info *info = &shader->selector->info;
474 struct si_pm4_state *pm4;
475 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
476 unsigned num_sgprs, num_user_sgprs;
477 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
478 uint64_t va;
479 bool has_centroid;
480 unsigned input_ena = shader->config.spi_ps_input_ena;
481
482 /* we need to enable at least one of them, otherwise we hang the GPU */
483 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
484 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
485 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
486 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
487 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
488 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
489 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
490 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
491
492 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
493
494 if (!pm4)
495 return;
496
497 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
498 * Possible vaules:
499 * 0 -> Position = pixel center
500 * 1 -> Position = pixel centroid
501 * 2 -> Position = at sample position
502 *
503 * From GLSL 4.5 specification, section 7.1:
504 * "The variable gl_FragCoord is available as an input variable from
505 * within fragment shaders and it holds the window relative coordinates
506 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
507 * value can be for any location within the pixel, or one of the
508 * fragment samples. The use of centroid does not further restrict
509 * this value to be inside the current primitive."
510 *
511 * Meaning that centroid has no effect and we can return anything within
512 * the pixel. Thus, return the value at sample position, because that's
513 * the most accurate one shaders can get.
514 */
515 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
516
517 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
518 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
519 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
520
521 spi_shader_col_format = si_get_spi_shader_col_format(shader);
522 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
523
524 /* This must be non-zero for alpha-test/kill to work.
525 * The hardware ignores the EXEC mask if no export memory is allocated.
526 * Don't add this to CB_SHADER_MASK.
527 */
528 if (!spi_shader_col_format &&
529 !info->writes_z && !info->writes_stencil && !info->writes_samplemask &&
530 (shader->selector->info.uses_kill ||
531 shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS))
532 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
533
534 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
535 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
536 shader->config.spi_ps_input_addr);
537
538 /* Set interpolation controls. */
539 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
540 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
541
542 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
543 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
544
545 /* Set registers. */
546 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
547 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
548
549 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
550 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
551 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
552 info->writes_z ? V_028710_SPI_SHADER_32_R :
553 V_028710_SPI_SHADER_ZERO);
554
555 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
556 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
557
558 va = shader->bo->gpu_address;
559 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
560 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
561 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
562
563 num_user_sgprs = SI_PS_NUM_USER_SGPR;
564 num_sgprs = shader->config.num_sgprs;
565 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
566 if ((num_user_sgprs + 1) > num_sgprs) {
567 /* Last 2 reserved SGPRs are used for VCC */
568 num_sgprs = num_user_sgprs + 1 + 2;
569 }
570 assert(num_sgprs <= 104);
571
572 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
573 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
574 S_00B028_SGPRS((num_sgprs - 1) / 8) |
575 S_00B028_DX10_CLAMP(1) |
576 S_00B028_FLOAT_MODE(shader->config.float_mode));
577 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
578 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
579 S_00B02C_USER_SGPR(num_user_sgprs) |
580 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
581 }
582
583 static void si_shader_init_pm4_state(struct si_shader *shader)
584 {
585
586 if (shader->pm4)
587 si_pm4_free_state_simple(shader->pm4);
588
589 switch (shader->selector->type) {
590 case PIPE_SHADER_VERTEX:
591 if (shader->key.vs.as_ls)
592 si_shader_ls(shader);
593 else if (shader->key.vs.as_es)
594 si_shader_es(shader);
595 else
596 si_shader_vs(shader, NULL);
597 break;
598 case PIPE_SHADER_TESS_CTRL:
599 si_shader_hs(shader);
600 break;
601 case PIPE_SHADER_TESS_EVAL:
602 if (shader->key.tes.as_es)
603 si_shader_es(shader);
604 else
605 si_shader_vs(shader, NULL);
606 break;
607 case PIPE_SHADER_GEOMETRY:
608 si_shader_gs(shader);
609 si_shader_vs(shader->gs_copy_shader, shader);
610 break;
611 case PIPE_SHADER_FRAGMENT:
612 si_shader_ps(shader);
613 break;
614 default:
615 assert(0);
616 }
617 }
618
619 static unsigned si_get_alpha_test_func(struct si_context *sctx)
620 {
621 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
622 if (sctx->queued.named.dsa &&
623 !sctx->framebuffer.cb0_is_integer)
624 return sctx->queued.named.dsa->alpha_func;
625
626 return PIPE_FUNC_ALWAYS;
627 }
628
629 /* Compute the key for the hw shader variant */
630 static inline void si_shader_selector_key(struct pipe_context *ctx,
631 struct si_shader_selector *sel,
632 union si_shader_key *key)
633 {
634 struct si_context *sctx = (struct si_context *)ctx;
635 unsigned i;
636
637 memset(key, 0, sizeof(*key));
638
639 switch (sel->type) {
640 case PIPE_SHADER_VERTEX:
641 if (sctx->vertex_elements) {
642 unsigned count = MIN2(sel->info.num_inputs,
643 sctx->vertex_elements->count);
644 for (i = 0; i < count; ++i)
645 key->vs.prolog.instance_divisors[i] =
646 sctx->vertex_elements->elements[i].instance_divisor;
647 }
648 if (sctx->tes_shader.cso)
649 key->vs.as_ls = 1;
650 else if (sctx->gs_shader.cso)
651 key->vs.as_es = 1;
652
653 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
654 sctx->ps_shader.cso->info.uses_primid)
655 key->vs.epilog.export_prim_id = 1;
656 break;
657 case PIPE_SHADER_TESS_CTRL:
658 key->tcs.epilog.prim_mode =
659 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
660 break;
661 case PIPE_SHADER_TESS_EVAL:
662 if (sctx->gs_shader.cso)
663 key->tes.as_es = 1;
664 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
665 key->tes.epilog.export_prim_id = 1;
666 break;
667 case PIPE_SHADER_GEOMETRY:
668 break;
669 case PIPE_SHADER_FRAGMENT: {
670 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
671 struct si_state_blend *blend = sctx->queued.named.blend;
672
673 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
674 sel->info.colors_written == 0x1)
675 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
676
677 if (blend) {
678 /* Select the shader color format based on whether
679 * blending or alpha are needed.
680 */
681 key->ps.epilog.spi_shader_col_format =
682 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
683 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
684 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
685 sctx->framebuffer.spi_shader_col_format_blend) |
686 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
687 sctx->framebuffer.spi_shader_col_format_alpha) |
688 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
689 sctx->framebuffer.spi_shader_col_format);
690 } else
691 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
692
693 /* If alpha-to-coverage is enabled, we have to export alpha
694 * even if there is no color buffer.
695 */
696 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
697 blend && blend->alpha_to_coverage)
698 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
699
700 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
701 * to the range supported by the type if a channel has less
702 * than 16 bits and the export format is 16_ABGR.
703 */
704 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
705 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
706
707 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
708 if (!key->ps.epilog.last_cbuf) {
709 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
710 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
711 }
712
713 if (rs) {
714 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
715 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
716 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
717 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
718
719 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
720
721 if (sctx->queued.named.blend) {
722 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
723 rs->multisample_enable &&
724 !sctx->framebuffer.cb0_is_integer;
725 }
726
727 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
728 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
729 (is_line && rs->line_smooth)) &&
730 sctx->framebuffer.nr_samples <= 1;
731 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
732
733 key->ps.prolog.force_persample_interp =
734 rs->force_persample_interp &&
735 rs->multisample_enable &&
736 sctx->framebuffer.nr_samples > 1 &&
737 sctx->ps_iter_samples > 1 &&
738 (sel->info.uses_persp_center ||
739 sel->info.uses_persp_centroid ||
740 sel->info.uses_linear_center ||
741 sel->info.uses_linear_centroid);
742 }
743
744 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
745 break;
746 }
747 default:
748 assert(0);
749 }
750 }
751
752 /* Select the hw shader variant depending on the current state. */
753 static int si_shader_select_with_key(struct pipe_context *ctx,
754 struct si_shader_ctx_state *state,
755 union si_shader_key *key)
756 {
757 struct si_context *sctx = (struct si_context *)ctx;
758 struct si_shader_selector *sel = state->cso;
759 struct si_shader *current = state->current;
760 struct si_shader *iter, *shader = NULL;
761 int r;
762
763 /* Check if we don't need to change anything.
764 * This path is also used for most shaders that don't need multiple
765 * variants, it will cost just a computation of the key and this
766 * test. */
767 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
768 return 0;
769
770 pipe_mutex_lock(sel->mutex);
771
772 /* Find the shader variant. */
773 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
774 /* Don't check the "current" shader. We checked it above. */
775 if (current != iter &&
776 memcmp(&iter->key, key, sizeof(*key)) == 0) {
777 state->current = iter;
778 pipe_mutex_unlock(sel->mutex);
779 return 0;
780 }
781 }
782
783 /* Build a new shader. */
784 shader = CALLOC_STRUCT(si_shader);
785 if (!shader) {
786 pipe_mutex_unlock(sel->mutex);
787 return -ENOMEM;
788 }
789 shader->selector = sel;
790 shader->key = *key;
791
792 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
793 if (unlikely(r)) {
794 R600_ERR("Failed to build shader variant (type=%u) %d\n",
795 sel->type, r);
796 FREE(shader);
797 pipe_mutex_unlock(sel->mutex);
798 return r;
799 }
800 si_shader_init_pm4_state(shader);
801
802 if (!sel->last_variant) {
803 sel->first_variant = shader;
804 sel->last_variant = shader;
805 } else {
806 sel->last_variant->next_variant = shader;
807 sel->last_variant = shader;
808 }
809 state->current = shader;
810 pipe_mutex_unlock(sel->mutex);
811 return 0;
812 }
813
814 static int si_shader_select(struct pipe_context *ctx,
815 struct si_shader_ctx_state *state)
816 {
817 union si_shader_key key;
818
819 si_shader_selector_key(ctx, state->cso, &key);
820 return si_shader_select_with_key(ctx, state, &key);
821 }
822
823 static void *si_create_shader_selector(struct pipe_context *ctx,
824 const struct pipe_shader_state *state)
825 {
826 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
827 struct si_context *sctx = (struct si_context*)ctx;
828 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
829 int i;
830
831 if (!sel)
832 return NULL;
833
834 sel->tokens = tgsi_dup_tokens(state->tokens);
835 if (!sel->tokens) {
836 FREE(sel);
837 return NULL;
838 }
839
840 sel->so = state->stream_output;
841 tgsi_scan_shader(state->tokens, &sel->info);
842 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
843 p_atomic_inc(&sscreen->b.num_shaders_created);
844
845 /* Set which opcode uses which (i,j) pair. */
846 if (sel->info.uses_persp_opcode_interp_centroid)
847 sel->info.uses_persp_centroid = true;
848
849 if (sel->info.uses_linear_opcode_interp_centroid)
850 sel->info.uses_linear_centroid = true;
851
852 if (sel->info.uses_persp_opcode_interp_offset ||
853 sel->info.uses_persp_opcode_interp_sample)
854 sel->info.uses_persp_center = true;
855
856 if (sel->info.uses_linear_opcode_interp_offset ||
857 sel->info.uses_linear_opcode_interp_sample)
858 sel->info.uses_linear_center = true;
859
860 switch (sel->type) {
861 case PIPE_SHADER_GEOMETRY:
862 sel->gs_output_prim =
863 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
864 sel->gs_max_out_vertices =
865 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
866 sel->gs_num_invocations =
867 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
868 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
869 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
870 sel->gs_max_out_vertices;
871
872 sel->max_gs_stream = 0;
873 for (i = 0; i < sel->so.num_outputs; i++)
874 sel->max_gs_stream = MAX2(sel->max_gs_stream,
875 sel->so.output[i].stream);
876
877 sel->gs_input_verts_per_prim =
878 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
879 break;
880
881 case PIPE_SHADER_VERTEX:
882 case PIPE_SHADER_TESS_CTRL:
883 case PIPE_SHADER_TESS_EVAL:
884 for (i = 0; i < sel->info.num_outputs; i++) {
885 unsigned name = sel->info.output_semantic_name[i];
886 unsigned index = sel->info.output_semantic_index[i];
887
888 switch (name) {
889 case TGSI_SEMANTIC_TESSINNER:
890 case TGSI_SEMANTIC_TESSOUTER:
891 case TGSI_SEMANTIC_PATCH:
892 sel->patch_outputs_written |=
893 1llu << si_shader_io_get_unique_index(name, index);
894 break;
895 default:
896 sel->outputs_written |=
897 1llu << si_shader_io_get_unique_index(name, index);
898 }
899 }
900 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
901 break;
902
903 case PIPE_SHADER_FRAGMENT:
904 for (i = 0; i < 8; i++)
905 if (sel->info.colors_written & (1 << i))
906 sel->colors_written_4bit |= 0xf << (4 * i);
907
908 for (i = 0; i < sel->info.num_inputs; i++) {
909 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
910 int index = sel->info.input_semantic_index[i];
911 sel->color_attr_index[index] = i;
912 }
913 }
914 break;
915 }
916
917 /* DB_SHADER_CONTROL */
918 sel->db_shader_control =
919 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
920 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
921 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
922 S_02880C_KILL_ENABLE(sel->info.uses_kill);
923
924 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
925 case TGSI_FS_DEPTH_LAYOUT_GREATER:
926 sel->db_shader_control |=
927 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
928 break;
929 case TGSI_FS_DEPTH_LAYOUT_LESS:
930 sel->db_shader_control |=
931 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
932 break;
933 }
934
935 /* Compile the main shader part for use with a prolog and/or epilog. */
936 if (sel->type != PIPE_SHADER_GEOMETRY &&
937 !sscreen->use_monolithic_shaders) {
938 struct si_shader *shader = CALLOC_STRUCT(si_shader);
939
940 if (!shader)
941 goto error;
942
943 shader->selector = sel;
944
945 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
946 &sctx->b.debug) != 0) {
947 FREE(shader);
948 goto error;
949 }
950 sel->main_shader_part = shader;
951 }
952
953 /* Pre-compilation. */
954 if (sel->type == PIPE_SHADER_GEOMETRY ||
955 sscreen->b.debug_flags & DBG_PRECOMPILE) {
956 struct si_shader_ctx_state state = {sel};
957 union si_shader_key key;
958
959 memset(&key, 0, sizeof(key));
960
961 /* Set reasonable defaults, so that the shader key doesn't
962 * cause any code to be eliminated.
963 */
964 switch (sel->type) {
965 case PIPE_SHADER_TESS_CTRL:
966 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
967 break;
968 case PIPE_SHADER_FRAGMENT:
969 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
970 for (i = 0; i < 8; i++)
971 if (sel->info.colors_written & (1 << i))
972 key.ps.epilog.spi_shader_col_format |=
973 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
974 break;
975 }
976
977 if (si_shader_select_with_key(ctx, &state, &key))
978 goto error;
979 }
980
981 pipe_mutex_init(sel->mutex);
982 return sel;
983
984 error:
985 fprintf(stderr, "radeonsi: can't create a shader\n");
986 tgsi_free_tokens(sel->tokens);
987 FREE(sel);
988 return NULL;
989 }
990
991 /**
992 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
993 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
994 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
995 * called to emit the rest.
996 */
997 static void si_update_viewports_and_scissors(struct si_context *sctx)
998 {
999 struct tgsi_shader_info *info = si_get_vs_info(sctx);
1000
1001 if (!info || !info->writes_viewport_index)
1002 return;
1003
1004 if (sctx->scissors.dirty_mask)
1005 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1006 if (sctx->viewports.dirty_mask)
1007 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1008 }
1009
1010 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1011 {
1012 struct si_context *sctx = (struct si_context *)ctx;
1013 struct si_shader_selector *sel = state;
1014
1015 if (sctx->vs_shader.cso == sel)
1016 return;
1017
1018 sctx->vs_shader.cso = sel;
1019 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1020 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1021 si_update_viewports_and_scissors(sctx);
1022 }
1023
1024 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1025 {
1026 struct si_context *sctx = (struct si_context *)ctx;
1027 struct si_shader_selector *sel = state;
1028 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1029
1030 if (sctx->gs_shader.cso == sel)
1031 return;
1032
1033 sctx->gs_shader.cso = sel;
1034 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1035 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1036 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1037
1038 if (enable_changed)
1039 si_shader_change_notify(sctx);
1040 si_update_viewports_and_scissors(sctx);
1041 }
1042
1043 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1044 {
1045 struct si_context *sctx = (struct si_context *)ctx;
1046 struct si_shader_selector *sel = state;
1047 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1048
1049 if (sctx->tcs_shader.cso == sel)
1050 return;
1051
1052 sctx->tcs_shader.cso = sel;
1053 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1054
1055 if (enable_changed)
1056 sctx->last_tcs = NULL; /* invalidate derived tess state */
1057 }
1058
1059 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1060 {
1061 struct si_context *sctx = (struct si_context *)ctx;
1062 struct si_shader_selector *sel = state;
1063 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1064
1065 if (sctx->tes_shader.cso == sel)
1066 return;
1067
1068 sctx->tes_shader.cso = sel;
1069 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1070 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1071 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1072
1073 if (enable_changed) {
1074 si_shader_change_notify(sctx);
1075 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1076 }
1077 si_update_viewports_and_scissors(sctx);
1078 }
1079
1080 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1081 {
1082 struct si_context *sctx = (struct si_context *)ctx;
1083 struct si_shader_selector *sel = state;
1084
1085 /* skip if supplied shader is one already in use */
1086 if (sctx->ps_shader.cso == sel)
1087 return;
1088
1089 sctx->ps_shader.cso = sel;
1090 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1091 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1092 }
1093
1094 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1095 {
1096 if (shader->pm4) {
1097 switch (shader->selector->type) {
1098 case PIPE_SHADER_VERTEX:
1099 if (shader->key.vs.as_ls)
1100 si_pm4_delete_state(sctx, ls, shader->pm4);
1101 else if (shader->key.vs.as_es)
1102 si_pm4_delete_state(sctx, es, shader->pm4);
1103 else
1104 si_pm4_delete_state(sctx, vs, shader->pm4);
1105 break;
1106 case PIPE_SHADER_TESS_CTRL:
1107 si_pm4_delete_state(sctx, hs, shader->pm4);
1108 break;
1109 case PIPE_SHADER_TESS_EVAL:
1110 if (shader->key.tes.as_es)
1111 si_pm4_delete_state(sctx, es, shader->pm4);
1112 else
1113 si_pm4_delete_state(sctx, vs, shader->pm4);
1114 break;
1115 case PIPE_SHADER_GEOMETRY:
1116 si_pm4_delete_state(sctx, gs, shader->pm4);
1117 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1118 break;
1119 case PIPE_SHADER_FRAGMENT:
1120 si_pm4_delete_state(sctx, ps, shader->pm4);
1121 break;
1122 }
1123 }
1124
1125 si_shader_destroy(shader);
1126 free(shader);
1127 }
1128
1129 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1130 {
1131 struct si_context *sctx = (struct si_context *)ctx;
1132 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1133 struct si_shader *p = sel->first_variant, *c;
1134 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1135 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1136 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1137 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1138 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1139 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1140 };
1141
1142 if (current_shader[sel->type]->cso == sel) {
1143 current_shader[sel->type]->cso = NULL;
1144 current_shader[sel->type]->current = NULL;
1145 }
1146
1147 while (p) {
1148 c = p->next_variant;
1149 si_delete_shader(sctx, p);
1150 p = c;
1151 }
1152
1153 if (sel->main_shader_part)
1154 si_delete_shader(sctx, sel->main_shader_part);
1155
1156 pipe_mutex_destroy(sel->mutex);
1157 free(sel->tokens);
1158 free(sel);
1159 }
1160
1161 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1162 struct si_shader *vs, unsigned name,
1163 unsigned index, unsigned interpolate)
1164 {
1165 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1166 unsigned j, ps_input_cntl = 0;
1167
1168 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1169 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1170 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1171
1172 if (name == TGSI_SEMANTIC_PCOORD ||
1173 (name == TGSI_SEMANTIC_TEXCOORD &&
1174 sctx->sprite_coord_enable & (1 << index))) {
1175 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1176 }
1177
1178 for (j = 0; j < vsinfo->num_outputs; j++) {
1179 if (name == vsinfo->output_semantic_name[j] &&
1180 index == vsinfo->output_semantic_index[j]) {
1181 ps_input_cntl |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
1182 break;
1183 }
1184 }
1185
1186 if (name == TGSI_SEMANTIC_PRIMID)
1187 /* PrimID is written after the last output. */
1188 ps_input_cntl |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
1189 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1190 /* No corresponding output found, load defaults into input.
1191 * Don't set any other bits.
1192 * (FLAT_SHADE=1 completely changes behavior) */
1193 ps_input_cntl = S_028644_OFFSET(0x20);
1194 }
1195 return ps_input_cntl;
1196 }
1197
1198 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1199 {
1200 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1201 struct si_shader *ps = sctx->ps_shader.current;
1202 struct si_shader *vs = si_get_vs_state(sctx);
1203 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1204 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1205
1206 if (!ps || !ps->selector->info.num_inputs)
1207 return;
1208
1209 num_interp = si_get_ps_num_interp(ps);
1210 assert(num_interp > 0);
1211 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1212
1213 for (i = 0; i < psinfo->num_inputs; i++) {
1214 unsigned name = psinfo->input_semantic_name[i];
1215 unsigned index = psinfo->input_semantic_index[i];
1216 unsigned interpolate = psinfo->input_interpolate[i];
1217
1218 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1219 interpolate));
1220 num_written++;
1221
1222 if (name == TGSI_SEMANTIC_COLOR) {
1223 assert(index < ARRAY_SIZE(bcol_interp));
1224 bcol_interp[index] = interpolate;
1225 }
1226 }
1227
1228 if (ps->key.ps.prolog.color_two_side) {
1229 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1230
1231 for (i = 0; i < 2; i++) {
1232 if (!(psinfo->colors_read & (0xf << (i * 4))))
1233 continue;
1234
1235 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1236 i, bcol_interp[i]));
1237 num_written++;
1238 }
1239 }
1240 assert(num_interp == num_written);
1241 }
1242
1243 /**
1244 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1245 */
1246 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1247 {
1248 if (sctx->init_config_has_vgt_flush)
1249 return;
1250
1251 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1252 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1253 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1254 si_pm4_cmd_end(sctx->init_config, false);
1255 sctx->init_config_has_vgt_flush = true;
1256 }
1257
1258 /* Initialize state related to ESGS / GSVS ring buffers */
1259 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1260 {
1261 struct si_shader_selector *es =
1262 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1263 struct si_shader_selector *gs = sctx->gs_shader.cso;
1264 struct si_pm4_state *pm4;
1265
1266 /* Chip constants. */
1267 unsigned num_se = sctx->screen->b.info.max_se;
1268 unsigned wave_size = 64;
1269 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1270 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1271 unsigned alignment = 256 * num_se;
1272 /* The maximum size is 63.999 MB per SE. */
1273 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1274
1275 /* Calculate the minimum size. */
1276 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1277 wave_size, alignment);
1278
1279 /* These are recommended sizes, not minimum sizes. */
1280 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1281 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1282 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1283 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1284
1285 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1286 esgs_ring_size = align(esgs_ring_size, alignment);
1287 gsvs_ring_size = align(gsvs_ring_size, alignment);
1288
1289 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1290 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1291
1292 /* Some rings don't have to be allocated if shaders don't use them.
1293 * (e.g. no varyings between ES and GS or GS and VS)
1294 */
1295 bool update_esgs = esgs_ring_size &&
1296 (!sctx->esgs_ring ||
1297 sctx->esgs_ring->width0 < esgs_ring_size);
1298 bool update_gsvs = gsvs_ring_size &&
1299 (!sctx->gsvs_ring ||
1300 sctx->gsvs_ring->width0 < gsvs_ring_size);
1301
1302 if (!update_esgs && !update_gsvs)
1303 return true;
1304
1305 if (update_esgs) {
1306 pipe_resource_reference(&sctx->esgs_ring, NULL);
1307 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1308 PIPE_USAGE_DEFAULT,
1309 esgs_ring_size);
1310 if (!sctx->esgs_ring)
1311 return false;
1312 }
1313
1314 if (update_gsvs) {
1315 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1316 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1317 PIPE_USAGE_DEFAULT,
1318 gsvs_ring_size);
1319 if (!sctx->gsvs_ring)
1320 return false;
1321 }
1322
1323 /* Create the "init_config_gs_rings" state. */
1324 pm4 = CALLOC_STRUCT(si_pm4_state);
1325 if (!pm4)
1326 return false;
1327
1328 if (sctx->b.chip_class >= CIK) {
1329 if (sctx->esgs_ring)
1330 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1331 sctx->esgs_ring->width0 / 256);
1332 if (sctx->gsvs_ring)
1333 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1334 sctx->gsvs_ring->width0 / 256);
1335 } else {
1336 if (sctx->esgs_ring)
1337 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1338 sctx->esgs_ring->width0 / 256);
1339 if (sctx->gsvs_ring)
1340 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1341 sctx->gsvs_ring->width0 / 256);
1342 }
1343
1344 /* Set the state. */
1345 if (sctx->init_config_gs_rings)
1346 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1347 sctx->init_config_gs_rings = pm4;
1348
1349 if (!sctx->init_config_has_vgt_flush) {
1350 si_init_config_add_vgt_flush(sctx);
1351 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1352 }
1353
1354 /* Flush the context to re-emit both init_config states. */
1355 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1356 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1357
1358 /* Set ring bindings. */
1359 if (sctx->esgs_ring) {
1360 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1361 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1362 true, true, 4, 64, 0);
1363 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1364 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1365 false, false, 0, 0, 0);
1366 }
1367 if (sctx->gsvs_ring)
1368 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1369 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1370 false, false, 0, 0, 0);
1371 return true;
1372 }
1373
1374 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1375 {
1376 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1377 uint64_t offset;
1378
1379 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1380 return;
1381
1382 sctx->last_gsvs_itemsize = gsvs_itemsize;
1383
1384 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1385 sctx->gsvs_ring, gsvs_itemsize,
1386 64, true, true, 4, 16, 0);
1387
1388 offset = gsvs_itemsize * 64;
1389 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1390 sctx->gsvs_ring, gsvs_itemsize,
1391 64, true, true, 4, 16, offset);
1392
1393 offset = (gsvs_itemsize * 2) * 64;
1394 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1395 sctx->gsvs_ring, gsvs_itemsize,
1396 64, true, true, 4, 16, offset);
1397
1398 offset = (gsvs_itemsize * 3) * 64;
1399 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1400 sctx->gsvs_ring, gsvs_itemsize,
1401 64, true, true, 4, 16, offset);
1402 }
1403
1404 /**
1405 * @returns 1 if \p sel has been updated to use a new scratch buffer
1406 * 0 if not
1407 * < 0 if there was a failure
1408 */
1409 static int si_update_scratch_buffer(struct si_context *sctx,
1410 struct si_shader *shader)
1411 {
1412 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1413 int r;
1414
1415 if (!shader)
1416 return 0;
1417
1418 /* This shader doesn't need a scratch buffer */
1419 if (shader->config.scratch_bytes_per_wave == 0)
1420 return 0;
1421
1422 /* This shader is already configured to use the current
1423 * scratch buffer. */
1424 if (shader->scratch_bo == sctx->scratch_buffer)
1425 return 0;
1426
1427 assert(sctx->scratch_buffer);
1428
1429 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1430
1431 /* Replace the shader bo with a new bo that has the relocs applied. */
1432 r = si_shader_binary_upload(sctx->screen, shader);
1433 if (r)
1434 return r;
1435
1436 /* Update the shader state to use the new shader bo. */
1437 si_shader_init_pm4_state(shader);
1438
1439 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1440
1441 return 1;
1442 }
1443
1444 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1445 {
1446 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1447 }
1448
1449 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1450 {
1451 return shader ? shader->config.scratch_bytes_per_wave : 0;
1452 }
1453
1454 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1455 {
1456 unsigned bytes = 0;
1457
1458 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1459 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1460 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1461 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1462 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1463 return bytes;
1464 }
1465
1466 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1467 {
1468 unsigned current_scratch_buffer_size =
1469 si_get_current_scratch_buffer_size(sctx);
1470 unsigned scratch_bytes_per_wave =
1471 si_get_max_scratch_bytes_per_wave(sctx);
1472 unsigned scratch_needed_size = scratch_bytes_per_wave *
1473 sctx->scratch_waves;
1474 unsigned spi_tmpring_size;
1475 int r;
1476
1477 if (scratch_needed_size > 0) {
1478 if (scratch_needed_size > current_scratch_buffer_size) {
1479 /* Create a bigger scratch buffer */
1480 pipe_resource_reference(
1481 (struct pipe_resource**)&sctx->scratch_buffer,
1482 NULL);
1483
1484 sctx->scratch_buffer =
1485 si_resource_create_custom(&sctx->screen->b.b,
1486 PIPE_USAGE_DEFAULT, scratch_needed_size);
1487 if (!sctx->scratch_buffer)
1488 return false;
1489 sctx->emit_scratch_reloc = true;
1490 }
1491
1492 /* Update the shaders, so they are using the latest scratch. The
1493 * scratch buffer may have been changed since these shaders were
1494 * last used, so we still need to try to update them, even if
1495 * they require scratch buffers smaller than the current size.
1496 */
1497 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1498 if (r < 0)
1499 return false;
1500 if (r == 1)
1501 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1502
1503 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1504 if (r < 0)
1505 return false;
1506 if (r == 1)
1507 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1508
1509 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1510 if (r < 0)
1511 return false;
1512 if (r == 1)
1513 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1514
1515 /* VS can be bound as LS, ES, or VS. */
1516 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1517 if (r < 0)
1518 return false;
1519 if (r == 1) {
1520 if (sctx->tes_shader.current)
1521 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1522 else if (sctx->gs_shader.current)
1523 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1524 else
1525 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1526 }
1527
1528 /* TES can be bound as ES or VS. */
1529 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1530 if (r < 0)
1531 return false;
1532 if (r == 1) {
1533 if (sctx->gs_shader.current)
1534 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1535 else
1536 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1537 }
1538 }
1539
1540 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1541 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1542 "scratch size should already be aligned correctly.");
1543
1544 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1545 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1546 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1547 sctx->spi_tmpring_size = spi_tmpring_size;
1548 sctx->emit_scratch_reloc = true;
1549 }
1550 return true;
1551 }
1552
1553 static void si_init_tess_factor_ring(struct si_context *sctx)
1554 {
1555 assert(!sctx->tf_ring);
1556
1557 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1558 PIPE_USAGE_DEFAULT,
1559 32768 * sctx->screen->b.info.max_se);
1560 if (!sctx->tf_ring)
1561 return;
1562
1563 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1564
1565 si_init_config_add_vgt_flush(sctx);
1566
1567 /* Append these registers to the init config state. */
1568 if (sctx->b.chip_class >= CIK) {
1569 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1570 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1571 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1572 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1573 } else {
1574 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1575 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1576 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1577 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1578 }
1579
1580 /* Flush the context to re-emit the init_config state.
1581 * This is done only once in a lifetime of a context.
1582 */
1583 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1584 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1585 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1586
1587 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1588 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1589 sctx->tf_ring->width0, false, false, 0, 0, 0);
1590 }
1591
1592 /**
1593 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1594 * VS passes its outputs to TES directly, so the fixed-function shader only
1595 * has to write TESSOUTER and TESSINNER.
1596 */
1597 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1598 {
1599 struct ureg_src const0, const1;
1600 struct ureg_dst tessouter, tessinner;
1601 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1602
1603 if (!ureg)
1604 return; /* if we get here, we're screwed */
1605
1606 assert(!sctx->fixed_func_tcs_shader.cso);
1607
1608 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1609 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1610 SI_DRIVER_STATE_CONST_BUF);
1611 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1612 SI_DRIVER_STATE_CONST_BUF);
1613
1614 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1615 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1616
1617 ureg_MOV(ureg, tessouter, const0);
1618 ureg_MOV(ureg, tessinner, const1);
1619 ureg_END(ureg);
1620
1621 sctx->fixed_func_tcs_shader.cso =
1622 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1623 }
1624
1625 static void si_update_vgt_shader_config(struct si_context *sctx)
1626 {
1627 /* Calculate the index of the config.
1628 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1629 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1630 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1631
1632 if (!*pm4) {
1633 uint32_t stages = 0;
1634
1635 *pm4 = CALLOC_STRUCT(si_pm4_state);
1636
1637 if (sctx->tes_shader.cso) {
1638 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1639 S_028B54_HS_EN(1);
1640
1641 if (sctx->gs_shader.cso)
1642 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1643 S_028B54_GS_EN(1) |
1644 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1645 else
1646 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1647 } else if (sctx->gs_shader.cso) {
1648 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1649 S_028B54_GS_EN(1) |
1650 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1651 }
1652
1653 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1654 }
1655 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1656 }
1657
1658 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1659 {
1660 struct pipe_stream_output_info *so = &shader->so;
1661 uint32_t enabled_stream_buffers_mask = 0;
1662 int i;
1663
1664 for (i = 0; i < so->num_outputs; i++)
1665 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1666 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1667 sctx->b.streamout.stride_in_dw = shader->so.stride;
1668 }
1669
1670 bool si_update_shaders(struct si_context *sctx)
1671 {
1672 struct pipe_context *ctx = (struct pipe_context*)sctx;
1673 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1674 int r;
1675
1676 /* Update stages before GS. */
1677 if (sctx->tes_shader.cso) {
1678 if (!sctx->tf_ring) {
1679 si_init_tess_factor_ring(sctx);
1680 if (!sctx->tf_ring)
1681 return false;
1682 }
1683
1684 /* VS as LS */
1685 r = si_shader_select(ctx, &sctx->vs_shader);
1686 if (r)
1687 return false;
1688 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1689
1690 if (sctx->tcs_shader.cso) {
1691 r = si_shader_select(ctx, &sctx->tcs_shader);
1692 if (r)
1693 return false;
1694 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1695 } else {
1696 if (!sctx->fixed_func_tcs_shader.cso) {
1697 si_generate_fixed_func_tcs(sctx);
1698 if (!sctx->fixed_func_tcs_shader.cso)
1699 return false;
1700 }
1701
1702 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1703 if (r)
1704 return false;
1705 si_pm4_bind_state(sctx, hs,
1706 sctx->fixed_func_tcs_shader.current->pm4);
1707 }
1708
1709 r = si_shader_select(ctx, &sctx->tes_shader);
1710 if (r)
1711 return false;
1712
1713 if (sctx->gs_shader.cso) {
1714 /* TES as ES */
1715 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1716 } else {
1717 /* TES as VS */
1718 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1719 si_update_so(sctx, sctx->tes_shader.cso);
1720 }
1721 } else if (sctx->gs_shader.cso) {
1722 /* VS as ES */
1723 r = si_shader_select(ctx, &sctx->vs_shader);
1724 if (r)
1725 return false;
1726 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1727 } else {
1728 /* VS as VS */
1729 r = si_shader_select(ctx, &sctx->vs_shader);
1730 if (r)
1731 return false;
1732 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1733 si_update_so(sctx, sctx->vs_shader.cso);
1734 }
1735
1736 /* Update GS. */
1737 if (sctx->gs_shader.cso) {
1738 r = si_shader_select(ctx, &sctx->gs_shader);
1739 if (r)
1740 return false;
1741 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1742 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1743 si_update_so(sctx, sctx->gs_shader.cso);
1744
1745 if (!si_update_gs_ring_buffers(sctx))
1746 return false;
1747
1748 si_update_gsvs_ring_bindings(sctx);
1749 } else {
1750 si_pm4_bind_state(sctx, gs, NULL);
1751 si_pm4_bind_state(sctx, es, NULL);
1752 }
1753
1754 si_update_vgt_shader_config(sctx);
1755
1756 if (sctx->ps_shader.cso) {
1757 unsigned db_shader_control =
1758 sctx->ps_shader.cso->db_shader_control |
1759 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
1760
1761 r = si_shader_select(ctx, &sctx->ps_shader);
1762 if (r)
1763 return false;
1764 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1765
1766 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1767 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1768 sctx->flatshade != rs->flatshade) {
1769 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1770 sctx->flatshade = rs->flatshade;
1771 si_mark_atom_dirty(sctx, &sctx->spi_map);
1772 }
1773
1774 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
1775 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1776
1777 if (sctx->ps_db_shader_control != db_shader_control) {
1778 sctx->ps_db_shader_control = db_shader_control;
1779 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1780 }
1781
1782 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
1783 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
1784 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1785
1786 if (sctx->b.chip_class == SI)
1787 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1788 }
1789 }
1790
1791 if (si_pm4_state_changed(sctx, ls) ||
1792 si_pm4_state_changed(sctx, hs) ||
1793 si_pm4_state_changed(sctx, es) ||
1794 si_pm4_state_changed(sctx, gs) ||
1795 si_pm4_state_changed(sctx, vs) ||
1796 si_pm4_state_changed(sctx, ps)) {
1797 if (!si_update_spi_tmpring_size(sctx))
1798 return false;
1799 }
1800 return true;
1801 }
1802
1803 void si_init_shader_functions(struct si_context *sctx)
1804 {
1805 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1806
1807 sctx->b.b.create_vs_state = si_create_shader_selector;
1808 sctx->b.b.create_tcs_state = si_create_shader_selector;
1809 sctx->b.b.create_tes_state = si_create_shader_selector;
1810 sctx->b.b.create_gs_state = si_create_shader_selector;
1811 sctx->b.b.create_fs_state = si_create_shader_selector;
1812
1813 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1814 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1815 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1816 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1817 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1818
1819 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1820 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1821 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1822 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1823 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1824 }