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radeonsi/gfx10: unbind NGG shaders when destroyed
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10)
422 return;
423
424 /* VS as VS, or VS as ES: */
425 if ((type == PIPE_SHADER_VERTEX &&
426 (!shader ||
427 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
428 /* TES as VS, or TES as ES: */
429 type == PIPE_SHADER_TESS_EVAL) {
430 unsigned vtx_reuse_depth = 30;
431
432 if (type == PIPE_SHADER_TESS_EVAL &&
433 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD)
435 vtx_reuse_depth = 14;
436
437 assert(pm4->shader);
438 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
439 }
440 }
441
442 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
443 {
444 if (shader->pm4)
445 si_pm4_clear_state(shader->pm4);
446 else
447 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
448
449 if (shader->pm4) {
450 shader->pm4->shader = shader;
451 return shader->pm4;
452 } else {
453 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
454 return NULL;
455 }
456 }
457
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
459 {
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs + 1;
462 }
463
464 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
465 {
466 struct si_pm4_state *pm4;
467 unsigned vgpr_comp_cnt;
468 uint64_t va;
469
470 assert(sscreen->info.chip_class <= GFX8);
471
472 pm4 = si_get_shader_pm4_state(shader);
473 if (!pm4)
474 return;
475
476 va = shader->bo->gpu_address;
477 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
478
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
482 */
483 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
484
485 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
486 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
487
488 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
489 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader->config.float_mode);
493 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
494 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
495 }
496
497 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
498 {
499 struct si_pm4_state *pm4;
500 uint64_t va;
501 unsigned ls_vgpr_comp_cnt = 0;
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 if (sscreen->info.chip_class >= GFX9) {
511 if (sscreen->info.chip_class >= GFX10) {
512 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
513 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
514 } else {
515 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
516 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
517 }
518
519 /* We need at least 2 components for LS.
520 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
521 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
522 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
523 * be loaded.
524 */
525 ls_vgpr_comp_cnt = 1;
526 if (shader->info.uses_instanceid) {
527 if (sscreen->info.chip_class >= GFX10)
528 ls_vgpr_comp_cnt = 3;
529 else
530 ls_vgpr_comp_cnt = 2;
531 }
532
533 unsigned num_user_sgprs =
534 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
535
536 shader->config.rsrc2 =
537 S_00B42C_USER_SGPR(num_user_sgprs) |
538 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
539
540 if (sscreen->info.chip_class >= GFX10)
541 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
542 else
543 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
544 } else {
545 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
546 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
547
548 shader->config.rsrc2 =
549 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
550 S_00B42C_OC_LDS_EN(1) |
551 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
552 }
553
554 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
555 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
556 (sscreen->info.chip_class <= GFX9 ?
557 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
558 S_00B428_DX10_CLAMP(1) |
559 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
560 S_00B428_FLOAT_MODE(shader->config.float_mode) |
561 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
562
563 if (sscreen->info.chip_class <= GFX8) {
564 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
565 shader->config.rsrc2);
566 }
567 }
568
569 static void si_emit_shader_es(struct si_context *sctx)
570 {
571 struct si_shader *shader = sctx->queued.named.es->shader;
572 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
573
574 if (!shader)
575 return;
576
577 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
578 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
579 shader->selector->esgs_itemsize / 4);
580
581 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
582 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
583 SI_TRACKED_VGT_TF_PARAM,
584 shader->vgt_tf_param);
585
586 if (shader->vgt_vertex_reuse_block_cntl)
587 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
588 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
589 shader->vgt_vertex_reuse_block_cntl);
590
591 if (initial_cdw != sctx->gfx_cs->current.cdw)
592 sctx->context_roll = true;
593 }
594
595 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
596 {
597 struct si_pm4_state *pm4;
598 unsigned num_user_sgprs;
599 unsigned vgpr_comp_cnt;
600 uint64_t va;
601 unsigned oc_lds_en;
602
603 assert(sscreen->info.chip_class <= GFX8);
604
605 pm4 = si_get_shader_pm4_state(shader);
606 if (!pm4)
607 return;
608
609 pm4->atom.emit = si_emit_shader_es;
610 va = shader->bo->gpu_address;
611 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
612
613 if (shader->selector->type == PIPE_SHADER_VERTEX) {
614 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
615 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
616 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
617 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
618 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
619 num_user_sgprs = SI_TES_NUM_USER_SGPR;
620 } else
621 unreachable("invalid shader selector type");
622
623 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
624
625 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
626 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
627 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
628 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
629 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
630 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
631 S_00B328_DX10_CLAMP(1) |
632 S_00B328_FLOAT_MODE(shader->config.float_mode));
633 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
634 S_00B32C_USER_SGPR(num_user_sgprs) |
635 S_00B32C_OC_LDS_EN(oc_lds_en) |
636 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
637
638 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
639 si_set_tesseval_regs(sscreen, shader->selector, pm4);
640
641 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
642 }
643
644 void gfx9_get_gs_info(struct si_shader_selector *es,
645 struct si_shader_selector *gs,
646 struct gfx9_gs_info *out)
647 {
648 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
649 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
650 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
651 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
652
653 /* All these are in dwords: */
654 /* We can't allow using the whole LDS, because GS waves compete with
655 * other shader stages for LDS space. */
656 const unsigned max_lds_size = 8 * 1024;
657 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
658 unsigned esgs_lds_size;
659
660 /* All these are per subgroup: */
661 const unsigned max_out_prims = 32 * 1024;
662 const unsigned max_es_verts = 255;
663 const unsigned ideal_gs_prims = 64;
664 unsigned max_gs_prims, gs_prims;
665 unsigned min_es_verts, es_verts, worst_case_es_verts;
666
667 if (uses_adjacency || gs_num_invocations > 1)
668 max_gs_prims = 127 / gs_num_invocations;
669 else
670 max_gs_prims = 255;
671
672 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
673 * Make sure we don't go over the maximum value.
674 */
675 if (gs->gs_max_out_vertices > 0) {
676 max_gs_prims = MIN2(max_gs_prims,
677 max_out_prims /
678 (gs->gs_max_out_vertices * gs_num_invocations));
679 }
680 assert(max_gs_prims > 0);
681
682 /* If the primitive has adjacency, halve the number of vertices
683 * that will be reused in multiple primitives.
684 */
685 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
686
687 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
688 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
689
690 /* Compute ESGS LDS size based on the worst case number of ES vertices
691 * needed to create the target number of GS prims per subgroup.
692 */
693 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
694
695 /* If total LDS usage is too big, refactor partitions based on ratio
696 * of ESGS item sizes.
697 */
698 if (esgs_lds_size > max_lds_size) {
699 /* Our target GS Prims Per Subgroup was too large. Calculate
700 * the maximum number of GS Prims Per Subgroup that will fit
701 * into LDS, capped by the maximum that the hardware can support.
702 */
703 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
704 max_gs_prims);
705 assert(gs_prims > 0);
706 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
707 max_es_verts);
708
709 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
710 assert(esgs_lds_size <= max_lds_size);
711 }
712
713 /* Now calculate remaining ESGS information. */
714 if (esgs_lds_size)
715 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
716 else
717 es_verts = max_es_verts;
718
719 /* Vertices for adjacency primitives are not always reused, so restore
720 * it for ES_VERTS_PER_SUBGRP.
721 */
722 min_es_verts = gs->gs_input_verts_per_prim;
723
724 /* For normal primitives, the VGT only checks if they are past the ES
725 * verts per subgroup after allocating a full GS primitive and if they
726 * are, kick off a new subgroup. But if those additional ES verts are
727 * unique (e.g. not reused) we need to make sure there is enough LDS
728 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
729 */
730 es_verts -= min_es_verts - 1;
731
732 out->es_verts_per_subgroup = es_verts;
733 out->gs_prims_per_subgroup = gs_prims;
734 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
735 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
736 gs->gs_max_out_vertices;
737 out->esgs_ring_size = 4 * esgs_lds_size;
738
739 assert(out->max_prims_per_subgroup <= max_out_prims);
740 }
741
742 static void si_emit_shader_gs(struct si_context *sctx)
743 {
744 struct si_shader *shader = sctx->queued.named.gs->shader;
745 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
746
747 if (!shader)
748 return;
749
750 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
751 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
752 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
753 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
754 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
755 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
756 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
757
758 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
759 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
760 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
761 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
762
763 /* R_028B38_VGT_GS_MAX_VERT_OUT */
764 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
765 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
766 shader->ctx_reg.gs.vgt_gs_max_vert_out);
767
768 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
769 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
770 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
771 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
772 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
773 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
774 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
776
777 /* R_028B90_VGT_GS_INSTANCE_CNT */
778 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
779 SI_TRACKED_VGT_GS_INSTANCE_CNT,
780 shader->ctx_reg.gs.vgt_gs_instance_cnt);
781
782 if (sctx->chip_class >= GFX9) {
783 /* R_028A44_VGT_GS_ONCHIP_CNTL */
784 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
785 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
786 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
787 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
788 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
789 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
790 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
791 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
792 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
793 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
794 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
795
796 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
797 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
798 SI_TRACKED_VGT_TF_PARAM,
799 shader->vgt_tf_param);
800 if (shader->vgt_vertex_reuse_block_cntl)
801 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
802 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
803 shader->vgt_vertex_reuse_block_cntl);
804 }
805
806 if (initial_cdw != sctx->gfx_cs->current.cdw)
807 sctx->context_roll = true;
808 }
809
810 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
811 {
812 struct si_shader_selector *sel = shader->selector;
813 const ubyte *num_components = sel->info.num_stream_output_components;
814 unsigned gs_num_invocations = sel->gs_num_invocations;
815 struct si_pm4_state *pm4;
816 uint64_t va;
817 unsigned max_stream = sel->max_gs_stream;
818 unsigned offset;
819
820 pm4 = si_get_shader_pm4_state(shader);
821 if (!pm4)
822 return;
823
824 pm4->atom.emit = si_emit_shader_gs;
825
826 offset = num_components[0] * sel->gs_max_out_vertices;
827 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
828
829 if (max_stream >= 1)
830 offset += num_components[1] * sel->gs_max_out_vertices;
831 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
832
833 if (max_stream >= 2)
834 offset += num_components[2] * sel->gs_max_out_vertices;
835 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
836
837 if (max_stream >= 3)
838 offset += num_components[3] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
840
841 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
842 assert(offset < (1 << 15));
843
844 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
845
846 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
847 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
850
851 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
852 S_028B90_ENABLE(gs_num_invocations > 0);
853
854 va = shader->bo->gpu_address;
855 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
856
857 if (sscreen->info.chip_class >= GFX9) {
858 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
859 unsigned es_type = shader->key.part.gs.es->type;
860 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
861
862 if (es_type == PIPE_SHADER_VERTEX)
863 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
864 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
865 else if (es_type == PIPE_SHADER_TESS_EVAL)
866 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
867 else
868 unreachable("invalid shader selector type");
869
870 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
871 * VGPR[0:4] are always loaded.
872 */
873 if (sel->info.uses_invocationid)
874 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
875 else if (sel->info.uses_primid)
876 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
877 else if (input_prim >= PIPE_PRIM_TRIANGLES)
878 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
879 else
880 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
881
882 unsigned num_user_sgprs;
883 if (es_type == PIPE_SHADER_VERTEX)
884 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
885 else
886 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
887
888 if (sscreen->info.chip_class >= GFX10) {
889 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
890 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
891 } else {
892 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
893 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
894 }
895
896 uint32_t rsrc1 =
897 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
898 S_00B228_DX10_CLAMP(1) |
899 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
900 S_00B228_FLOAT_MODE(shader->config.float_mode) |
901 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
902 uint32_t rsrc2 =
903 S_00B22C_USER_SGPR(num_user_sgprs) |
904 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
905 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
906 S_00B22C_LDS_SIZE(shader->config.lds_size) |
907 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
908
909 if (sscreen->info.chip_class >= GFX10) {
910 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
911 } else {
912 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
913 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
914 }
915
916 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
917 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
918
919 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
920 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
921 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
922 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
923 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
924 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
925 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
926 shader->key.part.gs.es->esgs_itemsize / 4;
927
928 if (es_type == PIPE_SHADER_TESS_EVAL)
929 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
930
931 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
932 NULL, pm4);
933 } else {
934 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
935 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
936
937 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
938 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
939 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
940 S_00B228_DX10_CLAMP(1) |
941 S_00B228_FLOAT_MODE(shader->config.float_mode));
942 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
943 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
944 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
945 }
946 }
947
948 /* Common tail code for NGG primitive shaders. */
949 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
950 struct si_shader *shader,
951 unsigned initial_cdw)
952 {
953 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
954 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
955 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
956 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
957 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
958 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
959 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
960 SI_TRACKED_VGT_PRIMITIVEID_EN,
961 shader->ctx_reg.ngg.vgt_primitiveid_en);
962 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
963 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
964 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
965 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
966 SI_TRACKED_VGT_GS_INSTANCE_CNT,
967 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
968 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
969 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
970 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
971 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
972 SI_TRACKED_VGT_REUSE_OFF,
973 shader->ctx_reg.ngg.vgt_reuse_off);
974 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
975 SI_TRACKED_SPI_VS_OUT_CONFIG,
976 shader->ctx_reg.ngg.spi_vs_out_config);
977 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
978 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
979 shader->ctx_reg.ngg.spi_shader_idx_format,
980 shader->ctx_reg.ngg.spi_shader_pos_format);
981 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
982 SI_TRACKED_PA_CL_VTE_CNTL,
983 shader->ctx_reg.ngg.pa_cl_vte_cntl);
984
985 if (initial_cdw != sctx->gfx_cs->current.cdw)
986 sctx->context_roll = true;
987
988 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
989 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
990 sctx->last_multi_vgt_param = shader->ge_cntl;
991 }
992 }
993
994 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
995 {
996 struct si_shader *shader = sctx->queued.named.gs->shader;
997 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
998
999 if (!shader)
1000 return;
1001
1002 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1003 }
1004
1005 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1006 {
1007 struct si_shader *shader = sctx->queued.named.gs->shader;
1008 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1009
1010 if (!shader)
1011 return;
1012
1013 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1014 SI_TRACKED_VGT_TF_PARAM,
1015 shader->vgt_tf_param);
1016
1017 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1018 }
1019
1020 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1021 {
1022 struct si_shader *shader = sctx->queued.named.gs->shader;
1023 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1024
1025 if (!shader)
1026 return;
1027
1028 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1029 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1030 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1031
1032 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1033 }
1034
1035 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1036 {
1037 struct si_shader *shader = sctx->queued.named.gs->shader;
1038 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1039
1040 if (!shader)
1041 return;
1042
1043 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1044 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1045 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1046 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1047 SI_TRACKED_VGT_TF_PARAM,
1048 shader->vgt_tf_param);
1049
1050 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1051 }
1052
1053 /**
1054 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1055 * in NGG mode.
1056 */
1057 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1058 {
1059 const struct si_shader_selector *gs_sel = shader->selector;
1060 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1061 enum pipe_shader_type gs_type = shader->selector->type;
1062 const struct si_shader_selector *es_sel =
1063 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1064 const struct tgsi_shader_info *es_info = &es_sel->info;
1065 enum pipe_shader_type es_type = es_sel->type;
1066 unsigned num_user_sgprs;
1067 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1068 uint64_t va;
1069 unsigned window_space =
1070 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1071 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1072 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1073 unsigned input_prim =
1074 gs_type == PIPE_SHADER_GEOMETRY ?
1075 gs_info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] :
1076 PIPE_PRIM_TRIANGLES; /* TODO: Optimize when primtype is known */
1077 bool break_wave_at_eoi = false;
1078 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1079 if (!pm4)
1080 return;
1081
1082 if (es_type == PIPE_SHADER_TESS_EVAL) {
1083 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1084 : gfx10_emit_shader_ngg_tess_nogs;
1085 } else {
1086 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1087 : gfx10_emit_shader_ngg_notess_nogs;
1088 }
1089
1090 va = shader->bo->gpu_address;
1091 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1092
1093 if (es_type == PIPE_SHADER_VERTEX) {
1094 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1095 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1096
1097 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1098 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1099 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1100 } else {
1101 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1102 }
1103 } else {
1104 assert(es_type == PIPE_SHADER_TESS_EVAL);
1105 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1106 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1107
1108 if (es_enable_prim_id || gs_info->uses_primid)
1109 break_wave_at_eoi = true;
1110 }
1111
1112 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1113 * VGPR[0:4] are always loaded.
1114 */
1115 if (gs_info->uses_invocationid)
1116 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1117 else if (gs_info->uses_primid)
1118 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1119 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1120 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1121 else
1122 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1123
1124 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1125 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1126 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1127 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1128 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1129 S_00B228_DX10_CLAMP(1) |
1130 S_00B228_MEM_ORDERED(1) |
1131 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1132 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1133 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1134 S_00B22C_USER_SGPR(num_user_sgprs) |
1135 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1136 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1137 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1138 S_00B22C_LDS_SIZE(shader->config.lds_size));
1139
1140 /* TODO: Use NO_PC_EXPORT when applicable. */
1141 nparams = MAX2(shader->info.nr_param_exports, 1);
1142 shader->ctx_reg.ngg.spi_vs_out_config =
1143 S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1144
1145 shader->ctx_reg.ngg.spi_shader_idx_format =
1146 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1147 shader->ctx_reg.ngg.spi_shader_pos_format =
1148 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1149 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1150 V_02870C_SPI_SHADER_4COMP :
1151 V_02870C_SPI_SHADER_NONE) |
1152 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1153 V_02870C_SPI_SHADER_4COMP :
1154 V_02870C_SPI_SHADER_NONE) |
1155 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1156 V_02870C_SPI_SHADER_4COMP :
1157 V_02870C_SPI_SHADER_NONE);
1158
1159 shader->ctx_reg.ngg.vgt_primitiveid_en =
1160 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1161 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1162
1163 if (gs_type == PIPE_SHADER_GEOMETRY) {
1164 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1165 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1166 } else {
1167 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1168 }
1169
1170 if (es_type == PIPE_SHADER_TESS_EVAL)
1171 si_set_tesseval_regs(sscreen, es_sel, pm4);
1172
1173 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1174 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1175 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1176 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1177 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1178 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1179 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1180 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1181 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1182 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1183 S_028B90_CNT(gs_num_invocations) |
1184 S_028B90_ENABLE(gs_num_invocations > 1) |
1185 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1186 shader->ngg.max_vert_out_per_gs_instance);
1187
1188 shader->ge_cntl =
1189 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1190 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1191 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1192
1193 if (window_space) {
1194 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1195 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1196 } else {
1197 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1198 S_028818_VTX_W0_FMT(1) |
1199 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1200 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1201 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1202 }
1203
1204 shader->ctx_reg.ngg.vgt_reuse_off =
1205 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1206 sscreen->info.chip_external_rev == 0x1 &&
1207 es_type == PIPE_SHADER_TESS_EVAL);
1208 }
1209
1210 static void si_emit_shader_vs(struct si_context *sctx)
1211 {
1212 struct si_shader *shader = sctx->queued.named.vs->shader;
1213 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1214
1215 if (!shader)
1216 return;
1217
1218 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1219 SI_TRACKED_VGT_GS_MODE,
1220 shader->ctx_reg.vs.vgt_gs_mode);
1221 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1222 SI_TRACKED_VGT_PRIMITIVEID_EN,
1223 shader->ctx_reg.vs.vgt_primitiveid_en);
1224
1225 if (sctx->chip_class <= GFX8) {
1226 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1227 SI_TRACKED_VGT_REUSE_OFF,
1228 shader->ctx_reg.vs.vgt_reuse_off);
1229 }
1230
1231 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1232 SI_TRACKED_SPI_VS_OUT_CONFIG,
1233 shader->ctx_reg.vs.spi_vs_out_config);
1234
1235 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1236 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1237 shader->ctx_reg.vs.spi_shader_pos_format);
1238
1239 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1240 SI_TRACKED_PA_CL_VTE_CNTL,
1241 shader->ctx_reg.vs.pa_cl_vte_cntl);
1242
1243 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1244 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1245 SI_TRACKED_VGT_TF_PARAM,
1246 shader->vgt_tf_param);
1247
1248 if (shader->vgt_vertex_reuse_block_cntl)
1249 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1250 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1251 shader->vgt_vertex_reuse_block_cntl);
1252
1253 if (initial_cdw != sctx->gfx_cs->current.cdw)
1254 sctx->context_roll = true;
1255 }
1256
1257 /**
1258 * Compute the state for \p shader, which will run as a vertex shader on the
1259 * hardware.
1260 *
1261 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1262 * is the copy shader.
1263 */
1264 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1265 struct si_shader_selector *gs)
1266 {
1267 const struct tgsi_shader_info *info = &shader->selector->info;
1268 struct si_pm4_state *pm4;
1269 unsigned num_user_sgprs, vgpr_comp_cnt;
1270 uint64_t va;
1271 unsigned nparams, oc_lds_en;
1272 unsigned window_space =
1273 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1274 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1275
1276 pm4 = si_get_shader_pm4_state(shader);
1277 if (!pm4)
1278 return;
1279
1280 pm4->atom.emit = si_emit_shader_vs;
1281
1282 /* We always write VGT_GS_MODE in the VS state, because every switch
1283 * between different shader pipelines involving a different GS or no
1284 * GS at all involves a switch of the VS (different GS use different
1285 * copy shaders). On the other hand, when the API switches from a GS to
1286 * no GS and then back to the same GS used originally, the GS state is
1287 * not sent again.
1288 */
1289 if (!gs) {
1290 unsigned mode = V_028A40_GS_OFF;
1291
1292 /* PrimID needs GS scenario A. */
1293 if (enable_prim_id)
1294 mode = V_028A40_GS_SCENARIO_A;
1295
1296 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1297 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1298 } else {
1299 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1300 sscreen->info.chip_class);
1301 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1302 }
1303
1304 if (sscreen->info.chip_class <= GFX8) {
1305 /* Reuse needs to be set off if we write oViewport. */
1306 shader->ctx_reg.vs.vgt_reuse_off =
1307 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1308 }
1309
1310 va = shader->bo->gpu_address;
1311 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1312
1313 if (gs) {
1314 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1315 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1316 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1317 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1318 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1319 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1320 */
1321 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1322
1323 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1324 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1325 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1326 } else {
1327 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1328 }
1329 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1330 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1331 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1332 } else
1333 unreachable("invalid shader selector type");
1334
1335 /* VS is required to export at least one param. */
1336 nparams = MAX2(shader->info.nr_param_exports, 1);
1337 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1338
1339 shader->ctx_reg.vs.spi_shader_pos_format =
1340 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1341 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1342 V_02870C_SPI_SHADER_4COMP :
1343 V_02870C_SPI_SHADER_NONE) |
1344 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1345 V_02870C_SPI_SHADER_4COMP :
1346 V_02870C_SPI_SHADER_NONE) |
1347 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1348 V_02870C_SPI_SHADER_4COMP :
1349 V_02870C_SPI_SHADER_NONE);
1350
1351 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1352
1353 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1354 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1355 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1356 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1357 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1358 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1359 S_00B128_DX10_CLAMP(1) |
1360 S_00B128_FLOAT_MODE(shader->config.float_mode));
1361 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1362 S_00B12C_USER_SGPR(num_user_sgprs) |
1363 S_00B12C_OC_LDS_EN(oc_lds_en) |
1364 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1365 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1366 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1367 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1368 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1369 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1370
1371 if (window_space)
1372 shader->ctx_reg.vs.pa_cl_vte_cntl =
1373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1374 else
1375 shader->ctx_reg.vs.pa_cl_vte_cntl =
1376 S_028818_VTX_W0_FMT(1) |
1377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1380
1381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1382 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1383
1384 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1385 }
1386
1387 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1388 {
1389 struct tgsi_shader_info *info = &ps->selector->info;
1390 unsigned num_colors = !!(info->colors_read & 0x0f) +
1391 !!(info->colors_read & 0xf0);
1392 unsigned num_interp = ps->selector->info.num_inputs +
1393 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1394
1395 assert(num_interp <= 32);
1396 return MIN2(num_interp, 32);
1397 }
1398
1399 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1400 {
1401 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1402 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1403
1404 /* If the i-th target format is set, all previous target formats must
1405 * be non-zero to avoid hangs.
1406 */
1407 for (i = 0; i < num_targets; i++)
1408 if (!(value & (0xf << (i * 4))))
1409 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1410
1411 return value;
1412 }
1413
1414 static void si_emit_shader_ps(struct si_context *sctx)
1415 {
1416 struct si_shader *shader = sctx->queued.named.ps->shader;
1417 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1418
1419 if (!shader)
1420 return;
1421
1422 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1423 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1424 SI_TRACKED_SPI_PS_INPUT_ENA,
1425 shader->ctx_reg.ps.spi_ps_input_ena,
1426 shader->ctx_reg.ps.spi_ps_input_addr);
1427
1428 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1429 SI_TRACKED_SPI_BARYC_CNTL,
1430 shader->ctx_reg.ps.spi_baryc_cntl);
1431 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1432 SI_TRACKED_SPI_PS_IN_CONTROL,
1433 shader->ctx_reg.ps.spi_ps_in_control);
1434
1435 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1436 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1437 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1438 shader->ctx_reg.ps.spi_shader_z_format,
1439 shader->ctx_reg.ps.spi_shader_col_format);
1440
1441 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1442 SI_TRACKED_CB_SHADER_MASK,
1443 shader->ctx_reg.ps.cb_shader_mask);
1444
1445 if (initial_cdw != sctx->gfx_cs->current.cdw)
1446 sctx->context_roll = true;
1447 }
1448
1449 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1450 {
1451 struct tgsi_shader_info *info = &shader->selector->info;
1452 struct si_pm4_state *pm4;
1453 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1454 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1455 uint64_t va;
1456 unsigned input_ena = shader->config.spi_ps_input_ena;
1457
1458 /* we need to enable at least one of them, otherwise we hang the GPU */
1459 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1460 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1461 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1462 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1463 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1464 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1465 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1466 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1467 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1468 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1469 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1470 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1471 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1472 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1473
1474 /* Validate interpolation optimization flags (read as implications). */
1475 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1476 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1477 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1478 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1479 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1480 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1481 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1482 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1483 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1484 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1485 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1486 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1487 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1488 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1489 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1490 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1491 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1492 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1493
1494 /* Validate cases when the optimizations are off (read as implications). */
1495 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1496 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1497 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1498 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1499 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1500 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1501
1502 pm4 = si_get_shader_pm4_state(shader);
1503 if (!pm4)
1504 return;
1505
1506 pm4->atom.emit = si_emit_shader_ps;
1507
1508 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1509 * Possible vaules:
1510 * 0 -> Position = pixel center
1511 * 1 -> Position = pixel centroid
1512 * 2 -> Position = at sample position
1513 *
1514 * From GLSL 4.5 specification, section 7.1:
1515 * "The variable gl_FragCoord is available as an input variable from
1516 * within fragment shaders and it holds the window relative coordinates
1517 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1518 * value can be for any location within the pixel, or one of the
1519 * fragment samples. The use of centroid does not further restrict
1520 * this value to be inside the current primitive."
1521 *
1522 * Meaning that centroid has no effect and we can return anything within
1523 * the pixel. Thus, return the value at sample position, because that's
1524 * the most accurate one shaders can get.
1525 */
1526 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1527
1528 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1529 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1530 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1531
1532 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1533 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1534
1535 /* Ensure that some export memory is always allocated, for two reasons:
1536 *
1537 * 1) Correctness: The hardware ignores the EXEC mask if no export
1538 * memory is allocated, so KILL and alpha test do not work correctly
1539 * without this.
1540 * 2) Performance: Every shader needs at least a NULL export, even when
1541 * it writes no color/depth output. The NULL export instruction
1542 * stalls without this setting.
1543 *
1544 * Don't add this to CB_SHADER_MASK.
1545 */
1546 if (!spi_shader_col_format &&
1547 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1548 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1549
1550 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1551 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1552
1553 /* Set interpolation controls. */
1554 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1555
1556 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1557 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1558 shader->ctx_reg.ps.spi_shader_z_format =
1559 ac_get_spi_shader_z_format(info->writes_z,
1560 info->writes_stencil,
1561 info->writes_samplemask);
1562 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1563 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1564
1565 va = shader->bo->gpu_address;
1566 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1567 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1568 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1569
1570 uint32_t rsrc1 =
1571 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1572 S_00B028_DX10_CLAMP(1) |
1573 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1574 S_00B028_FLOAT_MODE(shader->config.float_mode);
1575
1576 if (sscreen->info.chip_class < GFX10) {
1577 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1578 }
1579
1580 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1581 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1582 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1583 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1584 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1585 }
1586
1587 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1588 struct si_shader *shader)
1589 {
1590 switch (shader->selector->type) {
1591 case PIPE_SHADER_VERTEX:
1592 if (shader->key.as_ls)
1593 si_shader_ls(sscreen, shader);
1594 else if (shader->key.as_es)
1595 si_shader_es(sscreen, shader);
1596 else if (shader->key.as_ngg)
1597 gfx10_shader_ngg(sscreen, shader);
1598 else
1599 si_shader_vs(sscreen, shader, NULL);
1600 break;
1601 case PIPE_SHADER_TESS_CTRL:
1602 si_shader_hs(sscreen, shader);
1603 break;
1604 case PIPE_SHADER_TESS_EVAL:
1605 if (shader->key.as_es)
1606 si_shader_es(sscreen, shader);
1607 else if (shader->key.as_ngg)
1608 gfx10_shader_ngg(sscreen, shader);
1609 else
1610 si_shader_vs(sscreen, shader, NULL);
1611 break;
1612 case PIPE_SHADER_GEOMETRY:
1613 if (shader->key.as_ngg)
1614 gfx10_shader_ngg(sscreen, shader);
1615 else
1616 si_shader_gs(sscreen, shader);
1617 break;
1618 case PIPE_SHADER_FRAGMENT:
1619 si_shader_ps(sscreen, shader);
1620 break;
1621 default:
1622 assert(0);
1623 }
1624 }
1625
1626 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1627 {
1628 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1629 if (sctx->queued.named.dsa)
1630 return sctx->queued.named.dsa->alpha_func;
1631
1632 return PIPE_FUNC_ALWAYS;
1633 }
1634
1635 void si_shader_selector_key_vs(struct si_context *sctx,
1636 struct si_shader_selector *vs,
1637 struct si_shader_key *key,
1638 struct si_vs_prolog_bits *prolog_key)
1639 {
1640 if (!sctx->vertex_elements ||
1641 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1642 return;
1643
1644 struct si_vertex_elements *elts = sctx->vertex_elements;
1645
1646 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1647 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1648 prolog_key->unpack_instance_id_from_vertex_id =
1649 sctx->prim_discard_cs_instancing;
1650
1651 /* Prefer a monolithic shader to allow scheduling divisions around
1652 * VBO loads. */
1653 if (prolog_key->instance_divisor_is_fetched)
1654 key->opt.prefer_mono = 1;
1655
1656 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1657 unsigned count_mask = (1 << count) - 1;
1658 unsigned fix = elts->fix_fetch_always & count_mask;
1659 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1660
1661 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1662 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1663 while (mask) {
1664 unsigned i = u_bit_scan(&mask);
1665 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1666 unsigned vbidx = elts->vertex_buffer_index[i];
1667 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1668 unsigned align_mask = (1 << log_hw_load_size) - 1;
1669 if (vb->buffer_offset & align_mask ||
1670 vb->stride & align_mask) {
1671 fix |= 1 << i;
1672 opencode |= 1 << i;
1673 }
1674 }
1675 }
1676
1677 while (fix) {
1678 unsigned i = u_bit_scan(&fix);
1679 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1680 }
1681 key->mono.vs_fetch_opencode = opencode;
1682 }
1683
1684 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1685 struct si_shader_selector *vs,
1686 struct si_shader_key *key)
1687 {
1688 struct si_shader_selector *ps = sctx->ps_shader.cso;
1689
1690 key->opt.clip_disable =
1691 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1692 (vs->info.clipdist_writemask ||
1693 vs->info.writes_clipvertex) &&
1694 !vs->info.culldist_writemask;
1695
1696 /* Find out if PS is disabled. */
1697 bool ps_disabled = true;
1698 if (ps) {
1699 const struct si_state_blend *blend = sctx->queued.named.blend;
1700 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1701 bool ps_modifies_zs = ps->info.uses_kill ||
1702 ps->info.writes_z ||
1703 ps->info.writes_stencil ||
1704 ps->info.writes_samplemask ||
1705 alpha_to_coverage ||
1706 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1707 unsigned ps_colormask = si_get_total_colormask(sctx);
1708
1709 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1710 (!ps_colormask &&
1711 !ps_modifies_zs &&
1712 !ps->info.writes_memory);
1713 }
1714
1715 /* Find out which VS outputs aren't used by the PS. */
1716 uint64_t outputs_written = vs->outputs_written_before_ps;
1717 uint64_t inputs_read = 0;
1718
1719 /* Ignore outputs that are not passed from VS to PS. */
1720 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1721 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1722 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1723
1724 if (!ps_disabled) {
1725 inputs_read = ps->inputs_read;
1726 }
1727
1728 uint64_t linked = outputs_written & inputs_read;
1729
1730 key->opt.kill_outputs = ~linked & outputs_written;
1731 }
1732
1733 /* Compute the key for the hw shader variant */
1734 static inline void si_shader_selector_key(struct pipe_context *ctx,
1735 struct si_shader_selector *sel,
1736 union si_vgt_stages_key stages_key,
1737 struct si_shader_key *key)
1738 {
1739 struct si_context *sctx = (struct si_context *)ctx;
1740
1741 memset(key, 0, sizeof(*key));
1742
1743 switch (sel->type) {
1744 case PIPE_SHADER_VERTEX:
1745 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1746
1747 if (sctx->tes_shader.cso)
1748 key->as_ls = 1;
1749 else if (sctx->gs_shader.cso)
1750 key->as_es = 1;
1751 else {
1752 key->as_ngg = stages_key.u.ngg;
1753 si_shader_selector_key_hw_vs(sctx, sel, key);
1754
1755 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1756 key->mono.u.vs_export_prim_id = 1;
1757 }
1758 break;
1759 case PIPE_SHADER_TESS_CTRL:
1760 if (sctx->chip_class >= GFX9) {
1761 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1762 key, &key->part.tcs.ls_prolog);
1763 key->part.tcs.ls = sctx->vs_shader.cso;
1764
1765 /* When the LS VGPR fix is needed, monolithic shaders
1766 * can:
1767 * - avoid initializing EXEC in both the LS prolog
1768 * and the LS main part when !vs_needs_prolog
1769 * - remove the fixup for unused input VGPRs
1770 */
1771 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1772
1773 /* The LS output / HS input layout can be communicated
1774 * directly instead of via user SGPRs for merged LS-HS.
1775 * The LS VGPR fix prefers this too.
1776 */
1777 key->opt.prefer_mono = 1;
1778 }
1779
1780 key->part.tcs.epilog.prim_mode =
1781 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1782 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1783 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1784 key->part.tcs.epilog.tes_reads_tess_factors =
1785 sctx->tes_shader.cso->info.reads_tess_factors;
1786
1787 if (sel == sctx->fixed_func_tcs_shader.cso)
1788 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1789 break;
1790 case PIPE_SHADER_TESS_EVAL:
1791 if (sctx->gs_shader.cso)
1792 key->as_es = 1;
1793 else {
1794 key->as_ngg = stages_key.u.ngg;
1795 si_shader_selector_key_hw_vs(sctx, sel, key);
1796
1797 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1798 key->mono.u.vs_export_prim_id = 1;
1799 }
1800 break;
1801 case PIPE_SHADER_GEOMETRY:
1802 if (sctx->chip_class >= GFX9) {
1803 if (sctx->tes_shader.cso) {
1804 key->part.gs.es = sctx->tes_shader.cso;
1805 } else {
1806 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1807 key, &key->part.gs.vs_prolog);
1808 key->part.gs.es = sctx->vs_shader.cso;
1809 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1810 }
1811
1812 key->as_ngg = stages_key.u.ngg;
1813
1814 /* Merged ES-GS can have unbalanced wave usage.
1815 *
1816 * ES threads are per-vertex, while GS threads are
1817 * per-primitive. So without any amplification, there
1818 * are fewer GS threads than ES threads, which can result
1819 * in empty (no-op) GS waves. With too much amplification,
1820 * there are more GS threads than ES threads, which
1821 * can result in empty (no-op) ES waves.
1822 *
1823 * Non-monolithic shaders are implemented by setting EXEC
1824 * at the beginning of shader parts, and don't jump to
1825 * the end if EXEC is 0.
1826 *
1827 * Monolithic shaders use conditional blocks, so they can
1828 * jump and skip empty waves of ES or GS. So set this to
1829 * always use optimized variants, which are monolithic.
1830 */
1831 key->opt.prefer_mono = 1;
1832 }
1833 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1834 break;
1835 case PIPE_SHADER_FRAGMENT: {
1836 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1837 struct si_state_blend *blend = sctx->queued.named.blend;
1838
1839 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1840 sel->info.colors_written == 0x1)
1841 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1842
1843 if (blend) {
1844 /* Select the shader color format based on whether
1845 * blending or alpha are needed.
1846 */
1847 key->part.ps.epilog.spi_shader_col_format =
1848 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1849 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1850 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1851 sctx->framebuffer.spi_shader_col_format_blend) |
1852 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1853 sctx->framebuffer.spi_shader_col_format_alpha) |
1854 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1855 sctx->framebuffer.spi_shader_col_format);
1856 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1857
1858 /* The output for dual source blending should have
1859 * the same format as the first output.
1860 */
1861 if (blend->dual_src_blend)
1862 key->part.ps.epilog.spi_shader_col_format |=
1863 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1864 } else
1865 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1866
1867 /* If alpha-to-coverage is enabled, we have to export alpha
1868 * even if there is no color buffer.
1869 */
1870 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1871 blend && blend->alpha_to_coverage)
1872 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1873
1874 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1875 * to the range supported by the type if a channel has less
1876 * than 16 bits and the export format is 16_ABGR.
1877 */
1878 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1879 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1880 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1881 }
1882
1883 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1884 if (!key->part.ps.epilog.last_cbuf) {
1885 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1886 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1887 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1888 }
1889
1890 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1891 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1892
1893 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1894 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1895
1896 if (sctx->queued.named.blend) {
1897 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1898 rs->multisample_enable;
1899 }
1900
1901 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1902 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1903 (is_line && rs->line_smooth)) &&
1904 sctx->framebuffer.nr_samples <= 1;
1905 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1906
1907 if (sctx->ps_iter_samples > 1 &&
1908 sel->info.reads_samplemask) {
1909 key->part.ps.prolog.samplemask_log_ps_iter =
1910 util_logbase2(sctx->ps_iter_samples);
1911 }
1912
1913 if (rs->force_persample_interp &&
1914 rs->multisample_enable &&
1915 sctx->framebuffer.nr_samples > 1 &&
1916 sctx->ps_iter_samples > 1) {
1917 key->part.ps.prolog.force_persp_sample_interp =
1918 sel->info.uses_persp_center ||
1919 sel->info.uses_persp_centroid;
1920
1921 key->part.ps.prolog.force_linear_sample_interp =
1922 sel->info.uses_linear_center ||
1923 sel->info.uses_linear_centroid;
1924 } else if (rs->multisample_enable &&
1925 sctx->framebuffer.nr_samples > 1) {
1926 key->part.ps.prolog.bc_optimize_for_persp =
1927 sel->info.uses_persp_center &&
1928 sel->info.uses_persp_centroid;
1929 key->part.ps.prolog.bc_optimize_for_linear =
1930 sel->info.uses_linear_center &&
1931 sel->info.uses_linear_centroid;
1932 } else {
1933 /* Make sure SPI doesn't compute more than 1 pair
1934 * of (i,j), which is the optimization here. */
1935 key->part.ps.prolog.force_persp_center_interp =
1936 sel->info.uses_persp_center +
1937 sel->info.uses_persp_centroid +
1938 sel->info.uses_persp_sample > 1;
1939
1940 key->part.ps.prolog.force_linear_center_interp =
1941 sel->info.uses_linear_center +
1942 sel->info.uses_linear_centroid +
1943 sel->info.uses_linear_sample > 1;
1944
1945 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1946 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1947 }
1948
1949 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1950
1951 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1952 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1953 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1954 struct pipe_resource *tex = cb0->texture;
1955
1956 /* 1D textures are allocated and used as 2D on GFX9. */
1957 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1958 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1959 (tex->target == PIPE_TEXTURE_1D ||
1960 tex->target == PIPE_TEXTURE_1D_ARRAY);
1961 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1962 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1963 tex->target == PIPE_TEXTURE_CUBE ||
1964 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1965 tex->target == PIPE_TEXTURE_3D;
1966 }
1967 break;
1968 }
1969 default:
1970 assert(0);
1971 }
1972
1973 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1974 memset(&key->opt, 0, sizeof(key->opt));
1975 }
1976
1977 static void si_build_shader_variant(struct si_shader *shader,
1978 int thread_index,
1979 bool low_priority)
1980 {
1981 struct si_shader_selector *sel = shader->selector;
1982 struct si_screen *sscreen = sel->screen;
1983 struct ac_llvm_compiler *compiler;
1984 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1985
1986 if (thread_index >= 0) {
1987 if (low_priority) {
1988 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1989 compiler = &sscreen->compiler_lowp[thread_index];
1990 } else {
1991 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1992 compiler = &sscreen->compiler[thread_index];
1993 }
1994 if (!debug->async)
1995 debug = NULL;
1996 } else {
1997 assert(!low_priority);
1998 compiler = shader->compiler_ctx_state.compiler;
1999 }
2000
2001 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2002 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2003 sel->type);
2004 shader->compilation_failed = true;
2005 return;
2006 }
2007
2008 if (shader->compiler_ctx_state.is_debug_context) {
2009 FILE *f = open_memstream(&shader->shader_log,
2010 &shader->shader_log_size);
2011 if (f) {
2012 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
2013 fclose(f);
2014 }
2015 }
2016
2017 si_shader_init_pm4_state(sscreen, shader);
2018 }
2019
2020 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2021 {
2022 struct si_shader *shader = (struct si_shader *)job;
2023
2024 assert(thread_index >= 0);
2025
2026 si_build_shader_variant(shader, thread_index, true);
2027 }
2028
2029 static const struct si_shader_key zeroed;
2030
2031 static bool si_check_missing_main_part(struct si_screen *sscreen,
2032 struct si_shader_selector *sel,
2033 struct si_compiler_ctx_state *compiler_state,
2034 struct si_shader_key *key)
2035 {
2036 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2037
2038 if (!*mainp) {
2039 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2040
2041 if (!main_part)
2042 return false;
2043
2044 /* We can leave the fence as permanently signaled because the
2045 * main part becomes visible globally only after it has been
2046 * compiled. */
2047 util_queue_fence_init(&main_part->ready);
2048
2049 main_part->selector = sel;
2050 main_part->key.as_es = key->as_es;
2051 main_part->key.as_ls = key->as_ls;
2052 main_part->key.as_ngg = key->as_ngg;
2053 main_part->is_monolithic = false;
2054
2055 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2056 main_part, &compiler_state->debug) != 0) {
2057 FREE(main_part);
2058 return false;
2059 }
2060 *mainp = main_part;
2061 }
2062 return true;
2063 }
2064
2065 /**
2066 * Select a shader variant according to the shader key.
2067 *
2068 * \param optimized_or_none If the key describes an optimized shader variant and
2069 * the compilation isn't finished, don't select any
2070 * shader and return an error.
2071 */
2072 int si_shader_select_with_key(struct si_screen *sscreen,
2073 struct si_shader_ctx_state *state,
2074 struct si_compiler_ctx_state *compiler_state,
2075 struct si_shader_key *key,
2076 int thread_index,
2077 bool optimized_or_none)
2078 {
2079 struct si_shader_selector *sel = state->cso;
2080 struct si_shader_selector *previous_stage_sel = NULL;
2081 struct si_shader *current = state->current;
2082 struct si_shader *iter, *shader = NULL;
2083
2084 again:
2085 /* Check if we don't need to change anything.
2086 * This path is also used for most shaders that don't need multiple
2087 * variants, it will cost just a computation of the key and this
2088 * test. */
2089 if (likely(current &&
2090 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2091 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2092 if (current->is_optimized) {
2093 if (optimized_or_none)
2094 return -1;
2095
2096 memset(&key->opt, 0, sizeof(key->opt));
2097 goto current_not_ready;
2098 }
2099
2100 util_queue_fence_wait(&current->ready);
2101 }
2102
2103 return current->compilation_failed ? -1 : 0;
2104 }
2105 current_not_ready:
2106
2107 /* This must be done before the mutex is locked, because async GS
2108 * compilation calls this function too, and therefore must enter
2109 * the mutex first.
2110 *
2111 * Only wait if we are in a draw call. Don't wait if we are
2112 * in a compiler thread.
2113 */
2114 if (thread_index < 0)
2115 util_queue_fence_wait(&sel->ready);
2116
2117 mtx_lock(&sel->mutex);
2118
2119 /* Find the shader variant. */
2120 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2121 /* Don't check the "current" shader. We checked it above. */
2122 if (current != iter &&
2123 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2124 mtx_unlock(&sel->mutex);
2125
2126 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2127 /* If it's an optimized shader and its compilation has
2128 * been started but isn't done, use the unoptimized
2129 * shader so as not to cause a stall due to compilation.
2130 */
2131 if (iter->is_optimized) {
2132 if (optimized_or_none)
2133 return -1;
2134 memset(&key->opt, 0, sizeof(key->opt));
2135 goto again;
2136 }
2137
2138 util_queue_fence_wait(&iter->ready);
2139 }
2140
2141 if (iter->compilation_failed) {
2142 return -1; /* skip the draw call */
2143 }
2144
2145 state->current = iter;
2146 return 0;
2147 }
2148 }
2149
2150 /* Build a new shader. */
2151 shader = CALLOC_STRUCT(si_shader);
2152 if (!shader) {
2153 mtx_unlock(&sel->mutex);
2154 return -ENOMEM;
2155 }
2156
2157 util_queue_fence_init(&shader->ready);
2158
2159 shader->selector = sel;
2160 shader->key = *key;
2161 shader->compiler_ctx_state = *compiler_state;
2162
2163 /* If this is a merged shader, get the first shader's selector. */
2164 if (sscreen->info.chip_class >= GFX9) {
2165 if (sel->type == PIPE_SHADER_TESS_CTRL)
2166 previous_stage_sel = key->part.tcs.ls;
2167 else if (sel->type == PIPE_SHADER_GEOMETRY)
2168 previous_stage_sel = key->part.gs.es;
2169
2170 /* We need to wait for the previous shader. */
2171 if (previous_stage_sel && thread_index < 0)
2172 util_queue_fence_wait(&previous_stage_sel->ready);
2173 }
2174
2175 bool is_pure_monolithic =
2176 sscreen->use_monolithic_shaders ||
2177 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2178
2179 /* Compile the main shader part if it doesn't exist. This can happen
2180 * if the initial guess was wrong.
2181 *
2182 * The prim discard CS doesn't need the main shader part.
2183 */
2184 if (!is_pure_monolithic &&
2185 !key->opt.vs_as_prim_discard_cs) {
2186 bool ok = true;
2187
2188 /* Make sure the main shader part is present. This is needed
2189 * for shaders that can be compiled as VS, LS, or ES, and only
2190 * one of them is compiled at creation.
2191 *
2192 * It is also needed for GS, which can be compiled as non-NGG
2193 * and NGG.
2194 *
2195 * For merged shaders, check that the starting shader's main
2196 * part is present.
2197 */
2198 if (previous_stage_sel) {
2199 struct si_shader_key shader1_key = zeroed;
2200
2201 if (sel->type == PIPE_SHADER_TESS_CTRL)
2202 shader1_key.as_ls = 1;
2203 else if (sel->type == PIPE_SHADER_GEOMETRY)
2204 shader1_key.as_es = 1;
2205 else
2206 assert(0);
2207
2208 mtx_lock(&previous_stage_sel->mutex);
2209 ok = si_check_missing_main_part(sscreen,
2210 previous_stage_sel,
2211 compiler_state, &shader1_key);
2212 mtx_unlock(&previous_stage_sel->mutex);
2213 }
2214
2215 if (ok) {
2216 ok = si_check_missing_main_part(sscreen, sel,
2217 compiler_state, key);
2218 }
2219
2220 if (!ok) {
2221 FREE(shader);
2222 mtx_unlock(&sel->mutex);
2223 return -ENOMEM; /* skip the draw call */
2224 }
2225 }
2226
2227 /* Keep the reference to the 1st shader of merged shaders, so that
2228 * Gallium can't destroy it before we destroy the 2nd shader.
2229 *
2230 * Set sctx = NULL, because it's unused if we're not releasing
2231 * the shader, and we don't have any sctx here.
2232 */
2233 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2234 previous_stage_sel);
2235
2236 /* Monolithic-only shaders don't make a distinction between optimized
2237 * and unoptimized. */
2238 shader->is_monolithic =
2239 is_pure_monolithic ||
2240 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2241
2242 /* The prim discard CS is always optimized. */
2243 shader->is_optimized =
2244 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2245 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2246
2247 /* If it's an optimized shader, compile it asynchronously. */
2248 if (shader->is_optimized && thread_index < 0) {
2249 /* Compile it asynchronously. */
2250 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2251 shader, &shader->ready,
2252 si_build_shader_variant_low_priority, NULL);
2253
2254 /* Add only after the ready fence was reset, to guard against a
2255 * race with si_bind_XX_shader. */
2256 if (!sel->last_variant) {
2257 sel->first_variant = shader;
2258 sel->last_variant = shader;
2259 } else {
2260 sel->last_variant->next_variant = shader;
2261 sel->last_variant = shader;
2262 }
2263
2264 /* Use the default (unoptimized) shader for now. */
2265 memset(&key->opt, 0, sizeof(key->opt));
2266 mtx_unlock(&sel->mutex);
2267
2268 if (sscreen->options.sync_compile)
2269 util_queue_fence_wait(&shader->ready);
2270
2271 if (optimized_or_none)
2272 return -1;
2273 goto again;
2274 }
2275
2276 /* Reset the fence before adding to the variant list. */
2277 util_queue_fence_reset(&shader->ready);
2278
2279 if (!sel->last_variant) {
2280 sel->first_variant = shader;
2281 sel->last_variant = shader;
2282 } else {
2283 sel->last_variant->next_variant = shader;
2284 sel->last_variant = shader;
2285 }
2286
2287 mtx_unlock(&sel->mutex);
2288
2289 assert(!shader->is_optimized);
2290 si_build_shader_variant(shader, thread_index, false);
2291
2292 util_queue_fence_signal(&shader->ready);
2293
2294 if (!shader->compilation_failed)
2295 state->current = shader;
2296
2297 return shader->compilation_failed ? -1 : 0;
2298 }
2299
2300 static int si_shader_select(struct pipe_context *ctx,
2301 struct si_shader_ctx_state *state,
2302 union si_vgt_stages_key stages_key,
2303 struct si_compiler_ctx_state *compiler_state)
2304 {
2305 struct si_context *sctx = (struct si_context *)ctx;
2306 struct si_shader_key key;
2307
2308 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2309 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2310 &key, -1, false);
2311 }
2312
2313 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2314 bool streamout,
2315 struct si_shader_key *key)
2316 {
2317 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2318
2319 switch (info->processor) {
2320 case PIPE_SHADER_VERTEX:
2321 switch (next_shader) {
2322 case PIPE_SHADER_GEOMETRY:
2323 key->as_es = 1;
2324 break;
2325 case PIPE_SHADER_TESS_CTRL:
2326 case PIPE_SHADER_TESS_EVAL:
2327 key->as_ls = 1;
2328 break;
2329 default:
2330 /* If POSITION isn't written, it can only be a HW VS
2331 * if streamout is used. If streamout isn't used,
2332 * assume that it's a HW LS. (the next shader is TCS)
2333 * This heuristic is needed for separate shader objects.
2334 */
2335 if (!info->writes_position && !streamout)
2336 key->as_ls = 1;
2337 }
2338 break;
2339
2340 case PIPE_SHADER_TESS_EVAL:
2341 if (next_shader == PIPE_SHADER_GEOMETRY ||
2342 !info->writes_position)
2343 key->as_es = 1;
2344 break;
2345 }
2346 }
2347
2348 /**
2349 * Compile the main shader part or the monolithic shader as part of
2350 * si_shader_selector initialization. Since it can be done asynchronously,
2351 * there is no way to report compile failures to applications.
2352 */
2353 static void si_init_shader_selector_async(void *job, int thread_index)
2354 {
2355 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2356 struct si_screen *sscreen = sel->screen;
2357 struct ac_llvm_compiler *compiler;
2358 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2359
2360 assert(!debug->debug_message || debug->async);
2361 assert(thread_index >= 0);
2362 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2363 compiler = &sscreen->compiler[thread_index];
2364
2365 if (sel->nir)
2366 si_lower_nir(sel);
2367
2368 /* Compile the main shader part for use with a prolog and/or epilog.
2369 * If this fails, the driver will try to compile a monolithic shader
2370 * on demand.
2371 */
2372 if (!sscreen->use_monolithic_shaders) {
2373 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2374 void *ir_binary = NULL;
2375
2376 if (!shader) {
2377 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2378 return;
2379 }
2380
2381 /* We can leave the fence signaled because use of the default
2382 * main part is guarded by the selector's ready fence. */
2383 util_queue_fence_init(&shader->ready);
2384
2385 shader->selector = sel;
2386 shader->is_monolithic = false;
2387 si_parse_next_shader_property(&sel->info,
2388 sel->so.num_outputs != 0,
2389 &shader->key);
2390 if (sscreen->info.chip_class >= GFX10 &&
2391 !sscreen->options.disable_ngg &&
2392 (((sel->type == PIPE_SHADER_VERTEX ||
2393 sel->type == PIPE_SHADER_TESS_EVAL) &&
2394 !shader->key.as_ls && !shader->key.as_es) ||
2395 sel->type == PIPE_SHADER_GEOMETRY))
2396 shader->key.as_ngg = 1;
2397
2398 if (sel->tokens || sel->nir)
2399 ir_binary = si_get_ir_binary(sel);
2400
2401 /* Try to load the shader from the shader cache. */
2402 mtx_lock(&sscreen->shader_cache_mutex);
2403
2404 if (ir_binary &&
2405 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2406 mtx_unlock(&sscreen->shader_cache_mutex);
2407 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2408 } else {
2409 mtx_unlock(&sscreen->shader_cache_mutex);
2410
2411 /* Compile the shader if it hasn't been loaded from the cache. */
2412 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2413 debug) != 0) {
2414 FREE(shader);
2415 FREE(ir_binary);
2416 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2417 return;
2418 }
2419
2420 if (ir_binary) {
2421 mtx_lock(&sscreen->shader_cache_mutex);
2422 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2423 FREE(ir_binary);
2424 mtx_unlock(&sscreen->shader_cache_mutex);
2425 }
2426 }
2427
2428 *si_get_main_shader_part(sel, &shader->key) = shader;
2429
2430 /* Unset "outputs_written" flags for outputs converted to
2431 * DEFAULT_VAL, so that later inter-shader optimizations don't
2432 * try to eliminate outputs that don't exist in the final
2433 * shader.
2434 *
2435 * This is only done if non-monolithic shaders are enabled.
2436 */
2437 if ((sel->type == PIPE_SHADER_VERTEX ||
2438 sel->type == PIPE_SHADER_TESS_EVAL) &&
2439 !shader->key.as_ls &&
2440 !shader->key.as_es) {
2441 unsigned i;
2442
2443 for (i = 0; i < sel->info.num_outputs; i++) {
2444 unsigned offset = shader->info.vs_output_param_offset[i];
2445
2446 if (offset <= AC_EXP_PARAM_OFFSET_31)
2447 continue;
2448
2449 unsigned name = sel->info.output_semantic_name[i];
2450 unsigned index = sel->info.output_semantic_index[i];
2451 unsigned id;
2452
2453 switch (name) {
2454 case TGSI_SEMANTIC_GENERIC:
2455 /* don't process indices the function can't handle */
2456 if (index >= SI_MAX_IO_GENERIC)
2457 break;
2458 /* fall through */
2459 default:
2460 id = si_shader_io_get_unique_index(name, index, true);
2461 sel->outputs_written_before_ps &= ~(1ull << id);
2462 break;
2463 case TGSI_SEMANTIC_POSITION: /* ignore these */
2464 case TGSI_SEMANTIC_PSIZE:
2465 case TGSI_SEMANTIC_CLIPVERTEX:
2466 case TGSI_SEMANTIC_EDGEFLAG:
2467 break;
2468 }
2469 }
2470 }
2471 }
2472
2473 /* The GS copy shader is always pre-compiled.
2474 *
2475 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2476 * is only used in the (rare) non-NGG case.
2477 */
2478 if (sel->type == PIPE_SHADER_GEOMETRY) {
2479 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2480 if (!sel->gs_copy_shader) {
2481 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2482 return;
2483 }
2484
2485 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2486 }
2487 }
2488
2489 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2490 struct util_queue_fence *ready_fence,
2491 struct si_compiler_ctx_state *compiler_ctx_state,
2492 void *job, util_queue_execute_func execute)
2493 {
2494 util_queue_fence_init(ready_fence);
2495
2496 struct util_async_debug_callback async_debug;
2497 bool debug =
2498 (sctx->debug.debug_message && !sctx->debug.async) ||
2499 sctx->is_debug ||
2500 si_can_dump_shader(sctx->screen, processor);
2501
2502 if (debug) {
2503 u_async_debug_init(&async_debug);
2504 compiler_ctx_state->debug = async_debug.base;
2505 }
2506
2507 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2508 ready_fence, execute, NULL);
2509
2510 if (debug) {
2511 util_queue_fence_wait(ready_fence);
2512 u_async_debug_drain(&async_debug, &sctx->debug);
2513 u_async_debug_cleanup(&async_debug);
2514 }
2515
2516 if (sctx->screen->options.sync_compile)
2517 util_queue_fence_wait(ready_fence);
2518 }
2519
2520 /* Return descriptor slot usage masks from the given shader info. */
2521 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2522 uint32_t *const_and_shader_buffers,
2523 uint64_t *samplers_and_images)
2524 {
2525 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2526
2527 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2528 num_constbufs = util_last_bit(info->const_buffers_declared);
2529 /* two 8-byte images share one 16-byte slot */
2530 num_images = align(util_last_bit(info->images_declared), 2);
2531 num_samplers = util_last_bit(info->samplers_declared);
2532
2533 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2534 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2535 *const_and_shader_buffers =
2536 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2537
2538 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2539 start = si_get_image_slot(num_images - 1) / 2;
2540 *samplers_and_images =
2541 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2542 }
2543
2544 static void *si_create_shader_selector(struct pipe_context *ctx,
2545 const struct pipe_shader_state *state)
2546 {
2547 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2548 struct si_context *sctx = (struct si_context*)ctx;
2549 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2550 int i;
2551
2552 if (!sel)
2553 return NULL;
2554
2555 pipe_reference_init(&sel->reference, 1);
2556 sel->screen = sscreen;
2557 sel->compiler_ctx_state.debug = sctx->debug;
2558 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2559
2560 sel->so = state->stream_output;
2561
2562 if (state->type == PIPE_SHADER_IR_TGSI) {
2563 sel->tokens = tgsi_dup_tokens(state->tokens);
2564 if (!sel->tokens) {
2565 FREE(sel);
2566 return NULL;
2567 }
2568
2569 tgsi_scan_shader(state->tokens, &sel->info);
2570 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2571 } else {
2572 assert(state->type == PIPE_SHADER_IR_NIR);
2573
2574 sel->nir = state->ir.nir;
2575
2576 si_nir_opts(sel->nir);
2577 si_nir_scan_shader(sel->nir, &sel->info);
2578 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2579 }
2580
2581 sel->type = sel->info.processor;
2582 p_atomic_inc(&sscreen->num_shaders_created);
2583 si_get_active_slot_masks(&sel->info,
2584 &sel->active_const_and_shader_buffers,
2585 &sel->active_samplers_and_images);
2586
2587 /* Record which streamout buffers are enabled. */
2588 for (i = 0; i < sel->so.num_outputs; i++) {
2589 sel->enabled_streamout_buffer_mask |=
2590 (1 << sel->so.output[i].output_buffer) <<
2591 (sel->so.output[i].stream * 4);
2592 }
2593
2594 /* The prolog is a no-op if there are no inputs. */
2595 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2596 sel->info.num_inputs &&
2597 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2598
2599 sel->force_correct_derivs_after_kill =
2600 sel->type == PIPE_SHADER_FRAGMENT &&
2601 sel->info.uses_derivatives &&
2602 sel->info.uses_kill &&
2603 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2604
2605 sel->prim_discard_cs_allowed =
2606 sel->type == PIPE_SHADER_VERTEX &&
2607 !sel->info.uses_bindless_images &&
2608 !sel->info.uses_bindless_samplers &&
2609 !sel->info.writes_memory &&
2610 !sel->info.writes_viewport_index &&
2611 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2612 !sel->so.num_outputs;
2613
2614 /* Set which opcode uses which (i,j) pair. */
2615 if (sel->info.uses_persp_opcode_interp_centroid)
2616 sel->info.uses_persp_centroid = true;
2617
2618 if (sel->info.uses_linear_opcode_interp_centroid)
2619 sel->info.uses_linear_centroid = true;
2620
2621 if (sel->info.uses_persp_opcode_interp_offset ||
2622 sel->info.uses_persp_opcode_interp_sample)
2623 sel->info.uses_persp_center = true;
2624
2625 if (sel->info.uses_linear_opcode_interp_offset ||
2626 sel->info.uses_linear_opcode_interp_sample)
2627 sel->info.uses_linear_center = true;
2628
2629 switch (sel->type) {
2630 case PIPE_SHADER_GEOMETRY:
2631 sel->gs_output_prim =
2632 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2633 sel->gs_max_out_vertices =
2634 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2635 sel->gs_num_invocations =
2636 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2637 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2638 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2639 sel->gs_max_out_vertices;
2640
2641 sel->max_gs_stream = 0;
2642 for (i = 0; i < sel->so.num_outputs; i++)
2643 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2644 sel->so.output[i].stream);
2645
2646 sel->gs_input_verts_per_prim =
2647 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2648 break;
2649
2650 case PIPE_SHADER_TESS_CTRL:
2651 /* Always reserve space for these. */
2652 sel->patch_outputs_written |=
2653 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2654 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2655 /* fall through */
2656 case PIPE_SHADER_VERTEX:
2657 case PIPE_SHADER_TESS_EVAL:
2658 for (i = 0; i < sel->info.num_outputs; i++) {
2659 unsigned name = sel->info.output_semantic_name[i];
2660 unsigned index = sel->info.output_semantic_index[i];
2661
2662 switch (name) {
2663 case TGSI_SEMANTIC_TESSINNER:
2664 case TGSI_SEMANTIC_TESSOUTER:
2665 case TGSI_SEMANTIC_PATCH:
2666 sel->patch_outputs_written |=
2667 1ull << si_shader_io_get_unique_index_patch(name, index);
2668 break;
2669
2670 case TGSI_SEMANTIC_GENERIC:
2671 /* don't process indices the function can't handle */
2672 if (index >= SI_MAX_IO_GENERIC)
2673 break;
2674 /* fall through */
2675 default:
2676 sel->outputs_written |=
2677 1ull << si_shader_io_get_unique_index(name, index, false);
2678 sel->outputs_written_before_ps |=
2679 1ull << si_shader_io_get_unique_index(name, index, true);
2680 break;
2681 case TGSI_SEMANTIC_EDGEFLAG:
2682 break;
2683 }
2684 }
2685 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2686 sel->lshs_vertex_stride = sel->esgs_itemsize;
2687
2688 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2689 * will start on a different bank. (except for the maximum 32*16).
2690 */
2691 if (sel->lshs_vertex_stride < 32*16)
2692 sel->lshs_vertex_stride += 4;
2693
2694 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2695 * conflicts, i.e. each vertex will start at a different bank.
2696 */
2697 if (sctx->chip_class >= GFX9)
2698 sel->esgs_itemsize += 4;
2699
2700 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2701 break;
2702
2703 case PIPE_SHADER_FRAGMENT:
2704 for (i = 0; i < sel->info.num_inputs; i++) {
2705 unsigned name = sel->info.input_semantic_name[i];
2706 unsigned index = sel->info.input_semantic_index[i];
2707
2708 switch (name) {
2709 case TGSI_SEMANTIC_GENERIC:
2710 /* don't process indices the function can't handle */
2711 if (index >= SI_MAX_IO_GENERIC)
2712 break;
2713 /* fall through */
2714 default:
2715 sel->inputs_read |=
2716 1ull << si_shader_io_get_unique_index(name, index, true);
2717 break;
2718 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2719 break;
2720 }
2721 }
2722
2723 for (i = 0; i < 8; i++)
2724 if (sel->info.colors_written & (1 << i))
2725 sel->colors_written_4bit |= 0xf << (4 * i);
2726
2727 for (i = 0; i < sel->info.num_inputs; i++) {
2728 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2729 int index = sel->info.input_semantic_index[i];
2730 sel->color_attr_index[index] = i;
2731 }
2732 }
2733 break;
2734 }
2735
2736 /* PA_CL_VS_OUT_CNTL */
2737 bool misc_vec_ena =
2738 sel->info.writes_psize || sel->info.writes_edgeflag ||
2739 sel->info.writes_layer || sel->info.writes_viewport_index;
2740 sel->pa_cl_vs_out_cntl =
2741 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2742 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2743 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2744 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2745 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2746 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2747 sel->clipdist_mask = sel->info.writes_clipvertex ?
2748 SIX_BITS : sel->info.clipdist_writemask;
2749 sel->culldist_mask = sel->info.culldist_writemask <<
2750 sel->info.num_written_clipdistance;
2751
2752 /* DB_SHADER_CONTROL */
2753 sel->db_shader_control =
2754 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2755 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2756 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2757 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2758
2759 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2760 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2761 sel->db_shader_control |=
2762 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2763 break;
2764 case TGSI_FS_DEPTH_LAYOUT_LESS:
2765 sel->db_shader_control |=
2766 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2767 break;
2768 }
2769
2770 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2771 *
2772 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2773 * --|-----------|------------|------------|--------------------|-------------------|-------------
2774 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2775 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2776 * 2 | false | true | n/a | LateZ | 1 | 0
2777 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2778 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2779 *
2780 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2781 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2782 *
2783 * Don't use ReZ without profiling !!!
2784 *
2785 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2786 * shaders.
2787 */
2788 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2789 /* Cases 3, 4. */
2790 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2791 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2792 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2793 } else if (sel->info.writes_memory) {
2794 /* Case 2. */
2795 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2796 S_02880C_EXEC_ON_HIER_FAIL(1);
2797 } else {
2798 /* Case 1. */
2799 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2800 }
2801
2802 (void) mtx_init(&sel->mutex, mtx_plain);
2803
2804 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2805 &sel->compiler_ctx_state, sel,
2806 si_init_shader_selector_async);
2807 return sel;
2808 }
2809
2810 static void si_update_streamout_state(struct si_context *sctx)
2811 {
2812 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2813
2814 if (!shader_with_so)
2815 return;
2816
2817 sctx->streamout.enabled_stream_buffers_mask =
2818 shader_with_so->enabled_streamout_buffer_mask;
2819 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2820 }
2821
2822 static void si_update_clip_regs(struct si_context *sctx,
2823 struct si_shader_selector *old_hw_vs,
2824 struct si_shader *old_hw_vs_variant,
2825 struct si_shader_selector *next_hw_vs,
2826 struct si_shader *next_hw_vs_variant)
2827 {
2828 if (next_hw_vs &&
2829 (!old_hw_vs ||
2830 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2831 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2832 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2833 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2834 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2835 !old_hw_vs_variant ||
2836 !next_hw_vs_variant ||
2837 old_hw_vs_variant->key.opt.clip_disable !=
2838 next_hw_vs_variant->key.opt.clip_disable))
2839 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2840 }
2841
2842 static void si_update_common_shader_state(struct si_context *sctx)
2843 {
2844 sctx->uses_bindless_samplers =
2845 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2846 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2847 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2848 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2849 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2850 sctx->uses_bindless_images =
2851 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2852 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2853 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2854 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2855 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2856 sctx->do_update_shaders = true;
2857 }
2858
2859 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2860 {
2861 struct si_context *sctx = (struct si_context *)ctx;
2862 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2863 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2864 struct si_shader_selector *sel = state;
2865
2866 if (sctx->vs_shader.cso == sel)
2867 return;
2868
2869 sctx->vs_shader.cso = sel;
2870 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2871 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2872
2873 si_update_common_shader_state(sctx);
2874 si_update_vs_viewport_state(sctx);
2875 si_set_active_descriptors_for_shader(sctx, sel);
2876 si_update_streamout_state(sctx);
2877 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2878 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2879 }
2880
2881 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2882 {
2883 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2884 (sctx->tes_shader.cso &&
2885 sctx->tes_shader.cso->info.uses_primid) ||
2886 (sctx->tcs_shader.cso &&
2887 sctx->tcs_shader.cso->info.uses_primid) ||
2888 (sctx->gs_shader.cso &&
2889 sctx->gs_shader.cso->info.uses_primid) ||
2890 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2891 sctx->ps_shader.cso->info.uses_primid);
2892 }
2893
2894 static bool si_update_ngg(struct si_context *sctx)
2895 {
2896 if (sctx->chip_class <= GFX9 ||
2897 sctx->screen->options.disable_ngg)
2898 return false;
2899
2900 bool new_ngg = true;
2901
2902 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2903 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2904 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2905 new_ngg = false;
2906
2907 if (new_ngg != sctx->ngg) {
2908 sctx->ngg = new_ngg;
2909 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2910 return true;
2911 }
2912 return false;
2913 }
2914
2915 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2916 {
2917 struct si_context *sctx = (struct si_context *)ctx;
2918 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2919 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2920 struct si_shader_selector *sel = state;
2921 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2922 bool ngg_changed;
2923
2924 if (sctx->gs_shader.cso == sel)
2925 return;
2926
2927 sctx->gs_shader.cso = sel;
2928 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2929 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2930
2931 si_update_common_shader_state(sctx);
2932 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2933
2934 ngg_changed = si_update_ngg(sctx);
2935 if (ngg_changed || enable_changed)
2936 si_shader_change_notify(sctx);
2937 if (enable_changed) {
2938 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2939 si_update_tess_uses_prim_id(sctx);
2940 }
2941 si_update_vs_viewport_state(sctx);
2942 si_set_active_descriptors_for_shader(sctx, sel);
2943 si_update_streamout_state(sctx);
2944 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2945 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2946 }
2947
2948 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2949 {
2950 struct si_context *sctx = (struct si_context *)ctx;
2951 struct si_shader_selector *sel = state;
2952 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2953
2954 if (sctx->tcs_shader.cso == sel)
2955 return;
2956
2957 sctx->tcs_shader.cso = sel;
2958 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2959 si_update_tess_uses_prim_id(sctx);
2960
2961 si_update_common_shader_state(sctx);
2962
2963 if (enable_changed)
2964 sctx->last_tcs = NULL; /* invalidate derived tess state */
2965
2966 si_set_active_descriptors_for_shader(sctx, sel);
2967 }
2968
2969 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2970 {
2971 struct si_context *sctx = (struct si_context *)ctx;
2972 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2973 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2974 struct si_shader_selector *sel = state;
2975 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2976
2977 if (sctx->tes_shader.cso == sel)
2978 return;
2979
2980 sctx->tes_shader.cso = sel;
2981 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2982 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2983 si_update_tess_uses_prim_id(sctx);
2984
2985 si_update_common_shader_state(sctx);
2986 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2987
2988 if (enable_changed) {
2989 si_update_ngg(sctx);
2990 si_shader_change_notify(sctx);
2991 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2992 }
2993 si_update_vs_viewport_state(sctx);
2994 si_set_active_descriptors_for_shader(sctx, sel);
2995 si_update_streamout_state(sctx);
2996 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2997 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2998 }
2999
3000 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3001 {
3002 struct si_context *sctx = (struct si_context *)ctx;
3003 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3004 struct si_shader_selector *sel = state;
3005
3006 /* skip if supplied shader is one already in use */
3007 if (old_sel == sel)
3008 return;
3009
3010 sctx->ps_shader.cso = sel;
3011 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3012
3013 si_update_common_shader_state(sctx);
3014 if (sel) {
3015 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3016 si_update_tess_uses_prim_id(sctx);
3017
3018 if (!old_sel ||
3019 old_sel->info.colors_written != sel->info.colors_written)
3020 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3021
3022 if (sctx->screen->has_out_of_order_rast &&
3023 (!old_sel ||
3024 old_sel->info.writes_memory != sel->info.writes_memory ||
3025 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3026 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3027 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3028 }
3029 si_set_active_descriptors_for_shader(sctx, sel);
3030 si_update_ps_colorbuf0_slot(sctx);
3031 }
3032
3033 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3034 {
3035 if (shader->is_optimized) {
3036 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3037 &shader->ready);
3038 }
3039
3040 util_queue_fence_destroy(&shader->ready);
3041
3042 if (shader->pm4) {
3043 /* If destroyed shaders were not unbound, the next compiled
3044 * shader variant could get the same pointer address and so
3045 * binding it to the same shader stage would be considered
3046 * a no-op, causing random behavior.
3047 */
3048 switch (shader->selector->type) {
3049 case PIPE_SHADER_VERTEX:
3050 if (shader->key.as_ls) {
3051 assert(sctx->chip_class <= GFX8);
3052 si_pm4_delete_state(sctx, ls, shader->pm4);
3053 } else if (shader->key.as_es) {
3054 assert(sctx->chip_class <= GFX8);
3055 si_pm4_delete_state(sctx, es, shader->pm4);
3056 } else if (shader->key.as_ngg) {
3057 si_pm4_delete_state(sctx, gs, shader->pm4);
3058 } else {
3059 si_pm4_delete_state(sctx, vs, shader->pm4);
3060 }
3061 break;
3062 case PIPE_SHADER_TESS_CTRL:
3063 si_pm4_delete_state(sctx, hs, shader->pm4);
3064 break;
3065 case PIPE_SHADER_TESS_EVAL:
3066 if (shader->key.as_es) {
3067 assert(sctx->chip_class <= GFX8);
3068 si_pm4_delete_state(sctx, es, shader->pm4);
3069 } else if (shader->key.as_ngg) {
3070 si_pm4_delete_state(sctx, gs, shader->pm4);
3071 } else {
3072 si_pm4_delete_state(sctx, vs, shader->pm4);
3073 }
3074 break;
3075 case PIPE_SHADER_GEOMETRY:
3076 if (shader->is_gs_copy_shader)
3077 si_pm4_delete_state(sctx, vs, shader->pm4);
3078 else
3079 si_pm4_delete_state(sctx, gs, shader->pm4);
3080 break;
3081 case PIPE_SHADER_FRAGMENT:
3082 si_pm4_delete_state(sctx, ps, shader->pm4);
3083 break;
3084 }
3085 }
3086
3087 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3088 si_shader_destroy(shader);
3089 free(shader);
3090 }
3091
3092 void si_destroy_shader_selector(struct si_context *sctx,
3093 struct si_shader_selector *sel)
3094 {
3095 struct si_shader *p = sel->first_variant, *c;
3096 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3097 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3098 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3099 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3100 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3101 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3102 };
3103
3104 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3105
3106 if (current_shader[sel->type]->cso == sel) {
3107 current_shader[sel->type]->cso = NULL;
3108 current_shader[sel->type]->current = NULL;
3109 }
3110
3111 while (p) {
3112 c = p->next_variant;
3113 si_delete_shader(sctx, p);
3114 p = c;
3115 }
3116
3117 if (sel->main_shader_part)
3118 si_delete_shader(sctx, sel->main_shader_part);
3119 if (sel->main_shader_part_ls)
3120 si_delete_shader(sctx, sel->main_shader_part_ls);
3121 if (sel->main_shader_part_es)
3122 si_delete_shader(sctx, sel->main_shader_part_es);
3123 if (sel->main_shader_part_ngg)
3124 si_delete_shader(sctx, sel->main_shader_part_ngg);
3125 if (sel->gs_copy_shader)
3126 si_delete_shader(sctx, sel->gs_copy_shader);
3127
3128 util_queue_fence_destroy(&sel->ready);
3129 mtx_destroy(&sel->mutex);
3130 free(sel->tokens);
3131 ralloc_free(sel->nir);
3132 free(sel);
3133 }
3134
3135 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3136 {
3137 struct si_context *sctx = (struct si_context *)ctx;
3138 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3139
3140 si_shader_selector_reference(sctx, &sel, NULL);
3141 }
3142
3143 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3144 struct si_shader *vs, unsigned name,
3145 unsigned index, unsigned interpolate)
3146 {
3147 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3148 unsigned j, offset, ps_input_cntl = 0;
3149
3150 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3151 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3152 name == TGSI_SEMANTIC_PRIMID)
3153 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3154
3155 if (name == TGSI_SEMANTIC_PCOORD ||
3156 (name == TGSI_SEMANTIC_TEXCOORD &&
3157 sctx->sprite_coord_enable & (1 << index))) {
3158 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3159 }
3160
3161 for (j = 0; j < vsinfo->num_outputs; j++) {
3162 if (name == vsinfo->output_semantic_name[j] &&
3163 index == vsinfo->output_semantic_index[j]) {
3164 offset = vs->info.vs_output_param_offset[j];
3165
3166 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3167 /* The input is loaded from parameter memory. */
3168 ps_input_cntl |= S_028644_OFFSET(offset);
3169 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3170 if (offset == AC_EXP_PARAM_UNDEFINED) {
3171 /* This can happen with depth-only rendering. */
3172 offset = 0;
3173 } else {
3174 /* The input is a DEFAULT_VAL constant. */
3175 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3176 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3177 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3178 }
3179
3180 ps_input_cntl = S_028644_OFFSET(0x20) |
3181 S_028644_DEFAULT_VAL(offset);
3182 }
3183 break;
3184 }
3185 }
3186
3187 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3188 /* PrimID is written after the last output when HW VS is used. */
3189 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3190 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3191 /* No corresponding output found, load defaults into input.
3192 * Don't set any other bits.
3193 * (FLAT_SHADE=1 completely changes behavior) */
3194 ps_input_cntl = S_028644_OFFSET(0x20);
3195 /* D3D 9 behaviour. GL is undefined */
3196 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3197 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3198 }
3199 return ps_input_cntl;
3200 }
3201
3202 static void si_emit_spi_map(struct si_context *sctx)
3203 {
3204 struct si_shader *ps = sctx->ps_shader.current;
3205 struct si_shader *vs = si_get_vs_state(sctx);
3206 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3207 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3208 unsigned spi_ps_input_cntl[32];
3209
3210 if (!ps || !ps->selector->info.num_inputs)
3211 return;
3212
3213 num_interp = si_get_ps_num_interp(ps);
3214 assert(num_interp > 0);
3215
3216 for (i = 0; i < psinfo->num_inputs; i++) {
3217 unsigned name = psinfo->input_semantic_name[i];
3218 unsigned index = psinfo->input_semantic_index[i];
3219 unsigned interpolate = psinfo->input_interpolate[i];
3220
3221 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3222 index, interpolate);
3223
3224 if (name == TGSI_SEMANTIC_COLOR) {
3225 assert(index < ARRAY_SIZE(bcol_interp));
3226 bcol_interp[index] = interpolate;
3227 }
3228 }
3229
3230 if (ps->key.part.ps.prolog.color_two_side) {
3231 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3232
3233 for (i = 0; i < 2; i++) {
3234 if (!(psinfo->colors_read & (0xf << (i * 4))))
3235 continue;
3236
3237 spi_ps_input_cntl[num_written++] =
3238 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3239
3240 }
3241 }
3242 assert(num_interp == num_written);
3243
3244 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3245 /* Dota 2: Only ~16% of SPI map updates set different values. */
3246 /* Talos: Only ~9% of SPI map updates set different values. */
3247 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3248 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3249 spi_ps_input_cntl,
3250 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3251
3252 if (initial_cdw != sctx->gfx_cs->current.cdw)
3253 sctx->context_roll = true;
3254 }
3255
3256 /**
3257 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3258 */
3259 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3260 {
3261 if (sctx->init_config_has_vgt_flush)
3262 return;
3263
3264 /* Done by Vulkan before VGT_FLUSH. */
3265 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3266 si_pm4_cmd_add(sctx->init_config,
3267 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3268 si_pm4_cmd_end(sctx->init_config, false);
3269
3270 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3271 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3272 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3273 si_pm4_cmd_end(sctx->init_config, false);
3274 sctx->init_config_has_vgt_flush = true;
3275 }
3276
3277 /* Initialize state related to ESGS / GSVS ring buffers */
3278 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3279 {
3280 struct si_shader_selector *es =
3281 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3282 struct si_shader_selector *gs = sctx->gs_shader.cso;
3283 struct si_pm4_state *pm4;
3284
3285 /* Chip constants. */
3286 unsigned num_se = sctx->screen->info.max_se;
3287 unsigned wave_size = 64;
3288 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3289 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3290 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3291 */
3292 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3293 unsigned alignment = 256 * num_se;
3294 /* The maximum size is 63.999 MB per SE. */
3295 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3296
3297 /* Calculate the minimum size. */
3298 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3299 wave_size, alignment);
3300
3301 /* These are recommended sizes, not minimum sizes. */
3302 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3303 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3304 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3305 gs->max_gsvs_emit_size;
3306
3307 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3308 esgs_ring_size = align(esgs_ring_size, alignment);
3309 gsvs_ring_size = align(gsvs_ring_size, alignment);
3310
3311 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3312 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3313
3314 /* Some rings don't have to be allocated if shaders don't use them.
3315 * (e.g. no varyings between ES and GS or GS and VS)
3316 *
3317 * GFX9 doesn't have the ESGS ring.
3318 */
3319 bool update_esgs = sctx->chip_class <= GFX8 &&
3320 esgs_ring_size &&
3321 (!sctx->esgs_ring ||
3322 sctx->esgs_ring->width0 < esgs_ring_size);
3323 bool update_gsvs = gsvs_ring_size &&
3324 (!sctx->gsvs_ring ||
3325 sctx->gsvs_ring->width0 < gsvs_ring_size);
3326
3327 if (!update_esgs && !update_gsvs)
3328 return true;
3329
3330 if (update_esgs) {
3331 pipe_resource_reference(&sctx->esgs_ring, NULL);
3332 sctx->esgs_ring =
3333 pipe_aligned_buffer_create(sctx->b.screen,
3334 SI_RESOURCE_FLAG_UNMAPPABLE,
3335 PIPE_USAGE_DEFAULT,
3336 esgs_ring_size, alignment);
3337 if (!sctx->esgs_ring)
3338 return false;
3339 }
3340
3341 if (update_gsvs) {
3342 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3343 sctx->gsvs_ring =
3344 pipe_aligned_buffer_create(sctx->b.screen,
3345 SI_RESOURCE_FLAG_UNMAPPABLE,
3346 PIPE_USAGE_DEFAULT,
3347 gsvs_ring_size, alignment);
3348 if (!sctx->gsvs_ring)
3349 return false;
3350 }
3351
3352 /* Create the "init_config_gs_rings" state. */
3353 pm4 = CALLOC_STRUCT(si_pm4_state);
3354 if (!pm4)
3355 return false;
3356
3357 if (sctx->chip_class >= GFX7) {
3358 if (sctx->esgs_ring) {
3359 assert(sctx->chip_class <= GFX8);
3360 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3361 sctx->esgs_ring->width0 / 256);
3362 }
3363 if (sctx->gsvs_ring)
3364 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3365 sctx->gsvs_ring->width0 / 256);
3366 } else {
3367 if (sctx->esgs_ring)
3368 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3369 sctx->esgs_ring->width0 / 256);
3370 if (sctx->gsvs_ring)
3371 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3372 sctx->gsvs_ring->width0 / 256);
3373 }
3374
3375 /* Set the state. */
3376 if (sctx->init_config_gs_rings)
3377 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3378 sctx->init_config_gs_rings = pm4;
3379
3380 if (!sctx->init_config_has_vgt_flush) {
3381 si_init_config_add_vgt_flush(sctx);
3382 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3383 }
3384
3385 /* Flush the context to re-emit both init_config states. */
3386 sctx->initial_gfx_cs_size = 0; /* force flush */
3387 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3388
3389 /* Set ring bindings. */
3390 if (sctx->esgs_ring) {
3391 assert(sctx->chip_class <= GFX8);
3392 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3393 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3394 true, true, 4, 64, 0);
3395 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3396 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3397 false, false, 0, 0, 0);
3398 }
3399 if (sctx->gsvs_ring) {
3400 si_set_ring_buffer(sctx, SI_RING_GSVS,
3401 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3402 false, false, 0, 0, 0);
3403 }
3404
3405 return true;
3406 }
3407
3408 static void si_shader_lock(struct si_shader *shader)
3409 {
3410 mtx_lock(&shader->selector->mutex);
3411 if (shader->previous_stage_sel) {
3412 assert(shader->previous_stage_sel != shader->selector);
3413 mtx_lock(&shader->previous_stage_sel->mutex);
3414 }
3415 }
3416
3417 static void si_shader_unlock(struct si_shader *shader)
3418 {
3419 if (shader->previous_stage_sel)
3420 mtx_unlock(&shader->previous_stage_sel->mutex);
3421 mtx_unlock(&shader->selector->mutex);
3422 }
3423
3424 /**
3425 * @returns 1 if \p sel has been updated to use a new scratch buffer
3426 * 0 if not
3427 * < 0 if there was a failure
3428 */
3429 static int si_update_scratch_buffer(struct si_context *sctx,
3430 struct si_shader *shader)
3431 {
3432 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3433
3434 if (!shader)
3435 return 0;
3436
3437 /* This shader doesn't need a scratch buffer */
3438 if (shader->config.scratch_bytes_per_wave == 0)
3439 return 0;
3440
3441 /* Prevent race conditions when updating:
3442 * - si_shader::scratch_bo
3443 * - si_shader::binary::code
3444 * - si_shader::previous_stage::binary::code.
3445 */
3446 si_shader_lock(shader);
3447
3448 /* This shader is already configured to use the current
3449 * scratch buffer. */
3450 if (shader->scratch_bo == sctx->scratch_buffer) {
3451 si_shader_unlock(shader);
3452 return 0;
3453 }
3454
3455 assert(sctx->scratch_buffer);
3456
3457 /* Replace the shader bo with a new bo that has the relocs applied. */
3458 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3459 si_shader_unlock(shader);
3460 return -1;
3461 }
3462
3463 /* Update the shader state to use the new shader bo. */
3464 si_shader_init_pm4_state(sctx->screen, shader);
3465
3466 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3467
3468 si_shader_unlock(shader);
3469 return 1;
3470 }
3471
3472 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3473 {
3474 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3475 }
3476
3477 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3478 {
3479 return shader ? shader->config.scratch_bytes_per_wave : 0;
3480 }
3481
3482 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3483 {
3484 if (!sctx->tes_shader.cso)
3485 return NULL; /* tessellation disabled */
3486
3487 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3488 sctx->fixed_func_tcs_shader.current;
3489 }
3490
3491 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3492 {
3493 unsigned bytes = 0;
3494
3495 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3496 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3497 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3498 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3499
3500 if (sctx->tes_shader.cso) {
3501 struct si_shader *tcs = si_get_tcs_current(sctx);
3502
3503 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3504 }
3505 return bytes;
3506 }
3507
3508 static bool si_update_scratch_relocs(struct si_context *sctx)
3509 {
3510 struct si_shader *tcs = si_get_tcs_current(sctx);
3511 int r;
3512
3513 /* Update the shaders, so that they are using the latest scratch.
3514 * The scratch buffer may have been changed since these shaders were
3515 * last used, so we still need to try to update them, even if they
3516 * require scratch buffers smaller than the current size.
3517 */
3518 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3519 if (r < 0)
3520 return false;
3521 if (r == 1)
3522 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3523
3524 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3525 if (r < 0)
3526 return false;
3527 if (r == 1)
3528 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3529
3530 r = si_update_scratch_buffer(sctx, tcs);
3531 if (r < 0)
3532 return false;
3533 if (r == 1)
3534 si_pm4_bind_state(sctx, hs, tcs->pm4);
3535
3536 /* VS can be bound as LS, ES, or VS. */
3537 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3538 if (r < 0)
3539 return false;
3540 if (r == 1) {
3541 if (sctx->vs_shader.current->key.as_ls)
3542 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3543 else if (sctx->vs_shader.current->key.as_es)
3544 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3545 else if (sctx->vs_shader.current->key.as_ngg)
3546 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3547 else
3548 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3549 }
3550
3551 /* TES can be bound as ES or VS. */
3552 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3553 if (r < 0)
3554 return false;
3555 if (r == 1) {
3556 if (sctx->tes_shader.current->key.as_es)
3557 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3558 else if (sctx->tes_shader.current->key.as_ngg)
3559 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3560 else
3561 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3562 }
3563
3564 return true;
3565 }
3566
3567 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3568 {
3569 unsigned current_scratch_buffer_size =
3570 si_get_current_scratch_buffer_size(sctx);
3571 unsigned scratch_bytes_per_wave =
3572 si_get_max_scratch_bytes_per_wave(sctx);
3573 unsigned scratch_needed_size = scratch_bytes_per_wave *
3574 sctx->scratch_waves;
3575 unsigned spi_tmpring_size;
3576
3577 if (scratch_needed_size > 0) {
3578 if (scratch_needed_size > current_scratch_buffer_size) {
3579 /* Create a bigger scratch buffer */
3580 si_resource_reference(&sctx->scratch_buffer, NULL);
3581
3582 sctx->scratch_buffer =
3583 si_aligned_buffer_create(&sctx->screen->b,
3584 SI_RESOURCE_FLAG_UNMAPPABLE,
3585 PIPE_USAGE_DEFAULT,
3586 scratch_needed_size, 256);
3587 if (!sctx->scratch_buffer)
3588 return false;
3589
3590 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3591 si_context_add_resource_size(sctx,
3592 &sctx->scratch_buffer->b.b);
3593 }
3594
3595 if (!si_update_scratch_relocs(sctx))
3596 return false;
3597 }
3598
3599 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3600 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3601 "scratch size should already be aligned correctly.");
3602
3603 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3604 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3605 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3606 sctx->spi_tmpring_size = spi_tmpring_size;
3607 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3608 }
3609 return true;
3610 }
3611
3612 static void si_init_tess_factor_ring(struct si_context *sctx)
3613 {
3614 assert(!sctx->tess_rings);
3615
3616 /* The address must be aligned to 2^19, because the shader only
3617 * receives the high 13 bits.
3618 */
3619 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3620 SI_RESOURCE_FLAG_32BIT,
3621 PIPE_USAGE_DEFAULT,
3622 sctx->screen->tess_offchip_ring_size +
3623 sctx->screen->tess_factor_ring_size,
3624 1 << 19);
3625 if (!sctx->tess_rings)
3626 return;
3627
3628 si_init_config_add_vgt_flush(sctx);
3629
3630 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3631 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3632
3633 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3634 sctx->screen->tess_offchip_ring_size;
3635
3636 /* Append these registers to the init config state. */
3637 if (sctx->chip_class >= GFX7) {
3638 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3639 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3640 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3641 factor_va >> 8);
3642 if (sctx->chip_class >= GFX10)
3643 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3644 S_030984_BASE_HI(factor_va >> 40));
3645 else if (sctx->chip_class == GFX9)
3646 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3647 S_030944_BASE_HI(factor_va >> 40));
3648 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3649 sctx->screen->vgt_hs_offchip_param);
3650 } else {
3651 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3652 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3653 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3654 factor_va >> 8);
3655 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3656 sctx->screen->vgt_hs_offchip_param);
3657 }
3658
3659 /* Flush the context to re-emit the init_config state.
3660 * This is done only once in a lifetime of a context.
3661 */
3662 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3663 sctx->initial_gfx_cs_size = 0; /* force flush */
3664 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3665 }
3666
3667 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3668 union si_vgt_stages_key key)
3669 {
3670 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3671 uint32_t stages = 0;
3672
3673 if (key.u.tess) {
3674 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3675 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3676
3677 if (key.u.gs)
3678 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3679 S_028B54_GS_EN(1);
3680 else if (key.u.ngg)
3681 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3682 else
3683 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3684 } else if (key.u.gs) {
3685 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3686 S_028B54_GS_EN(1);
3687 } else if (key.u.ngg) {
3688 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3689 }
3690
3691 if (key.u.ngg) {
3692 stages |= S_028B54_PRIMGEN_EN(1);
3693 if (key.u.streamout)
3694 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3695 } else if (key.u.gs)
3696 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3697
3698 if (screen->info.chip_class >= GFX9)
3699 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3700
3701 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3702 return pm4;
3703 }
3704
3705 static void si_update_vgt_shader_config(struct si_context *sctx,
3706 union si_vgt_stages_key key)
3707 {
3708 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3709
3710 if (unlikely(!*pm4))
3711 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3712 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3713 }
3714
3715 bool si_update_shaders(struct si_context *sctx)
3716 {
3717 struct pipe_context *ctx = (struct pipe_context*)sctx;
3718 struct si_compiler_ctx_state compiler_state;
3719 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3720 struct si_shader *old_vs = si_get_vs_state(sctx);
3721 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3722 struct si_shader *old_ps = sctx->ps_shader.current;
3723 union si_vgt_stages_key key;
3724 unsigned old_spi_shader_col_format =
3725 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3726 int r;
3727
3728 compiler_state.compiler = &sctx->compiler;
3729 compiler_state.debug = sctx->debug;
3730 compiler_state.is_debug_context = sctx->is_debug;
3731
3732 key.index = 0;
3733
3734 if (sctx->tes_shader.cso)
3735 key.u.tess = 1;
3736 if (sctx->gs_shader.cso)
3737 key.u.gs = 1;
3738
3739 if (sctx->chip_class >= GFX10) {
3740 key.u.ngg = sctx->ngg;
3741
3742 if (sctx->gs_shader.cso)
3743 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3744 else if (sctx->tes_shader.cso)
3745 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3746 else
3747 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3748 }
3749
3750 /* Update TCS and TES. */
3751 if (sctx->tes_shader.cso) {
3752 if (!sctx->tess_rings) {
3753 si_init_tess_factor_ring(sctx);
3754 if (!sctx->tess_rings)
3755 return false;
3756 }
3757
3758 if (sctx->tcs_shader.cso) {
3759 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3760 &compiler_state);
3761 if (r)
3762 return false;
3763 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3764 } else {
3765 if (!sctx->fixed_func_tcs_shader.cso) {
3766 sctx->fixed_func_tcs_shader.cso =
3767 si_create_fixed_func_tcs(sctx);
3768 if (!sctx->fixed_func_tcs_shader.cso)
3769 return false;
3770 }
3771
3772 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3773 key, &compiler_state);
3774 if (r)
3775 return false;
3776 si_pm4_bind_state(sctx, hs,
3777 sctx->fixed_func_tcs_shader.current->pm4);
3778 }
3779
3780 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3781 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3782 if (r)
3783 return false;
3784
3785 if (sctx->gs_shader.cso) {
3786 /* TES as ES */
3787 assert(sctx->chip_class <= GFX8);
3788 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3789 } else if (key.u.ngg) {
3790 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3791 } else {
3792 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3793 }
3794 }
3795 } else {
3796 if (sctx->chip_class <= GFX8)
3797 si_pm4_bind_state(sctx, ls, NULL);
3798 si_pm4_bind_state(sctx, hs, NULL);
3799 }
3800
3801 /* Update GS. */
3802 if (sctx->gs_shader.cso) {
3803 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3804 if (r)
3805 return false;
3806 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3807 if (!key.u.ngg) {
3808 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3809
3810 if (!si_update_gs_ring_buffers(sctx))
3811 return false;
3812 } else {
3813 si_pm4_bind_state(sctx, vs, NULL);
3814 }
3815 } else {
3816 if (!key.u.ngg) {
3817 si_pm4_bind_state(sctx, gs, NULL);
3818 if (sctx->chip_class <= GFX8)
3819 si_pm4_bind_state(sctx, es, NULL);
3820 }
3821 }
3822
3823 /* Update VS. */
3824 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3825 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3826 if (r)
3827 return false;
3828
3829 if (!key.u.tess && !key.u.gs) {
3830 if (key.u.ngg) {
3831 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3832 si_pm4_bind_state(sctx, vs, NULL);
3833 } else {
3834 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3835 }
3836 } else if (sctx->tes_shader.cso) {
3837 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3838 } else {
3839 assert(sctx->gs_shader.cso);
3840 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3841 }
3842 }
3843
3844 si_update_vgt_shader_config(sctx, key);
3845
3846 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3847 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3848
3849 if (sctx->ps_shader.cso) {
3850 unsigned db_shader_control;
3851
3852 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3853 if (r)
3854 return false;
3855 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3856
3857 db_shader_control =
3858 sctx->ps_shader.cso->db_shader_control |
3859 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3860
3861 if (si_pm4_state_changed(sctx, ps) ||
3862 si_pm4_state_changed(sctx, vs) ||
3863 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3864 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3865 sctx->flatshade != rs->flatshade) {
3866 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3867 sctx->flatshade = rs->flatshade;
3868 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3869 }
3870
3871 if (sctx->screen->rbplus_allowed &&
3872 si_pm4_state_changed(sctx, ps) &&
3873 (!old_ps ||
3874 old_spi_shader_col_format !=
3875 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3876 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3877
3878 if (sctx->ps_db_shader_control != db_shader_control) {
3879 sctx->ps_db_shader_control = db_shader_control;
3880 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3881 if (sctx->screen->dpbb_allowed)
3882 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3883 }
3884
3885 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3886 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3887 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3888
3889 if (sctx->chip_class == GFX6)
3890 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3891
3892 if (sctx->framebuffer.nr_samples <= 1)
3893 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3894 }
3895 }
3896
3897 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3898 si_pm4_state_enabled_and_changed(sctx, hs) ||
3899 si_pm4_state_enabled_and_changed(sctx, es) ||
3900 si_pm4_state_enabled_and_changed(sctx, gs) ||
3901 si_pm4_state_enabled_and_changed(sctx, vs) ||
3902 si_pm4_state_enabled_and_changed(sctx, ps)) {
3903 if (!si_update_spi_tmpring_size(sctx))
3904 return false;
3905 }
3906
3907 if (sctx->chip_class >= GFX7) {
3908 if (si_pm4_state_enabled_and_changed(sctx, ls))
3909 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3910 else if (!sctx->queued.named.ls)
3911 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3912
3913 if (si_pm4_state_enabled_and_changed(sctx, hs))
3914 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3915 else if (!sctx->queued.named.hs)
3916 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3917
3918 if (si_pm4_state_enabled_and_changed(sctx, es))
3919 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3920 else if (!sctx->queued.named.es)
3921 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3922
3923 if (si_pm4_state_enabled_and_changed(sctx, gs))
3924 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3925 else if (!sctx->queued.named.gs)
3926 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3927
3928 if (si_pm4_state_enabled_and_changed(sctx, vs))
3929 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3930 else if (!sctx->queued.named.vs)
3931 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3932
3933 if (si_pm4_state_enabled_and_changed(sctx, ps))
3934 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3935 else if (!sctx->queued.named.ps)
3936 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3937 }
3938
3939 sctx->do_update_shaders = false;
3940 return true;
3941 }
3942
3943 static void si_emit_scratch_state(struct si_context *sctx)
3944 {
3945 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3946
3947 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3948 sctx->spi_tmpring_size);
3949
3950 if (sctx->scratch_buffer) {
3951 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3952 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3953 RADEON_PRIO_SCRATCH_BUFFER);
3954 }
3955 }
3956
3957 void si_init_shader_functions(struct si_context *sctx)
3958 {
3959 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3960 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3961
3962 sctx->b.create_vs_state = si_create_shader_selector;
3963 sctx->b.create_tcs_state = si_create_shader_selector;
3964 sctx->b.create_tes_state = si_create_shader_selector;
3965 sctx->b.create_gs_state = si_create_shader_selector;
3966 sctx->b.create_fs_state = si_create_shader_selector;
3967
3968 sctx->b.bind_vs_state = si_bind_vs_shader;
3969 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3970 sctx->b.bind_tes_state = si_bind_tes_shader;
3971 sctx->b.bind_gs_state = si_bind_gs_shader;
3972 sctx->b.bind_fs_state = si_bind_ps_shader;
3973
3974 sctx->b.delete_vs_state = si_delete_shader_selector;
3975 sctx->b.delete_tcs_state = si_delete_shader_selector;
3976 sctx->b.delete_tes_state = si_delete_shader_selector;
3977 sctx->b.delete_gs_state = si_delete_shader_selector;
3978 sctx->b.delete_fs_state = si_delete_shader_selector;
3979 }