2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 #include "radeon/r600_cs.h"
29 #include "util/u_memory.h"
31 static void si_set_streamout_enable(struct si_context
*sctx
, bool enable
);
33 static inline void si_so_target_reference(struct si_streamout_target
**dst
,
34 struct pipe_stream_output_target
*src
)
36 pipe_so_target_reference((struct pipe_stream_output_target
**)dst
, src
);
39 static struct pipe_stream_output_target
*
40 si_create_so_target(struct pipe_context
*ctx
,
41 struct pipe_resource
*buffer
,
42 unsigned buffer_offset
,
45 struct si_context
*sctx
= (struct si_context
*)ctx
;
46 struct si_streamout_target
*t
;
47 struct r600_resource
*rbuffer
= (struct r600_resource
*)buffer
;
49 t
= CALLOC_STRUCT(si_streamout_target
);
54 u_suballocator_alloc(sctx
->b
.allocator_zeroed_memory
, 4, 4,
55 &t
->buf_filled_size_offset
,
56 (struct pipe_resource
**)&t
->buf_filled_size
);
57 if (!t
->buf_filled_size
) {
62 t
->b
.reference
.count
= 1;
64 pipe_resource_reference(&t
->b
.buffer
, buffer
);
65 t
->b
.buffer_offset
= buffer_offset
;
66 t
->b
.buffer_size
= buffer_size
;
68 util_range_add(&rbuffer
->valid_buffer_range
, buffer_offset
,
69 buffer_offset
+ buffer_size
);
73 static void si_so_target_destroy(struct pipe_context
*ctx
,
74 struct pipe_stream_output_target
*target
)
76 struct si_streamout_target
*t
= (struct si_streamout_target
*)target
;
77 pipe_resource_reference(&t
->b
.buffer
, NULL
);
78 r600_resource_reference(&t
->buf_filled_size
, NULL
);
82 void si_streamout_buffers_dirty(struct si_context
*sctx
)
84 if (!sctx
->streamout
.enabled_mask
)
87 si_mark_atom_dirty(sctx
, &sctx
->streamout
.begin_atom
);
88 si_set_streamout_enable(sctx
, true);
91 static void si_set_streamout_targets(struct pipe_context
*ctx
,
93 struct pipe_stream_output_target
**targets
,
94 const unsigned *offsets
)
96 struct si_context
*sctx
= (struct si_context
*)ctx
;
97 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
98 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
99 unsigned old_num_targets
= sctx
->streamout
.num_targets
;
102 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
103 if (sctx
->streamout
.num_targets
&& sctx
->streamout
.begin_emitted
) {
104 /* Since streamout uses vector writes which go through TC L2
105 * and most other clients can use TC L2 as well, we don't need
108 * The only cases which requires flushing it is VGT DMA index
109 * fetching (on <= CIK) and indirect draw data, which are rare
110 * cases. Thus, flag the TC L2 dirtiness in the resource and
111 * handle it at draw call time.
113 for (i
= 0; i
< sctx
->streamout
.num_targets
; i
++)
114 if (sctx
->streamout
.targets
[i
])
115 r600_resource(sctx
->streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
117 /* Invalidate the scalar cache in case a streamout buffer is
118 * going to be used as a constant buffer.
120 * Invalidate TC L1, because streamout bypasses it (done by
121 * setting GLC=1 in the store instruction), but it can contain
122 * outdated data of streamout buffers.
124 * VS_PARTIAL_FLUSH is required if the buffers are going to be
125 * used as an input immediately.
127 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
128 SI_CONTEXT_INV_VMEM_L1
|
129 SI_CONTEXT_VS_PARTIAL_FLUSH
;
132 /* All readers of the streamout targets need to be finished before we can
133 * start writing to the targets.
136 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
137 SI_CONTEXT_CS_PARTIAL_FLUSH
;
139 /* Streamout buffers must be bound in 2 places:
140 * 1) in VGT by setting the VGT_STRMOUT registers
141 * 2) as shader resources
144 /* Stop streamout. */
145 if (sctx
->streamout
.num_targets
&& sctx
->streamout
.begin_emitted
)
146 si_emit_streamout_end(sctx
);
148 /* Set the new targets. */
149 unsigned enabled_mask
= 0, append_bitmask
= 0;
150 for (i
= 0; i
< num_targets
; i
++) {
151 si_so_target_reference(&sctx
->streamout
.targets
[i
], targets
[i
]);
155 si_context_add_resource_size(ctx
, targets
[i
]->buffer
);
156 enabled_mask
|= 1 << i
;
158 if (offsets
[i
] == ((unsigned)-1))
159 append_bitmask
|= 1 << i
;
162 for (; i
< sctx
->streamout
.num_targets
; i
++)
163 si_so_target_reference(&sctx
->streamout
.targets
[i
], NULL
);
165 sctx
->streamout
.enabled_mask
= enabled_mask
;
166 sctx
->streamout
.num_targets
= num_targets
;
167 sctx
->streamout
.append_bitmask
= append_bitmask
;
169 /* Update dirty state bits. */
171 si_streamout_buffers_dirty(sctx
);
173 si_set_atom_dirty(sctx
, &sctx
->streamout
.begin_atom
, false);
174 si_set_streamout_enable(sctx
, false);
177 /* Set the shader resources.*/
178 for (i
= 0; i
< num_targets
; i
++) {
179 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
182 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
183 uint64_t va
= r600_resource(buffer
)->gpu_address
;
185 /* Set the descriptor.
187 * On VI, the format must be non-INVALID, otherwise
188 * the buffer will be considered not bound and store
189 * instructions will be no-ops.
191 uint32_t *desc
= descs
->list
+ bufidx
*4;
193 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
194 desc
[2] = 0xffffffff;
195 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
196 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
197 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
198 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
199 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
201 /* Set the resource. */
202 pipe_resource_reference(&buffers
->buffers
[bufidx
],
204 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
205 (struct r600_resource
*)buffer
,
206 buffers
->shader_usage
,
207 RADEON_PRIO_SHADER_RW_BUFFER
,
209 r600_resource(buffer
)->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
211 buffers
->enabled_mask
|= 1u << bufidx
;
213 /* Clear the descriptor and unset the resource. */
214 memset(descs
->list
+ bufidx
*4, 0,
215 sizeof(uint32_t) * 4);
216 pipe_resource_reference(&buffers
->buffers
[bufidx
],
218 buffers
->enabled_mask
&= ~(1u << bufidx
);
221 for (; i
< old_num_targets
; i
++) {
222 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
223 /* Clear the descriptor and unset the resource. */
224 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
225 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
226 buffers
->enabled_mask
&= ~(1u << bufidx
);
229 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
232 static void si_flush_vgt_streamout(struct si_context
*sctx
)
234 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
235 unsigned reg_strmout_cntl
;
237 /* The register is at different places on different ASICs. */
238 if (sctx
->b
.chip_class
>= CIK
) {
239 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
240 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
242 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
243 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
246 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
247 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
249 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
250 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
251 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
253 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
254 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
255 radeon_emit(cs
, 4); /* poll interval */
258 static void si_emit_streamout_begin(struct si_context
*sctx
, struct r600_atom
*atom
)
260 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
261 struct si_streamout_target
**t
= sctx
->streamout
.targets
;
262 uint16_t *stride_in_dw
= sctx
->streamout
.stride_in_dw
;
265 si_flush_vgt_streamout(sctx
);
267 for (i
= 0; i
< sctx
->streamout
.num_targets
; i
++) {
271 t
[i
]->stride_in_dw
= stride_in_dw
[i
];
273 /* SI binds streamout buffers as shader resources.
274 * VGT only counts primitives and tells the shader
275 * through SGPRs what to do. */
276 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
277 radeon_emit(cs
, (t
[i
]->b
.buffer_offset
+
278 t
[i
]->b
.buffer_size
) >> 2); /* BUFFER_SIZE (in DW) */
279 radeon_emit(cs
, stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
281 if (sctx
->streamout
.append_bitmask
& (1 << i
) && t
[i
]->buf_filled_size_valid
) {
282 uint64_t va
= t
[i
]->buf_filled_size
->gpu_address
+
283 t
[i
]->buf_filled_size_offset
;
286 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
287 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
288 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
289 radeon_emit(cs
, 0); /* unused */
290 radeon_emit(cs
, 0); /* unused */
291 radeon_emit(cs
, va
); /* src address lo */
292 radeon_emit(cs
, va
>> 32); /* src address hi */
294 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
295 t
[i
]->buf_filled_size
,
297 RADEON_PRIO_SO_FILLED_SIZE
);
299 /* Start from the beginning. */
300 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
301 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
302 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
303 radeon_emit(cs
, 0); /* unused */
304 radeon_emit(cs
, 0); /* unused */
305 radeon_emit(cs
, t
[i
]->b
.buffer_offset
>> 2); /* buffer offset in DW */
306 radeon_emit(cs
, 0); /* unused */
310 sctx
->streamout
.begin_emitted
= true;
313 void si_emit_streamout_end(struct si_context
*sctx
)
315 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
316 struct si_streamout_target
**t
= sctx
->streamout
.targets
;
320 si_flush_vgt_streamout(sctx
);
322 for (i
= 0; i
< sctx
->streamout
.num_targets
; i
++) {
326 va
= t
[i
]->buf_filled_size
->gpu_address
+ t
[i
]->buf_filled_size_offset
;
327 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
328 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
329 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
330 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
331 radeon_emit(cs
, va
); /* dst address lo */
332 radeon_emit(cs
, va
>> 32); /* dst address hi */
333 radeon_emit(cs
, 0); /* unused */
334 radeon_emit(cs
, 0); /* unused */
336 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
337 t
[i
]->buf_filled_size
,
339 RADEON_PRIO_SO_FILLED_SIZE
);
341 /* Zero the buffer size. The counters (primitives generated,
342 * primitives emitted) may be enabled even if there is not
343 * buffer bound. This ensures that the primitives-emitted query
344 * won't increment. */
345 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
347 t
[i
]->buf_filled_size_valid
= true;
350 sctx
->streamout
.begin_emitted
= false;
353 /* STREAMOUT CONFIG DERIVED STATE
355 * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
356 * The buffer mask is an independent state, so no writes occur if there
357 * are no buffers bound.
360 static void si_emit_streamout_enable(struct si_context
*sctx
,
361 struct r600_atom
*atom
)
363 radeon_set_context_reg_seq(sctx
->b
.gfx_cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
364 radeon_emit(sctx
->b
.gfx_cs
,
365 S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx
)) |
366 S_028B94_RAST_STREAM(0) |
367 S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx
)) |
368 S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx
)) |
369 S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx
)));
370 radeon_emit(sctx
->b
.gfx_cs
,
371 sctx
->streamout
.hw_enabled_mask
&
372 sctx
->streamout
.enabled_stream_buffers_mask
);
375 static void si_set_streamout_enable(struct si_context
*sctx
, bool enable
)
377 bool old_strmout_en
= si_get_strmout_en(sctx
);
378 unsigned old_hw_enabled_mask
= sctx
->streamout
.hw_enabled_mask
;
380 sctx
->streamout
.streamout_enabled
= enable
;
382 sctx
->streamout
.hw_enabled_mask
= sctx
->streamout
.enabled_mask
|
383 (sctx
->streamout
.enabled_mask
<< 4) |
384 (sctx
->streamout
.enabled_mask
<< 8) |
385 (sctx
->streamout
.enabled_mask
<< 12);
387 if ((old_strmout_en
!= si_get_strmout_en(sctx
)) ||
388 (old_hw_enabled_mask
!= sctx
->streamout
.hw_enabled_mask
))
389 si_mark_atom_dirty(sctx
, &sctx
->streamout
.enable_atom
);
392 void si_update_prims_generated_query_state(struct si_context
*sctx
,
393 unsigned type
, int diff
)
395 if (type
== PIPE_QUERY_PRIMITIVES_GENERATED
) {
396 bool old_strmout_en
= si_get_strmout_en(sctx
);
398 sctx
->streamout
.num_prims_gen_queries
+= diff
;
399 assert(sctx
->streamout
.num_prims_gen_queries
>= 0);
401 sctx
->streamout
.prims_gen_query_enabled
=
402 sctx
->streamout
.num_prims_gen_queries
!= 0;
404 if (old_strmout_en
!= si_get_strmout_en(sctx
))
405 si_mark_atom_dirty(sctx
, &sctx
->streamout
.enable_atom
);
409 void si_init_streamout_functions(struct si_context
*sctx
)
411 sctx
->b
.b
.create_stream_output_target
= si_create_so_target
;
412 sctx
->b
.b
.stream_output_target_destroy
= si_so_target_destroy
;
413 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
414 sctx
->streamout
.begin_atom
.emit
= si_emit_streamout_begin
;
415 sctx
->streamout
.enable_atom
.emit
= si_emit_streamout_enable
;