src/gallium/drivers/radeonsi/si_state_viewport.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_build_pm4.h"
  26 #include "util/u_viewport.h"
  27 #include "tgsi/tgsi_scan.h"
  28
  29 #define SI_MAX_SCISSOR 16384
  30
  31 static void si_set_scissor_states(struct pipe_context *pctx,
  32                                   unsigned start_slot,
  33                                   unsigned num_scissors,
  34                                   const struct pipe_scissor_state *state)
  35 {
  36         struct si_context *ctx = (struct si_context *)pctx;
  37         int i;
  38
  39         for (i = 0; i < num_scissors; i++)
  40                 ctx->scissors.states[start_slot + i] = state[i];
  41
  42         if (!ctx->queued.named.rasterizer ||
  43             !ctx->queued.named.rasterizer->scissor_enable)
  44                 return;
  45
  46         ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
  47         si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
  48 }
  49
  50 /* Since the guard band disables clipping, we have to clip per-pixel
  51  * using a scissor.
  52  */
  53 static void si_get_scissor_from_viewport(struct si_context *ctx,
  54                                          const struct pipe_viewport_state *vp,
  55                                          struct si_signed_scissor *scissor)
  56 {
  57         float tmp, minx, miny, maxx, maxy;
  58
  59         /* Convert (-1, -1) and (1, 1) from clip space into window space. */
  60         minx = -vp->scale[0] + vp->translate[0];
  61         miny = -vp->scale[1] + vp->translate[1];
  62         maxx = vp->scale[0] + vp->translate[0];
  63         maxy = vp->scale[1] + vp->translate[1];
  64
  65         /* Handle inverted viewports. */
  66         if (minx > maxx) {
  67                 tmp = minx;
  68                 minx = maxx;
  69                 maxx = tmp;
  70         }
  71         if (miny > maxy) {
  72                 tmp = miny;
  73                 miny = maxy;
  74                 maxy = tmp;
  75         }
  76
  77         /* Convert to integer and round up the max bounds. */
  78         scissor->minx = minx;
  79         scissor->miny = miny;
  80         scissor->maxx = ceilf(maxx);
  81         scissor->maxy = ceilf(maxy);
  82 }
  83
  84 static void si_clamp_scissor(struct si_context *ctx,
  85                              struct pipe_scissor_state *out,
  86                              struct si_signed_scissor *scissor)
  87 {
  88         out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
  89         out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
  90         out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
  91         out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
  92 }
  93
  94 static void si_clip_scissor(struct pipe_scissor_state *out,
  95                             struct pipe_scissor_state *clip)
  96 {
  97         out->minx = MAX2(out->minx, clip->minx);
  98         out->miny = MAX2(out->miny, clip->miny);
  99         out->maxx = MIN2(out->maxx, clip->maxx);
 100         out->maxy = MIN2(out->maxy, clip->maxy);
 101 }
 102
 103 static void si_scissor_make_union(struct si_signed_scissor *out,
 104                                   struct si_signed_scissor *in)
 105 {
 106         out->minx = MIN2(out->minx, in->minx);
 107         out->miny = MIN2(out->miny, in->miny);
 108         out->maxx = MAX2(out->maxx, in->maxx);
 109         out->maxy = MAX2(out->maxy, in->maxy);
 110         out->quant_mode = MIN2(out->quant_mode, in->quant_mode);
 111 }
 112
 113 static void si_emit_one_scissor(struct si_context *ctx,
 114                                 struct radeon_cmdbuf *cs,
 115                                 struct si_signed_scissor *vp_scissor,
 116                                 struct pipe_scissor_state *scissor)
 117 {
 118         struct pipe_scissor_state final;
 119
 120         if (ctx->vs_disables_clipping_viewport) {
 121                 final.minx = final.miny = 0;
 122                 final.maxx = final.maxy = SI_MAX_SCISSOR;
 123         } else {
 124                 si_clamp_scissor(ctx, &final, vp_scissor);
 125         }
 126
 127         if (scissor)
 128                 si_clip_scissor(&final, scissor);
 129
 130         /* Workaround for a hw bug on SI that occurs when PA_SU_HARDWARE_-
 131          * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
 132          */
 133         if (ctx->chip_class == SI && (final.maxx == 0 || final.maxy == 0)) {
 134                 radeon_emit(cs, S_028250_TL_X(1) |
 135                                 S_028250_TL_Y(1) |
 136                                 S_028250_WINDOW_OFFSET_DISABLE(1));
 137                 radeon_emit(cs, S_028254_BR_X(1) |
 138                                 S_028254_BR_Y(1));
 139                 return;
 140         }
 141
 142         radeon_emit(cs, S_028250_TL_X(final.minx) |
 143                         S_028250_TL_Y(final.miny) |
 144                         S_028250_WINDOW_OFFSET_DISABLE(1));
 145         radeon_emit(cs, S_028254_BR_X(final.maxx) |
 146                         S_028254_BR_Y(final.maxy));
 147 }
 148
 149 static void si_emit_guardband(struct si_context *ctx)
 150 {
 151         const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
 152         struct si_signed_scissor vp_as_scissor;
 153         struct pipe_viewport_state vp;
 154         float left, top, right, bottom, max_range, guardband_x, guardband_y;
 155         float discard_x, discard_y;
 156
 157         if (ctx->vs_writes_viewport_index) {
 158                 /* Shaders can draw to any viewport. Make a union of all
 159                  * viewports. */
 160                 vp_as_scissor = ctx->viewports.as_scissor[0];
 161                 for (unsigned i = 1; i < SI_MAX_VIEWPORTS; i++) {
 162                         si_scissor_make_union(&vp_as_scissor,
 163                                               &ctx->viewports.as_scissor[i]);
 164                 }
 165         } else {
 166                 vp_as_scissor = ctx->viewports.as_scissor[0];
 167         }
 168
 169         /* Blits don't set the viewport state. The vertex shader determines
 170          * the viewport size by scaling the coordinates, so we don't know
 171          * how large the viewport is. Assume the worst case.
 172          */
 173         if (ctx->vs_disables_clipping_viewport)
 174                 vp_as_scissor.quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
 175
 176         /* Determine the optimal hardware screen offset to center the viewport
 177          * within the viewport range in order to maximize the guardband size.
 178          */
 179         int hw_screen_offset_x = (vp_as_scissor.maxx + vp_as_scissor.minx) / 2;
 180         int hw_screen_offset_y = (vp_as_scissor.maxy + vp_as_scissor.miny) / 2;
 181
 182         const unsigned hw_screen_offset_max = 8176;
 183         /* SI-CI need to align the offset to an ubertile consisting of all SEs. */
 184         const unsigned hw_screen_offset_alignment =
 185                 ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
 186
 187         hw_screen_offset_x = CLAMP(hw_screen_offset_x, 0, hw_screen_offset_max);
 188         hw_screen_offset_y = CLAMP(hw_screen_offset_y, 0, hw_screen_offset_max);
 189
 190         /* Align the screen offset by dropping the low 4 bits. */
 191         hw_screen_offset_x &= ~(hw_screen_offset_alignment - 1);
 192         hw_screen_offset_y &= ~(hw_screen_offset_alignment - 1);
 193
 194         /* Apply the offset to center the viewport and maximize the guardband. */
 195         vp_as_scissor.minx -= hw_screen_offset_x;
 196         vp_as_scissor.maxx -= hw_screen_offset_x;
 197         vp_as_scissor.miny -= hw_screen_offset_y;
 198         vp_as_scissor.maxy -= hw_screen_offset_y;
 199
 200         /* Reconstruct the viewport transformation from the scissor. */
 201         vp.translate[0] = (vp_as_scissor.minx + vp_as_scissor.maxx) / 2.0;
 202         vp.translate[1] = (vp_as_scissor.miny + vp_as_scissor.maxy) / 2.0;
 203         vp.scale[0] = vp_as_scissor.maxx - vp.translate[0];
 204         vp.scale[1] = vp_as_scissor.maxy - vp.translate[1];
 205
 206         /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
 207         if (vp_as_scissor.minx == vp_as_scissor.maxx)
 208                 vp.scale[0] = 0.5;
 209         if (vp_as_scissor.miny == vp_as_scissor.maxy)
 210                 vp.scale[1] = 0.5;
 211
 212         /* Find the biggest guard band that is inside the supported viewport
 213          * range. The guard band is specified as a horizontal and vertical
 214          * distance from (0,0) in clip space.
 215          *
 216          * This is done by applying the inverse viewport transformation
 217          * on the viewport limits to get those limits in clip space.
 218          *
 219          * The viewport range is [-max_viewport_size/2, max_viewport_size/2].
 220          */
 221         static unsigned max_viewport_size[] = {65535, 16383, 4095};
 222         assert(vp_as_scissor.quant_mode < ARRAY_SIZE(max_viewport_size));
 223         max_range = max_viewport_size[vp_as_scissor.quant_mode] / 2;
 224         left   = (-max_range - vp.translate[0]) / vp.scale[0];
 225         right  = ( max_range - vp.translate[0]) / vp.scale[0];
 226         top    = (-max_range - vp.translate[1]) / vp.scale[1];
 227         bottom = ( max_range - vp.translate[1]) / vp.scale[1];
 228
 229         assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
 230
 231         guardband_x = MIN2(-left, right);
 232         guardband_y = MIN2(-top, bottom);
 233
 234         discard_x = 1.0;
 235         discard_y = 1.0;
 236
 237         if (unlikely(util_prim_is_points_or_lines(ctx->current_rast_prim))) {
 238                 /* When rendering wide points or lines, we need to be more
 239                  * conservative about when to discard them entirely. */
 240                 float pixels;
 241
 242                 if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
 243                         pixels = rs->max_point_size;
 244                 else
 245                         pixels = rs->line_width;
 246
 247                 /* Add half the point size / line width */
 248                 discard_x += pixels / (2.0 * vp.scale[0]);
 249                 discard_y += pixels / (2.0 * vp.scale[1]);
 250
 251                 /* Discard primitives that would lie entirely outside the clip
 252                  * region. */
 253                 discard_x = MIN2(discard_x, guardband_x);
 254                 discard_y = MIN2(discard_y, guardband_y);
 255         }
 256
 257         /* If any of the GB registers is updated, all of them must be updated.
 258          * R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
 259          * R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
 260          */
 261         unsigned initial_cdw = ctx->gfx_cs->current.cdw;
 262         radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
 263                                     SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ,
 264                                     fui(guardband_y), fui(discard_y),
 265                                     fui(guardband_x), fui(discard_x));
 266         radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
 267                                    SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
 268                                    S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x >> 4) |
 269                                    S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
 270         radeon_opt_set_context_reg(ctx, R_028BE4_PA_SU_VTX_CNTL,
 271                                    SI_TRACKED_PA_SU_VTX_CNTL,
 272                                    S_028BE4_PIX_CENTER(rs->half_pixel_center) |
 273                                    S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
 274                                                        vp_as_scissor.quant_mode));
 275         if (initial_cdw != ctx->gfx_cs->current.cdw)
 276                 ctx->context_roll_counter++;
 277 }
 278
 279 static void si_emit_scissors(struct si_context *ctx)
 280 {
 281         struct radeon_cmdbuf *cs = ctx->gfx_cs;
 282         struct pipe_scissor_state *states = ctx->scissors.states;
 283         unsigned mask = ctx->scissors.dirty_mask;
 284         bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
 285
 286         /* The simple case: Only 1 viewport is active. */
 287         if (!ctx->vs_writes_viewport_index) {
 288                 struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
 289
 290                 if (!(mask & 1))
 291                         return;
 292
 293                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
 294                 si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
 295                 ctx->scissors.dirty_mask &= ~1; /* clear one bit */
 296                 return;
 297         }
 298
 299         while (mask) {
 300                 int start, count, i;
 301
 302                 u_bit_scan_consecutive_range(&mask, &start, &count);
 303
 304                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
 305                                                start * 4 * 2, count * 2);
 306                 for (i = start; i < start+count; i++) {
 307                         si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
 308                                             scissor_enabled ? &states[i] : NULL);
 309                 }
 310         }
 311         ctx->scissors.dirty_mask = 0;
 312 }
 313
 314 static void si_set_viewport_states(struct pipe_context *pctx,
 315                                    unsigned start_slot,
 316                                    unsigned num_viewports,
 317                                    const struct pipe_viewport_state *state)
 318 {
 319         struct si_context *ctx = (struct si_context *)pctx;
 320         unsigned mask;
 321         int i;
 322
 323         for (i = 0; i < num_viewports; i++) {
 324                 unsigned index = start_slot + i;
 325                 struct si_signed_scissor *scissor = &ctx->viewports.as_scissor[index];
 326
 327                 ctx->viewports.states[index] = state[i];
 328
 329                 si_get_scissor_from_viewport(ctx, &state[i], scissor);
 330
 331                 unsigned w = scissor->maxx - scissor->minx;
 332                 unsigned h = scissor->maxy - scissor->miny;
 333                 unsigned max_extent = MAX2(w, h);
 334
 335                 /* Determine the best quantization mode (subpixel precision),
 336                  * but also leave enough space for the guardband.
 337                  *
 338                  * Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
 339                  * and Raven1. What we do depends on the chip:
 340                  * - Vega10: Never use primitive binning.
 341                  * - Raven1: Always use QUANT_MODE == 16_8.
 342                  */
 343                 if (ctx->family == CHIP_RAVEN)
 344                         max_extent = 16384; /* Use QUANT_MODE == 16_8. */
 345
 346                 if (max_extent <= 1024) /* 4K scanline area for guardband */
 347                         scissor->quant_mode = SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
 348                 else if (max_extent <= 4096) /* 16K scanline area for guardband */
 349                         scissor->quant_mode = SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
 350                 else /* 64K scanline area for guardband */
 351                         scissor->quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
 352         }
 353
 354         mask = ((1 << num_viewports) - 1) << start_slot;
 355         ctx->viewports.dirty_mask |= mask;
 356         ctx->viewports.depth_range_dirty_mask |= mask;
 357         ctx->scissors.dirty_mask |= mask;
 358         si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 359         si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
 360         si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 361 }
 362
 363 static void si_emit_one_viewport(struct si_context *ctx,
 364                                  struct pipe_viewport_state *state)
 365 {
 366         struct radeon_cmdbuf *cs = ctx->gfx_cs;
 367
 368         radeon_emit(cs, fui(state->scale[0]));
 369         radeon_emit(cs, fui(state->translate[0]));
 370         radeon_emit(cs, fui(state->scale[1]));
 371         radeon_emit(cs, fui(state->translate[1]));
 372         radeon_emit(cs, fui(state->scale[2]));
 373         radeon_emit(cs, fui(state->translate[2]));
 374 }
 375
 376 static void si_emit_viewports(struct si_context *ctx)
 377 {
 378         struct radeon_cmdbuf *cs = ctx->gfx_cs;
 379         struct pipe_viewport_state *states = ctx->viewports.states;
 380         unsigned mask = ctx->viewports.dirty_mask;
 381
 382         /* The simple case: Only 1 viewport is active. */
 383         if (!ctx->vs_writes_viewport_index) {
 384                 if (!(mask & 1))
 385                         return;
 386
 387                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
 388                 si_emit_one_viewport(ctx, &states[0]);
 389                 ctx->viewports.dirty_mask &= ~1; /* clear one bit */
 390                 return;
 391         }
 392
 393         while (mask) {
 394                 int start, count, i;
 395
 396                 u_bit_scan_consecutive_range(&mask, &start, &count);
 397
 398                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
 399                                                start * 4 * 6, count * 6);
 400                 for (i = start; i < start+count; i++)
 401                         si_emit_one_viewport(ctx, &states[i]);
 402         }
 403         ctx->viewports.dirty_mask = 0;
 404 }
 405
 406 static inline void
 407 si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
 408                       bool window_space_position, float *zmin, float *zmax)
 409 {
 410         if (window_space_position) {
 411                 *zmin = 0;
 412                 *zmax = 1;
 413                 return;
 414         }
 415         util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
 416 }
 417
 418 static void si_emit_depth_ranges(struct si_context *ctx)
 419 {
 420         struct radeon_cmdbuf *cs = ctx->gfx_cs;
 421         struct pipe_viewport_state *states = ctx->viewports.states;
 422         unsigned mask = ctx->viewports.depth_range_dirty_mask;
 423         bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
 424         bool window_space = ctx->vs_disables_clipping_viewport;
 425         float zmin, zmax;
 426
 427         /* The simple case: Only 1 viewport is active. */
 428         if (!ctx->vs_writes_viewport_index) {
 429                 if (!(mask & 1))
 430                         return;
 431
 432                 si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
 433                                       &zmin, &zmax);
 434
 435                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
 436                 radeon_emit(cs, fui(zmin));
 437                 radeon_emit(cs, fui(zmax));
 438                 ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
 439                 return;
 440         }
 441
 442         while (mask) {
 443                 int start, count, i;
 444
 445                 u_bit_scan_consecutive_range(&mask, &start, &count);
 446
 447                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
 448                                            start * 4 * 2, count * 2);
 449                 for (i = start; i < start+count; i++) {
 450                         si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
 451                                               &zmin, &zmax);
 452                         radeon_emit(cs, fui(zmin));
 453                         radeon_emit(cs, fui(zmax));
 454                 }
 455         }
 456         ctx->viewports.depth_range_dirty_mask = 0;
 457 }
 458
 459 static void si_emit_viewport_states(struct si_context *ctx)
 460 {
 461         si_emit_viewports(ctx);
 462         si_emit_depth_ranges(ctx);
 463 }
 464
 465 /**
 466  * This reacts to 2 state changes:
 467  * - VS.writes_viewport_index
 468  * - VS output position in window space (enable/disable)
 469  *
 470  * Normally, we only emit 1 viewport and 1 scissor if no shader is using
 471  * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
 472  * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
 473  * called to emit the rest.
 474  */
 475 void si_update_vs_viewport_state(struct si_context *ctx)
 476 {
 477         struct tgsi_shader_info *info = si_get_vs_info(ctx);
 478         bool vs_window_space;
 479
 480         if (!info)
 481                 return;
 482
 483         /* When the VS disables clipping and viewport transformation. */
 484         vs_window_space =
 485                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 486
 487         if (ctx->vs_disables_clipping_viewport != vs_window_space) {
 488                 ctx->vs_disables_clipping_viewport = vs_window_space;
 489                 ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 490                 ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 491                 si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 492                 si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 493         }
 494
 495         /* Viewport index handling. */
 496         if (ctx->vs_writes_viewport_index == info->writes_viewport_index)
 497                 return;
 498
 499         /* This changes how the guardband is computed. */
 500         ctx->vs_writes_viewport_index = info->writes_viewport_index;
 501         si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
 502
 503         if (!ctx->vs_writes_viewport_index)
 504                 return;
 505
 506         if (ctx->scissors.dirty_mask)
 507             si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 508
 509         if (ctx->viewports.dirty_mask ||
 510             ctx->viewports.depth_range_dirty_mask)
 511             si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 512 }
 513
 514 static void si_emit_window_rectangles(struct si_context *sctx)
 515 {
 516         /* There are four clipping rectangles. Their corner coordinates are inclusive.
 517          * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
 518          * on whether the pixel is inside cliprects 0-3, respectively. For example,
 519          * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
 520          * the number 3 (binary 0011).
 521          *
 522          * If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
 523          */
 524         struct radeon_cmdbuf *cs = sctx->gfx_cs;
 525         static const unsigned outside[4] = {
 526                 /* outside rectangle 0 */
 527                 V_02820C_OUT |
 528                 V_02820C_IN_1 |
 529                 V_02820C_IN_2 |
 530                 V_02820C_IN_21 |
 531                 V_02820C_IN_3 |
 532                 V_02820C_IN_31 |
 533                 V_02820C_IN_32 |
 534                 V_02820C_IN_321,
 535                 /* outside rectangles 0, 1 */
 536                 V_02820C_OUT |
 537                 V_02820C_IN_2 |
 538                 V_02820C_IN_3 |
 539                 V_02820C_IN_32,
 540                 /* outside rectangles 0, 1, 2 */
 541                 V_02820C_OUT |
 542                 V_02820C_IN_3,
 543                 /* outside rectangles 0, 1, 2, 3 */
 544                 V_02820C_OUT,
 545         };
 546         const unsigned disabled = 0xffff; /* all inside and outside cases */
 547         unsigned num_rectangles = sctx->num_window_rectangles;
 548         struct pipe_scissor_state *rects = sctx->window_rectangles;
 549         unsigned rule;
 550
 551         assert(num_rectangles <= 4);
 552
 553         if (num_rectangles == 0)
 554                 rule = disabled;
 555         else if (sctx->window_rectangles_include)
 556                 rule = ~outside[num_rectangles - 1];
 557         else
 558                 rule = outside[num_rectangles - 1];
 559
 560         radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE,
 561                                    SI_TRACKED_PA_SC_CLIPRECT_RULE, rule);
 562         if (num_rectangles == 0)
 563                 return;
 564
 565         radeon_set_context_reg_seq(cs, R_028210_PA_SC_CLIPRECT_0_TL,
 566                                    num_rectangles * 2);
 567         for (unsigned i = 0; i < num_rectangles; i++) {
 568                 radeon_emit(cs, S_028210_TL_X(rects[i].minx) |
 569                                 S_028210_TL_Y(rects[i].miny));
 570                 radeon_emit(cs, S_028214_BR_X(rects[i].maxx) |
 571                                 S_028214_BR_Y(rects[i].maxy));
 572         }
 573 }
 574
 575 static void si_set_window_rectangles(struct pipe_context *ctx,
 576                                      boolean include,
 577                                      unsigned num_rectangles,
 578                                      const struct pipe_scissor_state *rects)
 579 {
 580         struct si_context *sctx = (struct si_context *)ctx;
 581
 582         sctx->num_window_rectangles = num_rectangles;
 583         sctx->window_rectangles_include = include;
 584         if (num_rectangles) {
 585                 memcpy(sctx->window_rectangles, rects,
 586                        sizeof(*rects) * num_rectangles);
 587         }
 588
 589         si_mark_atom_dirty(sctx, &sctx->atoms.s.window_rectangles);
 590 }
 591
 592 void si_init_viewport_functions(struct si_context *ctx)
 593 {
 594         ctx->atoms.s.guardband.emit = si_emit_guardband;
 595         ctx->atoms.s.scissors.emit = si_emit_scissors;
 596         ctx->atoms.s.viewports.emit = si_emit_viewport_states;
 597         ctx->atoms.s.window_rectangles.emit = si_emit_window_rectangles;
 598
 599         ctx->b.set_scissor_states = si_set_scissor_states;
 600         ctx->b.set_viewport_states = si_set_viewport_states;
 601         ctx->b.set_window_rectangles = si_set_window_rectangles;
 602
 603         for (unsigned i = 0; i < 16; i++)
 604                 ctx->viewports.as_scissor[i].quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
 605 }