2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "state_tracker/drm_driver.h"
31 #include "util/format/u_format.h"
32 #include "util/os_time.h"
33 #include "util/u_log.h"
34 #include "util/u_memory.h"
35 #include "util/u_pack_color.h"
36 #include "util/u_resource.h"
37 #include "util/u_surface.h"
38 #include "util/u_transfer.h"
43 #include "amd/addrlib/inc/addrinterface.h"
45 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
46 const struct pipe_resource
*templ
,
47 bool tc_compatible_htile
);
49 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
50 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
51 unsigned src_level
, const struct pipe_box
*src_box
)
56 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (src
->buffer
.b
.b
.nr_samples
> 1 || dst
->buffer
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (src
->is_depth
|| dst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(src
, src_level
) || vi_dcc_enabled(dst
, dst_level
))
78 * src: Both texture and SDMA paths need decompression. Use SDMA.
79 * dst: If overwriting the whole texture, discard CMASK and use
80 * SDMA. Otherwise, use the 3D path.
82 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
83 /* The CMASK clear is only enabled for the first level. */
84 assert(dst_level
== 0);
85 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
, dstx
, dsty
, dstz
,
86 src_box
->width
, src_box
->height
, src_box
->depth
))
89 si_texture_discard_cmask(sctx
->screen
, dst
);
92 /* All requirements are met. Prepare textures for SDMA. */
93 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
94 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
96 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
97 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
102 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
103 static void si_copy_region_with_blit(struct pipe_context
*pipe
, struct pipe_resource
*dst
,
104 unsigned dst_level
, unsigned dstx
, unsigned dsty
,
105 unsigned dstz
, struct pipe_resource
*src
, unsigned src_level
,
106 const struct pipe_box
*src_box
)
108 struct pipe_blit_info blit
;
110 memset(&blit
, 0, sizeof(blit
));
111 blit
.src
.resource
= src
;
112 blit
.src
.format
= src
->format
;
113 blit
.src
.level
= src_level
;
114 blit
.src
.box
= *src_box
;
115 blit
.dst
.resource
= dst
;
116 blit
.dst
.format
= dst
->format
;
117 blit
.dst
.level
= dst_level
;
118 blit
.dst
.box
.x
= dstx
;
119 blit
.dst
.box
.y
= dsty
;
120 blit
.dst
.box
.z
= dstz
;
121 blit
.dst
.box
.width
= src_box
->width
;
122 blit
.dst
.box
.height
= src_box
->height
;
123 blit
.dst
.box
.depth
= src_box
->depth
;
124 blit
.mask
= util_format_get_mask(dst
->format
);
125 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
128 pipe
->blit(pipe
, &blit
);
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
135 struct si_context
*sctx
= (struct si_context
*)ctx
;
136 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
137 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
138 struct pipe_resource
*src
= transfer
->resource
;
140 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
141 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
145 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
148 /* Copy from a transfer's staging texture to a full GPU one. */
149 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
151 struct si_context
*sctx
= (struct si_context
*)ctx
;
152 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
153 struct pipe_resource
*dst
= transfer
->resource
;
154 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
155 struct pipe_box sbox
;
157 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
159 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
160 si_copy_region_with_blit(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
,
161 transfer
->box
.z
, src
, 0, &sbox
);
165 if (util_format_is_compressed(dst
->format
)) {
166 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
167 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
170 sctx
->dma_copy(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
, src
,
174 static unsigned si_texture_get_offset(struct si_screen
*sscreen
, struct si_texture
*tex
,
175 unsigned level
, const struct pipe_box
*box
, unsigned *stride
,
176 unsigned *layer_stride
)
178 if (sscreen
->info
.chip_class
>= GFX9
) {
179 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
180 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
185 /* Each texture is an array of slices. Each slice is an array
186 * of mipmap levels. */
187 return tex
->surface
.u
.gfx9
.surf_offset
+ box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
188 tex
->surface
.u
.gfx9
.offset
[level
] +
189 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.gfx9
.surf_pitch
+
190 box
->x
/ tex
->surface
.blk_w
) *
193 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
* tex
->surface
.bpe
;
194 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
195 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
198 return tex
->surface
.u
.legacy
.level
[level
].offset
;
200 /* Each texture is an array of mipmap levels. Each level is
201 * an array of slices. */
202 return tex
->surface
.u
.legacy
.level
[level
].offset
+
203 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
204 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
205 box
->x
/ tex
->surface
.blk_w
) *
210 static int si_init_surface(struct si_screen
*sscreen
, struct radeon_surf
*surface
,
211 const struct pipe_resource
*ptex
, enum radeon_surf_mode array_mode
,
212 bool is_imported
, bool is_scanout
, bool is_flushed_depth
,
213 bool tc_compatible_htile
)
215 const struct util_format_description
*desc
= util_format_description(ptex
->format
);
216 bool is_depth
, is_stencil
;
218 unsigned bpe
, flags
= 0;
220 is_depth
= util_format_has_depth(desc
);
221 is_stencil
= util_format_has_stencil(desc
);
223 if (!is_flushed_depth
&& ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
224 bpe
= 4; /* stencil is allocated separately */
226 bpe
= util_format_get_blocksize(ptex
->format
);
227 assert(util_is_power_of_two_or_zero(bpe
));
230 if (!is_flushed_depth
&& is_depth
) {
231 flags
|= RADEON_SURF_ZBUFFER
;
233 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
234 flags
|= RADEON_SURF_NO_HTILE
;
235 } else if (tc_compatible_htile
&&
236 (sscreen
->info
.chip_class
>= GFX9
|| array_mode
== RADEON_SURF_MODE_2D
)) {
237 /* TC-compatible HTILE only supports Z32_FLOAT.
238 * GFX9 also supports Z16_UNORM.
239 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
240 * the format for transfers.
242 if (sscreen
->info
.chip_class
== GFX8
)
245 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
249 flags
|= RADEON_SURF_SBUFFER
;
252 if (sscreen
->info
.chip_class
>= GFX8
&&
253 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
|| ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
254 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
255 flags
|= RADEON_SURF_DISABLE_DCC
;
257 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
258 if (sscreen
->info
.family
== CHIP_STONEY
&& bpe
== 16 && ptex
->nr_samples
>= 2)
259 flags
|= RADEON_SURF_DISABLE_DCC
;
261 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
262 if (sscreen
->info
.chip_class
== GFX8
&& ptex
->nr_storage_samples
>= 4 && ptex
->array_size
> 1)
263 flags
|= RADEON_SURF_DISABLE_DCC
;
265 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
266 if (sscreen
->info
.chip_class
== GFX9
&&
267 (ptex
->nr_storage_samples
>= 4 ||
268 (sscreen
->info
.family
== CHIP_RAVEN
&& ptex
->nr_storage_samples
>= 2 && bpe
< 4)))
269 flags
|= RADEON_SURF_DISABLE_DCC
;
271 /* TODO: GFX10: DCC causes corruption with MSAA. */
272 if (sscreen
->info
.chip_class
>= GFX10
&& ptex
->nr_storage_samples
>= 2)
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 /* Shared textures must always set up DCC.
276 * If it's not present, it will be disabled by
277 * si_get_opaque_metadata later.
279 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
280 flags
|= RADEON_SURF_DISABLE_DCC
;
283 /* This should catch bugs in gallium users setting incorrect flags. */
284 assert(ptex
->nr_samples
<= 1 && ptex
->array_size
== 1 && ptex
->depth0
== 1 &&
285 ptex
->last_level
== 0 && !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
287 flags
|= RADEON_SURF_SCANOUT
;
290 if (ptex
->bind
& PIPE_BIND_SHARED
)
291 flags
|= RADEON_SURF_SHAREABLE
;
293 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
294 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
295 flags
|= RADEON_SURF_NO_FMASK
;
297 if (sscreen
->info
.chip_class
== GFX9
&& (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
)) {
298 flags
|= RADEON_SURF_FORCE_MICRO_TILE_MODE
;
299 surface
->micro_tile_mode
= SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex
->flags
);
302 if (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
) {
303 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
305 if (sscreen
->info
.chip_class
>= GFX10
)
306 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
309 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
, array_mode
, surface
);
317 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
)
319 struct si_screen
*sscreen
= sctx
->screen
;
320 struct pipe_context
*ctx
= &sctx
->b
;
322 if (ctx
== sscreen
->aux_context
)
323 simple_mtx_lock(&sscreen
->aux_context_lock
);
325 unsigned n
= sctx
->num_decompress_calls
;
326 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
328 /* Flush only if any fast clear elimination took place. */
329 if (n
!= sctx
->num_decompress_calls
)
330 ctx
->flush(ctx
, NULL
, 0);
332 if (ctx
== sscreen
->aux_context
)
333 simple_mtx_unlock(&sscreen
->aux_context_lock
);
336 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
)
338 if (!tex
->cmask_buffer
)
341 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
344 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
345 tex
->dirty_level_mask
= 0;
347 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
349 if (tex
->cmask_buffer
!= &tex
->buffer
)
350 si_resource_reference(&tex
->cmask_buffer
, NULL
);
352 tex
->cmask_buffer
= NULL
;
354 /* Notify all contexts about the change. */
355 p_atomic_inc(&sscreen
->dirty_tex_counter
);
356 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
359 static bool si_can_disable_dcc(struct si_texture
*tex
)
361 /* We can't disable DCC if it can be written by another process. */
362 return tex
->surface
.dcc_offset
&&
363 (!tex
->buffer
.b
.is_shared
||
364 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
367 static bool si_texture_discard_dcc(struct si_screen
*sscreen
, struct si_texture
*tex
)
369 if (!si_can_disable_dcc(tex
))
372 assert(tex
->dcc_separate_buffer
== NULL
);
375 ac_surface_zero_dcc_fields(&tex
->surface
);
377 /* Notify all contexts about the change. */
378 p_atomic_inc(&sscreen
->dirty_tex_counter
);
383 * Disable DCC for the texture. (first decompress, then discard metadata).
385 * There is unresolved multi-context synchronization issue between
386 * screen::aux_context and the current context. If applications do this with
387 * multiple contexts, it's already undefined behavior for them and we don't
388 * have to worry about that. The scenario is:
390 * If context 1 disables DCC and context 2 has queued commands that write
391 * to the texture via CB with DCC enabled, and the order of operations is
393 * context 2 queues draw calls rendering to the texture, but doesn't flush
394 * context 1 disables DCC and flushes
395 * context 1 & 2 reset descriptors and FB state
396 * context 2 flushes (new compressed tiles written by the draw calls)
397 * context 1 & 2 read garbage, because DCC is disabled, yet there are
400 * \param sctx the current context if you have one, or sscreen->aux_context
403 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
405 struct si_screen
*sscreen
= sctx
->screen
;
407 if (!sctx
->has_graphics
)
408 return si_texture_discard_dcc(sscreen
, tex
);
410 if (!si_can_disable_dcc(tex
))
413 if (&sctx
->b
== sscreen
->aux_context
)
414 simple_mtx_lock(&sscreen
->aux_context_lock
);
416 /* Decompress DCC. */
417 si_decompress_dcc(sctx
, tex
);
418 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
420 if (&sctx
->b
== sscreen
->aux_context
)
421 simple_mtx_unlock(&sscreen
->aux_context_lock
);
423 return si_texture_discard_dcc(sscreen
, tex
);
426 static void si_reallocate_texture_inplace(struct si_context
*sctx
, struct si_texture
*tex
,
427 unsigned new_bind_flag
, bool invalidate_storage
)
429 struct pipe_screen
*screen
= sctx
->b
.screen
;
430 struct si_texture
*new_tex
;
431 struct pipe_resource templ
= tex
->buffer
.b
.b
;
434 templ
.bind
|= new_bind_flag
;
436 if (tex
->buffer
.b
.is_shared
|| tex
->num_planes
> 1)
439 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
440 if (tex
->surface
.is_linear
)
443 /* This fails with MSAA, depth, and compressed textures. */
444 if (si_choose_tiling(sctx
->screen
, &templ
, false) != RADEON_SURF_MODE_LINEAR_ALIGNED
)
448 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
452 /* Copy the pixels to the new texture. */
453 if (!invalidate_storage
) {
454 for (i
= 0; i
<= templ
.last_level
; i
++) {
457 u_box_3d(0, 0, 0, u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
458 util_num_layers(&templ
, i
), &box
);
460 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0, &tex
->buffer
.b
.b
, i
, &box
);
464 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
465 si_texture_discard_cmask(sctx
->screen
, tex
);
466 si_texture_discard_dcc(sctx
->screen
, tex
);
469 /* Replace the structure fields of tex. */
470 tex
->buffer
.b
.b
.bind
= templ
.bind
;
471 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
472 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
473 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
474 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
475 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
476 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
477 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
478 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
480 tex
->surface
= new_tex
->surface
;
481 si_texture_reference(&tex
->flushed_depth_texture
, new_tex
->flushed_depth_texture
);
483 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
484 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
485 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
487 if (tex
->cmask_buffer
== &tex
->buffer
)
488 tex
->cmask_buffer
= NULL
;
490 si_resource_reference(&tex
->cmask_buffer
, NULL
);
492 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
493 tex
->cmask_buffer
= &tex
->buffer
;
495 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
497 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
498 tex
->cb_color_info
= new_tex
->cb_color_info
;
499 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
, sizeof(tex
->color_clear_value
));
500 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
502 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
503 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
504 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
505 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
506 tex
->db_render_format
= new_tex
->db_render_format
;
507 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
508 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
509 tex
->depth_cleared
= new_tex
->depth_cleared
;
510 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
511 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
512 tex
->db_compatible
= new_tex
->db_compatible
;
513 tex
->can_sample_z
= new_tex
->can_sample_z
;
514 tex
->can_sample_s
= new_tex
->can_sample_s
;
516 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
517 tex
->displayable_dcc_dirty
= new_tex
->displayable_dcc_dirty
;
518 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
519 si_resource_reference(&tex
->dcc_separate_buffer
, new_tex
->dcc_separate_buffer
);
520 si_resource_reference(&tex
->last_dcc_separate_buffer
, new_tex
->last_dcc_separate_buffer
);
522 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
523 assert(!tex
->surface
.htile_offset
);
524 assert(!tex
->cmask_buffer
);
525 assert(!tex
->surface
.fmask_size
);
526 assert(!tex
->surface
.dcc_offset
);
527 assert(!tex
->is_depth
);
530 si_texture_reference(&new_tex
, NULL
);
532 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
535 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
)
537 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
538 struct radeon_bo_metadata md
;
540 memset(&md
, 0, sizeof(md
));
542 assert(tex
->dcc_separate_buffer
== NULL
);
543 assert(tex
->surface
.fmask_size
== 0);
545 static const unsigned char swizzle
[] = {PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
, PIPE_SWIZZLE_Z
,
547 bool is_array
= util_texture_is_array(res
->target
);
550 sscreen
->make_texture_descriptor(sscreen
, tex
, true, res
->target
, res
->format
, swizzle
, 0,
551 res
->last_level
, 0, is_array
? res
->array_size
- 1 : 0,
552 res
->width0
, res
->height0
, res
->depth0
, desc
, NULL
);
553 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0], 0, 0,
554 tex
->surface
.blk_w
, false, false, desc
);
556 ac_surface_get_umd_metadata(&sscreen
->info
, &tex
->surface
,
557 tex
->buffer
.b
.b
.last_level
+ 1,
558 desc
, &md
.size_metadata
, md
.metadata
);
559 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
, &tex
->surface
);
562 static bool si_has_displayable_dcc(struct si_texture
*tex
)
564 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
566 if (sscreen
->info
.chip_class
<= GFX8
)
569 return tex
->surface
.is_displayable
&& tex
->surface
.dcc_offset
;
572 static bool si_resource_get_param(struct pipe_screen
*screen
, struct pipe_context
*context
,
573 struct pipe_resource
*resource
, unsigned plane
, unsigned layer
,
574 enum pipe_resource_param param
, unsigned handle_usage
,
577 for (unsigned i
= 0; i
< plane
; i
++)
578 resource
= resource
->next
;
580 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
581 struct si_texture
*tex
= (struct si_texture
*)resource
;
582 struct winsys_handle whandle
;
585 case PIPE_RESOURCE_PARAM_NPLANES
:
586 *value
= resource
->target
== PIPE_BUFFER
? 1 : tex
->num_planes
;
589 case PIPE_RESOURCE_PARAM_STRIDE
:
590 if (resource
->target
== PIPE_BUFFER
)
592 else if (sscreen
->info
.chip_class
>= GFX9
)
593 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
595 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
598 case PIPE_RESOURCE_PARAM_OFFSET
:
599 if (resource
->target
== PIPE_BUFFER
)
601 else if (sscreen
->info
.chip_class
>= GFX9
)
602 *value
= tex
->surface
.u
.gfx9
.surf_offset
+ layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
604 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
605 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
608 case PIPE_RESOURCE_PARAM_MODIFIER
:
609 *value
= DRM_FORMAT_MOD_INVALID
;
612 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
613 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
614 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
615 memset(&whandle
, 0, sizeof(whandle
));
617 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
618 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
619 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
620 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
621 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
622 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
624 if (!screen
->resource_get_handle(screen
, context
, resource
, &whandle
, handle_usage
))
627 *value
= whandle
.handle
;
633 static void si_texture_get_info(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
634 unsigned *pstride
, unsigned *poffset
)
639 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
644 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
649 static bool si_texture_get_handle(struct pipe_screen
*screen
, struct pipe_context
*ctx
,
650 struct pipe_resource
*resource
, struct winsys_handle
*whandle
,
653 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
654 struct si_context
*sctx
;
655 struct si_resource
*res
= si_resource(resource
);
656 struct si_texture
*tex
= (struct si_texture
*)resource
;
657 bool update_metadata
= false;
658 unsigned stride
, offset
, slice_size
;
661 ctx
= threaded_context_unwrap_sync(ctx
);
662 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
664 if (resource
->target
!= PIPE_BUFFER
) {
665 /* Individual planes are chained pipe_resource instances. */
666 for (unsigned i
= 0; i
< whandle
->plane
; i
++) {
667 resource
= resource
->next
;
668 res
= si_resource(resource
);
669 tex
= (struct si_texture
*)resource
;
672 /* This is not supported now, but it might be required for OpenCL
673 * interop in the future.
675 if (resource
->nr_samples
> 1 || tex
->is_depth
)
678 /* Move a suballocated texture into a non-suballocated allocation. */
679 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) || tex
->surface
.tile_swizzle
||
680 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
681 sscreen
->info
.has_local_buffers
)) {
682 assert(!res
->b
.is_shared
);
683 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_SHARED
, false);
685 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
686 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
687 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
688 assert(tex
->surface
.tile_swizzle
== 0);
691 /* Since shader image stores don't support DCC on GFX8,
692 * disable it for external clients that want write
695 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
696 /* Displayable DCC requires an explicit flush. */
697 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && si_has_displayable_dcc(tex
))) {
698 if (si_texture_disable_dcc(sctx
, tex
)) {
699 update_metadata
= true;
700 /* si_texture_disable_dcc flushes the context */
705 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
706 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
707 /* Eliminate fast clear (both CMASK and DCC) */
708 si_eliminate_fast_color_clear(sctx
, tex
);
709 /* eliminate_fast_color_clear flushes the context */
712 /* Disable CMASK if flush_resource isn't going
715 if (tex
->cmask_buffer
)
716 si_texture_discard_cmask(sscreen
, tex
);
720 if ((!res
->b
.is_shared
|| update_metadata
) && whandle
->offset
== 0)
721 si_set_tex_bo_metadata(sscreen
, tex
);
723 if (sscreen
->info
.chip_class
>= GFX9
) {
724 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
726 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
729 /* Buffer exports are for the OpenCL interop. */
730 /* Move a suballocated buffer into a non-suballocated allocation. */
731 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
732 /* A DMABUF export always fails if the BO is local. */
733 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
734 sscreen
->info
.has_local_buffers
)) {
735 assert(!res
->b
.is_shared
);
737 /* Allocate a new buffer with PIPE_BIND_SHARED. */
738 struct pipe_resource templ
= res
->b
.b
;
739 templ
.bind
|= PIPE_BIND_SHARED
;
741 struct pipe_resource
*newb
= screen
->resource_create(screen
, &templ
);
745 /* Copy the old buffer contents to the new one. */
747 u_box_1d(0, newb
->width0
, &box
);
748 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0, &res
->b
.b
, 0, &box
);
750 /* Move the new buffer storage to the old pipe_resource. */
751 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
752 pipe_resource_reference(&newb
, NULL
);
754 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
755 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
762 si_texture_get_info(screen
, resource
, &stride
, &offset
);
765 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
767 if (res
->b
.is_shared
) {
768 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
771 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
772 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
773 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
775 res
->b
.is_shared
= true;
776 res
->external_usage
= usage
;
779 whandle
->stride
= stride
;
780 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
782 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
785 static void si_texture_destroy(struct pipe_screen
*screen
, struct pipe_resource
*ptex
)
787 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
788 struct si_texture
*tex
= (struct si_texture
*)ptex
;
789 struct si_resource
*resource
= &tex
->buffer
;
791 if (sscreen
->info
.chip_class
>= GFX9
)
792 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
794 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
796 if (tex
->cmask_buffer
!= &tex
->buffer
) {
797 si_resource_reference(&tex
->cmask_buffer
, NULL
);
799 pb_reference(&resource
->buf
, NULL
);
800 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
801 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
805 static const struct u_resource_vtbl si_texture_vtbl
;
807 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
808 struct u_log_context
*log
)
812 /* Common parameters. */
814 " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
815 "blk_h=%u, array_size=%u, last_level=%u, "
816 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
817 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
, tex
->buffer
.b
.b
.depth0
,
818 tex
->surface
.blk_w
, tex
->surface
.blk_h
, tex
->buffer
.b
.b
.array_size
,
819 tex
->buffer
.b
.b
.last_level
, tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
820 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
822 if (sscreen
->info
.chip_class
>= GFX9
) {
824 " Surf: size=%" PRIu64
", slice_size=%" PRIu64
", "
825 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
826 tex
->surface
.surf_size
, tex
->surface
.u
.gfx9
.surf_slice_size
,
827 tex
->surface
.surf_alignment
, tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
828 tex
->surface
.u
.gfx9
.surf
.epitch
, tex
->surface
.u
.gfx9
.surf_pitch
);
830 if (tex
->surface
.fmask_offset
) {
832 " FMASK: offset=%" PRIu64
", size=%" PRIu64
", "
833 "alignment=%u, swmode=%u, epitch=%u\n",
834 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
,
835 tex
->surface
.fmask_alignment
, tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
836 tex
->surface
.u
.gfx9
.fmask
.epitch
);
839 if (tex
->cmask_buffer
) {
841 " CMask: offset=%" PRIu64
", size=%u, "
843 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
844 tex
->surface
.cmask_alignment
);
847 if (tex
->surface
.htile_offset
) {
849 " HTile: offset=%" PRIu64
", size=%u, alignment=%u\n",
850 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
851 tex
->surface
.htile_alignment
);
854 if (tex
->surface
.dcc_offset
) {
856 " DCC: offset=%" PRIu64
", size=%u, "
857 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
858 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
,
859 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
, tex
->surface
.num_dcc_levels
);
862 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
863 u_log_printf(log
, " Stencil: offset=%" PRIu64
", swmode=%u, epitch=%u\n",
864 tex
->surface
.u
.gfx9
.stencil_offset
, tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
865 tex
->surface
.u
.gfx9
.stencil
.epitch
);
871 " Layout: size=%" PRIu64
", alignment=%u, bankw=%u, "
872 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
873 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
874 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
,
875 tex
->surface
.u
.legacy
.mtilea
, tex
->surface
.u
.legacy
.tile_split
,
876 tex
->surface
.u
.legacy
.pipe_config
, (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
878 if (tex
->surface
.fmask_offset
)
881 " FMask: offset=%" PRIu64
", size=%" PRIu64
", alignment=%u, pitch_in_pixels=%u, "
882 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
883 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
884 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
, tex
->surface
.u
.legacy
.fmask
.bankh
,
885 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
, tex
->surface
.u
.legacy
.fmask
.tiling_index
);
887 if (tex
->cmask_buffer
)
889 " CMask: offset=%" PRIu64
", size=%u, alignment=%u, "
890 "slice_tile_max=%u\n",
891 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
892 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
894 if (tex
->surface
.htile_offset
)
896 " HTile: offset=%" PRIu64
", size=%u, "
897 "alignment=%u, TC_compatible = %u\n",
898 tex
->surface
.htile_offset
, tex
->surface
.htile_size
, tex
->surface
.htile_alignment
,
899 tex
->tc_compatible_htile
);
901 if (tex
->surface
.dcc_offset
) {
902 u_log_printf(log
, " DCC: offset=%" PRIu64
", size=%u, alignment=%u\n",
903 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
904 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
906 " DCCLevel[%i]: enabled=%u, offset=%u, "
907 "fast_clear_size=%u\n",
908 i
, i
< tex
->surface
.num_dcc_levels
, tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
909 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
912 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
914 " Level[%i]: offset=%" PRIu64
", slice_size=%" PRIu64
", "
915 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
916 "mode=%u, tiling_index = %u\n",
917 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
918 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
919 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
920 u_minify(tex
->buffer
.b
.b
.depth0
, i
), tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
921 tex
->surface
.u
.legacy
.level
[i
].nblk_y
, tex
->surface
.u
.legacy
.level
[i
].mode
,
922 tex
->surface
.u
.legacy
.tiling_index
[i
]);
924 if (tex
->surface
.has_stencil
) {
925 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
926 tex
->surface
.u
.legacy
.stencil_tile_split
);
927 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
929 " StencilLevel[%i]: offset=%" PRIu64
", "
930 "slice_size=%" PRIu64
", npix_x=%u, "
931 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
932 "mode=%u, tiling_index = %u\n",
933 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
934 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
935 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
936 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
937 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
938 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
939 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
940 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
946 * Common function for si_texture_create and si_texture_from_handle.
948 * \param screen screen
949 * \param base resource template
950 * \param surface radeon_surf
951 * \param plane0 if a non-zero plane is being created, this is the first plane
952 * \param imported_buf from si_texture_from_handle
953 * \param offset offset for non-zero planes or imported buffers
954 * \param alloc_size the size to allocate if plane0 != NULL
955 * \param alignment alignment for the allocation
957 static struct si_texture
*si_texture_create_object(struct pipe_screen
*screen
,
958 const struct pipe_resource
*base
,
959 const struct radeon_surf
*surface
,
960 const struct si_texture
*plane0
,
961 struct pb_buffer
*imported_buf
,
962 uint64_t offset
, unsigned pitch_in_bytes
,
963 uint64_t alloc_size
, unsigned alignment
)
965 struct si_texture
*tex
;
966 struct si_resource
*resource
;
967 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
969 tex
= CALLOC_STRUCT(si_texture
);
973 resource
= &tex
->buffer
;
974 resource
->b
.b
= *base
;
975 resource
->b
.vtbl
= &si_texture_vtbl
;
976 pipe_reference_init(&resource
->b
.b
.reference
, 1);
977 resource
->b
.b
.screen
= screen
;
979 /* don't include stencil-only formats which we don't support for rendering */
980 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
981 tex
->surface
= *surface
;
982 tex
->tc_compatible_htile
= false; /* This will be enabled on demand. */
984 /* TC-compatible HTILE:
985 * - GFX8 only supports Z32_FLOAT.
986 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
987 if (tex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) {
988 if (sscreen
->info
.chip_class
>= GFX9
&& base
->format
== PIPE_FORMAT_Z16_UNORM
)
989 tex
->db_render_format
= base
->format
;
991 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
992 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
993 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
996 tex
->db_render_format
= base
->format
;
999 /* Applies to GCN. */
1000 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1002 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1003 * between frames, so the only thing that can enable separate DCC
1004 * with DRI2 is multiple slow clears within a frame.
1006 tex
->ps_draw_ratio
= 0;
1008 ac_surface_override_offset_stride(&sscreen
->info
, &tex
->surface
,
1009 tex
->buffer
.b
.b
.last_level
+ 1,
1010 offset
, pitch_in_bytes
/ tex
->surface
.bpe
);
1012 if (tex
->is_depth
) {
1013 if (sscreen
->info
.chip_class
>= GFX9
) {
1014 tex
->can_sample_z
= true;
1015 tex
->can_sample_s
= true;
1017 /* Stencil texturing with HTILE doesn't work
1018 * with mipmapping on Navi10-14. */
1019 if (sscreen
->info
.chip_class
== GFX10
&& base
->last_level
> 0)
1020 tex
->htile_stencil_disabled
= true;
1022 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1023 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1026 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1028 if (tex
->surface
.cmask_offset
) {
1029 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1030 tex
->cmask_buffer
= &tex
->buffer
;
1035 /* The buffer is shared with the first plane. */
1036 resource
->bo_size
= plane0
->buffer
.bo_size
;
1037 resource
->bo_alignment
= plane0
->buffer
.bo_alignment
;
1038 resource
->flags
= plane0
->buffer
.flags
;
1039 resource
->domains
= plane0
->buffer
.domains
;
1040 resource
->vram_usage
= plane0
->buffer
.vram_usage
;
1041 resource
->gart_usage
= plane0
->buffer
.gart_usage
;
1043 pb_reference(&resource
->buf
, plane0
->buffer
.buf
);
1044 resource
->gpu_address
= plane0
->buffer
.gpu_address
;
1045 } else if (!(surface
->flags
& RADEON_SURF_IMPORTED
)) {
1046 /* Create the backing buffer. */
1047 si_init_resource_fields(sscreen
, resource
, alloc_size
, alignment
);
1049 if (!si_alloc_resource(sscreen
, resource
))
1052 resource
->buf
= imported_buf
;
1053 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1054 resource
->bo_size
= imported_buf
->size
;
1055 resource
->bo_alignment
= imported_buf
->alignment
;
1056 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1057 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1058 resource
->vram_usage
= resource
->bo_size
;
1059 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1060 resource
->gart_usage
= resource
->bo_size
;
1061 if (sscreen
->ws
->buffer_get_flags
)
1062 resource
->flags
= sscreen
->ws
->buffer_get_flags(resource
->buf
);
1065 if (tex
->cmask_buffer
) {
1066 /* Initialize the cmask to 0xCC (= compressed state). */
1067 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
, tex
->surface
.cmask_offset
,
1068 tex
->surface
.cmask_size
, 0xCCCCCCCC);
1070 if (tex
->surface
.htile_offset
) {
1071 uint32_t clear_value
= 0;
1073 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1074 clear_value
= 0x0000030F;
1076 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.htile_offset
,
1077 tex
->surface
.htile_size
, clear_value
);
1080 /* Initialize DCC only if the texture is not being imported. */
1081 if (!(surface
->flags
& RADEON_SURF_IMPORTED
) && tex
->surface
.dcc_offset
) {
1082 /* Clear DCC to black for all tiles with DCC enabled.
1084 * This fixes corruption in 3DMark Slingshot Extreme, which
1085 * uses uninitialized textures, causing corruption.
1087 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1088 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1089 /* Simple case - all tiles have DCC enabled. */
1090 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1091 tex
->surface
.dcc_size
, DCC_CLEAR_COLOR_0000
);
1092 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1093 /* Clear to uncompressed. Clearing this to black is complicated. */
1094 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1095 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1097 /* GFX8: Initialize mipmap levels and multisamples separately. */
1098 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1099 /* Clearing this to black is complicated. */
1100 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1101 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1103 /* Clear the enabled mipmap levels to black. */
1106 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1107 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1110 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1111 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1114 /* Mipmap levels with DCC. */
1116 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
, size
,
1117 DCC_CLEAR_COLOR_0000
);
1119 /* Mipmap levels without DCC. */
1120 if (size
!= tex
->surface
.dcc_size
) {
1121 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
+ size
,
1122 tex
->surface
.dcc_size
- size
, DCC_UNCOMPRESSED
);
1127 /* Initialize displayable DCC that requires the retile blit. */
1128 if (tex
->surface
.dcc_retile_map_offset
) {
1129 /* Uninitialized DCC can hang the display hw.
1130 * Clear to white to indicate that. */
1131 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.display_dcc_offset
,
1132 tex
->surface
.u
.gfx9
.display_dcc_size
, DCC_CLEAR_COLOR_1111
);
1134 /* Upload the DCC retile map.
1135 * Use a staging buffer for the upload, because
1136 * the buffer backing the texture is unmappable.
1138 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1139 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1140 struct si_resource
*buf
= si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1141 num_elements
* (use_uint16
? 2 : 4),
1142 sscreen
->info
.tcc_cache_line_size
);
1143 uint32_t *ui
= (uint32_t *)sscreen
->ws
->buffer_map(buf
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
1144 uint16_t *us
= (uint16_t *)ui
;
1146 /* Upload the retile map into a staging buffer. */
1148 for (unsigned i
= 0; i
< num_elements
; i
++)
1149 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1151 for (unsigned i
= 0; i
< num_elements
; i
++)
1152 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1155 /* Copy the staging buffer to the buffer backing the texture. */
1156 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1158 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1159 simple_mtx_lock(&sscreen
->aux_context_lock
);
1160 si_sdma_copy_buffer(sctx
, &tex
->buffer
.b
.b
, &buf
->b
.b
, tex
->surface
.dcc_retile_map_offset
,
1161 0, buf
->b
.b
.width0
);
1162 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1163 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1165 si_resource_reference(&buf
, NULL
);
1169 /* Initialize the CMASK base register value. */
1170 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1172 if (sscreen
->debug_flags
& DBG(VM
)) {
1174 "VM start=0x%" PRIX64
" end=0x%" PRIX64
1175 " | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1176 tex
->buffer
.gpu_address
, tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1177 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+ 1,
1178 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1181 if (sscreen
->debug_flags
& DBG(TEX
)) {
1183 struct u_log_context log
;
1184 u_log_context_init(&log
);
1185 si_print_texture_info(sscreen
, tex
, &log
);
1186 u_log_new_page_print(&log
, stdout
);
1188 u_log_context_destroy(&log
);
1195 if (sscreen
->info
.chip_class
>= GFX9
)
1196 free(surface
->u
.gfx9
.dcc_retile_map
);
1200 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
1201 const struct pipe_resource
*templ
,
1202 bool tc_compatible_htile
)
1204 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1205 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1206 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1207 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1209 /* MSAA resources must be 2D tiled. */
1210 if (templ
->nr_samples
> 1)
1211 return RADEON_SURF_MODE_2D
;
1213 /* Transfer resources should be linear. */
1214 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1215 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1217 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1218 * which requires 2D tiling.
1220 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1221 return RADEON_SURF_MODE_2D
;
1223 /* Handle common candidates for the linear mode.
1224 * Compressed textures and DB surfaces must always be tiled.
1226 if (!force_tiling
&& !is_depth_stencil
&& !util_format_is_compressed(templ
->format
)) {
1227 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1228 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1230 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1231 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1232 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1234 /* Cursors are linear on AMD GCN.
1235 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1236 if (templ
->bind
& PIPE_BIND_CURSOR
)
1237 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1239 if (templ
->bind
& PIPE_BIND_LINEAR
)
1240 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1242 /* Textures with a very small height are recommended to be linear. */
1243 if (templ
->target
== PIPE_TEXTURE_1D
|| templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1244 /* Only very thin and long 2D textures should benefit from
1245 * linear_aligned. */
1246 (templ
->width0
> 8 && templ
->height0
<= 2))
1247 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1249 /* Textures likely to be mapped often. */
1250 if (templ
->usage
== PIPE_USAGE_STAGING
|| templ
->usage
== PIPE_USAGE_STREAM
)
1251 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1254 /* Make small textures 1D tiled. */
1255 if (templ
->width0
<= 16 || templ
->height0
<= 16 || (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1256 return RADEON_SURF_MODE_1D
;
1258 /* The allocator will switch to 1D if needed. */
1259 return RADEON_SURF_MODE_2D
;
1262 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1263 const struct pipe_resource
*templ
)
1265 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1266 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1268 if (templ
->nr_samples
>= 2) {
1269 /* This is hackish (overwriting the const pipe_resource template),
1270 * but should be harmless and state trackers can also see
1271 * the overriden number of samples in the created pipe_resource.
1273 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1274 ((struct pipe_resource
*)templ
)->nr_samples
=
1275 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_z_samples
;
1276 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1277 ((struct pipe_resource
*)templ
)->nr_samples
= sscreen
->eqaa_force_coverage_samples
;
1278 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_color_samples
;
1282 bool is_flushed_depth
=
1283 templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
|| templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1284 bool tc_compatible_htile
=
1285 sscreen
->info
.chip_class
>= GFX8
&&
1286 /* There are issues with TC-compatible HTILE on Tonga (and
1287 * Iceland is the same design), and documented bug workarounds
1288 * don't help. For example, this fails:
1289 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1291 sscreen
->info
.family
!= CHIP_TONGA
&& sscreen
->info
.family
!= CHIP_ICELAND
&&
1292 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1293 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) && !is_flushed_depth
&&
1294 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1296 enum radeon_surf_mode tile_mode
= si_choose_tiling(sscreen
, templ
, tc_compatible_htile
);
1298 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1301 SI_TEXTURE_MAX_PLANES
= 3
1303 struct radeon_surf surface
[SI_TEXTURE_MAX_PLANES
] = {};
1304 struct pipe_resource plane_templ
[SI_TEXTURE_MAX_PLANES
];
1305 uint64_t plane_offset
[SI_TEXTURE_MAX_PLANES
] = {};
1306 uint64_t total_size
= 0;
1307 unsigned max_alignment
= 0;
1308 unsigned num_planes
= util_format_get_num_planes(templ
->format
);
1309 assert(num_planes
<= SI_TEXTURE_MAX_PLANES
);
1311 /* Compute texture or plane layouts and offsets. */
1312 for (unsigned i
= 0; i
< num_planes
; i
++) {
1313 plane_templ
[i
] = *templ
;
1314 plane_templ
[i
].format
= util_format_get_plane_format(templ
->format
, i
);
1315 plane_templ
[i
].width0
= util_format_get_plane_width(templ
->format
, i
, templ
->width0
);
1316 plane_templ
[i
].height0
= util_format_get_plane_height(templ
->format
, i
, templ
->height0
);
1318 /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't
1319 * reallocate the storage to add PIPE_BIND_SHARED, because it's
1320 * shared by 3 pipe_resources.
1323 plane_templ
[i
].bind
|= PIPE_BIND_SHARED
;
1325 if (si_init_surface(sscreen
, &surface
[i
], &plane_templ
[i
], tile_mode
, false,
1326 plane_templ
[i
].bind
& PIPE_BIND_SCANOUT
, is_flushed_depth
,
1327 tc_compatible_htile
))
1330 plane_offset
[i
] = align64(total_size
, surface
[i
].surf_alignment
);
1331 total_size
= plane_offset
[i
] + surface
[i
].total_size
;
1332 max_alignment
= MAX2(max_alignment
, surface
[i
].surf_alignment
);
1335 struct si_texture
*plane0
= NULL
, *last_plane
= NULL
;
1337 for (unsigned i
= 0; i
< num_planes
; i
++) {
1338 struct si_texture
*tex
=
1339 si_texture_create_object(screen
, &plane_templ
[i
], &surface
[i
], plane0
, NULL
,
1340 plane_offset
[i
], 0, total_size
, max_alignment
);
1342 si_texture_reference(&plane0
, NULL
);
1346 tex
->plane_index
= i
;
1347 tex
->num_planes
= num_planes
;
1350 plane0
= last_plane
= tex
;
1352 last_plane
->buffer
.b
.b
.next
= &tex
->buffer
.b
.b
;
1357 return (struct pipe_resource
*)plane0
;
1360 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1361 const struct pipe_resource
*templ
,
1362 struct pb_buffer
*buf
, unsigned stride
,
1363 uint64_t offset
, unsigned usage
,
1366 struct radeon_surf surface
= {};
1367 struct radeon_bo_metadata metadata
= {};
1368 struct si_texture
*tex
;
1371 /* Ignore metadata for non-zero planes. */
1376 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
, &surface
);
1379 * The bo metadata is unset for un-dedicated images. So we fall
1380 * back to linear. See answer to question 5 of the
1381 * VK_KHX_external_memory spec for some details.
1383 * It is possible that this case isn't going to work if the
1384 * surface pitch isn't correctly aligned by default.
1386 * In order to support it correctly we require multi-image
1387 * metadata to be syncrhonized between radv and radeonsi. The
1388 * semantics of associating multiple image metadata to a memory
1389 * object on the vulkan export side are not concretely defined
1392 * All the use cases we are aware of at the moment for memory
1393 * objects use dedicated allocations. So lets keep the initial
1394 * implementation simple.
1396 * A possible alternative is to attempt to reconstruct the
1397 * tiling information when the TexParameter TEXTURE_TILING_EXT
1400 metadata
.mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1403 r
= si_init_surface(sscreen
, &surface
, templ
, metadata
.mode
, true,
1404 surface
.flags
& RADEON_SURF_SCANOUT
, false, false);
1408 tex
= si_texture_create_object(&sscreen
->b
, templ
, &surface
, NULL
, buf
,
1409 offset
, stride
, 0, 0);
1413 tex
->buffer
.b
.is_shared
= true;
1414 tex
->buffer
.external_usage
= usage
;
1415 tex
->num_planes
= 1;
1417 /* Account for multiple planes with lowered yuv import. */
1418 struct pipe_resource
*next_plane
= tex
->buffer
.b
.b
.next
;
1420 struct si_texture
*next_tex
= (struct si_texture
*)next_plane
;
1421 ++next_tex
->num_planes
;
1423 next_plane
= next_plane
->next
;
1426 if (!ac_surface_set_umd_metadata(&sscreen
->info
, &tex
->surface
,
1427 tex
->buffer
.b
.b
.nr_storage_samples
,
1428 tex
->buffer
.b
.b
.last_level
+ 1,
1429 metadata
.size_metadata
,
1430 metadata
.metadata
)) {
1431 si_texture_reference(&tex
, NULL
);
1435 /* Displayable DCC requires an explicit flush. */
1436 if (dedicated
&& offset
== 0 && !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1437 si_has_displayable_dcc(tex
)) {
1438 /* TODO: do we need to decompress DCC? */
1439 if (si_texture_discard_dcc(sscreen
, tex
)) {
1440 /* Update BO metadata after disabling DCC. */
1441 si_set_tex_bo_metadata(sscreen
, tex
);
1445 assert(tex
->surface
.tile_swizzle
== 0);
1446 return &tex
->buffer
.b
.b
;
1449 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1450 const struct pipe_resource
*templ
,
1451 struct winsys_handle
*whandle
, unsigned usage
)
1453 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1454 struct pb_buffer
*buf
= NULL
;
1456 /* Support only 2D textures without mipmaps */
1457 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1458 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1459 templ
->last_level
!= 0)
1462 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
1466 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, whandle
->stride
, whandle
->offset
,
1470 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
)
1472 struct si_texture
*tex
= (struct si_texture
*)texture
;
1473 struct pipe_resource resource
;
1474 enum pipe_format pipe_format
= texture
->format
;
1476 assert(!tex
->flushed_depth_texture
);
1478 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1479 switch (pipe_format
) {
1480 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1481 /* Save memory by not allocating the S plane. */
1482 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1484 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1485 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1486 /* Save memory bandwidth by not copying the
1487 * stencil part during flush.
1489 * This potentially increases memory bandwidth
1490 * if an application uses both Z and S texturing
1491 * simultaneously (a flushed Z24S8 texture
1492 * would be stored compactly), but how often
1493 * does that really happen?
1495 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1499 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1500 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1502 /* DB->CB copies to an 8bpp surface don't work. */
1503 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1506 memset(&resource
, 0, sizeof(resource
));
1507 resource
.target
= texture
->target
;
1508 resource
.format
= pipe_format
;
1509 resource
.width0
= texture
->width0
;
1510 resource
.height0
= texture
->height0
;
1511 resource
.depth0
= texture
->depth0
;
1512 resource
.array_size
= texture
->array_size
;
1513 resource
.last_level
= texture
->last_level
;
1514 resource
.nr_samples
= texture
->nr_samples
;
1515 resource
.usage
= PIPE_USAGE_DEFAULT
;
1516 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1517 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1519 tex
->flushed_depth_texture
=
1520 (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1521 if (!tex
->flushed_depth_texture
) {
1522 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1529 * Initialize the pipe_resource descriptor to be of the same size as the box,
1530 * which is supposed to hold a subregion of the texture "orig" at the given
1533 static void si_init_temp_resource_from_box(struct pipe_resource
*res
, struct pipe_resource
*orig
,
1534 const struct pipe_box
*box
, unsigned level
,
1537 memset(res
, 0, sizeof(*res
));
1538 res
->format
= orig
->format
;
1539 res
->width0
= box
->width
;
1540 res
->height0
= box
->height
;
1542 res
->array_size
= 1;
1543 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1546 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&& util_format_is_compressed(orig
->format
)) {
1547 /* Transfer resources are allocated with linear tiling, which is
1548 * not supported for compressed formats.
1550 unsigned blocksize
= util_format_get_blocksize(orig
->format
);
1552 if (blocksize
== 8) {
1553 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1555 assert(blocksize
== 16);
1556 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1559 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1560 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1563 /* We must set the correct texture target and dimensions for a 3D box. */
1564 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1565 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1566 res
->array_size
= box
->depth
;
1568 res
->target
= PIPE_TEXTURE_2D
;
1572 static bool si_can_invalidate_texture(struct si_screen
*sscreen
, struct si_texture
*tex
,
1573 unsigned transfer_usage
, const struct pipe_box
*box
)
1575 return !tex
->buffer
.b
.is_shared
&& !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1576 !(transfer_usage
& PIPE_TRANSFER_READ
) && tex
->buffer
.b
.b
.last_level
== 0 &&
1577 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0, box
->x
, box
->y
, box
->z
, box
->width
,
1578 box
->height
, box
->depth
);
1581 static void si_texture_invalidate_storage(struct si_context
*sctx
, struct si_texture
*tex
)
1583 struct si_screen
*sscreen
= sctx
->screen
;
1585 /* There is no point in discarding depth and tiled buffers. */
1586 assert(!tex
->is_depth
);
1587 assert(tex
->surface
.is_linear
);
1589 /* Reallocate the buffer in the same pipe_resource. */
1590 si_alloc_resource(sscreen
, &tex
->buffer
);
1592 /* Initialize the CMASK base address (needed even without CMASK). */
1593 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1595 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1597 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1600 static void *si_texture_transfer_map(struct pipe_context
*ctx
, struct pipe_resource
*texture
,
1601 unsigned level
, unsigned usage
, const struct pipe_box
*box
,
1602 struct pipe_transfer
**ptransfer
)
1604 struct si_context
*sctx
= (struct si_context
*)ctx
;
1605 struct si_texture
*tex
= (struct si_texture
*)texture
;
1606 struct si_transfer
*trans
;
1607 struct si_resource
*buf
;
1608 unsigned offset
= 0;
1610 bool use_staging_texture
= false;
1612 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1613 assert(box
->width
&& box
->height
&& box
->depth
);
1615 /* If we are uploading into FP16 or R11G11B10_FLOAT via a blit, CB clobbers NaNs,
1616 * so in order to preserve them exactly, we have to use the compute blit.
1617 * The compute blit is used only when the destination doesn't have DCC, so
1618 * disable it here, which is kinda a hack.
1620 * This makes KHR-GL45.texture_view.view_classes pass on gfx9.
1621 * gfx10 has the same issue, but the test doesn't use a large enough texture
1622 * to enable DCC and fail, so it always passes.
1624 const struct util_format_description
*desc
= util_format_description(texture
->format
);
1625 if (vi_dcc_enabled(tex
, level
) &&
1626 desc
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
&&
1627 desc
->channel
[0].size
< 32)
1628 si_texture_disable_dcc(sctx
, tex
);
1630 if (tex
->is_depth
) {
1631 /* Depth textures use staging unconditionally. */
1632 use_staging_texture
= true;
1634 /* Degrade the tile mode if we get too many transfers on APUs.
1635 * On dGPUs, the staging texture is always faster.
1636 * Only count uploads that are at least 4x4 pixels large.
1638 if (!sctx
->screen
->info
.has_dedicated_vram
&& level
== 0 && box
->width
>= 4 &&
1639 box
->height
>= 4 && p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1640 bool can_invalidate
= si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
);
1642 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_LINEAR
, can_invalidate
);
1645 /* Tiled textures need to be converted into a linear texture for CPU
1646 * access. The staging texture is always linear and is placed in GART.
1648 * Reading from VRAM or GTT WC is slow, always use the staging
1649 * texture in this case.
1651 * Use the staging texture for uploads if the underlying BO
1654 if (!tex
->surface
.is_linear
)
1655 use_staging_texture
= true;
1656 else if (usage
& PIPE_TRANSFER_READ
)
1657 use_staging_texture
=
1658 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
|| tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1659 /* Write & linear only: */
1660 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
, RADEON_USAGE_READWRITE
) ||
1661 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0, RADEON_USAGE_READWRITE
)) {
1663 if (si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
))
1664 si_texture_invalidate_storage(sctx
, tex
);
1666 use_staging_texture
= true;
1670 trans
= CALLOC_STRUCT(si_transfer
);
1673 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1674 trans
->b
.b
.level
= level
;
1675 trans
->b
.b
.usage
= usage
;
1676 trans
->b
.b
.box
= *box
;
1678 if (use_staging_texture
) {
1679 struct pipe_resource resource
;
1680 struct si_texture
*staging
;
1682 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, SI_RESOURCE_FLAG_TRANSFER
);
1683 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ? PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1685 /* Since depth-stencil textures don't support linear tiling,
1686 * blit from ZS to color and vice versa. u_blitter will do
1687 * the packing for these formats.
1690 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1692 /* Create the temporary texture. */
1693 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1695 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1698 trans
->staging
= &staging
->buffer
;
1700 /* Just get the strides. */
1701 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
, &trans
->b
.b
.stride
,
1702 &trans
->b
.b
.layer_stride
);
1704 if (usage
& PIPE_TRANSFER_READ
)
1705 si_copy_to_staging_texture(ctx
, trans
);
1707 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1709 buf
= trans
->staging
;
1711 /* the resource is mapped directly */
1712 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
, &trans
->b
.b
.stride
,
1713 &trans
->b
.b
.layer_stride
);
1717 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1718 * we don't run out of the CPU address space.
1720 if (sizeof(void *) == 4)
1721 usage
|= RADEON_TRANSFER_TEMPORARY
;
1723 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1726 *ptransfer
= &trans
->b
.b
;
1727 return map
+ offset
;
1730 si_resource_reference(&trans
->staging
, NULL
);
1731 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1736 static void si_texture_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*transfer
)
1738 struct si_context
*sctx
= (struct si_context
*)ctx
;
1739 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1740 struct pipe_resource
*texture
= transfer
->resource
;
1741 struct si_texture
*tex
= (struct si_texture
*)texture
;
1743 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1744 * we don't run out of the CPU address space.
1746 if (sizeof(void *) == 4) {
1747 struct si_resource
*buf
= stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1749 sctx
->ws
->buffer_unmap(buf
->buf
);
1752 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
1753 si_copy_from_staging_texture(ctx
, stransfer
);
1755 if (stransfer
->staging
) {
1756 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1757 si_resource_reference(&stransfer
->staging
, NULL
);
1760 /* Heuristic for {upload, draw, upload, draw, ..}:
1762 * Flush the gfx IB if we've allocated too much texture storage.
1764 * The idea is that we don't want to build IBs that use too much
1765 * memory and put pressure on the kernel memory manager and we also
1766 * want to make temporary and invalidated buffers go idle ASAP to
1767 * decrease the total memory usage or make them reusable. The memory
1768 * usage will be slightly higher than given here because of the buffer
1769 * cache in the winsys.
1771 * The result is that the kernel memory manager is never a bottleneck.
1773 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1774 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1775 sctx
->num_alloc_tex_transfer_bytes
= 0;
1778 pipe_resource_reference(&transfer
->resource
, NULL
);
1782 static const struct u_resource_vtbl si_texture_vtbl
= {
1783 NULL
, /* get_handle */
1784 si_texture_destroy
, /* resource_destroy */
1785 si_texture_transfer_map
, /* transfer_map */
1786 u_default_transfer_flush_region
, /* transfer_flush_region */
1787 si_texture_transfer_unmap
, /* transfer_unmap */
1790 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1792 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
1793 enum pipe_format format2
)
1795 const struct util_format_description
*desc1
, *desc2
;
1797 /* No format change - exit early. */
1798 if (format1
== format2
)
1801 format1
= si_simplify_cb_format(format1
);
1802 format2
= si_simplify_cb_format(format2
);
1804 /* Check again after format adjustments. */
1805 if (format1
== format2
)
1808 desc1
= util_format_description(format1
);
1809 desc2
= util_format_description(format2
);
1811 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
|| desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1814 /* Float and non-float are totally incompatible. */
1815 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1816 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1819 /* Channel sizes must match across DCC formats.
1820 * Comparing just the first 2 channels should be enough.
1822 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1823 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1826 /* Everything below is not needed if the driver never uses the DCC
1827 * clear code with the value of 1.
1830 /* If the clear values are all 1 or all 0, this constraint can be
1832 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
1835 /* Channel types must match if the clear value of 1 is used.
1836 * The type categories are only float, signed, unsigned.
1837 * NORM and INT are always compatible.
1839 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1840 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1846 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
1847 enum pipe_format view_format
)
1849 struct si_texture
*stex
= (struct si_texture
*)tex
;
1851 return vi_dcc_enabled(stex
, level
) &&
1852 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
, tex
->format
, view_format
);
1855 /* This can't be merged with the above function, because
1856 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1857 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
1858 unsigned level
, enum pipe_format view_format
)
1860 struct si_texture
*stex
= (struct si_texture
*)tex
;
1862 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1863 if (!si_texture_disable_dcc(sctx
, stex
))
1864 si_decompress_dcc(sctx
, stex
);
1867 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1868 struct pipe_resource
*texture
,
1869 const struct pipe_surface
*templ
, unsigned width0
,
1870 unsigned height0
, unsigned width
, unsigned height
)
1872 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
1877 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1878 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1880 pipe_reference_init(&surface
->base
.reference
, 1);
1881 pipe_resource_reference(&surface
->base
.texture
, texture
);
1882 surface
->base
.context
= pipe
;
1883 surface
->base
.format
= templ
->format
;
1884 surface
->base
.width
= width
;
1885 surface
->base
.height
= height
;
1886 surface
->base
.u
= templ
->u
;
1888 surface
->width0
= width0
;
1889 surface
->height0
= height0
;
1891 surface
->dcc_incompatible
=
1892 texture
->target
!= PIPE_BUFFER
&&
1893 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
, templ
->format
);
1894 return &surface
->base
;
1897 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
, struct pipe_resource
*tex
,
1898 const struct pipe_surface
*templ
)
1900 unsigned level
= templ
->u
.tex
.level
;
1901 unsigned width
= u_minify(tex
->width0
, level
);
1902 unsigned height
= u_minify(tex
->height0
, level
);
1903 unsigned width0
= tex
->width0
;
1904 unsigned height0
= tex
->height0
;
1906 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1907 const struct util_format_description
*tex_desc
= util_format_description(tex
->format
);
1908 const struct util_format_description
*templ_desc
= util_format_description(templ
->format
);
1910 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1912 /* Adjust size of surface if and only if the block width or
1913 * height is changed. */
1914 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1915 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1916 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1917 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1919 width
= nblks_x
* templ_desc
->block
.width
;
1920 height
= nblks_y
* templ_desc
->block
.height
;
1922 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1923 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1927 return si_create_surface_custom(pipe
, tex
, templ
, width0
, height0
, width
, height
);
1930 static void si_surface_destroy(struct pipe_context
*pipe
, struct pipe_surface
*surface
)
1932 pipe_resource_reference(&surface
->texture
, NULL
);
1936 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1938 const struct util_format_description
*desc
= util_format_description(format
);
1940 #define HAS_SWIZZLE(chan, swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1942 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1943 return V_028C70_SWAP_STD
;
1945 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1948 switch (desc
->nr_channels
) {
1950 if (HAS_SWIZZLE(0, X
))
1951 return V_028C70_SWAP_STD
; /* X___ */
1952 else if (HAS_SWIZZLE(3, X
))
1953 return V_028C70_SWAP_ALT_REV
; /* ___X */
1956 if ((HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, Y
)) || (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, NONE
)) ||
1957 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, Y
)))
1958 return V_028C70_SWAP_STD
; /* XY__ */
1959 else if ((HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, X
)) ||
1960 (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, NONE
)) ||
1961 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, X
)))
1963 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
1964 else if (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(3, Y
))
1965 return V_028C70_SWAP_ALT
; /* X__Y */
1966 else if (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(3, X
))
1967 return V_028C70_SWAP_ALT_REV
; /* Y__X */
1970 if (HAS_SWIZZLE(0, X
))
1971 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
1972 else if (HAS_SWIZZLE(0, Z
))
1973 return V_028C70_SWAP_STD_REV
; /* ZYX */
1976 /* check the middle channels, the 1st and 4th channel can be NONE */
1977 if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, Z
)) {
1978 return V_028C70_SWAP_STD
; /* XYZW */
1979 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, Y
)) {
1980 return V_028C70_SWAP_STD_REV
; /* WZYX */
1981 } else if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, X
)) {
1982 return V_028C70_SWAP_ALT
; /* ZYXW */
1983 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, W
)) {
1986 return V_028C70_SWAP_ALT_REV
;
1988 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
1995 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1997 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
, int slot
)
2001 if (sctx
->dcc_stats
[slot
].query_active
)
2002 vi_separate_dcc_stop_query(sctx
, sctx
->dcc_stats
[slot
].tex
);
2004 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2005 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2006 sctx
->b
.destroy_query(&sctx
->b
, sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2007 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2010 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2014 * Return the per-context slot where DCC statistics queries for the texture live.
2016 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
, struct si_texture
*tex
)
2018 int i
, empty_slot
= -1;
2020 /* Remove zombie textures (textures kept alive by this array only). */
2021 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2022 if (sctx
->dcc_stats
[i
].tex
&& sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2023 vi_dcc_clean_up_context_slot(sctx
, i
);
2025 /* Find the texture. */
2026 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2027 /* Return if found. */
2028 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2029 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2033 /* Record the first seen empty slot. */
2034 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2038 /* Not found. Remove the oldest member to make space in the array. */
2039 if (empty_slot
== -1) {
2040 int oldest_slot
= 0;
2042 /* Find the oldest slot. */
2043 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2044 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2045 sctx
->dcc_stats
[i
].last_use_timestamp
)
2048 /* Clean up the oldest slot. */
2049 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2050 empty_slot
= oldest_slot
;
2053 /* Add the texture to the new slot. */
2054 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2055 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2059 static struct pipe_query
*vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2061 struct si_query_hw
*query
=
2062 (struct si_query_hw
*)sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2064 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2065 return (struct pipe_query
*)query
;
2069 * Called when binding a color buffer.
2071 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
)
2073 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2075 assert(!sctx
->dcc_stats
[i
].query_active
);
2077 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2078 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2080 /* begin or resume the query */
2081 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2082 sctx
->dcc_stats
[i
].query_active
= true;
2086 * Called when unbinding a color buffer.
2088 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
)
2090 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2092 assert(sctx
->dcc_stats
[i
].query_active
);
2093 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2095 /* pause or end the query */
2096 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2097 sctx
->dcc_stats
[i
].query_active
= false;
2100 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2102 /* The minimum number of fullscreen draws per frame that is required
2104 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2107 /* Called by fast clear. */
2108 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
)
2110 /* The intent is to use this with shared displayable back buffers,
2111 * but it's not strictly limited only to them.
2113 if (!tex
->buffer
.b
.is_shared
||
2114 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2115 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
|| tex
->buffer
.b
.b
.last_level
> 0 ||
2116 !tex
->surface
.dcc_size
|| sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2117 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2120 assert(sctx
->chip_class
>= GFX8
);
2122 if (tex
->surface
.dcc_offset
)
2123 return; /* already enabled */
2125 /* Enable the DCC stat gathering. */
2126 if (!tex
->dcc_gather_statistics
) {
2127 tex
->dcc_gather_statistics
= true;
2128 vi_separate_dcc_start_query(sctx
, tex
);
2131 if (!vi_should_enable_separate_dcc(tex
))
2132 return; /* stats show that DCC decompression is too expensive */
2134 assert(tex
->surface
.num_dcc_levels
);
2135 assert(!tex
->dcc_separate_buffer
);
2137 si_texture_discard_cmask(sctx
->screen
, tex
);
2139 /* Get a DCC buffer. */
2140 if (tex
->last_dcc_separate_buffer
) {
2141 assert(tex
->dcc_gather_statistics
);
2142 assert(!tex
->dcc_separate_buffer
);
2143 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2144 tex
->last_dcc_separate_buffer
= NULL
;
2146 tex
->dcc_separate_buffer
=
2147 si_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
2148 tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
2149 if (!tex
->dcc_separate_buffer
)
2153 /* dcc_offset is the absolute GPUVM address. */
2154 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2156 /* no need to flag anything since this is called by fast clear that
2157 * flags framebuffer state
2162 * Called by pipe_context::flush_resource, the place where DCC decompression
2165 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
)
2167 struct si_context
*sctx
= (struct si_context
*)ctx
;
2168 struct pipe_query
*tmp
;
2169 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2170 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2171 bool disable
= false;
2173 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2174 union pipe_query_result result
;
2176 /* Read the results. */
2177 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2178 ctx
->get_query_result(ctx
, query
, true, &result
);
2179 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2181 /* Compute the approximate number of fullscreen draws. */
2182 tex
->ps_draw_ratio
= result
.pipeline_statistics
.ps_invocations
/
2183 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2184 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2186 disable
= tex
->dcc_separate_buffer
&& !vi_should_enable_separate_dcc(tex
);
2189 tex
->num_slow_clears
= 0;
2191 /* stop the statistics query for ps_stats[0] */
2193 vi_separate_dcc_stop_query(sctx
, tex
);
2195 /* Move the queries in the queue by one. */
2196 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2197 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2198 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2199 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2201 /* create and start a new query as ps_stats[0] */
2203 vi_separate_dcc_start_query(sctx
, tex
);
2206 assert(!tex
->last_dcc_separate_buffer
);
2207 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2208 tex
->dcc_separate_buffer
= NULL
;
2209 tex
->surface
.dcc_offset
= 0;
2210 /* no need to flag anything since this is called after
2211 * decompression that re-sets framebuffer state
2216 static struct pipe_memory_object
*
2217 si_memobj_from_handle(struct pipe_screen
*screen
, struct winsys_handle
*whandle
, bool dedicated
)
2219 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2220 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2221 struct pb_buffer
*buf
= NULL
;
2226 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
2232 memobj
->b
.dedicated
= dedicated
;
2234 memobj
->stride
= whandle
->stride
;
2236 return (struct pipe_memory_object
*)memobj
;
2239 static void si_memobj_destroy(struct pipe_screen
*screen
, struct pipe_memory_object
*_memobj
)
2241 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2243 pb_reference(&memobj
->buf
, NULL
);
2247 static struct pipe_resource
*si_texture_from_memobj(struct pipe_screen
*screen
,
2248 const struct pipe_resource
*templ
,
2249 struct pipe_memory_object
*_memobj
,
2252 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2253 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2254 struct pipe_resource
*tex
= si_texture_from_winsys_buffer(
2255 sscreen
, templ
, memobj
->buf
, memobj
->stride
, offset
,
2256 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
| PIPE_HANDLE_USAGE_SHADER_WRITE
, memobj
->b
.dedicated
);
2260 /* si_texture_from_winsys_buffer doesn't increment refcount of
2261 * memobj->buf, so increment it here.
2263 struct pb_buffer
*buf
= NULL
;
2264 pb_reference(&buf
, memobj
->buf
);
2268 static bool si_check_resource_capability(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
2271 struct si_texture
*tex
= (struct si_texture
*)resource
;
2273 /* Buffers only support the linear flag. */
2274 if (resource
->target
== PIPE_BUFFER
)
2275 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2277 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2280 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2283 /* TODO: PIPE_BIND_CURSOR - do we care? */
2287 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2289 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2290 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2291 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2292 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2293 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2294 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2295 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2296 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2299 void si_init_context_texture_functions(struct si_context
*sctx
)
2301 sctx
->b
.create_surface
= si_create_surface
;
2302 sctx
->b
.surface_destroy
= si_surface_destroy
;