2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
40 #include "amd/common/gfx9d.h"
42 static enum radeon_surf_mode
43 si_choose_tiling(struct si_screen
*sscreen
,
44 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
47 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
48 struct si_texture
*dst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct si_texture
*src
,
53 const struct pipe_box
*src_box
)
58 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
63 dst
->buffer
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (src
->is_depth
|| dst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(src
, src_level
) ||
78 vi_dcc_enabled(dst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 si_texture_discard_cmask(sctx
->screen
, dst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
99 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
101 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(src
->format
) &
133 util_format_get_mask(dst
->format
);
134 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
137 pipe
->blit(pipe
, &blit
);
141 /* Copy from a full GPU texture to a transfer's staging one. */
142 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
144 struct si_context
*sctx
= (struct si_context
*)ctx
;
145 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
146 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
147 struct pipe_resource
*src
= transfer
->resource
;
149 if (src
->nr_samples
> 1) {
150 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
151 src
, transfer
->level
, &transfer
->box
);
155 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
159 /* Copy from a transfer's staging texture to a full GPU one. */
160 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
162 struct si_context
*sctx
= (struct si_context
*)ctx
;
163 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
164 struct pipe_resource
*dst
= transfer
->resource
;
165 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
166 struct pipe_box sbox
;
168 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
170 if (dst
->nr_samples
> 1) {
171 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
172 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
178 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
182 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
183 struct si_texture
*tex
, unsigned level
,
184 const struct pipe_box
*box
,
186 unsigned *layer_stride
)
188 if (sscreen
->info
.chip_class
>= GFX9
) {
189 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
190 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
195 /* Each texture is an array of slices. Each slice is an array
196 * of mipmap levels. */
197 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
198 tex
->surface
.u
.gfx9
.offset
[level
] +
199 (box
->y
/ tex
->surface
.blk_h
*
200 tex
->surface
.u
.gfx9
.surf_pitch
+
201 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
203 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
205 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
206 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
209 return tex
->surface
.u
.legacy
.level
[level
].offset
;
211 /* Each texture is an array of mipmap levels. Each level is
212 * an array of slices. */
213 return tex
->surface
.u
.legacy
.level
[level
].offset
+
214 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
215 (box
->y
/ tex
->surface
.blk_h
*
216 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
217 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
221 static int si_init_surface(struct si_screen
*sscreen
,
222 struct radeon_surf
*surface
,
223 const struct pipe_resource
*ptex
,
224 enum radeon_surf_mode array_mode
,
225 unsigned pitch_in_bytes_override
,
229 bool is_flushed_depth
,
230 bool tc_compatible_htile
)
232 const struct util_format_description
*desc
=
233 util_format_description(ptex
->format
);
234 bool is_depth
, is_stencil
;
236 unsigned i
, bpe
, flags
= 0;
238 is_depth
= util_format_has_depth(desc
);
239 is_stencil
= util_format_has_stencil(desc
);
241 if (!is_flushed_depth
&&
242 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
243 bpe
= 4; /* stencil is allocated separately */
245 bpe
= util_format_get_blocksize(ptex
->format
);
246 assert(util_is_power_of_two_or_zero(bpe
));
249 if (!is_flushed_depth
&& is_depth
) {
250 flags
|= RADEON_SURF_ZBUFFER
;
252 if (tc_compatible_htile
&&
253 (sscreen
->info
.chip_class
>= GFX9
||
254 array_mode
== RADEON_SURF_MODE_2D
)) {
255 /* TC-compatible HTILE only supports Z32_FLOAT.
256 * GFX9 also supports Z16_UNORM.
257 * On VI, promote Z16 to Z32. DB->CB copies will convert
258 * the format for transfers.
260 if (sscreen
->info
.chip_class
== VI
)
263 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
267 flags
|= RADEON_SURF_SBUFFER
;
270 if (sscreen
->info
.chip_class
>= VI
&&
271 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
272 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
273 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
274 flags
|= RADEON_SURF_DISABLE_DCC
;
276 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
277 if (sscreen
->info
.family
== CHIP_STONEY
&&
278 bpe
== 16 && ptex
->nr_samples
>= 2)
279 flags
|= RADEON_SURF_DISABLE_DCC
;
281 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
282 if (sscreen
->info
.chip_class
== VI
&&
283 ptex
->nr_storage_samples
>= 4 &&
284 ptex
->array_size
> 1)
285 flags
|= RADEON_SURF_DISABLE_DCC
;
287 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
288 if (sscreen
->info
.chip_class
>= GFX9
&&
289 ptex
->nr_storage_samples
>= 4)
290 flags
|= RADEON_SURF_DISABLE_DCC
;
292 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
293 /* This should catch bugs in gallium users setting incorrect flags. */
294 assert(ptex
->nr_samples
<= 1 &&
295 ptex
->array_size
== 1 &&
297 ptex
->last_level
== 0 &&
298 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
300 flags
|= RADEON_SURF_SCANOUT
;
303 if (ptex
->bind
& PIPE_BIND_SHARED
)
304 flags
|= RADEON_SURF_SHAREABLE
;
306 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
307 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
308 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
310 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
311 array_mode
, surface
);
316 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
318 if (sscreen
->info
.chip_class
>= GFX9
) {
320 surface
->u
.gfx9
.surf_pitch
= pitch
;
321 surface
->u
.gfx9
.surf_slice_size
=
322 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
324 surface
->u
.gfx9
.surf_offset
= offset
;
327 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
328 surface
->u
.legacy
.level
[0].slice_size_dw
=
329 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
332 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
333 surface
->u
.legacy
.level
[i
].offset
+= offset
;
339 static void si_get_display_metadata(struct si_screen
*sscreen
,
340 struct radeon_surf
*surf
,
341 struct radeon_bo_metadata
*metadata
,
342 enum radeon_surf_mode
*array_mode
,
345 if (sscreen
->info
.chip_class
>= GFX9
) {
346 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
347 *array_mode
= RADEON_SURF_MODE_2D
;
349 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
351 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
352 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
354 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
356 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
357 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
358 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
361 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
362 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
363 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
364 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
365 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
366 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
368 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
369 *array_mode
= RADEON_SURF_MODE_2D
;
370 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
371 *array_mode
= RADEON_SURF_MODE_1D
;
373 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
375 *is_scanout
= metadata
->u
.legacy
.scanout
;
379 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
380 struct si_texture
*tex
)
382 struct si_screen
*sscreen
= sctx
->screen
;
383 struct pipe_context
*ctx
= &sctx
->b
;
385 if (ctx
== sscreen
->aux_context
)
386 mtx_lock(&sscreen
->aux_context_lock
);
388 unsigned n
= sctx
->num_decompress_calls
;
389 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
391 /* Flush only if any fast clear elimination took place. */
392 if (n
!= sctx
->num_decompress_calls
)
393 ctx
->flush(ctx
, NULL
, 0);
395 if (ctx
== sscreen
->aux_context
)
396 mtx_unlock(&sscreen
->aux_context_lock
);
399 void si_texture_discard_cmask(struct si_screen
*sscreen
,
400 struct si_texture
*tex
)
402 if (!tex
->cmask_buffer
)
405 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
408 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
409 tex
->dirty_level_mask
= 0;
411 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
413 if (tex
->cmask_buffer
!= &tex
->buffer
)
414 si_resource_reference(&tex
->cmask_buffer
, NULL
);
416 tex
->cmask_buffer
= NULL
;
418 /* Notify all contexts about the change. */
419 p_atomic_inc(&sscreen
->dirty_tex_counter
);
420 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
423 static bool si_can_disable_dcc(struct si_texture
*tex
)
425 /* We can't disable DCC if it can be written by another process. */
426 return tex
->dcc_offset
&&
427 (!tex
->buffer
.b
.is_shared
||
428 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
431 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
432 struct si_texture
*tex
)
434 if (!si_can_disable_dcc(tex
))
437 assert(tex
->dcc_separate_buffer
== NULL
);
442 /* Notify all contexts about the change. */
443 p_atomic_inc(&sscreen
->dirty_tex_counter
);
448 * Disable DCC for the texture. (first decompress, then discard metadata).
450 * There is unresolved multi-context synchronization issue between
451 * screen::aux_context and the current context. If applications do this with
452 * multiple contexts, it's already undefined behavior for them and we don't
453 * have to worry about that. The scenario is:
455 * If context 1 disables DCC and context 2 has queued commands that write
456 * to the texture via CB with DCC enabled, and the order of operations is
458 * context 2 queues draw calls rendering to the texture, but doesn't flush
459 * context 1 disables DCC and flushes
460 * context 1 & 2 reset descriptors and FB state
461 * context 2 flushes (new compressed tiles written by the draw calls)
462 * context 1 & 2 read garbage, because DCC is disabled, yet there are
465 * \param sctx the current context if you have one, or sscreen->aux_context
468 bool si_texture_disable_dcc(struct si_context
*sctx
,
469 struct si_texture
*tex
)
471 struct si_screen
*sscreen
= sctx
->screen
;
473 if (!sctx
->has_graphics
)
474 return si_texture_discard_dcc(sscreen
, tex
);
476 if (!si_can_disable_dcc(tex
))
479 if (&sctx
->b
== sscreen
->aux_context
)
480 mtx_lock(&sscreen
->aux_context_lock
);
482 /* Decompress DCC. */
483 si_decompress_dcc(sctx
, tex
);
484 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
486 if (&sctx
->b
== sscreen
->aux_context
)
487 mtx_unlock(&sscreen
->aux_context_lock
);
489 return si_texture_discard_dcc(sscreen
, tex
);
492 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
493 struct si_texture
*tex
,
494 unsigned new_bind_flag
,
495 bool invalidate_storage
)
497 struct pipe_screen
*screen
= sctx
->b
.screen
;
498 struct si_texture
*new_tex
;
499 struct pipe_resource templ
= tex
->buffer
.b
.b
;
502 templ
.bind
|= new_bind_flag
;
504 if (tex
->buffer
.b
.is_shared
)
507 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
508 if (tex
->surface
.is_linear
)
511 /* This fails with MSAA, depth, and compressed textures. */
512 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
513 RADEON_SURF_MODE_LINEAR_ALIGNED
)
517 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
521 /* Copy the pixels to the new texture. */
522 if (!invalidate_storage
) {
523 for (i
= 0; i
<= templ
.last_level
; i
++) {
527 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
528 util_num_layers(&templ
, i
), &box
);
530 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
531 &tex
->buffer
.b
.b
, i
, &box
);
535 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
536 si_texture_discard_cmask(sctx
->screen
, tex
);
537 si_texture_discard_dcc(sctx
->screen
, tex
);
540 /* Replace the structure fields of tex. */
541 tex
->buffer
.b
.b
.bind
= templ
.bind
;
542 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
543 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
544 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
545 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
546 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
547 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
548 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
549 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
551 tex
->surface
= new_tex
->surface
;
552 tex
->size
= new_tex
->size
;
553 si_texture_reference(&tex
->flushed_depth_texture
,
554 new_tex
->flushed_depth_texture
);
556 tex
->fmask_offset
= new_tex
->fmask_offset
;
557 tex
->cmask_offset
= new_tex
->cmask_offset
;
558 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
560 if (tex
->cmask_buffer
== &tex
->buffer
)
561 tex
->cmask_buffer
= NULL
;
563 si_resource_reference(&tex
->cmask_buffer
, NULL
);
565 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
566 tex
->cmask_buffer
= &tex
->buffer
;
568 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
570 tex
->dcc_offset
= new_tex
->dcc_offset
;
571 tex
->cb_color_info
= new_tex
->cb_color_info
;
572 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
573 sizeof(tex
->color_clear_value
));
574 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
576 tex
->htile_offset
= new_tex
->htile_offset
;
577 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
578 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
579 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
580 tex
->db_render_format
= new_tex
->db_render_format
;
581 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
582 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
583 tex
->depth_cleared
= new_tex
->depth_cleared
;
584 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
585 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
586 tex
->db_compatible
= new_tex
->db_compatible
;
587 tex
->can_sample_z
= new_tex
->can_sample_z
;
588 tex
->can_sample_s
= new_tex
->can_sample_s
;
590 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
591 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
592 si_resource_reference(&tex
->dcc_separate_buffer
,
593 new_tex
->dcc_separate_buffer
);
594 si_resource_reference(&tex
->last_dcc_separate_buffer
,
595 new_tex
->last_dcc_separate_buffer
);
597 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
598 assert(!tex
->htile_offset
);
599 assert(!tex
->cmask_buffer
);
600 assert(!tex
->surface
.fmask_size
);
601 assert(!tex
->dcc_offset
);
602 assert(!tex
->is_depth
);
605 si_texture_reference(&new_tex
, NULL
);
607 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
610 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
612 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
615 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
616 struct si_texture
*tex
)
618 struct radeon_surf
*surface
= &tex
->surface
;
619 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
620 struct radeon_bo_metadata md
;
622 memset(&md
, 0, sizeof(md
));
624 if (sscreen
->info
.chip_class
>= GFX9
) {
625 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
627 if (tex
->dcc_offset
&& !tex
->dcc_separate_buffer
) {
628 uint64_t dcc_offset
= tex
->dcc_offset
;
630 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
631 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
632 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
633 md
.u
.gfx9
.dcc_independent_64B
= 1;
636 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
637 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
638 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
639 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
640 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
641 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
642 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
643 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
644 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
645 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
646 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
647 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
650 assert(tex
->dcc_separate_buffer
== NULL
);
651 assert(tex
->surface
.fmask_size
== 0);
653 /* Metadata image format format version 1:
654 * [0] = 1 (metadata format identifier)
655 * [1] = (VENDOR_ID << 16) | PCI_ID
656 * [2:9] = image descriptor for the whole resource
657 * [2] is always 0, because the base address is cleared
658 * [9] is the DCC offset bits [39:8] from the beginning of
660 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
663 md
.metadata
[0] = 1; /* metadata image format version 1 */
665 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
666 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
668 static const unsigned char swizzle
[] = {
674 bool is_array
= util_texture_is_array(res
->target
);
677 si_make_texture_descriptor(sscreen
, tex
, true,
678 res
->target
, res
->format
,
679 swizzle
, 0, res
->last_level
, 0,
680 is_array
? res
->array_size
- 1 : 0,
681 res
->width0
, res
->height0
, res
->depth0
,
684 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
685 0, 0, tex
->surface
.blk_w
, false, desc
);
687 /* Clear the base address and set the relative DCC offset. */
689 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
690 desc
[7] = tex
->dcc_offset
>> 8;
692 /* Dwords [2:9] contain the image descriptor. */
693 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
694 md
.size_metadata
= 10 * 4;
696 /* Dwords [10:..] contain the mipmap level offsets. */
697 if (sscreen
->info
.chip_class
<= VI
) {
698 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
699 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
701 md
.size_metadata
+= (1 + res
->last_level
) * 4;
704 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
707 static void si_get_opaque_metadata(struct si_screen
*sscreen
,
708 struct si_texture
*tex
,
709 struct radeon_bo_metadata
*md
)
711 uint32_t *desc
= &md
->metadata
[2];
713 if (sscreen
->info
.chip_class
< VI
)
716 /* Return if DCC is enabled. The texture should be set up with it
719 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
720 md
->metadata
[0] != 0 &&
721 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
722 G_008F28_COMPRESSION_EN(desc
[6])) {
723 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
725 if (sscreen
->info
.chip_class
>= GFX9
) {
726 /* Fix up parameters for displayable DCC. Some state
727 * trackers don't set the SCANOUT flag when importing
728 * displayable images, so we have to recover the correct
731 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
732 G_008F24_META_PIPE_ALIGNED(desc
[5]);
733 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
734 G_008F24_META_RB_ALIGNED(desc
[5]);
736 /* If DCC is unaligned, this can only be a displayable image. */
737 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
738 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
739 tex
->surface
.is_displayable
= true;
744 /* Disable DCC. These are always set by texture_from_handle and must
750 static bool si_has_displayable_dcc(struct si_texture
*tex
)
752 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
754 if (sscreen
->info
.chip_class
<= VI
)
757 /* This needs a cache flush before scanout.
758 * (it can't be scanned out and rendered to simultaneously)
760 if (sscreen
->info
.use_display_dcc_unaligned
&&
762 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
763 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
769 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
770 struct pipe_context
*ctx
,
771 struct pipe_resource
*resource
,
772 struct winsys_handle
*whandle
,
775 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
776 struct si_context
*sctx
;
777 struct si_resource
*res
= si_resource(resource
);
778 struct si_texture
*tex
= (struct si_texture
*)resource
;
779 bool update_metadata
= false;
780 unsigned stride
, offset
, slice_size
;
783 ctx
= threaded_context_unwrap_sync(ctx
);
784 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
786 if (resource
->target
!= PIPE_BUFFER
) {
787 /* This is not supported now, but it might be required for OpenCL
788 * interop in the future.
790 if (resource
->nr_samples
> 1 || tex
->is_depth
)
793 /* Move a suballocated texture into a non-suballocated allocation. */
794 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
795 tex
->surface
.tile_swizzle
||
796 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
797 sscreen
->info
.has_local_buffers
&&
798 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
799 assert(!res
->b
.is_shared
);
800 si_reallocate_texture_inplace(sctx
, tex
,
801 PIPE_BIND_SHARED
, false);
803 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
804 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
805 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
806 assert(tex
->surface
.tile_swizzle
== 0);
809 /* Since shader image stores don't support DCC on VI,
810 * disable it for external clients that want write
813 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) ||
814 /* Displayable DCC requires an explicit flush. */
815 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
816 si_has_displayable_dcc(tex
))) {
817 if (si_texture_disable_dcc(sctx
, tex
)) {
818 update_metadata
= true;
819 /* si_texture_disable_dcc flushes the context */
824 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
825 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
826 /* Eliminate fast clear (both CMASK and DCC) */
827 si_eliminate_fast_color_clear(sctx
, tex
);
828 /* eliminate_fast_color_clear flushes the context */
831 /* Disable CMASK if flush_resource isn't going
834 if (tex
->cmask_buffer
)
835 si_texture_discard_cmask(sscreen
, tex
);
839 if (!res
->b
.is_shared
|| update_metadata
)
840 si_set_tex_bo_metadata(sscreen
, tex
);
842 if (sscreen
->info
.chip_class
>= GFX9
) {
843 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
844 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
846 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
848 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
849 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
851 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
854 /* Buffer exports are for the OpenCL interop. */
855 /* Move a suballocated buffer into a non-suballocated allocation. */
856 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
857 /* A DMABUF export always fails if the BO is local. */
858 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
859 sscreen
->info
.has_local_buffers
)) {
860 assert(!res
->b
.is_shared
);
862 /* Allocate a new buffer with PIPE_BIND_SHARED. */
863 struct pipe_resource templ
= res
->b
.b
;
864 templ
.bind
|= PIPE_BIND_SHARED
;
866 struct pipe_resource
*newb
=
867 screen
->resource_create(screen
, &templ
);
871 /* Copy the old buffer contents to the new one. */
873 u_box_1d(0, newb
->width0
, &box
);
874 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
877 /* Move the new buffer storage to the old pipe_resource. */
878 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
879 pipe_resource_reference(&newb
, NULL
);
881 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
882 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
892 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
894 if (res
->b
.is_shared
) {
895 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
898 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
899 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
900 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
902 res
->b
.is_shared
= true;
903 res
->external_usage
= usage
;
906 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
907 slice_size
, whandle
);
910 static void si_texture_destroy(struct pipe_screen
*screen
,
911 struct pipe_resource
*ptex
)
913 struct si_texture
*tex
= (struct si_texture
*)ptex
;
914 struct si_resource
*resource
= &tex
->buffer
;
916 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
918 if (tex
->cmask_buffer
!= &tex
->buffer
) {
919 si_resource_reference(&tex
->cmask_buffer
, NULL
);
921 pb_reference(&resource
->buf
, NULL
);
922 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
923 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
927 static const struct u_resource_vtbl si_texture_vtbl
;
929 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
930 struct si_texture
*tex
)
932 unsigned cl_width
, cl_height
, width
, height
;
933 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
934 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
936 assert(sscreen
->info
.chip_class
<= VI
);
938 tex
->surface
.htile_size
= 0;
940 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
941 !sscreen
->info
.htile_cmask_support_1d_tiling
)
944 /* Overalign HTILE on P2 configs to work around GPU hangs in
945 * piglit/depthstencil-render-miplevels 585.
947 * This has been confirmed to help Kabini & Stoney, where the hangs
948 * are always reproducible. I think I have seen the test hang
949 * on Carrizo too, though it was very rare there.
951 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
980 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
981 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
983 slice_elements
= (width
* height
) / (8 * 8);
984 slice_bytes
= slice_elements
* 4;
986 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
987 base_align
= num_pipes
* pipe_interleave_bytes
;
989 tex
->surface
.htile_alignment
= base_align
;
990 tex
->surface
.htile_size
=
991 util_num_layers(&tex
->buffer
.b
.b
, 0) *
992 align(slice_bytes
, base_align
);
995 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
996 struct si_texture
*tex
)
998 if (sscreen
->info
.chip_class
<= VI
&& !tex
->tc_compatible_htile
)
999 si_texture_get_htile_size(sscreen
, tex
);
1001 if (!tex
->surface
.htile_size
)
1004 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1005 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1008 void si_print_texture_info(struct si_screen
*sscreen
,
1009 struct si_texture
*tex
, struct u_log_context
*log
)
1013 /* Common parameters. */
1014 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1015 "blk_h=%u, array_size=%u, last_level=%u, "
1016 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1017 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1018 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1020 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1021 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1022 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1024 if (sscreen
->info
.chip_class
>= GFX9
) {
1025 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1026 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1027 tex
->surface
.surf_size
,
1028 tex
->surface
.u
.gfx9
.surf_slice_size
,
1029 tex
->surface
.surf_alignment
,
1030 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1031 tex
->surface
.u
.gfx9
.surf
.epitch
,
1032 tex
->surface
.u
.gfx9
.surf_pitch
);
1034 if (tex
->surface
.fmask_size
) {
1035 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1036 "alignment=%u, swmode=%u, epitch=%u\n",
1038 tex
->surface
.fmask_size
,
1039 tex
->surface
.fmask_alignment
,
1040 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1041 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1044 if (tex
->cmask_buffer
) {
1045 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1046 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1048 tex
->surface
.cmask_size
,
1049 tex
->surface
.cmask_alignment
,
1050 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1051 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1054 if (tex
->htile_offset
) {
1055 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1056 "rb_aligned=%u, pipe_aligned=%u\n",
1058 tex
->surface
.htile_size
,
1059 tex
->surface
.htile_alignment
,
1060 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1061 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1064 if (tex
->dcc_offset
) {
1065 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1066 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1067 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1068 tex
->surface
.dcc_alignment
,
1069 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1070 tex
->surface
.num_dcc_levels
);
1073 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1074 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1075 tex
->surface
.u
.gfx9
.stencil_offset
,
1076 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1077 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1082 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1083 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1084 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1085 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1086 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1087 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1089 if (tex
->surface
.fmask_size
)
1090 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1091 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1092 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1093 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1094 tex
->surface
.u
.legacy
.fmask
.bankh
,
1095 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1096 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1098 if (tex
->cmask_buffer
)
1099 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1100 "slice_tile_max=%u\n",
1101 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1102 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1104 if (tex
->htile_offset
)
1105 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1106 "alignment=%u, TC_compatible = %u\n",
1107 tex
->htile_offset
, tex
->surface
.htile_size
,
1108 tex
->surface
.htile_alignment
,
1109 tex
->tc_compatible_htile
);
1111 if (tex
->dcc_offset
) {
1112 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1113 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1114 tex
->surface
.dcc_alignment
);
1115 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1116 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1117 "fast_clear_size=%u\n",
1118 i
, i
< tex
->surface
.num_dcc_levels
,
1119 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1120 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1123 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1124 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1125 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1126 "mode=%u, tiling_index = %u\n",
1127 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1128 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1129 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1130 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1131 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1132 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1133 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1134 tex
->surface
.u
.legacy
.level
[i
].mode
,
1135 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1137 if (tex
->surface
.has_stencil
) {
1138 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1139 tex
->surface
.u
.legacy
.stencil_tile_split
);
1140 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1141 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1142 "slice_size=%"PRIu64
", npix_x=%u, "
1143 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1144 "mode=%u, tiling_index = %u\n",
1145 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1146 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1147 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1148 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1149 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1150 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1151 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1152 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1153 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1158 /* Common processing for si_texture_create and si_texture_from_handle */
1159 static struct si_texture
*
1160 si_texture_create_object(struct pipe_screen
*screen
,
1161 const struct pipe_resource
*base
,
1162 struct pb_buffer
*buf
,
1163 struct radeon_surf
*surface
)
1165 struct si_texture
*tex
;
1166 struct si_resource
*resource
;
1167 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1169 tex
= CALLOC_STRUCT(si_texture
);
1173 resource
= &tex
->buffer
;
1174 resource
->b
.b
= *base
;
1175 resource
->b
.b
.next
= NULL
;
1176 resource
->b
.vtbl
= &si_texture_vtbl
;
1177 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1178 resource
->b
.b
.screen
= screen
;
1180 /* don't include stencil-only formats which we don't support for rendering */
1181 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1183 tex
->surface
= *surface
;
1184 tex
->size
= tex
->surface
.surf_size
;
1186 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1187 (tex
->surface
.flags
&
1188 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1190 /* TC-compatible HTILE:
1191 * - VI only supports Z32_FLOAT.
1192 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1193 if (tex
->tc_compatible_htile
) {
1194 if (sscreen
->info
.chip_class
>= GFX9
&&
1195 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1196 tex
->db_render_format
= base
->format
;
1198 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1199 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1200 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1203 tex
->db_render_format
= base
->format
;
1206 /* Applies to GCN. */
1207 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1209 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1210 * between frames, so the only thing that can enable separate DCC
1211 * with DRI2 is multiple slow clears within a frame.
1213 tex
->ps_draw_ratio
= 0;
1215 if (tex
->is_depth
) {
1216 if (sscreen
->info
.chip_class
>= GFX9
) {
1217 tex
->can_sample_z
= true;
1218 tex
->can_sample_s
= true;
1220 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1221 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1224 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1225 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1226 tex
->db_compatible
= true;
1228 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1229 si_texture_allocate_htile(sscreen
, tex
);
1232 if (base
->nr_samples
> 1 &&
1234 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1235 /* Allocate FMASK. */
1236 tex
->fmask_offset
= align64(tex
->size
,
1237 tex
->surface
.fmask_alignment
);
1238 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1240 /* Allocate CMASK. */
1241 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1242 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1243 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1244 tex
->cmask_buffer
= &tex
->buffer
;
1246 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
)
1250 /* Shared textures must always set up DCC here.
1251 * If it's not present, it will be disabled by
1252 * apply_opaque_metadata later.
1254 if (tex
->surface
.dcc_size
&&
1255 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1256 (sscreen
->info
.use_display_dcc_unaligned
||
1257 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
))) {
1258 /* Add space for the DCC buffer. */
1259 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1260 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1264 /* Now create the backing buffer. */
1266 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1267 tex
->surface
.surf_alignment
);
1269 if (!si_alloc_resource(sscreen
, resource
))
1272 resource
->buf
= buf
;
1273 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1274 resource
->bo_size
= buf
->size
;
1275 resource
->bo_alignment
= buf
->alignment
;
1276 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1277 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1278 resource
->vram_usage
= buf
->size
;
1279 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1280 resource
->gart_usage
= buf
->size
;
1283 if (tex
->cmask_buffer
) {
1284 /* Initialize the cmask to 0xCC (= compressed state). */
1285 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1286 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1289 if (tex
->htile_offset
) {
1290 uint32_t clear_value
= 0;
1292 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1293 clear_value
= 0x0000030F;
1295 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1297 tex
->surface
.htile_size
,
1301 /* Initialize DCC only if the texture is not being imported. */
1302 if (!buf
&& tex
->dcc_offset
) {
1303 /* Clear DCC to black for all tiles with DCC enabled.
1305 * This fixes corruption in 3DMark Slingshot Extreme, which
1306 * uses uninitialized textures, causing corruption.
1308 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1309 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1310 /* Simple case - all tiles have DCC enabled. */
1311 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1313 tex
->surface
.dcc_size
,
1314 DCC_CLEAR_COLOR_0000
);
1315 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1316 /* Clear to uncompressed. Clearing this to black is complicated. */
1317 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1319 tex
->surface
.dcc_size
,
1322 /* GFX8: Initialize mipmap levels and multisamples separately. */
1323 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1324 /* Clearing this to black is complicated. */
1325 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1327 tex
->surface
.dcc_size
,
1330 /* Clear the enabled mipmap levels to black. */
1333 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1334 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1337 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1338 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1341 /* Mipmap levels with DCC. */
1343 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1344 tex
->dcc_offset
, size
,
1345 DCC_CLEAR_COLOR_0000
);
1347 /* Mipmap levels without DCC. */
1348 if (size
!= tex
->surface
.dcc_size
) {
1349 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1350 tex
->dcc_offset
+ size
,
1351 tex
->surface
.dcc_size
- size
,
1358 /* Initialize the CMASK base register value. */
1359 tex
->cmask_base_address_reg
=
1360 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1362 if (sscreen
->debug_flags
& DBG(VM
)) {
1363 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1364 tex
->buffer
.gpu_address
,
1365 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1366 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1367 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1370 if (sscreen
->debug_flags
& DBG(TEX
)) {
1372 struct u_log_context log
;
1373 u_log_context_init(&log
);
1374 si_print_texture_info(sscreen
, tex
, &log
);
1375 u_log_new_page_print(&log
, stdout
);
1377 u_log_context_destroy(&log
);
1387 static enum radeon_surf_mode
1388 si_choose_tiling(struct si_screen
*sscreen
,
1389 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1391 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1392 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1393 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1394 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1396 /* MSAA resources must be 2D tiled. */
1397 if (templ
->nr_samples
> 1)
1398 return RADEON_SURF_MODE_2D
;
1400 /* Transfer resources should be linear. */
1401 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1402 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1404 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1405 * which requires 2D tiling.
1407 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1408 return RADEON_SURF_MODE_2D
;
1410 /* Handle common candidates for the linear mode.
1411 * Compressed textures and DB surfaces must always be tiled.
1413 if (!force_tiling
&&
1414 !is_depth_stencil
&&
1415 !util_format_is_compressed(templ
->format
)) {
1416 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1417 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1419 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1420 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1421 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1423 /* Cursors are linear on SI.
1424 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1425 if (templ
->bind
& PIPE_BIND_CURSOR
)
1426 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1428 if (templ
->bind
& PIPE_BIND_LINEAR
)
1429 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1431 /* Textures with a very small height are recommended to be linear. */
1432 if (templ
->target
== PIPE_TEXTURE_1D
||
1433 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1434 /* Only very thin and long 2D textures should benefit from
1435 * linear_aligned. */
1436 (templ
->width0
> 8 && templ
->height0
<= 2))
1437 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1439 /* Textures likely to be mapped often. */
1440 if (templ
->usage
== PIPE_USAGE_STAGING
||
1441 templ
->usage
== PIPE_USAGE_STREAM
)
1442 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1445 /* Make small textures 1D tiled. */
1446 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1447 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1448 return RADEON_SURF_MODE_1D
;
1450 /* The allocator will switch to 1D if needed. */
1451 return RADEON_SURF_MODE_2D
;
1454 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1455 const struct pipe_resource
*templ
)
1457 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1458 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1460 if (templ
->nr_samples
>= 2) {
1461 /* This is hackish (overwriting the const pipe_resource template),
1462 * but should be harmless and state trackers can also see
1463 * the overriden number of samples in the created pipe_resource.
1465 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1466 ((struct pipe_resource
*)templ
)->nr_samples
=
1467 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1468 sscreen
->eqaa_force_z_samples
;
1469 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1470 ((struct pipe_resource
*)templ
)->nr_samples
=
1471 sscreen
->eqaa_force_coverage_samples
;
1472 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1473 sscreen
->eqaa_force_color_samples
;
1477 struct radeon_surf surface
= {0};
1478 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1479 bool tc_compatible_htile
=
1480 sscreen
->info
.chip_class
>= VI
&&
1481 /* There are issues with TC-compatible HTILE on Tonga (and
1482 * Iceland is the same design), and documented bug workarounds
1483 * don't help. For example, this fails:
1484 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1486 sscreen
->info
.family
!= CHIP_TONGA
&&
1487 sscreen
->info
.family
!= CHIP_ICELAND
&&
1488 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1489 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1490 !is_flushed_depth
&&
1491 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1495 r
= si_init_surface(sscreen
, &surface
, templ
,
1496 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1497 0, 0, false, false, is_flushed_depth
,
1498 tc_compatible_htile
);
1503 return (struct pipe_resource
*)
1504 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1507 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1508 const struct pipe_resource
*templ
,
1509 struct pb_buffer
*buf
,
1515 enum radeon_surf_mode array_mode
;
1516 struct radeon_surf surface
= {};
1517 struct radeon_bo_metadata metadata
= {};
1518 struct si_texture
*tex
;
1523 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1524 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1525 &array_mode
, &is_scanout
);
1528 * The bo metadata is unset for un-dedicated images. So we fall
1529 * back to linear. See answer to question 5 of the
1530 * VK_KHX_external_memory spec for some details.
1532 * It is possible that this case isn't going to work if the
1533 * surface pitch isn't correctly aligned by default.
1535 * In order to support it correctly we require multi-image
1536 * metadata to be syncrhonized between radv and radeonsi. The
1537 * semantics of associating multiple image metadata to a memory
1538 * object on the vulkan export side are not concretely defined
1541 * All the use cases we are aware of at the moment for memory
1542 * objects use dedicated allocations. So lets keep the initial
1543 * implementation simple.
1545 * A possible alternative is to attempt to reconstruct the
1546 * tiling information when the TexParameter TEXTURE_TILING_EXT
1549 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1553 r
= si_init_surface(sscreen
, &surface
, templ
,
1554 array_mode
, stride
, offset
, true, is_scanout
,
1559 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1563 tex
->buffer
.b
.is_shared
= true;
1564 tex
->buffer
.external_usage
= usage
;
1566 si_get_opaque_metadata(sscreen
, tex
, &metadata
);
1568 /* Displayable DCC requires an explicit flush. */
1570 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1571 si_has_displayable_dcc(tex
)) {
1572 /* TODO: do we need to decompress DCC? */
1573 if (si_texture_discard_dcc(sscreen
, tex
)) {
1574 /* Update BO metadata after disabling DCC. */
1575 si_set_tex_bo_metadata(sscreen
, tex
);
1579 assert(tex
->surface
.tile_swizzle
== 0);
1580 return &tex
->buffer
.b
.b
;
1583 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1584 const struct pipe_resource
*templ
,
1585 struct winsys_handle
*whandle
,
1588 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1589 struct pb_buffer
*buf
= NULL
;
1590 unsigned stride
= 0, offset
= 0;
1592 /* Support only 2D textures without mipmaps */
1593 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1594 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1597 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1598 sscreen
->info
.max_alignment
,
1603 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1604 offset
, usage
, true);
1607 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1608 struct pipe_resource
*texture
,
1609 struct si_texture
**staging
)
1611 struct si_texture
*tex
= (struct si_texture
*)texture
;
1612 struct pipe_resource resource
;
1613 struct si_texture
**flushed_depth_texture
= staging
?
1614 staging
: &tex
->flushed_depth_texture
;
1615 enum pipe_format pipe_format
= texture
->format
;
1618 if (tex
->flushed_depth_texture
)
1619 return true; /* it's ready */
1621 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1622 switch (pipe_format
) {
1623 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1624 /* Save memory by not allocating the S plane. */
1625 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1627 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1628 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1629 /* Save memory bandwidth by not copying the
1630 * stencil part during flush.
1632 * This potentially increases memory bandwidth
1633 * if an application uses both Z and S texturing
1634 * simultaneously (a flushed Z24S8 texture
1635 * would be stored compactly), but how often
1636 * does that really happen?
1638 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1642 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1643 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1645 /* DB->CB copies to an 8bpp surface don't work. */
1646 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1650 memset(&resource
, 0, sizeof(resource
));
1651 resource
.target
= texture
->target
;
1652 resource
.format
= pipe_format
;
1653 resource
.width0
= texture
->width0
;
1654 resource
.height0
= texture
->height0
;
1655 resource
.depth0
= texture
->depth0
;
1656 resource
.array_size
= texture
->array_size
;
1657 resource
.last_level
= texture
->last_level
;
1658 resource
.nr_samples
= texture
->nr_samples
;
1659 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1660 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1661 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1664 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1666 *flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1667 if (*flushed_depth_texture
== NULL
) {
1668 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1675 * Initialize the pipe_resource descriptor to be of the same size as the box,
1676 * which is supposed to hold a subregion of the texture "orig" at the given
1679 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1680 struct pipe_resource
*orig
,
1681 const struct pipe_box
*box
,
1682 unsigned level
, unsigned flags
)
1684 memset(res
, 0, sizeof(*res
));
1685 res
->format
= orig
->format
;
1686 res
->width0
= box
->width
;
1687 res
->height0
= box
->height
;
1689 res
->array_size
= 1;
1690 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1693 /* We must set the correct texture target and dimensions for a 3D box. */
1694 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1695 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1696 res
->array_size
= box
->depth
;
1698 res
->target
= PIPE_TEXTURE_2D
;
1702 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1703 struct si_texture
*tex
,
1704 unsigned transfer_usage
,
1705 const struct pipe_box
*box
)
1707 return !tex
->buffer
.b
.is_shared
&&
1708 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1709 tex
->buffer
.b
.b
.last_level
== 0 &&
1710 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1711 box
->x
, box
->y
, box
->z
,
1712 box
->width
, box
->height
,
1716 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1717 struct si_texture
*tex
)
1719 struct si_screen
*sscreen
= sctx
->screen
;
1721 /* There is no point in discarding depth and tiled buffers. */
1722 assert(!tex
->is_depth
);
1723 assert(tex
->surface
.is_linear
);
1725 /* Reallocate the buffer in the same pipe_resource. */
1726 si_alloc_resource(sscreen
, &tex
->buffer
);
1728 /* Initialize the CMASK base address (needed even without CMASK). */
1729 tex
->cmask_base_address_reg
=
1730 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1732 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1734 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1737 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1738 struct pipe_resource
*texture
,
1741 const struct pipe_box
*box
,
1742 struct pipe_transfer
**ptransfer
)
1744 struct si_context
*sctx
= (struct si_context
*)ctx
;
1745 struct si_texture
*tex
= (struct si_texture
*)texture
;
1746 struct si_transfer
*trans
;
1747 struct si_resource
*buf
;
1748 unsigned offset
= 0;
1750 bool use_staging_texture
= false;
1752 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1753 assert(box
->width
&& box
->height
&& box
->depth
);
1755 /* Depth textures use staging unconditionally. */
1756 if (!tex
->is_depth
) {
1757 /* Degrade the tile mode if we get too many transfers on APUs.
1758 * On dGPUs, the staging texture is always faster.
1759 * Only count uploads that are at least 4x4 pixels large.
1761 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1763 box
->width
>= 4 && box
->height
>= 4 &&
1764 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1765 bool can_invalidate
=
1766 si_can_invalidate_texture(sctx
->screen
, tex
,
1769 si_reallocate_texture_inplace(sctx
, tex
,
1774 /* Tiled textures need to be converted into a linear texture for CPU
1775 * access. The staging texture is always linear and is placed in GART.
1777 * Reading from VRAM or GTT WC is slow, always use the staging
1778 * texture in this case.
1780 * Use the staging texture for uploads if the underlying BO
1783 if (!tex
->surface
.is_linear
)
1784 use_staging_texture
= true;
1785 else if (usage
& PIPE_TRANSFER_READ
)
1786 use_staging_texture
=
1787 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1788 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1789 /* Write & linear only: */
1790 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1791 RADEON_USAGE_READWRITE
) ||
1792 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1793 RADEON_USAGE_READWRITE
)) {
1795 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1797 si_texture_invalidate_storage(sctx
, tex
);
1799 use_staging_texture
= true;
1803 trans
= CALLOC_STRUCT(si_transfer
);
1806 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1807 trans
->b
.b
.level
= level
;
1808 trans
->b
.b
.usage
= usage
;
1809 trans
->b
.b
.box
= *box
;
1811 if (tex
->is_depth
) {
1812 struct si_texture
*staging_depth
;
1814 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
1815 /* MSAA depth buffers need to be converted to single sample buffers.
1817 * Mapping MSAA depth buffers can occur if ReadPixels is called
1818 * with a multisample GLX visual.
1820 * First downsample the depth buffer to a temporary texture,
1821 * then decompress the temporary one to staging.
1823 * Only the region being mapped is transfered.
1825 struct pipe_resource resource
;
1827 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1829 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1830 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1834 if (usage
& PIPE_TRANSFER_READ
) {
1835 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1837 PRINT_ERR("failed to create a temporary depth texture\n");
1841 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1842 si_blit_decompress_depth(ctx
, (struct si_texture
*)temp
, staging_depth
,
1843 0, 0, 0, box
->depth
, 0, 0);
1844 pipe_resource_reference(&temp
, NULL
);
1847 /* Just get the strides. */
1848 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1850 &trans
->b
.b
.layer_stride
);
1852 /* XXX: only readback the rectangle which is being mapped? */
1853 /* XXX: when discard is true, no need to read back from depth texture */
1854 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1855 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1859 si_blit_decompress_depth(ctx
, tex
, staging_depth
,
1861 box
->z
, box
->z
+ box
->depth
- 1,
1864 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1867 &trans
->b
.b
.layer_stride
);
1870 trans
->staging
= &staging_depth
->buffer
;
1871 buf
= trans
->staging
;
1872 } else if (use_staging_texture
) {
1873 struct pipe_resource resource
;
1874 struct si_texture
*staging
;
1876 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1877 SI_RESOURCE_FLAG_TRANSFER
);
1878 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1879 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1881 /* Create the temporary texture. */
1882 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1884 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1887 trans
->staging
= &staging
->buffer
;
1889 /* Just get the strides. */
1890 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1892 &trans
->b
.b
.layer_stride
);
1894 if (usage
& PIPE_TRANSFER_READ
)
1895 si_copy_to_staging_texture(ctx
, trans
);
1897 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1899 buf
= trans
->staging
;
1901 /* the resource is mapped directly */
1902 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1904 &trans
->b
.b
.layer_stride
);
1908 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1909 * we don't run out of the CPU address space.
1911 if (sizeof(void*) == 4)
1912 usage
|= RADEON_TRANSFER_TEMPORARY
;
1914 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1917 *ptransfer
= &trans
->b
.b
;
1918 return map
+ offset
;
1921 si_resource_reference(&trans
->staging
, NULL
);
1922 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1927 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1928 struct pipe_transfer
* transfer
)
1930 struct si_context
*sctx
= (struct si_context
*)ctx
;
1931 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1932 struct pipe_resource
*texture
= transfer
->resource
;
1933 struct si_texture
*tex
= (struct si_texture
*)texture
;
1935 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1936 * we don't run out of the CPU address space.
1938 if (sizeof(void*) == 4) {
1939 struct si_resource
*buf
=
1940 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1942 sctx
->ws
->buffer_unmap(buf
->buf
);
1945 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
) {
1946 if (tex
->is_depth
&& tex
->buffer
.b
.b
.nr_samples
<= 1) {
1947 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1948 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1949 &stransfer
->staging
->b
.b
, transfer
->level
,
1952 si_copy_from_staging_texture(ctx
, stransfer
);
1956 if (stransfer
->staging
) {
1957 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1958 si_resource_reference(&stransfer
->staging
, NULL
);
1961 /* Heuristic for {upload, draw, upload, draw, ..}:
1963 * Flush the gfx IB if we've allocated too much texture storage.
1965 * The idea is that we don't want to build IBs that use too much
1966 * memory and put pressure on the kernel memory manager and we also
1967 * want to make temporary and invalidated buffers go idle ASAP to
1968 * decrease the total memory usage or make them reusable. The memory
1969 * usage will be slightly higher than given here because of the buffer
1970 * cache in the winsys.
1972 * The result is that the kernel memory manager is never a bottleneck.
1974 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1975 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1976 sctx
->num_alloc_tex_transfer_bytes
= 0;
1979 pipe_resource_reference(&transfer
->resource
, NULL
);
1983 static const struct u_resource_vtbl si_texture_vtbl
=
1985 NULL
, /* get_handle */
1986 si_texture_destroy
, /* resource_destroy */
1987 si_texture_transfer_map
, /* transfer_map */
1988 u_default_transfer_flush_region
, /* transfer_flush_region */
1989 si_texture_transfer_unmap
, /* transfer_unmap */
1992 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1994 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1995 enum pipe_format format2
)
1997 const struct util_format_description
*desc1
, *desc2
;
1999 /* No format change - exit early. */
2000 if (format1
== format2
)
2003 format1
= si_simplify_cb_format(format1
);
2004 format2
= si_simplify_cb_format(format2
);
2006 /* Check again after format adjustments. */
2007 if (format1
== format2
)
2010 desc1
= util_format_description(format1
);
2011 desc2
= util_format_description(format2
);
2013 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2014 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2017 /* Float and non-float are totally incompatible. */
2018 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2019 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2022 /* Channel sizes must match across DCC formats.
2023 * Comparing just the first 2 channels should be enough.
2025 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2026 (desc1
->nr_channels
>= 2 &&
2027 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2030 /* Everything below is not needed if the driver never uses the DCC
2031 * clear code with the value of 1.
2034 /* If the clear values are all 1 or all 0, this constraint can be
2036 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
2039 /* Channel types must match if the clear value of 1 is used.
2040 * The type categories are only float, signed, unsigned.
2041 * NORM and INT are always compatible.
2043 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2044 (desc1
->nr_channels
>= 2 &&
2045 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2051 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2053 enum pipe_format view_format
)
2055 struct si_texture
*stex
= (struct si_texture
*)tex
;
2057 return vi_dcc_enabled(stex
, level
) &&
2058 !vi_dcc_formats_compatible(tex
->format
, view_format
);
2061 /* This can't be merged with the above function, because
2062 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2063 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2064 struct pipe_resource
*tex
,
2066 enum pipe_format view_format
)
2068 struct si_texture
*stex
= (struct si_texture
*)tex
;
2070 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2071 if (!si_texture_disable_dcc(sctx
, stex
))
2072 si_decompress_dcc(sctx
, stex
);
2075 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2076 struct pipe_resource
*texture
,
2077 const struct pipe_surface
*templ
,
2078 unsigned width0
, unsigned height0
,
2079 unsigned width
, unsigned height
)
2081 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2086 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2087 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2089 pipe_reference_init(&surface
->base
.reference
, 1);
2090 pipe_resource_reference(&surface
->base
.texture
, texture
);
2091 surface
->base
.context
= pipe
;
2092 surface
->base
.format
= templ
->format
;
2093 surface
->base
.width
= width
;
2094 surface
->base
.height
= height
;
2095 surface
->base
.u
= templ
->u
;
2097 surface
->width0
= width0
;
2098 surface
->height0
= height0
;
2100 surface
->dcc_incompatible
=
2101 texture
->target
!= PIPE_BUFFER
&&
2102 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2104 return &surface
->base
;
2107 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2108 struct pipe_resource
*tex
,
2109 const struct pipe_surface
*templ
)
2111 unsigned level
= templ
->u
.tex
.level
;
2112 unsigned width
= u_minify(tex
->width0
, level
);
2113 unsigned height
= u_minify(tex
->height0
, level
);
2114 unsigned width0
= tex
->width0
;
2115 unsigned height0
= tex
->height0
;
2117 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2118 const struct util_format_description
*tex_desc
2119 = util_format_description(tex
->format
);
2120 const struct util_format_description
*templ_desc
2121 = util_format_description(templ
->format
);
2123 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2125 /* Adjust size of surface if and only if the block width or
2126 * height is changed. */
2127 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2128 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2129 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2130 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2132 width
= nblks_x
* templ_desc
->block
.width
;
2133 height
= nblks_y
* templ_desc
->block
.height
;
2135 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2136 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2140 return si_create_surface_custom(pipe
, tex
, templ
,
2145 static void si_surface_destroy(struct pipe_context
*pipe
,
2146 struct pipe_surface
*surface
)
2148 pipe_resource_reference(&surface
->texture
, NULL
);
2152 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2154 const struct util_format_description
*desc
= util_format_description(format
);
2156 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2158 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2159 return V_028C70_SWAP_STD
;
2161 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2164 switch (desc
->nr_channels
) {
2166 if (HAS_SWIZZLE(0,X
))
2167 return V_028C70_SWAP_STD
; /* X___ */
2168 else if (HAS_SWIZZLE(3,X
))
2169 return V_028C70_SWAP_ALT_REV
; /* ___X */
2172 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2173 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2174 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2175 return V_028C70_SWAP_STD
; /* XY__ */
2176 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2177 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2178 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2180 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2181 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2182 return V_028C70_SWAP_ALT
; /* X__Y */
2183 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2184 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2187 if (HAS_SWIZZLE(0,X
))
2188 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2189 else if (HAS_SWIZZLE(0,Z
))
2190 return V_028C70_SWAP_STD_REV
; /* ZYX */
2193 /* check the middle channels, the 1st and 4th channel can be NONE */
2194 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2195 return V_028C70_SWAP_STD
; /* XYZW */
2196 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2197 return V_028C70_SWAP_STD_REV
; /* WZYX */
2198 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2199 return V_028C70_SWAP_ALT
; /* ZYXW */
2200 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2203 return V_028C70_SWAP_ALT_REV
;
2205 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2212 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2214 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2219 if (sctx
->dcc_stats
[slot
].query_active
)
2220 vi_separate_dcc_stop_query(sctx
,
2221 sctx
->dcc_stats
[slot
].tex
);
2223 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2224 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2225 sctx
->b
.destroy_query(&sctx
->b
,
2226 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2227 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2230 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2234 * Return the per-context slot where DCC statistics queries for the texture live.
2236 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2237 struct si_texture
*tex
)
2239 int i
, empty_slot
= -1;
2241 /* Remove zombie textures (textures kept alive by this array only). */
2242 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2243 if (sctx
->dcc_stats
[i
].tex
&&
2244 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2245 vi_dcc_clean_up_context_slot(sctx
, i
);
2247 /* Find the texture. */
2248 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2249 /* Return if found. */
2250 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2251 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2255 /* Record the first seen empty slot. */
2256 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2260 /* Not found. Remove the oldest member to make space in the array. */
2261 if (empty_slot
== -1) {
2262 int oldest_slot
= 0;
2264 /* Find the oldest slot. */
2265 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2266 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2267 sctx
->dcc_stats
[i
].last_use_timestamp
)
2270 /* Clean up the oldest slot. */
2271 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2272 empty_slot
= oldest_slot
;
2275 /* Add the texture to the new slot. */
2276 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2277 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2281 static struct pipe_query
*
2282 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2284 struct si_query_hw
*query
= (struct si_query_hw
*)
2285 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2287 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2288 return (struct pipe_query
*)query
;
2292 * Called when binding a color buffer.
2294 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2295 struct si_texture
*tex
)
2297 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2299 assert(!sctx
->dcc_stats
[i
].query_active
);
2301 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2302 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2304 /* begin or resume the query */
2305 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2306 sctx
->dcc_stats
[i
].query_active
= true;
2310 * Called when unbinding a color buffer.
2312 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2313 struct si_texture
*tex
)
2315 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2317 assert(sctx
->dcc_stats
[i
].query_active
);
2318 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2320 /* pause or end the query */
2321 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2322 sctx
->dcc_stats
[i
].query_active
= false;
2325 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2327 /* The minimum number of fullscreen draws per frame that is required
2329 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2332 /* Called by fast clear. */
2333 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2334 struct si_texture
*tex
)
2336 /* The intent is to use this with shared displayable back buffers,
2337 * but it's not strictly limited only to them.
2339 if (!tex
->buffer
.b
.is_shared
||
2340 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2341 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2342 tex
->buffer
.b
.b
.last_level
> 0 ||
2343 !tex
->surface
.dcc_size
||
2344 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2345 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2348 assert(sctx
->chip_class
>= VI
);
2350 if (tex
->dcc_offset
)
2351 return; /* already enabled */
2353 /* Enable the DCC stat gathering. */
2354 if (!tex
->dcc_gather_statistics
) {
2355 tex
->dcc_gather_statistics
= true;
2356 vi_separate_dcc_start_query(sctx
, tex
);
2359 if (!vi_should_enable_separate_dcc(tex
))
2360 return; /* stats show that DCC decompression is too expensive */
2362 assert(tex
->surface
.num_dcc_levels
);
2363 assert(!tex
->dcc_separate_buffer
);
2365 si_texture_discard_cmask(sctx
->screen
, tex
);
2367 /* Get a DCC buffer. */
2368 if (tex
->last_dcc_separate_buffer
) {
2369 assert(tex
->dcc_gather_statistics
);
2370 assert(!tex
->dcc_separate_buffer
);
2371 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2372 tex
->last_dcc_separate_buffer
= NULL
;
2374 tex
->dcc_separate_buffer
=
2375 si_aligned_buffer_create(sctx
->b
.screen
,
2376 SI_RESOURCE_FLAG_UNMAPPABLE
,
2378 tex
->surface
.dcc_size
,
2379 tex
->surface
.dcc_alignment
);
2380 if (!tex
->dcc_separate_buffer
)
2384 /* dcc_offset is the absolute GPUVM address. */
2385 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2387 /* no need to flag anything since this is called by fast clear that
2388 * flags framebuffer state
2393 * Called by pipe_context::flush_resource, the place where DCC decompression
2396 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2397 struct si_texture
*tex
)
2399 struct si_context
*sctx
= (struct si_context
*)ctx
;
2400 struct pipe_query
*tmp
;
2401 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2402 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2403 bool disable
= false;
2405 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2406 union pipe_query_result result
;
2408 /* Read the results. */
2409 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2410 ctx
->get_query_result(ctx
, query
,
2412 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2414 /* Compute the approximate number of fullscreen draws. */
2415 tex
->ps_draw_ratio
=
2416 result
.pipeline_statistics
.ps_invocations
/
2417 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2418 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2420 disable
= tex
->dcc_separate_buffer
&&
2421 !vi_should_enable_separate_dcc(tex
);
2424 tex
->num_slow_clears
= 0;
2426 /* stop the statistics query for ps_stats[0] */
2428 vi_separate_dcc_stop_query(sctx
, tex
);
2430 /* Move the queries in the queue by one. */
2431 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2432 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2433 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2434 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2436 /* create and start a new query as ps_stats[0] */
2438 vi_separate_dcc_start_query(sctx
, tex
);
2441 assert(!tex
->last_dcc_separate_buffer
);
2442 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2443 tex
->dcc_separate_buffer
= NULL
;
2444 tex
->dcc_offset
= 0;
2445 /* no need to flag anything since this is called after
2446 * decompression that re-sets framebuffer state
2451 static struct pipe_memory_object
*
2452 si_memobj_from_handle(struct pipe_screen
*screen
,
2453 struct winsys_handle
*whandle
,
2456 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2457 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2458 struct pb_buffer
*buf
= NULL
;
2459 uint32_t stride
, offset
;
2464 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2465 sscreen
->info
.max_alignment
,
2472 memobj
->b
.dedicated
= dedicated
;
2474 memobj
->stride
= stride
;
2476 return (struct pipe_memory_object
*)memobj
;
2481 si_memobj_destroy(struct pipe_screen
*screen
,
2482 struct pipe_memory_object
*_memobj
)
2484 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2486 pb_reference(&memobj
->buf
, NULL
);
2490 static struct pipe_resource
*
2491 si_texture_from_memobj(struct pipe_screen
*screen
,
2492 const struct pipe_resource
*templ
,
2493 struct pipe_memory_object
*_memobj
,
2496 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2497 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2498 struct pipe_resource
*tex
=
2499 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2500 memobj
->stride
, offset
,
2501 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2502 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2503 memobj
->b
.dedicated
);
2507 /* si_texture_from_winsys_buffer doesn't increment refcount of
2508 * memobj->buf, so increment it here.
2510 struct pb_buffer
*buf
= NULL
;
2511 pb_reference(&buf
, memobj
->buf
);
2515 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2516 struct pipe_resource
*resource
,
2519 struct si_texture
*tex
= (struct si_texture
*)resource
;
2521 /* Buffers only support the linear flag. */
2522 if (resource
->target
== PIPE_BUFFER
)
2523 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2525 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2528 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2531 /* TODO: PIPE_BIND_CURSOR - do we care? */
2535 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2537 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2538 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2539 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2540 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2541 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2542 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2545 void si_init_context_texture_functions(struct si_context
*sctx
)
2547 sctx
->b
.create_surface
= si_create_surface
;
2548 sctx
->b
.surface_destroy
= si_surface_destroy
;