2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include "amd/addrlib/inc/addrinterface.h"
42 static enum radeon_surf_mode
43 si_choose_tiling(struct si_screen
*sscreen
,
44 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
47 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
48 struct si_texture
*dst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct si_texture
*src
,
53 const struct pipe_box
*src_box
)
58 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
63 dst
->buffer
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (src
->is_depth
|| dst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(src
, src_level
) ||
78 vi_dcc_enabled(dst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 si_texture_discard_cmask(sctx
->screen
, dst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
99 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
101 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
145 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 if (util_format_is_compressed(dst
->format
)) {
177 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
178 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
181 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
182 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
186 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
187 struct si_texture
*tex
, unsigned level
,
188 const struct pipe_box
*box
,
190 unsigned *layer_stride
)
192 if (sscreen
->info
.chip_class
>= GFX9
) {
193 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
194 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
199 /* Each texture is an array of slices. Each slice is an array
200 * of mipmap levels. */
201 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
202 tex
->surface
.u
.gfx9
.offset
[level
] +
203 (box
->y
/ tex
->surface
.blk_h
*
204 tex
->surface
.u
.gfx9
.surf_pitch
+
205 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
207 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
209 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
210 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
213 return tex
->surface
.u
.legacy
.level
[level
].offset
;
215 /* Each texture is an array of mipmap levels. Each level is
216 * an array of slices. */
217 return tex
->surface
.u
.legacy
.level
[level
].offset
+
218 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
219 (box
->y
/ tex
->surface
.blk_h
*
220 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
221 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
225 static int si_init_surface(struct si_screen
*sscreen
,
226 struct radeon_surf
*surface
,
227 const struct pipe_resource
*ptex
,
228 enum radeon_surf_mode array_mode
,
229 unsigned pitch_in_bytes_override
,
233 bool is_flushed_depth
,
234 bool tc_compatible_htile
)
236 const struct util_format_description
*desc
=
237 util_format_description(ptex
->format
);
238 bool is_depth
, is_stencil
;
240 unsigned i
, bpe
, flags
= 0;
242 is_depth
= util_format_has_depth(desc
);
243 is_stencil
= util_format_has_stencil(desc
);
245 if (!is_flushed_depth
&&
246 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
247 bpe
= 4; /* stencil is allocated separately */
249 bpe
= util_format_get_blocksize(ptex
->format
);
250 assert(util_is_power_of_two_or_zero(bpe
));
253 if (!is_flushed_depth
&& is_depth
) {
254 flags
|= RADEON_SURF_ZBUFFER
;
256 if (tc_compatible_htile
&&
257 (sscreen
->info
.chip_class
>= GFX9
||
258 array_mode
== RADEON_SURF_MODE_2D
)) {
259 /* TC-compatible HTILE only supports Z32_FLOAT.
260 * GFX9 also supports Z16_UNORM.
261 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
262 * the format for transfers.
264 if (sscreen
->info
.chip_class
== GFX8
)
267 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
271 flags
|= RADEON_SURF_SBUFFER
;
274 if (sscreen
->info
.chip_class
>= GFX8
&&
275 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
276 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
277 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
278 flags
|= RADEON_SURF_DISABLE_DCC
;
280 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
281 if (sscreen
->info
.family
== CHIP_STONEY
&&
282 bpe
== 16 && ptex
->nr_samples
>= 2)
283 flags
|= RADEON_SURF_DISABLE_DCC
;
285 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
286 if (sscreen
->info
.chip_class
== GFX8
&&
287 ptex
->nr_storage_samples
>= 4 &&
288 ptex
->array_size
> 1)
289 flags
|= RADEON_SURF_DISABLE_DCC
;
291 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
292 if (sscreen
->info
.chip_class
== GFX9
&&
293 ptex
->nr_storage_samples
>= 4)
294 flags
|= RADEON_SURF_DISABLE_DCC
;
296 /* TODO: GFX10: DCC causes corruption with MSAA. */
297 if (sscreen
->info
.chip_class
>= GFX10
&&
298 ptex
->nr_storage_samples
>= 2)
299 flags
|= RADEON_SURF_DISABLE_DCC
;
301 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
302 /* This should catch bugs in gallium users setting incorrect flags. */
303 assert(ptex
->nr_samples
<= 1 &&
304 ptex
->array_size
== 1 &&
306 ptex
->last_level
== 0 &&
307 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
309 flags
|= RADEON_SURF_SCANOUT
;
312 if (ptex
->bind
& PIPE_BIND_SHARED
)
313 flags
|= RADEON_SURF_SHAREABLE
;
315 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
316 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
317 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
319 if (sscreen
->info
.chip_class
>= GFX10
&&
320 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
321 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
322 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
325 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
326 array_mode
, surface
);
331 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
333 if (sscreen
->info
.chip_class
>= GFX9
) {
335 surface
->u
.gfx9
.surf_pitch
= pitch
;
336 surface
->u
.gfx9
.surf_slice_size
=
337 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
339 surface
->u
.gfx9
.surf_offset
= offset
;
342 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
343 surface
->u
.legacy
.level
[0].slice_size_dw
=
344 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
347 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
348 surface
->u
.legacy
.level
[i
].offset
+= offset
;
354 static void si_get_display_metadata(struct si_screen
*sscreen
,
355 struct radeon_surf
*surf
,
356 struct radeon_bo_metadata
*metadata
,
357 enum radeon_surf_mode
*array_mode
,
360 if (sscreen
->info
.chip_class
>= GFX9
) {
361 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
362 *array_mode
= RADEON_SURF_MODE_2D
;
364 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
366 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
367 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
369 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
371 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
372 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
373 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
376 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
377 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
378 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
379 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
380 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
381 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
383 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
384 *array_mode
= RADEON_SURF_MODE_2D
;
385 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
386 *array_mode
= RADEON_SURF_MODE_1D
;
388 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
390 *is_scanout
= metadata
->u
.legacy
.scanout
;
394 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
395 struct si_texture
*tex
)
397 struct si_screen
*sscreen
= sctx
->screen
;
398 struct pipe_context
*ctx
= &sctx
->b
;
400 if (ctx
== sscreen
->aux_context
)
401 mtx_lock(&sscreen
->aux_context_lock
);
403 unsigned n
= sctx
->num_decompress_calls
;
404 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
406 /* Flush only if any fast clear elimination took place. */
407 if (n
!= sctx
->num_decompress_calls
)
408 ctx
->flush(ctx
, NULL
, 0);
410 if (ctx
== sscreen
->aux_context
)
411 mtx_unlock(&sscreen
->aux_context_lock
);
414 void si_texture_discard_cmask(struct si_screen
*sscreen
,
415 struct si_texture
*tex
)
417 if (!tex
->cmask_buffer
)
420 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
423 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
424 tex
->dirty_level_mask
= 0;
426 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
428 if (tex
->cmask_buffer
!= &tex
->buffer
)
429 si_resource_reference(&tex
->cmask_buffer
, NULL
);
431 tex
->cmask_buffer
= NULL
;
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
435 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
438 static bool si_can_disable_dcc(struct si_texture
*tex
)
440 /* We can't disable DCC if it can be written by another process. */
441 return tex
->dcc_offset
&&
442 (!tex
->buffer
.b
.is_shared
||
443 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
446 static void si_texture_zero_dcc_fields(struct si_texture
*tex
)
449 tex
->display_dcc_offset
= 0;
450 tex
->dcc_retile_map_offset
= 0;
453 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
454 struct si_texture
*tex
)
456 if (!si_can_disable_dcc(tex
)) {
457 assert(tex
->display_dcc_offset
== 0);
461 assert(tex
->dcc_separate_buffer
== NULL
);
464 si_texture_zero_dcc_fields(tex
);
466 /* Notify all contexts about the change. */
467 p_atomic_inc(&sscreen
->dirty_tex_counter
);
472 * Disable DCC for the texture. (first decompress, then discard metadata).
474 * There is unresolved multi-context synchronization issue between
475 * screen::aux_context and the current context. If applications do this with
476 * multiple contexts, it's already undefined behavior for them and we don't
477 * have to worry about that. The scenario is:
479 * If context 1 disables DCC and context 2 has queued commands that write
480 * to the texture via CB with DCC enabled, and the order of operations is
482 * context 2 queues draw calls rendering to the texture, but doesn't flush
483 * context 1 disables DCC and flushes
484 * context 1 & 2 reset descriptors and FB state
485 * context 2 flushes (new compressed tiles written by the draw calls)
486 * context 1 & 2 read garbage, because DCC is disabled, yet there are
489 * \param sctx the current context if you have one, or sscreen->aux_context
492 bool si_texture_disable_dcc(struct si_context
*sctx
,
493 struct si_texture
*tex
)
495 struct si_screen
*sscreen
= sctx
->screen
;
497 if (!sctx
->has_graphics
)
498 return si_texture_discard_dcc(sscreen
, tex
);
500 if (!si_can_disable_dcc(tex
))
503 if (&sctx
->b
== sscreen
->aux_context
)
504 mtx_lock(&sscreen
->aux_context_lock
);
506 /* Decompress DCC. */
507 si_decompress_dcc(sctx
, tex
);
508 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
510 if (&sctx
->b
== sscreen
->aux_context
)
511 mtx_unlock(&sscreen
->aux_context_lock
);
513 return si_texture_discard_dcc(sscreen
, tex
);
516 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
517 struct si_texture
*tex
,
518 unsigned new_bind_flag
,
519 bool invalidate_storage
)
521 struct pipe_screen
*screen
= sctx
->b
.screen
;
522 struct si_texture
*new_tex
;
523 struct pipe_resource templ
= tex
->buffer
.b
.b
;
526 templ
.bind
|= new_bind_flag
;
528 if (tex
->buffer
.b
.is_shared
)
531 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
532 if (tex
->surface
.is_linear
)
535 /* This fails with MSAA, depth, and compressed textures. */
536 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
537 RADEON_SURF_MODE_LINEAR_ALIGNED
)
541 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
545 /* Copy the pixels to the new texture. */
546 if (!invalidate_storage
) {
547 for (i
= 0; i
<= templ
.last_level
; i
++) {
551 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
552 util_num_layers(&templ
, i
), &box
);
554 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
555 &tex
->buffer
.b
.b
, i
, &box
);
559 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
560 si_texture_discard_cmask(sctx
->screen
, tex
);
561 si_texture_discard_dcc(sctx
->screen
, tex
);
564 /* Replace the structure fields of tex. */
565 tex
->buffer
.b
.b
.bind
= templ
.bind
;
566 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
567 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
568 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
569 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
570 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
571 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
572 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
573 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
575 tex
->surface
= new_tex
->surface
;
576 tex
->size
= new_tex
->size
;
577 si_texture_reference(&tex
->flushed_depth_texture
,
578 new_tex
->flushed_depth_texture
);
580 tex
->fmask_offset
= new_tex
->fmask_offset
;
581 tex
->cmask_offset
= new_tex
->cmask_offset
;
582 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
584 if (tex
->cmask_buffer
== &tex
->buffer
)
585 tex
->cmask_buffer
= NULL
;
587 si_resource_reference(&tex
->cmask_buffer
, NULL
);
589 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
590 tex
->cmask_buffer
= &tex
->buffer
;
592 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
594 tex
->dcc_offset
= new_tex
->dcc_offset
;
595 tex
->cb_color_info
= new_tex
->cb_color_info
;
596 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
597 sizeof(tex
->color_clear_value
));
598 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
600 tex
->htile_offset
= new_tex
->htile_offset
;
601 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
602 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
603 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
604 tex
->db_render_format
= new_tex
->db_render_format
;
605 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
606 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
607 tex
->depth_cleared
= new_tex
->depth_cleared
;
608 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
609 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
610 tex
->db_compatible
= new_tex
->db_compatible
;
611 tex
->can_sample_z
= new_tex
->can_sample_z
;
612 tex
->can_sample_s
= new_tex
->can_sample_s
;
614 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
615 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
616 si_resource_reference(&tex
->dcc_separate_buffer
,
617 new_tex
->dcc_separate_buffer
);
618 si_resource_reference(&tex
->last_dcc_separate_buffer
,
619 new_tex
->last_dcc_separate_buffer
);
621 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
622 assert(!tex
->htile_offset
);
623 assert(!tex
->cmask_buffer
);
624 assert(!tex
->surface
.fmask_size
);
625 assert(!tex
->dcc_offset
);
626 assert(!tex
->is_depth
);
629 si_texture_reference(&new_tex
, NULL
);
631 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
634 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
636 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
639 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
640 struct si_texture
*tex
)
642 struct radeon_surf
*surface
= &tex
->surface
;
643 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
644 struct radeon_bo_metadata md
;
646 memset(&md
, 0, sizeof(md
));
648 if (sscreen
->info
.chip_class
>= GFX9
) {
649 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
651 if (tex
->dcc_offset
&& !tex
->dcc_separate_buffer
) {
652 uint64_t dcc_offset
=
653 tex
->display_dcc_offset
? tex
->display_dcc_offset
656 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
657 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
658 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
659 md
.u
.gfx9
.dcc_independent_64B
= 1;
662 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
663 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
664 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
665 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
666 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
667 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
668 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
669 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
670 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
671 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
672 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
673 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
676 assert(tex
->dcc_separate_buffer
== NULL
);
677 assert(tex
->surface
.fmask_size
== 0);
679 /* Metadata image format format version 1:
680 * [0] = 1 (metadata format identifier)
681 * [1] = (VENDOR_ID << 16) | PCI_ID
682 * [2:9] = image descriptor for the whole resource
683 * [2] is always 0, because the base address is cleared
684 * [9] is the DCC offset bits [39:8] from the beginning of
686 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
689 md
.metadata
[0] = 1; /* metadata image format version 1 */
691 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
692 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
694 static const unsigned char swizzle
[] = {
700 bool is_array
= util_texture_is_array(res
->target
);
703 sscreen
->make_texture_descriptor(sscreen
, tex
, true,
704 res
->target
, res
->format
,
705 swizzle
, 0, res
->last_level
, 0,
706 is_array
? res
->array_size
- 1 : 0,
707 res
->width0
, res
->height0
, res
->depth0
,
710 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
711 0, 0, tex
->surface
.blk_w
, false, desc
);
713 /* Clear the base address and set the relative DCC offset. */
715 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
717 switch (sscreen
->info
.chip_class
) {
722 desc
[7] = tex
->dcc_offset
>> 8;
725 desc
[7] = tex
->dcc_offset
>> 8;
726 desc
[5] &= C_008F24_META_DATA_ADDRESS
;
727 desc
[5] |= S_008F24_META_DATA_ADDRESS(tex
->dcc_offset
>> 40);
730 desc
[6] &= C_00A018_META_DATA_ADDRESS_LO
;
731 desc
[6] |= S_00A018_META_DATA_ADDRESS_LO(tex
->dcc_offset
>> 8);
732 desc
[7] = tex
->dcc_offset
>> 16;
739 /* Dwords [2:9] contain the image descriptor. */
740 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
741 md
.size_metadata
= 10 * 4;
743 /* Dwords [10:..] contain the mipmap level offsets. */
744 if (sscreen
->info
.chip_class
<= GFX8
) {
745 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
746 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
748 md
.size_metadata
+= (1 + res
->last_level
) * 4;
751 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
754 static bool si_read_tex_bo_metadata(struct si_screen
*sscreen
,
755 struct si_texture
*tex
,
756 struct radeon_bo_metadata
*md
)
758 uint32_t *desc
= &md
->metadata
[2];
760 if (md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
761 md
->metadata
[0] == 0 || /* invalid version number */
762 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */ {
763 /* Disable DCC because it might not be enabled. */
764 si_texture_zero_dcc_fields(tex
);
766 /* Don't report an error if the texture comes from an incompatible driver,
767 * but this might not work.
772 /* Validate that sample counts and the number of mipmap levels match. */
773 unsigned last_level
= G_008F1C_LAST_LEVEL(desc
[3]);
774 unsigned type
= G_008F1C_TYPE(desc
[3]);
776 if (type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA
||
777 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
778 unsigned log_samples
=
779 util_logbase2(MAX2(1, tex
->buffer
.b
.b
.nr_storage_samples
));
781 if (last_level
!= log_samples
) {
782 fprintf(stderr
, "radeonsi: invalid MSAA texture import, "
783 "metadata has log2(samples) = %u, the caller set %u\n",
784 last_level
, log_samples
);
788 if (last_level
!= tex
->buffer
.b
.b
.last_level
) {
789 fprintf(stderr
, "radeonsi: invalid mipmapped texture import, "
790 "metadata has last_level = %u, the caller set %u\n",
791 last_level
, tex
->buffer
.b
.b
.last_level
);
796 if (sscreen
->info
.chip_class
>= GFX8
&&
797 G_008F28_COMPRESSION_EN(desc
[6])) {
798 /* Read DCC information.
800 * Some state trackers don't set the SCANOUT flag when
801 * importing displayable images, which affects PIPE_ALIGNED
802 * and RB_ALIGNED, so we need to recover them here.
804 switch (sscreen
->info
.chip_class
) {
806 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
811 ((uint64_t)desc
[7] << 8) |
812 ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
813 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
814 G_008F24_META_PIPE_ALIGNED(desc
[5]);
815 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
816 G_008F24_META_RB_ALIGNED(desc
[5]);
818 /* If DCC is unaligned, this can only be a displayable image. */
819 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
820 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
821 tex
->surface
.is_displayable
= true;
826 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) |
827 ((uint64_t)desc
[7] << 16);
828 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
829 G_00A018_META_PIPE_ALIGNED(desc
[6]);
837 /* Disable DCC. dcc_offset is always set by texture_from_handle
838 * and must be cleared here.
840 si_texture_zero_dcc_fields(tex
);
846 static bool si_has_displayable_dcc(struct si_texture
*tex
)
848 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
850 if (sscreen
->info
.chip_class
<= GFX8
)
853 /* This needs a cache flush before scanout.
854 * (it can't be scanned out and rendered to simultaneously)
856 if (sscreen
->info
.use_display_dcc_unaligned
&&
858 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
859 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
862 /* This needs an explicit flush (flush_resource). */
863 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
864 tex
->display_dcc_offset
)
870 static void si_texture_get_info(struct pipe_screen
* screen
,
871 struct pipe_resource
*resource
,
875 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
876 struct si_texture
*tex
= (struct si_texture
*)resource
;
880 if (!sscreen
|| !tex
)
883 if (resource
->target
!= PIPE_BUFFER
) {
884 if (sscreen
->info
.chip_class
>= GFX9
) {
885 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
886 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
889 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
890 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
902 static bool si_texture_get_handle(struct pipe_screen
* screen
,
903 struct pipe_context
*ctx
,
904 struct pipe_resource
*resource
,
905 struct winsys_handle
*whandle
,
908 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
909 struct si_context
*sctx
;
910 struct si_resource
*res
= si_resource(resource
);
911 struct si_texture
*tex
= (struct si_texture
*)resource
;
912 bool update_metadata
= false;
913 unsigned stride
, offset
, slice_size
;
916 ctx
= threaded_context_unwrap_sync(ctx
);
917 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
919 if (resource
->target
!= PIPE_BUFFER
) {
920 /* This is not supported now, but it might be required for OpenCL
921 * interop in the future.
923 if (resource
->nr_samples
> 1 || tex
->is_depth
)
926 /* Move a suballocated texture into a non-suballocated allocation. */
927 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
928 tex
->surface
.tile_swizzle
||
929 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
930 sscreen
->info
.has_local_buffers
)) {
931 assert(!res
->b
.is_shared
);
932 si_reallocate_texture_inplace(sctx
, tex
,
933 PIPE_BIND_SHARED
, false);
935 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
936 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
937 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
938 assert(tex
->surface
.tile_swizzle
== 0);
941 /* Since shader image stores don't support DCC on GFX8,
942 * disable it for external clients that want write
945 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) ||
946 /* Displayable DCC requires an explicit flush. */
947 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
948 si_has_displayable_dcc(tex
))) {
949 if (si_texture_disable_dcc(sctx
, tex
)) {
950 update_metadata
= true;
951 /* si_texture_disable_dcc flushes the context */
956 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
957 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
958 /* Eliminate fast clear (both CMASK and DCC) */
959 si_eliminate_fast_color_clear(sctx
, tex
);
960 /* eliminate_fast_color_clear flushes the context */
963 /* Disable CMASK if flush_resource isn't going
966 if (tex
->cmask_buffer
)
967 si_texture_discard_cmask(sscreen
, tex
);
971 if (!res
->b
.is_shared
|| update_metadata
)
972 si_set_tex_bo_metadata(sscreen
, tex
);
974 if (sscreen
->info
.chip_class
>= GFX9
) {
975 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
977 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
980 /* Buffer exports are for the OpenCL interop. */
981 /* Move a suballocated buffer into a non-suballocated allocation. */
982 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
983 /* A DMABUF export always fails if the BO is local. */
984 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
985 sscreen
->info
.has_local_buffers
)) {
986 assert(!res
->b
.is_shared
);
988 /* Allocate a new buffer with PIPE_BIND_SHARED. */
989 struct pipe_resource templ
= res
->b
.b
;
990 templ
.bind
|= PIPE_BIND_SHARED
;
992 struct pipe_resource
*newb
=
993 screen
->resource_create(screen
, &templ
);
997 /* Copy the old buffer contents to the new one. */
999 u_box_1d(0, newb
->width0
, &box
);
1000 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
1001 &res
->b
.b
, 0, &box
);
1003 /* Move the new buffer storage to the old pipe_resource. */
1004 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
1005 pipe_resource_reference(&newb
, NULL
);
1007 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
1008 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
1015 si_texture_get_info(screen
, resource
, &stride
, &offset
);
1018 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
1020 if (res
->b
.is_shared
) {
1021 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
1024 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1025 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1026 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1028 res
->b
.is_shared
= true;
1029 res
->external_usage
= usage
;
1032 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, stride
,
1033 offset
, slice_size
, whandle
);
1036 static void si_texture_destroy(struct pipe_screen
*screen
,
1037 struct pipe_resource
*ptex
)
1039 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1040 struct si_texture
*tex
= (struct si_texture
*)ptex
;
1041 struct si_resource
*resource
= &tex
->buffer
;
1043 if (sscreen
->info
.chip_class
>= GFX9
)
1044 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
1046 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
1048 if (tex
->cmask_buffer
!= &tex
->buffer
) {
1049 si_resource_reference(&tex
->cmask_buffer
, NULL
);
1051 pb_reference(&resource
->buf
, NULL
);
1052 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
1053 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
1057 static const struct u_resource_vtbl si_texture_vtbl
;
1059 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
1060 struct si_texture
*tex
)
1062 unsigned cl_width
, cl_height
, width
, height
;
1063 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
1064 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
1066 assert(sscreen
->info
.chip_class
<= GFX8
);
1068 tex
->surface
.htile_size
= 0;
1070 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
1071 !sscreen
->info
.htile_cmask_support_1d_tiling
)
1074 /* Overalign HTILE on P2 configs to work around GPU hangs in
1075 * piglit/depthstencil-render-miplevels 585.
1077 * This has been confirmed to help Kabini & Stoney, where the hangs
1078 * are always reproducible. I think I have seen the test hang
1079 * on Carrizo too, though it was very rare there.
1081 if (sscreen
->info
.chip_class
>= GFX7
&& num_pipes
< 4)
1084 switch (num_pipes
) {
1110 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
1111 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
1113 slice_elements
= (width
* height
) / (8 * 8);
1114 slice_bytes
= slice_elements
* 4;
1116 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1117 base_align
= num_pipes
* pipe_interleave_bytes
;
1119 tex
->surface
.htile_alignment
= base_align
;
1120 tex
->surface
.htile_size
=
1121 util_num_layers(&tex
->buffer
.b
.b
, 0) *
1122 align(slice_bytes
, base_align
);
1125 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1126 struct si_texture
*tex
)
1128 if (sscreen
->info
.chip_class
<= GFX8
&& !tex
->tc_compatible_htile
)
1129 si_texture_get_htile_size(sscreen
, tex
);
1131 if (!tex
->surface
.htile_size
)
1134 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1135 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1138 void si_print_texture_info(struct si_screen
*sscreen
,
1139 struct si_texture
*tex
, struct u_log_context
*log
)
1143 /* Common parameters. */
1144 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1145 "blk_h=%u, array_size=%u, last_level=%u, "
1146 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1147 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1148 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1150 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1151 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1152 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1154 if (sscreen
->info
.chip_class
>= GFX9
) {
1155 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1156 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1157 tex
->surface
.surf_size
,
1158 tex
->surface
.u
.gfx9
.surf_slice_size
,
1159 tex
->surface
.surf_alignment
,
1160 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1161 tex
->surface
.u
.gfx9
.surf
.epitch
,
1162 tex
->surface
.u
.gfx9
.surf_pitch
);
1164 if (tex
->fmask_offset
) {
1165 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1166 "alignment=%u, swmode=%u, epitch=%u\n",
1168 tex
->surface
.fmask_size
,
1169 tex
->surface
.fmask_alignment
,
1170 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1171 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1174 if (tex
->cmask_buffer
) {
1175 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1176 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1178 tex
->surface
.cmask_size
,
1179 tex
->surface
.cmask_alignment
,
1180 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1181 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1184 if (tex
->htile_offset
) {
1185 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1186 "rb_aligned=%u, pipe_aligned=%u\n",
1188 tex
->surface
.htile_size
,
1189 tex
->surface
.htile_alignment
,
1190 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1191 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1194 if (tex
->dcc_offset
) {
1195 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1196 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1197 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1198 tex
->surface
.dcc_alignment
,
1199 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1200 tex
->surface
.num_dcc_levels
);
1203 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1204 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1205 tex
->surface
.u
.gfx9
.stencil_offset
,
1206 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1207 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1212 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1213 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1214 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1215 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1216 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1217 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1219 if (tex
->fmask_offset
)
1220 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1221 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1222 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1223 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1224 tex
->surface
.u
.legacy
.fmask
.bankh
,
1225 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1226 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1228 if (tex
->cmask_buffer
)
1229 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1230 "slice_tile_max=%u\n",
1231 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1232 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1234 if (tex
->htile_offset
)
1235 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1236 "alignment=%u, TC_compatible = %u\n",
1237 tex
->htile_offset
, tex
->surface
.htile_size
,
1238 tex
->surface
.htile_alignment
,
1239 tex
->tc_compatible_htile
);
1241 if (tex
->dcc_offset
) {
1242 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1243 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1244 tex
->surface
.dcc_alignment
);
1245 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1246 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1247 "fast_clear_size=%u\n",
1248 i
, i
< tex
->surface
.num_dcc_levels
,
1249 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1250 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1253 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1254 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1255 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1256 "mode=%u, tiling_index = %u\n",
1257 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1258 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1259 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1260 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1261 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1262 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1263 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1264 tex
->surface
.u
.legacy
.level
[i
].mode
,
1265 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1267 if (tex
->surface
.has_stencil
) {
1268 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1269 tex
->surface
.u
.legacy
.stencil_tile_split
);
1270 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1271 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1272 "slice_size=%"PRIu64
", npix_x=%u, "
1273 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1274 "mode=%u, tiling_index = %u\n",
1275 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1276 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1277 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1278 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1279 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1280 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1281 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1282 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1283 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1288 /* Common processing for si_texture_create and si_texture_from_handle */
1289 static struct si_texture
*
1290 si_texture_create_object(struct pipe_screen
*screen
,
1291 const struct pipe_resource
*base
,
1292 struct pb_buffer
*buf
,
1293 struct radeon_surf
*surface
)
1295 struct si_texture
*tex
;
1296 struct si_resource
*resource
;
1297 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1299 tex
= CALLOC_STRUCT(si_texture
);
1303 resource
= &tex
->buffer
;
1304 resource
->b
.b
= *base
;
1305 resource
->b
.b
.next
= NULL
;
1306 resource
->b
.vtbl
= &si_texture_vtbl
;
1307 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1308 resource
->b
.b
.screen
= screen
;
1310 /* don't include stencil-only formats which we don't support for rendering */
1311 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1313 tex
->surface
= *surface
;
1314 tex
->size
= tex
->surface
.surf_size
;
1316 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1317 (tex
->surface
.flags
&
1318 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1320 /* TC-compatible HTILE:
1321 * - GFX8 only supports Z32_FLOAT.
1322 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1323 if (tex
->tc_compatible_htile
) {
1324 if (sscreen
->info
.chip_class
>= GFX9
&&
1325 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1326 tex
->db_render_format
= base
->format
;
1328 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1329 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1330 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1333 tex
->db_render_format
= base
->format
;
1336 /* Applies to GCN. */
1337 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1339 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1340 * between frames, so the only thing that can enable separate DCC
1341 * with DRI2 is multiple slow clears within a frame.
1343 tex
->ps_draw_ratio
= 0;
1345 if (tex
->is_depth
) {
1346 if (sscreen
->info
.chip_class
>= GFX9
) {
1347 tex
->can_sample_z
= true;
1348 tex
->can_sample_s
= true;
1350 /* Stencil texturing with HTILE doesn't work
1351 * with mipmapping on Navi10-14. */
1352 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1353 sscreen
->info
.family
== CHIP_NAVI12
||
1354 sscreen
->info
.family
== CHIP_NAVI14
) &&
1355 base
->last_level
> 0)
1356 tex
->htile_stencil_disabled
= true;
1358 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1359 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1362 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1363 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1364 tex
->db_compatible
= true;
1366 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1367 si_texture_allocate_htile(sscreen
, tex
);
1370 if (base
->nr_samples
> 1 &&
1372 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1373 /* Allocate FMASK. */
1374 tex
->fmask_offset
= align64(tex
->size
,
1375 tex
->surface
.fmask_alignment
);
1376 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1378 /* Allocate CMASK. */
1379 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1380 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1381 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1382 tex
->cmask_buffer
= &tex
->buffer
;
1384 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
)
1388 /* Shared textures must always set up DCC here.
1389 * If it's not present, it will be disabled by
1390 * si_get_opaque_metadata later.
1392 if (tex
->surface
.dcc_size
&&
1393 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1394 (sscreen
->info
.use_display_dcc_unaligned
||
1395 sscreen
->info
.use_display_dcc_with_retile_blit
||
1396 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
))) {
1397 /* Add space for the DCC buffer. */
1398 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1399 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1401 if (sscreen
->info
.chip_class
>= GFX9
&&
1402 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
) {
1403 /* Add space for the displayable DCC buffer. */
1404 tex
->display_dcc_offset
=
1405 align64(tex
->size
, tex
->surface
.u
.gfx9
.display_dcc_alignment
);
1406 tex
->size
= tex
->display_dcc_offset
+
1407 tex
->surface
.u
.gfx9
.display_dcc_size
;
1409 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1410 tex
->dcc_retile_map_offset
=
1411 align64(tex
->size
, sscreen
->info
.tcc_cache_line_size
);
1413 if (tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
) {
1414 tex
->size
= tex
->dcc_retile_map_offset
+
1415 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 2;
1417 tex
->size
= tex
->dcc_retile_map_offset
+
1418 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 4;
1424 /* Now create the backing buffer. */
1426 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1427 tex
->surface
.surf_alignment
);
1429 if (!si_alloc_resource(sscreen
, resource
))
1432 resource
->buf
= buf
;
1433 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1434 resource
->bo_size
= buf
->size
;
1435 resource
->bo_alignment
= buf
->alignment
;
1436 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1437 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1438 resource
->vram_usage
= buf
->size
;
1439 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1440 resource
->gart_usage
= buf
->size
;
1443 if (tex
->cmask_buffer
) {
1444 /* Initialize the cmask to 0xCC (= compressed state). */
1445 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1446 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1449 if (tex
->htile_offset
) {
1450 uint32_t clear_value
= 0;
1452 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1453 clear_value
= 0x0000030F;
1455 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1457 tex
->surface
.htile_size
,
1461 /* Initialize DCC only if the texture is not being imported. */
1462 if (!buf
&& tex
->dcc_offset
) {
1463 /* Clear DCC to black for all tiles with DCC enabled.
1465 * This fixes corruption in 3DMark Slingshot Extreme, which
1466 * uses uninitialized textures, causing corruption.
1468 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1469 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1470 /* Simple case - all tiles have DCC enabled. */
1471 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1473 tex
->surface
.dcc_size
,
1474 DCC_CLEAR_COLOR_0000
);
1475 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1476 /* Clear to uncompressed. Clearing this to black is complicated. */
1477 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1479 tex
->surface
.dcc_size
,
1482 /* GFX8: Initialize mipmap levels and multisamples separately. */
1483 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1484 /* Clearing this to black is complicated. */
1485 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1487 tex
->surface
.dcc_size
,
1490 /* Clear the enabled mipmap levels to black. */
1493 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1494 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1497 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1498 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1501 /* Mipmap levels with DCC. */
1503 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1504 tex
->dcc_offset
, size
,
1505 DCC_CLEAR_COLOR_0000
);
1507 /* Mipmap levels without DCC. */
1508 if (size
!= tex
->surface
.dcc_size
) {
1509 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1510 tex
->dcc_offset
+ size
,
1511 tex
->surface
.dcc_size
- size
,
1517 /* Upload the DCC retile map. */
1518 if (tex
->dcc_retile_map_offset
) {
1519 /* Use a staging buffer for the upload, because
1520 * the buffer backing the texture is unmappable.
1522 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1523 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1524 struct si_resource
*buf
=
1525 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1526 num_elements
* (use_uint16
? 2 : 4),
1527 sscreen
->info
.tcc_cache_line_size
);
1528 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1529 PIPE_TRANSFER_WRITE
);
1530 uint16_t *us
= (uint16_t*)ui
;
1532 /* Upload the retile map into a staging buffer. */
1534 for (unsigned i
= 0; i
< num_elements
; i
++)
1535 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1537 for (unsigned i
= 0; i
< num_elements
; i
++)
1538 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1541 /* Copy the staging buffer to the buffer backing the texture. */
1542 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1543 struct pipe_box box
;
1544 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1546 assert(tex
->dcc_retile_map_offset
<= UINT_MAX
);
1547 mtx_lock(&sscreen
->aux_context_lock
);
1548 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1549 tex
->dcc_retile_map_offset
, 0, 0,
1550 &buf
->b
.b
, 0, &box
);
1551 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1552 mtx_unlock(&sscreen
->aux_context_lock
);
1554 si_resource_reference(&buf
, NULL
);
1558 /* Initialize the CMASK base register value. */
1559 tex
->cmask_base_address_reg
=
1560 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1562 if (sscreen
->debug_flags
& DBG(VM
)) {
1563 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1564 tex
->buffer
.gpu_address
,
1565 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1566 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1567 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1570 if (sscreen
->debug_flags
& DBG(TEX
)) {
1572 struct u_log_context log
;
1573 u_log_context_init(&log
);
1574 si_print_texture_info(sscreen
, tex
, &log
);
1575 u_log_new_page_print(&log
, stdout
);
1577 u_log_context_destroy(&log
);
1584 if (sscreen
->info
.chip_class
>= GFX9
)
1585 free(surface
->u
.gfx9
.dcc_retile_map
);
1589 static enum radeon_surf_mode
1590 si_choose_tiling(struct si_screen
*sscreen
,
1591 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1593 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1594 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1595 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1596 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1598 /* MSAA resources must be 2D tiled. */
1599 if (templ
->nr_samples
> 1)
1600 return RADEON_SURF_MODE_2D
;
1602 /* Transfer resources should be linear. */
1603 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1604 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1606 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1607 * which requires 2D tiling.
1609 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1610 return RADEON_SURF_MODE_2D
;
1612 /* Handle common candidates for the linear mode.
1613 * Compressed textures and DB surfaces must always be tiled.
1615 if (!force_tiling
&&
1616 !is_depth_stencil
&&
1617 !util_format_is_compressed(templ
->format
)) {
1618 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1619 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1621 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1622 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1623 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1625 /* Cursors are linear on AMD GCN.
1626 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1627 if (templ
->bind
& PIPE_BIND_CURSOR
)
1628 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1630 if (templ
->bind
& PIPE_BIND_LINEAR
)
1631 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1633 /* Textures with a very small height are recommended to be linear. */
1634 if (templ
->target
== PIPE_TEXTURE_1D
||
1635 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1636 /* Only very thin and long 2D textures should benefit from
1637 * linear_aligned. */
1638 (templ
->width0
> 8 && templ
->height0
<= 2))
1639 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1641 /* Textures likely to be mapped often. */
1642 if (templ
->usage
== PIPE_USAGE_STAGING
||
1643 templ
->usage
== PIPE_USAGE_STREAM
)
1644 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1647 /* Make small textures 1D tiled. */
1648 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1649 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1650 return RADEON_SURF_MODE_1D
;
1652 /* The allocator will switch to 1D if needed. */
1653 return RADEON_SURF_MODE_2D
;
1656 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1657 const struct pipe_resource
*templ
)
1659 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1660 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1662 if (templ
->nr_samples
>= 2) {
1663 /* This is hackish (overwriting the const pipe_resource template),
1664 * but should be harmless and state trackers can also see
1665 * the overriden number of samples in the created pipe_resource.
1667 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1668 ((struct pipe_resource
*)templ
)->nr_samples
=
1669 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1670 sscreen
->eqaa_force_z_samples
;
1671 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1672 ((struct pipe_resource
*)templ
)->nr_samples
=
1673 sscreen
->eqaa_force_coverage_samples
;
1674 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1675 sscreen
->eqaa_force_color_samples
;
1679 struct radeon_surf surface
= {0};
1680 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1681 bool tc_compatible_htile
=
1682 sscreen
->info
.chip_class
>= GFX8
&&
1683 /* There are issues with TC-compatible HTILE on Tonga (and
1684 * Iceland is the same design), and documented bug workarounds
1685 * don't help. For example, this fails:
1686 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1688 sscreen
->info
.family
!= CHIP_TONGA
&&
1689 sscreen
->info
.family
!= CHIP_ICELAND
&&
1690 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1691 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1692 !is_flushed_depth
&&
1693 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1697 r
= si_init_surface(sscreen
, &surface
, templ
,
1698 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1699 0, 0, false, false, is_flushed_depth
,
1700 tc_compatible_htile
);
1705 return (struct pipe_resource
*)
1706 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1709 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1710 const struct pipe_resource
*templ
,
1711 struct pb_buffer
*buf
,
1717 enum radeon_surf_mode array_mode
;
1718 struct radeon_surf surface
= {};
1719 struct radeon_bo_metadata metadata
= {};
1720 struct si_texture
*tex
;
1725 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1726 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1727 &array_mode
, &is_scanout
);
1730 * The bo metadata is unset for un-dedicated images. So we fall
1731 * back to linear. See answer to question 5 of the
1732 * VK_KHX_external_memory spec for some details.
1734 * It is possible that this case isn't going to work if the
1735 * surface pitch isn't correctly aligned by default.
1737 * In order to support it correctly we require multi-image
1738 * metadata to be syncrhonized between radv and radeonsi. The
1739 * semantics of associating multiple image metadata to a memory
1740 * object on the vulkan export side are not concretely defined
1743 * All the use cases we are aware of at the moment for memory
1744 * objects use dedicated allocations. So lets keep the initial
1745 * implementation simple.
1747 * A possible alternative is to attempt to reconstruct the
1748 * tiling information when the TexParameter TEXTURE_TILING_EXT
1751 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1755 r
= si_init_surface(sscreen
, &surface
, templ
,
1756 array_mode
, stride
, offset
, true, is_scanout
,
1761 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1765 tex
->buffer
.b
.is_shared
= true;
1766 tex
->buffer
.external_usage
= usage
;
1768 if (!si_read_tex_bo_metadata(sscreen
, tex
, &metadata
)) {
1769 si_texture_reference(&tex
, NULL
);
1773 /* Displayable DCC requires an explicit flush. */
1775 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1776 si_has_displayable_dcc(tex
)) {
1777 /* TODO: do we need to decompress DCC? */
1778 if (si_texture_discard_dcc(sscreen
, tex
)) {
1779 /* Update BO metadata after disabling DCC. */
1780 si_set_tex_bo_metadata(sscreen
, tex
);
1784 assert(tex
->surface
.tile_swizzle
== 0);
1785 return &tex
->buffer
.b
.b
;
1788 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1789 const struct pipe_resource
*templ
,
1790 struct winsys_handle
*whandle
,
1793 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1794 struct pb_buffer
*buf
= NULL
;
1796 /* Support only 2D textures without mipmaps */
1797 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1798 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1799 templ
->last_level
!= 0)
1802 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1803 sscreen
->info
.max_alignment
);
1807 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
,
1808 whandle
->stride
, whandle
->offset
,
1812 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1813 struct pipe_resource
*texture
)
1815 struct si_texture
*tex
= (struct si_texture
*)texture
;
1816 struct pipe_resource resource
;
1817 enum pipe_format pipe_format
= texture
->format
;
1819 assert(!tex
->flushed_depth_texture
);
1821 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1822 switch (pipe_format
) {
1823 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1824 /* Save memory by not allocating the S plane. */
1825 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1827 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1828 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1829 /* Save memory bandwidth by not copying the
1830 * stencil part during flush.
1832 * This potentially increases memory bandwidth
1833 * if an application uses both Z and S texturing
1834 * simultaneously (a flushed Z24S8 texture
1835 * would be stored compactly), but how often
1836 * does that really happen?
1838 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1842 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1843 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1845 /* DB->CB copies to an 8bpp surface don't work. */
1846 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1849 memset(&resource
, 0, sizeof(resource
));
1850 resource
.target
= texture
->target
;
1851 resource
.format
= pipe_format
;
1852 resource
.width0
= texture
->width0
;
1853 resource
.height0
= texture
->height0
;
1854 resource
.depth0
= texture
->depth0
;
1855 resource
.array_size
= texture
->array_size
;
1856 resource
.last_level
= texture
->last_level
;
1857 resource
.nr_samples
= texture
->nr_samples
;
1858 resource
.usage
= PIPE_USAGE_DEFAULT
;
1859 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1860 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1862 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1863 if (!tex
->flushed_depth_texture
) {
1864 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1871 * Initialize the pipe_resource descriptor to be of the same size as the box,
1872 * which is supposed to hold a subregion of the texture "orig" at the given
1875 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1876 struct pipe_resource
*orig
,
1877 const struct pipe_box
*box
,
1878 unsigned level
, unsigned flags
)
1880 memset(res
, 0, sizeof(*res
));
1881 res
->format
= orig
->format
;
1882 res
->width0
= box
->width
;
1883 res
->height0
= box
->height
;
1885 res
->array_size
= 1;
1886 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1889 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1890 util_format_is_compressed(orig
->format
)) {
1891 /* Transfer resources are allocated with linear tiling, which is
1892 * not supported for compressed formats.
1894 unsigned blocksize
=
1895 util_format_get_blocksize(orig
->format
);
1897 if (blocksize
== 8) {
1898 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1900 assert(blocksize
== 16);
1901 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1904 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1905 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1908 /* We must set the correct texture target and dimensions for a 3D box. */
1909 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1910 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1911 res
->array_size
= box
->depth
;
1913 res
->target
= PIPE_TEXTURE_2D
;
1917 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1918 struct si_texture
*tex
,
1919 unsigned transfer_usage
,
1920 const struct pipe_box
*box
)
1922 return !tex
->buffer
.b
.is_shared
&&
1923 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1924 tex
->buffer
.b
.b
.last_level
== 0 &&
1925 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1926 box
->x
, box
->y
, box
->z
,
1927 box
->width
, box
->height
,
1931 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1932 struct si_texture
*tex
)
1934 struct si_screen
*sscreen
= sctx
->screen
;
1936 /* There is no point in discarding depth and tiled buffers. */
1937 assert(!tex
->is_depth
);
1938 assert(tex
->surface
.is_linear
);
1940 /* Reallocate the buffer in the same pipe_resource. */
1941 si_alloc_resource(sscreen
, &tex
->buffer
);
1943 /* Initialize the CMASK base address (needed even without CMASK). */
1944 tex
->cmask_base_address_reg
=
1945 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1947 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1949 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1952 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1953 struct pipe_resource
*texture
,
1956 const struct pipe_box
*box
,
1957 struct pipe_transfer
**ptransfer
)
1959 struct si_context
*sctx
= (struct si_context
*)ctx
;
1960 struct si_texture
*tex
= (struct si_texture
*)texture
;
1961 struct si_transfer
*trans
;
1962 struct si_resource
*buf
;
1963 unsigned offset
= 0;
1965 bool use_staging_texture
= false;
1967 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1968 assert(box
->width
&& box
->height
&& box
->depth
);
1970 if (tex
->is_depth
) {
1971 /* Depth textures use staging unconditionally. */
1972 use_staging_texture
= true;
1974 /* Degrade the tile mode if we get too many transfers on APUs.
1975 * On dGPUs, the staging texture is always faster.
1976 * Only count uploads that are at least 4x4 pixels large.
1978 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1980 box
->width
>= 4 && box
->height
>= 4 &&
1981 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1982 bool can_invalidate
=
1983 si_can_invalidate_texture(sctx
->screen
, tex
,
1986 si_reallocate_texture_inplace(sctx
, tex
,
1991 /* Tiled textures need to be converted into a linear texture for CPU
1992 * access. The staging texture is always linear and is placed in GART.
1994 * Reading from VRAM or GTT WC is slow, always use the staging
1995 * texture in this case.
1997 * Use the staging texture for uploads if the underlying BO
2000 if (!tex
->surface
.is_linear
)
2001 use_staging_texture
= true;
2002 else if (usage
& PIPE_TRANSFER_READ
)
2003 use_staging_texture
=
2004 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
2005 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
2006 /* Write & linear only: */
2007 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
2008 RADEON_USAGE_READWRITE
) ||
2009 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
2010 RADEON_USAGE_READWRITE
)) {
2012 if (si_can_invalidate_texture(sctx
->screen
, tex
,
2014 si_texture_invalidate_storage(sctx
, tex
);
2016 use_staging_texture
= true;
2020 trans
= CALLOC_STRUCT(si_transfer
);
2023 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
2024 trans
->b
.b
.level
= level
;
2025 trans
->b
.b
.usage
= usage
;
2026 trans
->b
.b
.box
= *box
;
2028 if (use_staging_texture
) {
2029 struct pipe_resource resource
;
2030 struct si_texture
*staging
;
2032 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
2033 SI_RESOURCE_FLAG_TRANSFER
);
2034 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
2035 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
2037 /* Since depth-stencil textures don't support linear tiling,
2038 * blit from ZS to color and vice versa. u_blitter will do
2039 * the packing for these formats.
2042 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
2044 /* Create the temporary texture. */
2045 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
2047 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
2050 trans
->staging
= &staging
->buffer
;
2052 /* Just get the strides. */
2053 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
2055 &trans
->b
.b
.layer_stride
);
2057 if (usage
& PIPE_TRANSFER_READ
)
2058 si_copy_to_staging_texture(ctx
, trans
);
2060 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
2062 buf
= trans
->staging
;
2064 /* the resource is mapped directly */
2065 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
2067 &trans
->b
.b
.layer_stride
);
2071 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2072 * we don't run out of the CPU address space.
2074 if (sizeof(void*) == 4)
2075 usage
|= RADEON_TRANSFER_TEMPORARY
;
2077 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
2080 *ptransfer
= &trans
->b
.b
;
2081 return map
+ offset
;
2084 si_resource_reference(&trans
->staging
, NULL
);
2085 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
2090 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
2091 struct pipe_transfer
* transfer
)
2093 struct si_context
*sctx
= (struct si_context
*)ctx
;
2094 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
2095 struct pipe_resource
*texture
= transfer
->resource
;
2096 struct si_texture
*tex
= (struct si_texture
*)texture
;
2098 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2099 * we don't run out of the CPU address space.
2101 if (sizeof(void*) == 4) {
2102 struct si_resource
*buf
=
2103 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2105 sctx
->ws
->buffer_unmap(buf
->buf
);
2108 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
2109 si_copy_from_staging_texture(ctx
, stransfer
);
2111 if (stransfer
->staging
) {
2112 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2113 si_resource_reference(&stransfer
->staging
, NULL
);
2116 /* Heuristic for {upload, draw, upload, draw, ..}:
2118 * Flush the gfx IB if we've allocated too much texture storage.
2120 * The idea is that we don't want to build IBs that use too much
2121 * memory and put pressure on the kernel memory manager and we also
2122 * want to make temporary and invalidated buffers go idle ASAP to
2123 * decrease the total memory usage or make them reusable. The memory
2124 * usage will be slightly higher than given here because of the buffer
2125 * cache in the winsys.
2127 * The result is that the kernel memory manager is never a bottleneck.
2129 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2130 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2131 sctx
->num_alloc_tex_transfer_bytes
= 0;
2134 pipe_resource_reference(&transfer
->resource
, NULL
);
2138 static const struct u_resource_vtbl si_texture_vtbl
=
2140 NULL
, /* get_handle */
2141 si_texture_destroy
, /* resource_destroy */
2142 si_texture_transfer_map
, /* transfer_map */
2143 u_default_transfer_flush_region
, /* transfer_flush_region */
2144 si_texture_transfer_unmap
, /* transfer_unmap */
2147 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2149 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
2150 enum pipe_format format1
,
2151 enum pipe_format format2
)
2153 const struct util_format_description
*desc1
, *desc2
;
2155 /* No format change - exit early. */
2156 if (format1
== format2
)
2159 format1
= si_simplify_cb_format(format1
);
2160 format2
= si_simplify_cb_format(format2
);
2162 /* Check again after format adjustments. */
2163 if (format1
== format2
)
2166 desc1
= util_format_description(format1
);
2167 desc2
= util_format_description(format2
);
2169 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2170 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2173 /* Float and non-float are totally incompatible. */
2174 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2175 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2178 /* Channel sizes must match across DCC formats.
2179 * Comparing just the first 2 channels should be enough.
2181 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2182 (desc1
->nr_channels
>= 2 &&
2183 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2186 /* Everything below is not needed if the driver never uses the DCC
2187 * clear code with the value of 1.
2190 /* If the clear values are all 1 or all 0, this constraint can be
2192 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2195 /* Channel types must match if the clear value of 1 is used.
2196 * The type categories are only float, signed, unsigned.
2197 * NORM and INT are always compatible.
2199 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2200 (desc1
->nr_channels
>= 2 &&
2201 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2207 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2209 enum pipe_format view_format
)
2211 struct si_texture
*stex
= (struct si_texture
*)tex
;
2213 return vi_dcc_enabled(stex
, level
) &&
2214 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
,
2215 tex
->format
, view_format
);
2218 /* This can't be merged with the above function, because
2219 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2220 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2221 struct pipe_resource
*tex
,
2223 enum pipe_format view_format
)
2225 struct si_texture
*stex
= (struct si_texture
*)tex
;
2227 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2228 if (!si_texture_disable_dcc(sctx
, stex
))
2229 si_decompress_dcc(sctx
, stex
);
2232 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2233 struct pipe_resource
*texture
,
2234 const struct pipe_surface
*templ
,
2235 unsigned width0
, unsigned height0
,
2236 unsigned width
, unsigned height
)
2238 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2243 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2244 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2246 pipe_reference_init(&surface
->base
.reference
, 1);
2247 pipe_resource_reference(&surface
->base
.texture
, texture
);
2248 surface
->base
.context
= pipe
;
2249 surface
->base
.format
= templ
->format
;
2250 surface
->base
.width
= width
;
2251 surface
->base
.height
= height
;
2252 surface
->base
.u
= templ
->u
;
2254 surface
->width0
= width0
;
2255 surface
->height0
= height0
;
2257 surface
->dcc_incompatible
=
2258 texture
->target
!= PIPE_BUFFER
&&
2259 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2261 return &surface
->base
;
2264 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2265 struct pipe_resource
*tex
,
2266 const struct pipe_surface
*templ
)
2268 unsigned level
= templ
->u
.tex
.level
;
2269 unsigned width
= u_minify(tex
->width0
, level
);
2270 unsigned height
= u_minify(tex
->height0
, level
);
2271 unsigned width0
= tex
->width0
;
2272 unsigned height0
= tex
->height0
;
2274 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2275 const struct util_format_description
*tex_desc
2276 = util_format_description(tex
->format
);
2277 const struct util_format_description
*templ_desc
2278 = util_format_description(templ
->format
);
2280 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2282 /* Adjust size of surface if and only if the block width or
2283 * height is changed. */
2284 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2285 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2286 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2287 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2289 width
= nblks_x
* templ_desc
->block
.width
;
2290 height
= nblks_y
* templ_desc
->block
.height
;
2292 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2293 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2297 return si_create_surface_custom(pipe
, tex
, templ
,
2302 static void si_surface_destroy(struct pipe_context
*pipe
,
2303 struct pipe_surface
*surface
)
2305 pipe_resource_reference(&surface
->texture
, NULL
);
2309 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2311 const struct util_format_description
*desc
= util_format_description(format
);
2313 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2315 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2316 return V_028C70_SWAP_STD
;
2318 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2321 switch (desc
->nr_channels
) {
2323 if (HAS_SWIZZLE(0,X
))
2324 return V_028C70_SWAP_STD
; /* X___ */
2325 else if (HAS_SWIZZLE(3,X
))
2326 return V_028C70_SWAP_ALT_REV
; /* ___X */
2329 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2330 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2331 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2332 return V_028C70_SWAP_STD
; /* XY__ */
2333 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2334 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2335 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2337 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2338 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2339 return V_028C70_SWAP_ALT
; /* X__Y */
2340 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2341 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2344 if (HAS_SWIZZLE(0,X
))
2345 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2346 else if (HAS_SWIZZLE(0,Z
))
2347 return V_028C70_SWAP_STD_REV
; /* ZYX */
2350 /* check the middle channels, the 1st and 4th channel can be NONE */
2351 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2352 return V_028C70_SWAP_STD
; /* XYZW */
2353 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2354 return V_028C70_SWAP_STD_REV
; /* WZYX */
2355 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2356 return V_028C70_SWAP_ALT
; /* ZYXW */
2357 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2360 return V_028C70_SWAP_ALT_REV
;
2362 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2369 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2371 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2376 if (sctx
->dcc_stats
[slot
].query_active
)
2377 vi_separate_dcc_stop_query(sctx
,
2378 sctx
->dcc_stats
[slot
].tex
);
2380 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2381 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2382 sctx
->b
.destroy_query(&sctx
->b
,
2383 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2384 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2387 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2391 * Return the per-context slot where DCC statistics queries for the texture live.
2393 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2394 struct si_texture
*tex
)
2396 int i
, empty_slot
= -1;
2398 /* Remove zombie textures (textures kept alive by this array only). */
2399 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2400 if (sctx
->dcc_stats
[i
].tex
&&
2401 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2402 vi_dcc_clean_up_context_slot(sctx
, i
);
2404 /* Find the texture. */
2405 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2406 /* Return if found. */
2407 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2408 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2412 /* Record the first seen empty slot. */
2413 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2417 /* Not found. Remove the oldest member to make space in the array. */
2418 if (empty_slot
== -1) {
2419 int oldest_slot
= 0;
2421 /* Find the oldest slot. */
2422 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2423 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2424 sctx
->dcc_stats
[i
].last_use_timestamp
)
2427 /* Clean up the oldest slot. */
2428 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2429 empty_slot
= oldest_slot
;
2432 /* Add the texture to the new slot. */
2433 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2434 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2438 static struct pipe_query
*
2439 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2441 struct si_query_hw
*query
= (struct si_query_hw
*)
2442 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2444 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2445 return (struct pipe_query
*)query
;
2449 * Called when binding a color buffer.
2451 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2452 struct si_texture
*tex
)
2454 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2456 assert(!sctx
->dcc_stats
[i
].query_active
);
2458 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2459 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2461 /* begin or resume the query */
2462 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2463 sctx
->dcc_stats
[i
].query_active
= true;
2467 * Called when unbinding a color buffer.
2469 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2470 struct si_texture
*tex
)
2472 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2474 assert(sctx
->dcc_stats
[i
].query_active
);
2475 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2477 /* pause or end the query */
2478 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2479 sctx
->dcc_stats
[i
].query_active
= false;
2482 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2484 /* The minimum number of fullscreen draws per frame that is required
2486 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2489 /* Called by fast clear. */
2490 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2491 struct si_texture
*tex
)
2493 /* The intent is to use this with shared displayable back buffers,
2494 * but it's not strictly limited only to them.
2496 if (!tex
->buffer
.b
.is_shared
||
2497 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2498 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2499 tex
->buffer
.b
.b
.last_level
> 0 ||
2500 !tex
->surface
.dcc_size
||
2501 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2502 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2505 assert(sctx
->chip_class
>= GFX8
);
2507 if (tex
->dcc_offset
)
2508 return; /* already enabled */
2510 /* Enable the DCC stat gathering. */
2511 if (!tex
->dcc_gather_statistics
) {
2512 tex
->dcc_gather_statistics
= true;
2513 vi_separate_dcc_start_query(sctx
, tex
);
2516 if (!vi_should_enable_separate_dcc(tex
))
2517 return; /* stats show that DCC decompression is too expensive */
2519 assert(tex
->surface
.num_dcc_levels
);
2520 assert(!tex
->dcc_separate_buffer
);
2522 si_texture_discard_cmask(sctx
->screen
, tex
);
2524 /* Get a DCC buffer. */
2525 if (tex
->last_dcc_separate_buffer
) {
2526 assert(tex
->dcc_gather_statistics
);
2527 assert(!tex
->dcc_separate_buffer
);
2528 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2529 tex
->last_dcc_separate_buffer
= NULL
;
2531 tex
->dcc_separate_buffer
=
2532 si_aligned_buffer_create(sctx
->b
.screen
,
2533 SI_RESOURCE_FLAG_UNMAPPABLE
,
2535 tex
->surface
.dcc_size
,
2536 tex
->surface
.dcc_alignment
);
2537 if (!tex
->dcc_separate_buffer
)
2541 /* dcc_offset is the absolute GPUVM address. */
2542 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2544 /* no need to flag anything since this is called by fast clear that
2545 * flags framebuffer state
2550 * Called by pipe_context::flush_resource, the place where DCC decompression
2553 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2554 struct si_texture
*tex
)
2556 struct si_context
*sctx
= (struct si_context
*)ctx
;
2557 struct pipe_query
*tmp
;
2558 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2559 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2560 bool disable
= false;
2562 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2563 union pipe_query_result result
;
2565 /* Read the results. */
2566 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2567 ctx
->get_query_result(ctx
, query
,
2569 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2571 /* Compute the approximate number of fullscreen draws. */
2572 tex
->ps_draw_ratio
=
2573 result
.pipeline_statistics
.ps_invocations
/
2574 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2575 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2577 disable
= tex
->dcc_separate_buffer
&&
2578 !vi_should_enable_separate_dcc(tex
);
2581 tex
->num_slow_clears
= 0;
2583 /* stop the statistics query for ps_stats[0] */
2585 vi_separate_dcc_stop_query(sctx
, tex
);
2587 /* Move the queries in the queue by one. */
2588 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2589 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2590 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2591 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2593 /* create and start a new query as ps_stats[0] */
2595 vi_separate_dcc_start_query(sctx
, tex
);
2598 assert(!tex
->last_dcc_separate_buffer
);
2599 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2600 tex
->dcc_separate_buffer
= NULL
;
2601 tex
->dcc_offset
= 0;
2602 /* no need to flag anything since this is called after
2603 * decompression that re-sets framebuffer state
2608 static struct pipe_memory_object
*
2609 si_memobj_from_handle(struct pipe_screen
*screen
,
2610 struct winsys_handle
*whandle
,
2613 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2614 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2615 struct pb_buffer
*buf
= NULL
;
2620 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2621 sscreen
->info
.max_alignment
);
2627 memobj
->b
.dedicated
= dedicated
;
2629 memobj
->stride
= whandle
->stride
;
2631 return (struct pipe_memory_object
*)memobj
;
2636 si_memobj_destroy(struct pipe_screen
*screen
,
2637 struct pipe_memory_object
*_memobj
)
2639 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2641 pb_reference(&memobj
->buf
, NULL
);
2645 static struct pipe_resource
*
2646 si_texture_from_memobj(struct pipe_screen
*screen
,
2647 const struct pipe_resource
*templ
,
2648 struct pipe_memory_object
*_memobj
,
2651 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2652 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2653 struct pipe_resource
*tex
=
2654 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2655 memobj
->stride
, offset
,
2656 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2657 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2658 memobj
->b
.dedicated
);
2662 /* si_texture_from_winsys_buffer doesn't increment refcount of
2663 * memobj->buf, so increment it here.
2665 struct pb_buffer
*buf
= NULL
;
2666 pb_reference(&buf
, memobj
->buf
);
2670 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2671 struct pipe_resource
*resource
,
2674 struct si_texture
*tex
= (struct si_texture
*)resource
;
2676 /* Buffers only support the linear flag. */
2677 if (resource
->target
== PIPE_BUFFER
)
2678 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2680 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2683 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2686 /* TODO: PIPE_BIND_CURSOR - do we care? */
2690 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2692 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2693 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2694 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2695 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2696 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2697 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2698 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2701 void si_init_context_texture_functions(struct si_context
*sctx
)
2703 sctx
->b
.create_surface
= si_create_surface
;
2704 sctx
->b
.surface_destroy
= si_surface_destroy
;