2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include "amd/addrlib/inc/addrinterface.h"
41 #include "drm-uapi/drm_fourcc.h"
43 static enum radeon_surf_mode
44 si_choose_tiling(struct si_screen
*sscreen
,
45 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
48 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
49 struct si_texture
*dst
,
50 unsigned dst_level
, unsigned dstx
,
51 unsigned dsty
, unsigned dstz
,
52 struct si_texture
*src
,
54 const struct pipe_box
*src_box
)
59 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
62 /* MSAA: Blits don't exist in the real world. */
63 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
64 dst
->buffer
.b
.b
.nr_samples
> 1)
67 /* Depth-stencil surfaces:
68 * When dst is linear, the DB->CB copy preserves HTILE.
69 * When dst is tiled, the 3D path must be used to update HTILE.
71 if (src
->is_depth
|| dst
->is_depth
)
75 * src: Use the 3D path. DCC decompression is expensive.
76 * dst: Use the 3D path to compress the pixels with DCC.
78 if (vi_dcc_enabled(src
, src_level
) ||
79 vi_dcc_enabled(dst
, dst_level
))
83 * src: Both texture and SDMA paths need decompression. Use SDMA.
84 * dst: If overwriting the whole texture, discard CMASK and use
85 * SDMA. Otherwise, use the 3D path.
87 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
88 /* The CMASK clear is only enabled for the first level. */
89 assert(dst_level
== 0);
90 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
91 dstx
, dsty
, dstz
, src_box
->width
,
92 src_box
->height
, src_box
->depth
))
95 si_texture_discard_cmask(sctx
->screen
, dst
);
98 /* All requirements are met. Prepare textures for SDMA. */
99 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
100 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
102 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
103 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
108 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
109 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
110 struct pipe_resource
*dst
,
112 unsigned dstx
, unsigned dsty
, unsigned dstz
,
113 struct pipe_resource
*src
,
115 const struct pipe_box
*src_box
)
117 struct pipe_blit_info blit
;
119 memset(&blit
, 0, sizeof(blit
));
120 blit
.src
.resource
= src
;
121 blit
.src
.format
= src
->format
;
122 blit
.src
.level
= src_level
;
123 blit
.src
.box
= *src_box
;
124 blit
.dst
.resource
= dst
;
125 blit
.dst
.format
= dst
->format
;
126 blit
.dst
.level
= dst_level
;
127 blit
.dst
.box
.x
= dstx
;
128 blit
.dst
.box
.y
= dsty
;
129 blit
.dst
.box
.z
= dstz
;
130 blit
.dst
.box
.width
= src_box
->width
;
131 blit
.dst
.box
.height
= src_box
->height
;
132 blit
.dst
.box
.depth
= src_box
->depth
;
133 blit
.mask
= util_format_get_mask(dst
->format
);
134 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
137 pipe
->blit(pipe
, &blit
);
141 /* Copy from a full GPU texture to a transfer's staging one. */
142 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
144 struct si_context
*sctx
= (struct si_context
*)ctx
;
145 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
146 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
147 struct pipe_resource
*src
= transfer
->resource
;
149 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
150 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
151 src
, transfer
->level
, &transfer
->box
);
155 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
159 /* Copy from a transfer's staging texture to a full GPU one. */
160 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
162 struct si_context
*sctx
= (struct si_context
*)ctx
;
163 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
164 struct pipe_resource
*dst
= transfer
->resource
;
165 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
166 struct pipe_box sbox
;
168 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
170 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
171 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
172 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 if (util_format_is_compressed(dst
->format
)) {
178 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
179 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
182 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
183 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
187 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
188 struct si_texture
*tex
, unsigned level
,
189 const struct pipe_box
*box
,
191 unsigned *layer_stride
)
193 if (sscreen
->info
.chip_class
>= GFX9
) {
194 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
195 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
200 /* Each texture is an array of slices. Each slice is an array
201 * of mipmap levels. */
202 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
203 tex
->surface
.u
.gfx9
.offset
[level
] +
204 (box
->y
/ tex
->surface
.blk_h
*
205 tex
->surface
.u
.gfx9
.surf_pitch
+
206 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
208 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
210 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
211 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
214 return tex
->surface
.u
.legacy
.level
[level
].offset
;
216 /* Each texture is an array of mipmap levels. Each level is
217 * an array of slices. */
218 return tex
->surface
.u
.legacy
.level
[level
].offset
+
219 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
220 (box
->y
/ tex
->surface
.blk_h
*
221 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
222 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
226 static int si_init_surface(struct si_screen
*sscreen
,
227 struct radeon_surf
*surface
,
228 const struct pipe_resource
*ptex
,
229 enum radeon_surf_mode array_mode
,
230 unsigned pitch_in_bytes_override
,
234 bool is_flushed_depth
,
235 bool tc_compatible_htile
)
237 const struct util_format_description
*desc
=
238 util_format_description(ptex
->format
);
239 bool is_depth
, is_stencil
;
241 unsigned i
, bpe
, flags
= 0;
243 is_depth
= util_format_has_depth(desc
);
244 is_stencil
= util_format_has_stencil(desc
);
246 if (!is_flushed_depth
&&
247 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
248 bpe
= 4; /* stencil is allocated separately */
250 bpe
= util_format_get_blocksize(ptex
->format
);
251 assert(util_is_power_of_two_or_zero(bpe
));
254 if (!is_flushed_depth
&& is_depth
) {
255 flags
|= RADEON_SURF_ZBUFFER
;
257 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
258 flags
|= RADEON_SURF_NO_HTILE
;
259 } else if (tc_compatible_htile
&&
260 (sscreen
->info
.chip_class
>= GFX9
||
261 array_mode
== RADEON_SURF_MODE_2D
)) {
262 /* TC-compatible HTILE only supports Z32_FLOAT.
263 * GFX9 also supports Z16_UNORM.
264 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
265 * the format for transfers.
267 if (sscreen
->info
.chip_class
== GFX8
)
270 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
274 flags
|= RADEON_SURF_SBUFFER
;
277 if (sscreen
->info
.chip_class
>= GFX8
&&
278 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
279 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
280 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
281 flags
|= RADEON_SURF_DISABLE_DCC
;
283 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
284 if (sscreen
->info
.family
== CHIP_STONEY
&&
285 bpe
== 16 && ptex
->nr_samples
>= 2)
286 flags
|= RADEON_SURF_DISABLE_DCC
;
288 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
289 if (sscreen
->info
.chip_class
== GFX8
&&
290 ptex
->nr_storage_samples
>= 4 &&
291 ptex
->array_size
> 1)
292 flags
|= RADEON_SURF_DISABLE_DCC
;
294 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
295 if (sscreen
->info
.chip_class
== GFX9
&&
296 ptex
->nr_storage_samples
>= 4)
297 flags
|= RADEON_SURF_DISABLE_DCC
;
299 /* TODO: GFX10: DCC causes corruption with MSAA. */
300 if (sscreen
->info
.chip_class
>= GFX10
&&
301 ptex
->nr_storage_samples
>= 2)
302 flags
|= RADEON_SURF_DISABLE_DCC
;
304 /* Shared textures must always set up DCC.
305 * If it's not present, it will be disabled by
306 * si_get_opaque_metadata later.
308 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
309 flags
|= RADEON_SURF_DISABLE_DCC
;
311 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
312 /* This should catch bugs in gallium users setting incorrect flags. */
313 assert(ptex
->nr_samples
<= 1 &&
314 ptex
->array_size
== 1 &&
316 ptex
->last_level
== 0 &&
317 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
319 flags
|= RADEON_SURF_SCANOUT
;
322 if (ptex
->bind
& PIPE_BIND_SHARED
)
323 flags
|= RADEON_SURF_SHAREABLE
;
325 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
326 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
327 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
328 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
329 flags
|= RADEON_SURF_NO_FMASK
;
331 if (sscreen
->info
.chip_class
>= GFX10
&&
332 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
333 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
334 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
337 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
338 array_mode
, surface
);
343 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
345 if (sscreen
->info
.chip_class
>= GFX9
) {
347 surface
->u
.gfx9
.surf_pitch
= pitch
;
348 if (ptex
->last_level
== 0)
349 surface
->u
.gfx9
.surf
.epitch
= pitch
- 1;
350 surface
->u
.gfx9
.surf_slice_size
=
351 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
353 surface
->u
.gfx9
.surf_offset
= offset
;
356 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
357 surface
->u
.legacy
.level
[0].slice_size_dw
=
358 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
361 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
362 surface
->u
.legacy
.level
[i
].offset
+= offset
;
368 static void si_get_display_metadata(struct si_screen
*sscreen
,
369 struct radeon_surf
*surf
,
370 struct radeon_bo_metadata
*metadata
,
371 enum radeon_surf_mode
*array_mode
,
374 if (sscreen
->info
.chip_class
>= GFX9
) {
375 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
376 *array_mode
= RADEON_SURF_MODE_2D
;
378 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
380 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
381 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
383 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
385 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
386 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
387 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
390 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
391 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
392 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
393 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
394 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
395 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
397 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
398 *array_mode
= RADEON_SURF_MODE_2D
;
399 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
400 *array_mode
= RADEON_SURF_MODE_1D
;
402 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
404 *is_scanout
= metadata
->u
.legacy
.scanout
;
408 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
409 struct si_texture
*tex
)
411 struct si_screen
*sscreen
= sctx
->screen
;
412 struct pipe_context
*ctx
= &sctx
->b
;
414 if (ctx
== sscreen
->aux_context
)
415 simple_mtx_lock(&sscreen
->aux_context_lock
);
417 unsigned n
= sctx
->num_decompress_calls
;
418 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
420 /* Flush only if any fast clear elimination took place. */
421 if (n
!= sctx
->num_decompress_calls
)
422 ctx
->flush(ctx
, NULL
, 0);
424 if (ctx
== sscreen
->aux_context
)
425 simple_mtx_unlock(&sscreen
->aux_context_lock
);
428 void si_texture_discard_cmask(struct si_screen
*sscreen
,
429 struct si_texture
*tex
)
431 if (!tex
->cmask_buffer
)
434 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
437 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
438 tex
->dirty_level_mask
= 0;
440 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
442 if (tex
->cmask_buffer
!= &tex
->buffer
)
443 si_resource_reference(&tex
->cmask_buffer
, NULL
);
445 tex
->cmask_buffer
= NULL
;
447 /* Notify all contexts about the change. */
448 p_atomic_inc(&sscreen
->dirty_tex_counter
);
449 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
452 static bool si_can_disable_dcc(struct si_texture
*tex
)
454 /* We can't disable DCC if it can be written by another process. */
455 return tex
->surface
.dcc_offset
&&
456 (!tex
->buffer
.b
.is_shared
||
457 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
460 static void si_texture_zero_dcc_fields(struct si_texture
*tex
)
462 tex
->surface
.dcc_offset
= 0;
463 tex
->surface
.display_dcc_offset
= 0;
464 tex
->surface
.dcc_retile_map_offset
= 0;
467 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
468 struct si_texture
*tex
)
470 if (!si_can_disable_dcc(tex
)) {
471 assert(tex
->surface
.display_dcc_offset
== 0);
475 assert(tex
->dcc_separate_buffer
== NULL
);
478 si_texture_zero_dcc_fields(tex
);
480 /* Notify all contexts about the change. */
481 p_atomic_inc(&sscreen
->dirty_tex_counter
);
486 * Disable DCC for the texture. (first decompress, then discard metadata).
488 * There is unresolved multi-context synchronization issue between
489 * screen::aux_context and the current context. If applications do this with
490 * multiple contexts, it's already undefined behavior for them and we don't
491 * have to worry about that. The scenario is:
493 * If context 1 disables DCC and context 2 has queued commands that write
494 * to the texture via CB with DCC enabled, and the order of operations is
496 * context 2 queues draw calls rendering to the texture, but doesn't flush
497 * context 1 disables DCC and flushes
498 * context 1 & 2 reset descriptors and FB state
499 * context 2 flushes (new compressed tiles written by the draw calls)
500 * context 1 & 2 read garbage, because DCC is disabled, yet there are
503 * \param sctx the current context if you have one, or sscreen->aux_context
506 bool si_texture_disable_dcc(struct si_context
*sctx
,
507 struct si_texture
*tex
)
509 struct si_screen
*sscreen
= sctx
->screen
;
511 if (!sctx
->has_graphics
)
512 return si_texture_discard_dcc(sscreen
, tex
);
514 if (!si_can_disable_dcc(tex
))
517 if (&sctx
->b
== sscreen
->aux_context
)
518 simple_mtx_lock(&sscreen
->aux_context_lock
);
520 /* Decompress DCC. */
521 si_decompress_dcc(sctx
, tex
);
522 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
524 if (&sctx
->b
== sscreen
->aux_context
)
525 simple_mtx_unlock(&sscreen
->aux_context_lock
);
527 return si_texture_discard_dcc(sscreen
, tex
);
530 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
531 struct si_texture
*tex
,
532 unsigned new_bind_flag
,
533 bool invalidate_storage
)
535 struct pipe_screen
*screen
= sctx
->b
.screen
;
536 struct si_texture
*new_tex
;
537 struct pipe_resource templ
= tex
->buffer
.b
.b
;
540 templ
.bind
|= new_bind_flag
;
542 if (tex
->buffer
.b
.is_shared
)
545 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
546 if (tex
->surface
.is_linear
)
549 /* This fails with MSAA, depth, and compressed textures. */
550 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
551 RADEON_SURF_MODE_LINEAR_ALIGNED
)
555 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
559 /* Copy the pixels to the new texture. */
560 if (!invalidate_storage
) {
561 for (i
= 0; i
<= templ
.last_level
; i
++) {
565 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
566 util_num_layers(&templ
, i
), &box
);
568 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
569 &tex
->buffer
.b
.b
, i
, &box
);
573 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
574 si_texture_discard_cmask(sctx
->screen
, tex
);
575 si_texture_discard_dcc(sctx
->screen
, tex
);
578 /* Replace the structure fields of tex. */
579 tex
->buffer
.b
.b
.bind
= templ
.bind
;
580 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
581 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
582 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
583 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
584 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
585 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
586 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
587 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
589 tex
->surface
= new_tex
->surface
;
590 si_texture_reference(&tex
->flushed_depth_texture
,
591 new_tex
->flushed_depth_texture
);
593 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
594 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
595 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
597 if (tex
->cmask_buffer
== &tex
->buffer
)
598 tex
->cmask_buffer
= NULL
;
600 si_resource_reference(&tex
->cmask_buffer
, NULL
);
602 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
603 tex
->cmask_buffer
= &tex
->buffer
;
605 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
607 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
608 tex
->cb_color_info
= new_tex
->cb_color_info
;
609 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
610 sizeof(tex
->color_clear_value
));
611 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
613 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
614 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
615 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
616 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
617 tex
->db_render_format
= new_tex
->db_render_format
;
618 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
619 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
620 tex
->depth_cleared
= new_tex
->depth_cleared
;
621 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
622 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
623 tex
->db_compatible
= new_tex
->db_compatible
;
624 tex
->can_sample_z
= new_tex
->can_sample_z
;
625 tex
->can_sample_s
= new_tex
->can_sample_s
;
627 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
628 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
629 si_resource_reference(&tex
->dcc_separate_buffer
,
630 new_tex
->dcc_separate_buffer
);
631 si_resource_reference(&tex
->last_dcc_separate_buffer
,
632 new_tex
->last_dcc_separate_buffer
);
634 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
635 assert(!tex
->surface
.htile_offset
);
636 assert(!tex
->cmask_buffer
);
637 assert(!tex
->surface
.fmask_size
);
638 assert(!tex
->surface
.dcc_offset
);
639 assert(!tex
->is_depth
);
642 si_texture_reference(&new_tex
, NULL
);
644 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
647 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
649 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
652 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
653 struct si_texture
*tex
)
655 struct radeon_surf
*surface
= &tex
->surface
;
656 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
657 struct radeon_bo_metadata md
;
659 memset(&md
, 0, sizeof(md
));
661 if (sscreen
->info
.chip_class
>= GFX9
) {
662 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
664 if (tex
->surface
.dcc_offset
&& !tex
->dcc_separate_buffer
) {
665 uint64_t dcc_offset
=
666 tex
->surface
.display_dcc_offset
? tex
->surface
.display_dcc_offset
667 : tex
->surface
.dcc_offset
;
669 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
670 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
671 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
672 md
.u
.gfx9
.dcc_independent_64B
= 1;
675 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
676 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
677 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
678 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
679 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
680 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
681 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
682 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
683 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
684 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
685 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
686 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
689 assert(tex
->dcc_separate_buffer
== NULL
);
690 assert(tex
->surface
.fmask_size
== 0);
692 /* Metadata image format format version 1:
693 * [0] = 1 (metadata format identifier)
694 * [1] = (VENDOR_ID << 16) | PCI_ID
695 * [2:9] = image descriptor for the whole resource
696 * [2] is always 0, because the base address is cleared
697 * [9] is the DCC offset bits [39:8] from the beginning of
699 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
702 md
.metadata
[0] = 1; /* metadata image format version 1 */
704 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
705 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
707 static const unsigned char swizzle
[] = {
713 bool is_array
= util_texture_is_array(res
->target
);
716 sscreen
->make_texture_descriptor(sscreen
, tex
, true,
717 res
->target
, res
->format
,
718 swizzle
, 0, res
->last_level
, 0,
719 is_array
? res
->array_size
- 1 : 0,
720 res
->width0
, res
->height0
, res
->depth0
,
723 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
724 0, 0, tex
->surface
.blk_w
, false, desc
);
726 /* Clear the base address and set the relative DCC offset. */
728 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
730 switch (sscreen
->info
.chip_class
) {
735 desc
[7] = tex
->surface
.dcc_offset
>> 8;
738 desc
[7] = tex
->surface
.dcc_offset
>> 8;
739 desc
[5] &= C_008F24_META_DATA_ADDRESS
;
740 desc
[5] |= S_008F24_META_DATA_ADDRESS(tex
->surface
.dcc_offset
>> 40);
743 desc
[6] &= C_00A018_META_DATA_ADDRESS_LO
;
744 desc
[6] |= S_00A018_META_DATA_ADDRESS_LO(tex
->surface
.dcc_offset
>> 8);
745 desc
[7] = tex
->surface
.dcc_offset
>> 16;
752 /* Dwords [2:9] contain the image descriptor. */
753 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
754 md
.size_metadata
= 10 * 4;
756 /* Dwords [10:..] contain the mipmap level offsets. */
757 if (sscreen
->info
.chip_class
<= GFX8
) {
758 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
759 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
761 md
.size_metadata
+= (1 + res
->last_level
) * 4;
764 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
767 static bool si_read_tex_bo_metadata(struct si_screen
*sscreen
,
768 struct si_texture
*tex
,
769 struct radeon_bo_metadata
*md
)
771 uint32_t *desc
= &md
->metadata
[2];
773 if (md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
774 md
->metadata
[0] == 0 || /* invalid version number */
775 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */ {
776 /* Disable DCC because it might not be enabled. */
777 si_texture_zero_dcc_fields(tex
);
779 /* Don't report an error if the texture comes from an incompatible driver,
780 * but this might not work.
785 /* Validate that sample counts and the number of mipmap levels match. */
786 unsigned last_level
= G_008F1C_LAST_LEVEL(desc
[3]);
787 unsigned type
= G_008F1C_TYPE(desc
[3]);
789 if (type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA
||
790 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
791 unsigned log_samples
=
792 util_logbase2(MAX2(1, tex
->buffer
.b
.b
.nr_storage_samples
));
794 if (last_level
!= log_samples
) {
795 fprintf(stderr
, "radeonsi: invalid MSAA texture import, "
796 "metadata has log2(samples) = %u, the caller set %u\n",
797 last_level
, log_samples
);
801 if (last_level
!= tex
->buffer
.b
.b
.last_level
) {
802 fprintf(stderr
, "radeonsi: invalid mipmapped texture import, "
803 "metadata has last_level = %u, the caller set %u\n",
804 last_level
, tex
->buffer
.b
.b
.last_level
);
809 if (sscreen
->info
.chip_class
>= GFX8
&&
810 G_008F28_COMPRESSION_EN(desc
[6])) {
811 /* Read DCC information.
813 * Some state trackers don't set the SCANOUT flag when
814 * importing displayable images, which affects PIPE_ALIGNED
815 * and RB_ALIGNED, so we need to recover them here.
817 switch (sscreen
->info
.chip_class
) {
819 tex
->surface
.dcc_offset
= (uint64_t)desc
[7] << 8;
823 tex
->surface
.dcc_offset
=
824 ((uint64_t)desc
[7] << 8) |
825 ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
826 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
827 G_008F24_META_PIPE_ALIGNED(desc
[5]);
828 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
829 G_008F24_META_RB_ALIGNED(desc
[5]);
831 /* If DCC is unaligned, this can only be a displayable image. */
832 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
833 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
834 tex
->surface
.is_displayable
= true;
838 tex
->surface
.dcc_offset
=
839 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) |
840 ((uint64_t)desc
[7] << 16);
841 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
842 G_00A018_META_PIPE_ALIGNED(desc
[6]);
850 /* Disable DCC. dcc_offset is always set by texture_from_handle
851 * and must be cleared here.
853 si_texture_zero_dcc_fields(tex
);
859 static bool si_has_displayable_dcc(struct si_texture
*tex
)
861 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
863 if (sscreen
->info
.chip_class
<= GFX8
)
866 /* This needs a cache flush before scanout.
867 * (it can't be scanned out and rendered to simultaneously)
869 if (sscreen
->info
.use_display_dcc_unaligned
&&
870 tex
->surface
.dcc_offset
&&
871 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
872 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
875 /* This needs an explicit flush (flush_resource). */
876 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
877 tex
->surface
.display_dcc_offset
)
883 static bool si_resource_get_param(struct pipe_screen
*screen
,
884 struct pipe_context
*context
,
885 struct pipe_resource
*resource
,
888 enum pipe_resource_param param
,
889 unsigned handle_usage
,
892 for (unsigned i
= 0; i
< plane
; i
++)
893 resource
= resource
->next
;
895 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
896 struct si_texture
*tex
= (struct si_texture
*)resource
;
897 struct winsys_handle whandle
;
900 case PIPE_RESOURCE_PARAM_NPLANES
:
904 case PIPE_RESOURCE_PARAM_STRIDE
:
905 if (resource
->target
== PIPE_BUFFER
)
907 else if (sscreen
->info
.chip_class
>= GFX9
)
908 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
910 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
913 case PIPE_RESOURCE_PARAM_OFFSET
:
914 if (resource
->target
== PIPE_BUFFER
)
916 else if (sscreen
->info
.chip_class
>= GFX9
)
917 *value
= tex
->surface
.u
.gfx9
.surf_offset
+
918 layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
920 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
921 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
924 case PIPE_RESOURCE_PARAM_MODIFIER
:
925 *value
= DRM_FORMAT_MOD_INVALID
;
928 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
929 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
930 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
931 memset(&whandle
, 0, sizeof(whandle
));
933 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
934 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
935 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
936 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
937 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
938 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
940 if (!screen
->resource_get_handle(screen
, context
, resource
,
941 &whandle
, handle_usage
))
944 *value
= whandle
.handle
;
950 static void si_texture_get_info(struct pipe_screen
* screen
,
951 struct pipe_resource
*resource
,
958 si_resource_get_param(screen
, NULL
, resource
, 0, 0,
959 PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
964 si_resource_get_param(screen
, NULL
, resource
, 0, 0,
965 PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
970 static bool si_texture_get_handle(struct pipe_screen
* screen
,
971 struct pipe_context
*ctx
,
972 struct pipe_resource
*resource
,
973 struct winsys_handle
*whandle
,
976 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
977 struct si_context
*sctx
;
978 struct si_resource
*res
= si_resource(resource
);
979 struct si_texture
*tex
= (struct si_texture
*)resource
;
980 bool update_metadata
= false;
981 unsigned stride
, offset
, slice_size
;
984 ctx
= threaded_context_unwrap_sync(ctx
);
985 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
987 if (resource
->target
!= PIPE_BUFFER
) {
988 /* This is not supported now, but it might be required for OpenCL
989 * interop in the future.
991 if (resource
->nr_samples
> 1 || tex
->is_depth
)
994 /* Move a suballocated texture into a non-suballocated allocation. */
995 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
996 tex
->surface
.tile_swizzle
||
997 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
998 sscreen
->info
.has_local_buffers
)) {
999 assert(!res
->b
.is_shared
);
1000 si_reallocate_texture_inplace(sctx
, tex
,
1001 PIPE_BIND_SHARED
, false);
1003 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
1004 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
1005 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
1006 assert(tex
->surface
.tile_swizzle
== 0);
1009 /* Since shader image stores don't support DCC on GFX8,
1010 * disable it for external clients that want write
1013 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
1014 /* Displayable DCC requires an explicit flush. */
1015 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1016 si_has_displayable_dcc(tex
))) {
1017 if (si_texture_disable_dcc(sctx
, tex
)) {
1018 update_metadata
= true;
1019 /* si_texture_disable_dcc flushes the context */
1024 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1025 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
1026 /* Eliminate fast clear (both CMASK and DCC) */
1027 si_eliminate_fast_color_clear(sctx
, tex
);
1028 /* eliminate_fast_color_clear flushes the context */
1031 /* Disable CMASK if flush_resource isn't going
1034 if (tex
->cmask_buffer
)
1035 si_texture_discard_cmask(sscreen
, tex
);
1039 if (!res
->b
.is_shared
|| update_metadata
)
1040 si_set_tex_bo_metadata(sscreen
, tex
);
1042 if (sscreen
->info
.chip_class
>= GFX9
) {
1043 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
1045 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
1048 /* Buffer exports are for the OpenCL interop. */
1049 /* Move a suballocated buffer into a non-suballocated allocation. */
1050 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
1051 /* A DMABUF export always fails if the BO is local. */
1052 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
1053 sscreen
->info
.has_local_buffers
)) {
1054 assert(!res
->b
.is_shared
);
1056 /* Allocate a new buffer with PIPE_BIND_SHARED. */
1057 struct pipe_resource templ
= res
->b
.b
;
1058 templ
.bind
|= PIPE_BIND_SHARED
;
1060 struct pipe_resource
*newb
=
1061 screen
->resource_create(screen
, &templ
);
1065 /* Copy the old buffer contents to the new one. */
1066 struct pipe_box box
;
1067 u_box_1d(0, newb
->width0
, &box
);
1068 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
1069 &res
->b
.b
, 0, &box
);
1071 /* Move the new buffer storage to the old pipe_resource. */
1072 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
1073 pipe_resource_reference(&newb
, NULL
);
1075 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
1076 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
1083 si_texture_get_info(screen
, resource
, &stride
, &offset
);
1086 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
1088 if (res
->b
.is_shared
) {
1089 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
1092 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1093 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1094 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1096 res
->b
.is_shared
= true;
1097 res
->external_usage
= usage
;
1100 whandle
->stride
= stride
;
1101 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
1103 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
1106 static void si_texture_destroy(struct pipe_screen
*screen
,
1107 struct pipe_resource
*ptex
)
1109 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1110 struct si_texture
*tex
= (struct si_texture
*)ptex
;
1111 struct si_resource
*resource
= &tex
->buffer
;
1113 if (sscreen
->info
.chip_class
>= GFX9
)
1114 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
1116 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
1118 if (tex
->cmask_buffer
!= &tex
->buffer
) {
1119 si_resource_reference(&tex
->cmask_buffer
, NULL
);
1121 pb_reference(&resource
->buf
, NULL
);
1122 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
1123 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
1127 static const struct u_resource_vtbl si_texture_vtbl
;
1129 void si_print_texture_info(struct si_screen
*sscreen
,
1130 struct si_texture
*tex
, struct u_log_context
*log
)
1134 /* Common parameters. */
1135 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1136 "blk_h=%u, array_size=%u, last_level=%u, "
1137 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1138 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1139 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1141 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1142 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1143 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1145 if (sscreen
->info
.chip_class
>= GFX9
) {
1146 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1147 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1148 tex
->surface
.surf_size
,
1149 tex
->surface
.u
.gfx9
.surf_slice_size
,
1150 tex
->surface
.surf_alignment
,
1151 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1152 tex
->surface
.u
.gfx9
.surf
.epitch
,
1153 tex
->surface
.u
.gfx9
.surf_pitch
);
1155 if (tex
->surface
.fmask_offset
) {
1156 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1157 "alignment=%u, swmode=%u, epitch=%u\n",
1158 tex
->surface
.fmask_offset
,
1159 tex
->surface
.fmask_size
,
1160 tex
->surface
.fmask_alignment
,
1161 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1162 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1165 if (tex
->cmask_buffer
) {
1166 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1167 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1168 tex
->surface
.cmask_offset
,
1169 tex
->surface
.cmask_size
,
1170 tex
->surface
.cmask_alignment
,
1171 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1172 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1175 if (tex
->surface
.htile_offset
) {
1176 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1177 "rb_aligned=%u, pipe_aligned=%u\n",
1178 tex
->surface
.htile_offset
,
1179 tex
->surface
.htile_size
,
1180 tex
->surface
.htile_alignment
,
1181 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1182 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1185 if (tex
->surface
.dcc_offset
) {
1186 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1187 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1188 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
,
1189 tex
->surface
.dcc_alignment
,
1190 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1191 tex
->surface
.num_dcc_levels
);
1194 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1195 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1196 tex
->surface
.u
.gfx9
.stencil_offset
,
1197 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1198 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1203 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1204 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1205 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1206 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1207 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1208 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1210 if (tex
->surface
.fmask_offset
)
1211 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1212 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1213 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1214 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1215 tex
->surface
.u
.legacy
.fmask
.bankh
,
1216 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1217 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1219 if (tex
->cmask_buffer
)
1220 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1221 "slice_tile_max=%u\n",
1222 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1223 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1225 if (tex
->surface
.htile_offset
)
1226 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1227 "alignment=%u, TC_compatible = %u\n",
1228 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
1229 tex
->surface
.htile_alignment
,
1230 tex
->tc_compatible_htile
);
1232 if (tex
->surface
.dcc_offset
) {
1233 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1234 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
,
1235 tex
->surface
.dcc_alignment
);
1236 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1237 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1238 "fast_clear_size=%u\n",
1239 i
, i
< tex
->surface
.num_dcc_levels
,
1240 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1241 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1244 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1245 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1246 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1247 "mode=%u, tiling_index = %u\n",
1248 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1249 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1250 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1251 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1252 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1253 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1254 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1255 tex
->surface
.u
.legacy
.level
[i
].mode
,
1256 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1258 if (tex
->surface
.has_stencil
) {
1259 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1260 tex
->surface
.u
.legacy
.stencil_tile_split
);
1261 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1262 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1263 "slice_size=%"PRIu64
", npix_x=%u, "
1264 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1265 "mode=%u, tiling_index = %u\n",
1266 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1267 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1268 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1269 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1270 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1271 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1272 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1273 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1274 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1279 /* Common processing for si_texture_create and si_texture_from_handle */
1280 static struct si_texture
*
1281 si_texture_create_object(struct pipe_screen
*screen
,
1282 const struct pipe_resource
*base
,
1283 struct pb_buffer
*buf
,
1284 struct radeon_surf
*surface
)
1286 struct si_texture
*tex
;
1287 struct si_resource
*resource
;
1288 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1290 tex
= CALLOC_STRUCT(si_texture
);
1294 resource
= &tex
->buffer
;
1295 resource
->b
.b
= *base
;
1296 resource
->b
.b
.next
= NULL
;
1297 resource
->b
.vtbl
= &si_texture_vtbl
;
1298 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1299 resource
->b
.b
.screen
= screen
;
1301 /* don't include stencil-only formats which we don't support for rendering */
1302 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1303 tex
->surface
= *surface
;
1304 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1305 (tex
->surface
.flags
&
1306 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1308 /* TC-compatible HTILE:
1309 * - GFX8 only supports Z32_FLOAT.
1310 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1311 if (tex
->tc_compatible_htile
) {
1312 if (sscreen
->info
.chip_class
>= GFX9
&&
1313 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1314 tex
->db_render_format
= base
->format
;
1316 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1317 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1318 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1321 tex
->db_render_format
= base
->format
;
1324 /* Applies to GCN. */
1325 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1327 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1328 * between frames, so the only thing that can enable separate DCC
1329 * with DRI2 is multiple slow clears within a frame.
1331 tex
->ps_draw_ratio
= 0;
1333 if (tex
->is_depth
) {
1334 if (sscreen
->info
.chip_class
>= GFX9
) {
1335 tex
->can_sample_z
= true;
1336 tex
->can_sample_s
= true;
1338 /* Stencil texturing with HTILE doesn't work
1339 * with mipmapping on Navi10-14. */
1340 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1341 sscreen
->info
.family
== CHIP_NAVI12
||
1342 sscreen
->info
.family
== CHIP_NAVI14
) &&
1343 base
->last_level
> 0)
1344 tex
->htile_stencil_disabled
= true;
1346 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1347 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1350 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1352 if (tex
->surface
.cmask_offset
) {
1353 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1354 tex
->cmask_buffer
= &tex
->buffer
;
1358 /* Now create the backing buffer. */
1360 si_init_resource_fields(sscreen
, resource
, tex
->surface
.total_size
,
1361 tex
->surface
.surf_alignment
);
1363 if (!si_alloc_resource(sscreen
, resource
))
1366 resource
->buf
= buf
;
1367 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1368 resource
->bo_size
= buf
->size
;
1369 resource
->bo_alignment
= buf
->alignment
;
1370 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1371 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1372 resource
->vram_usage
= buf
->size
;
1373 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1374 resource
->gart_usage
= buf
->size
;
1377 if (tex
->cmask_buffer
) {
1378 /* Initialize the cmask to 0xCC (= compressed state). */
1379 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1380 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
1383 if (tex
->surface
.htile_offset
) {
1384 uint32_t clear_value
= 0;
1386 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1387 clear_value
= 0x0000030F;
1389 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1390 tex
->surface
.htile_offset
,
1391 tex
->surface
.htile_size
,
1395 /* Initialize DCC only if the texture is not being imported. */
1396 if (!buf
&& tex
->surface
.dcc_offset
) {
1397 /* Clear DCC to black for all tiles with DCC enabled.
1399 * This fixes corruption in 3DMark Slingshot Extreme, which
1400 * uses uninitialized textures, causing corruption.
1402 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1403 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1404 /* Simple case - all tiles have DCC enabled. */
1405 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1406 tex
->surface
.dcc_offset
,
1407 tex
->surface
.dcc_size
,
1408 DCC_CLEAR_COLOR_0000
);
1409 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1410 /* Clear to uncompressed. Clearing this to black is complicated. */
1411 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1412 tex
->surface
.dcc_offset
,
1413 tex
->surface
.dcc_size
,
1416 /* GFX8: Initialize mipmap levels and multisamples separately. */
1417 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1418 /* Clearing this to black is complicated. */
1419 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1420 tex
->surface
.dcc_offset
,
1421 tex
->surface
.dcc_size
,
1424 /* Clear the enabled mipmap levels to black. */
1427 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1428 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1431 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1432 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1435 /* Mipmap levels with DCC. */
1437 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1438 tex
->surface
.dcc_offset
, size
,
1439 DCC_CLEAR_COLOR_0000
);
1441 /* Mipmap levels without DCC. */
1442 if (size
!= tex
->surface
.dcc_size
) {
1443 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1444 tex
->surface
.dcc_offset
+ size
,
1445 tex
->surface
.dcc_size
- size
,
1451 /* Initialize displayable DCC that requires the retile blit. */
1452 if (tex
->surface
.dcc_retile_map_offset
) {
1453 /* Uninitialized DCC can hang the display hw.
1454 * Clear to white to indicate that. */
1455 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1456 tex
->surface
.display_dcc_offset
,
1457 tex
->surface
.u
.gfx9
.display_dcc_size
,
1458 DCC_CLEAR_COLOR_1111
);
1460 /* Upload the DCC retile map.
1461 * Use a staging buffer for the upload, because
1462 * the buffer backing the texture is unmappable.
1464 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1465 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1466 struct si_resource
*buf
=
1467 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1468 num_elements
* (use_uint16
? 2 : 4),
1469 sscreen
->info
.tcc_cache_line_size
);
1470 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1471 PIPE_TRANSFER_WRITE
);
1472 uint16_t *us
= (uint16_t*)ui
;
1474 /* Upload the retile map into a staging buffer. */
1476 for (unsigned i
= 0; i
< num_elements
; i
++)
1477 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1479 for (unsigned i
= 0; i
< num_elements
; i
++)
1480 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1483 /* Copy the staging buffer to the buffer backing the texture. */
1484 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1485 struct pipe_box box
;
1486 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1488 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1489 simple_mtx_lock(&sscreen
->aux_context_lock
);
1490 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1491 tex
->surface
.dcc_retile_map_offset
, 0, 0,
1492 &buf
->b
.b
, 0, &box
);
1493 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1494 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1496 si_resource_reference(&buf
, NULL
);
1500 /* Initialize the CMASK base register value. */
1501 tex
->cmask_base_address_reg
=
1502 (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1504 if (sscreen
->debug_flags
& DBG(VM
)) {
1505 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1506 tex
->buffer
.gpu_address
,
1507 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1508 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1509 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1512 if (sscreen
->debug_flags
& DBG(TEX
)) {
1514 struct u_log_context log
;
1515 u_log_context_init(&log
);
1516 si_print_texture_info(sscreen
, tex
, &log
);
1517 u_log_new_page_print(&log
, stdout
);
1519 u_log_context_destroy(&log
);
1526 if (sscreen
->info
.chip_class
>= GFX9
)
1527 free(surface
->u
.gfx9
.dcc_retile_map
);
1531 static enum radeon_surf_mode
1532 si_choose_tiling(struct si_screen
*sscreen
,
1533 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1535 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1536 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1537 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1538 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1540 /* MSAA resources must be 2D tiled. */
1541 if (templ
->nr_samples
> 1)
1542 return RADEON_SURF_MODE_2D
;
1544 /* Transfer resources should be linear. */
1545 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1546 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1548 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1549 * which requires 2D tiling.
1551 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1552 return RADEON_SURF_MODE_2D
;
1554 /* Handle common candidates for the linear mode.
1555 * Compressed textures and DB surfaces must always be tiled.
1557 if (!force_tiling
&&
1558 !is_depth_stencil
&&
1559 !util_format_is_compressed(templ
->format
)) {
1560 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1561 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1563 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1564 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1565 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1567 /* Cursors are linear on AMD GCN.
1568 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1569 if (templ
->bind
& PIPE_BIND_CURSOR
)
1570 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1572 if (templ
->bind
& PIPE_BIND_LINEAR
)
1573 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1575 /* Textures with a very small height are recommended to be linear. */
1576 if (templ
->target
== PIPE_TEXTURE_1D
||
1577 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1578 /* Only very thin and long 2D textures should benefit from
1579 * linear_aligned. */
1580 (templ
->width0
> 8 && templ
->height0
<= 2))
1581 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1583 /* Textures likely to be mapped often. */
1584 if (templ
->usage
== PIPE_USAGE_STAGING
||
1585 templ
->usage
== PIPE_USAGE_STREAM
)
1586 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1589 /* Make small textures 1D tiled. */
1590 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1591 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1592 return RADEON_SURF_MODE_1D
;
1594 /* The allocator will switch to 1D if needed. */
1595 return RADEON_SURF_MODE_2D
;
1598 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1599 const struct pipe_resource
*templ
)
1601 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1602 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1604 if (templ
->nr_samples
>= 2) {
1605 /* This is hackish (overwriting the const pipe_resource template),
1606 * but should be harmless and state trackers can also see
1607 * the overriden number of samples in the created pipe_resource.
1609 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1610 ((struct pipe_resource
*)templ
)->nr_samples
=
1611 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1612 sscreen
->eqaa_force_z_samples
;
1613 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1614 ((struct pipe_resource
*)templ
)->nr_samples
=
1615 sscreen
->eqaa_force_coverage_samples
;
1616 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1617 sscreen
->eqaa_force_color_samples
;
1621 struct radeon_surf surface
= {0};
1622 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
||
1623 templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1624 bool tc_compatible_htile
=
1625 sscreen
->info
.chip_class
>= GFX8
&&
1626 /* There are issues with TC-compatible HTILE on Tonga (and
1627 * Iceland is the same design), and documented bug workarounds
1628 * don't help. For example, this fails:
1629 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1631 sscreen
->info
.family
!= CHIP_TONGA
&&
1632 sscreen
->info
.family
!= CHIP_ICELAND
&&
1633 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1634 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1635 !is_flushed_depth
&&
1636 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1640 r
= si_init_surface(sscreen
, &surface
, templ
,
1641 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1642 0, 0, false, false, is_flushed_depth
,
1643 tc_compatible_htile
);
1648 return (struct pipe_resource
*)
1649 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1652 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1653 const struct pipe_resource
*templ
,
1654 struct pb_buffer
*buf
,
1660 enum radeon_surf_mode array_mode
;
1661 struct radeon_surf surface
= {};
1662 struct radeon_bo_metadata metadata
= {};
1663 struct si_texture
*tex
;
1668 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1669 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1670 &array_mode
, &is_scanout
);
1673 * The bo metadata is unset for un-dedicated images. So we fall
1674 * back to linear. See answer to question 5 of the
1675 * VK_KHX_external_memory spec for some details.
1677 * It is possible that this case isn't going to work if the
1678 * surface pitch isn't correctly aligned by default.
1680 * In order to support it correctly we require multi-image
1681 * metadata to be syncrhonized between radv and radeonsi. The
1682 * semantics of associating multiple image metadata to a memory
1683 * object on the vulkan export side are not concretely defined
1686 * All the use cases we are aware of at the moment for memory
1687 * objects use dedicated allocations. So lets keep the initial
1688 * implementation simple.
1690 * A possible alternative is to attempt to reconstruct the
1691 * tiling information when the TexParameter TEXTURE_TILING_EXT
1694 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1698 r
= si_init_surface(sscreen
, &surface
, templ
,
1699 array_mode
, stride
, offset
, true, is_scanout
,
1704 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1708 tex
->buffer
.b
.is_shared
= true;
1709 tex
->buffer
.external_usage
= usage
;
1711 if (!si_read_tex_bo_metadata(sscreen
, tex
, &metadata
)) {
1712 si_texture_reference(&tex
, NULL
);
1716 /* Displayable DCC requires an explicit flush. */
1718 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1719 si_has_displayable_dcc(tex
)) {
1720 /* TODO: do we need to decompress DCC? */
1721 if (si_texture_discard_dcc(sscreen
, tex
)) {
1722 /* Update BO metadata after disabling DCC. */
1723 si_set_tex_bo_metadata(sscreen
, tex
);
1727 assert(tex
->surface
.tile_swizzle
== 0);
1728 return &tex
->buffer
.b
.b
;
1731 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1732 const struct pipe_resource
*templ
,
1733 struct winsys_handle
*whandle
,
1736 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1737 struct pb_buffer
*buf
= NULL
;
1739 /* Support only 2D textures without mipmaps */
1740 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1741 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1742 templ
->last_level
!= 0)
1745 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1746 sscreen
->info
.max_alignment
);
1750 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
,
1751 whandle
->stride
, whandle
->offset
,
1755 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1756 struct pipe_resource
*texture
)
1758 struct si_texture
*tex
= (struct si_texture
*)texture
;
1759 struct pipe_resource resource
;
1760 enum pipe_format pipe_format
= texture
->format
;
1762 assert(!tex
->flushed_depth_texture
);
1764 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1765 switch (pipe_format
) {
1766 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1767 /* Save memory by not allocating the S plane. */
1768 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1770 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1771 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1772 /* Save memory bandwidth by not copying the
1773 * stencil part during flush.
1775 * This potentially increases memory bandwidth
1776 * if an application uses both Z and S texturing
1777 * simultaneously (a flushed Z24S8 texture
1778 * would be stored compactly), but how often
1779 * does that really happen?
1781 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1785 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1786 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1788 /* DB->CB copies to an 8bpp surface don't work. */
1789 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1792 memset(&resource
, 0, sizeof(resource
));
1793 resource
.target
= texture
->target
;
1794 resource
.format
= pipe_format
;
1795 resource
.width0
= texture
->width0
;
1796 resource
.height0
= texture
->height0
;
1797 resource
.depth0
= texture
->depth0
;
1798 resource
.array_size
= texture
->array_size
;
1799 resource
.last_level
= texture
->last_level
;
1800 resource
.nr_samples
= texture
->nr_samples
;
1801 resource
.usage
= PIPE_USAGE_DEFAULT
;
1802 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1803 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1805 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1806 if (!tex
->flushed_depth_texture
) {
1807 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1814 * Initialize the pipe_resource descriptor to be of the same size as the box,
1815 * which is supposed to hold a subregion of the texture "orig" at the given
1818 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1819 struct pipe_resource
*orig
,
1820 const struct pipe_box
*box
,
1821 unsigned level
, unsigned flags
)
1823 memset(res
, 0, sizeof(*res
));
1824 res
->format
= orig
->format
;
1825 res
->width0
= box
->width
;
1826 res
->height0
= box
->height
;
1828 res
->array_size
= 1;
1829 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1832 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1833 util_format_is_compressed(orig
->format
)) {
1834 /* Transfer resources are allocated with linear tiling, which is
1835 * not supported for compressed formats.
1837 unsigned blocksize
=
1838 util_format_get_blocksize(orig
->format
);
1840 if (blocksize
== 8) {
1841 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1843 assert(blocksize
== 16);
1844 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1847 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1848 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1851 /* We must set the correct texture target and dimensions for a 3D box. */
1852 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1853 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1854 res
->array_size
= box
->depth
;
1856 res
->target
= PIPE_TEXTURE_2D
;
1860 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1861 struct si_texture
*tex
,
1862 unsigned transfer_usage
,
1863 const struct pipe_box
*box
)
1865 return !tex
->buffer
.b
.is_shared
&&
1866 !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1867 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1868 tex
->buffer
.b
.b
.last_level
== 0 &&
1869 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1870 box
->x
, box
->y
, box
->z
,
1871 box
->width
, box
->height
,
1875 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1876 struct si_texture
*tex
)
1878 struct si_screen
*sscreen
= sctx
->screen
;
1880 /* There is no point in discarding depth and tiled buffers. */
1881 assert(!tex
->is_depth
);
1882 assert(tex
->surface
.is_linear
);
1884 /* Reallocate the buffer in the same pipe_resource. */
1885 si_alloc_resource(sscreen
, &tex
->buffer
);
1887 /* Initialize the CMASK base address (needed even without CMASK). */
1888 tex
->cmask_base_address_reg
=
1889 (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1891 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1893 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1896 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1897 struct pipe_resource
*texture
,
1900 const struct pipe_box
*box
,
1901 struct pipe_transfer
**ptransfer
)
1903 struct si_context
*sctx
= (struct si_context
*)ctx
;
1904 struct si_texture
*tex
= (struct si_texture
*)texture
;
1905 struct si_transfer
*trans
;
1906 struct si_resource
*buf
;
1907 unsigned offset
= 0;
1909 bool use_staging_texture
= false;
1911 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1912 assert(box
->width
&& box
->height
&& box
->depth
);
1914 if (tex
->is_depth
) {
1915 /* Depth textures use staging unconditionally. */
1916 use_staging_texture
= true;
1918 /* Degrade the tile mode if we get too many transfers on APUs.
1919 * On dGPUs, the staging texture is always faster.
1920 * Only count uploads that are at least 4x4 pixels large.
1922 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1924 box
->width
>= 4 && box
->height
>= 4 &&
1925 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1926 bool can_invalidate
=
1927 si_can_invalidate_texture(sctx
->screen
, tex
,
1930 si_reallocate_texture_inplace(sctx
, tex
,
1935 /* Tiled textures need to be converted into a linear texture for CPU
1936 * access. The staging texture is always linear and is placed in GART.
1938 * Reading from VRAM or GTT WC is slow, always use the staging
1939 * texture in this case.
1941 * Use the staging texture for uploads if the underlying BO
1944 if (!tex
->surface
.is_linear
)
1945 use_staging_texture
= true;
1946 else if (usage
& PIPE_TRANSFER_READ
)
1947 use_staging_texture
=
1948 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1949 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1950 /* Write & linear only: */
1951 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1952 RADEON_USAGE_READWRITE
) ||
1953 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1954 RADEON_USAGE_READWRITE
)) {
1956 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1958 si_texture_invalidate_storage(sctx
, tex
);
1960 use_staging_texture
= true;
1964 trans
= CALLOC_STRUCT(si_transfer
);
1967 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1968 trans
->b
.b
.level
= level
;
1969 trans
->b
.b
.usage
= usage
;
1970 trans
->b
.b
.box
= *box
;
1972 if (use_staging_texture
) {
1973 struct pipe_resource resource
;
1974 struct si_texture
*staging
;
1976 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1977 SI_RESOURCE_FLAG_TRANSFER
);
1978 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1979 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1981 /* Since depth-stencil textures don't support linear tiling,
1982 * blit from ZS to color and vice versa. u_blitter will do
1983 * the packing for these formats.
1986 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1988 /* Create the temporary texture. */
1989 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1991 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1994 trans
->staging
= &staging
->buffer
;
1996 /* Just get the strides. */
1997 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1999 &trans
->b
.b
.layer_stride
);
2001 if (usage
& PIPE_TRANSFER_READ
)
2002 si_copy_to_staging_texture(ctx
, trans
);
2004 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
2006 buf
= trans
->staging
;
2008 /* the resource is mapped directly */
2009 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
2011 &trans
->b
.b
.layer_stride
);
2015 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2016 * we don't run out of the CPU address space.
2018 if (sizeof(void*) == 4)
2019 usage
|= RADEON_TRANSFER_TEMPORARY
;
2021 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
2024 *ptransfer
= &trans
->b
.b
;
2025 return map
+ offset
;
2028 si_resource_reference(&trans
->staging
, NULL
);
2029 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
2034 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
2035 struct pipe_transfer
* transfer
)
2037 struct si_context
*sctx
= (struct si_context
*)ctx
;
2038 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
2039 struct pipe_resource
*texture
= transfer
->resource
;
2040 struct si_texture
*tex
= (struct si_texture
*)texture
;
2042 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2043 * we don't run out of the CPU address space.
2045 if (sizeof(void*) == 4) {
2046 struct si_resource
*buf
=
2047 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2049 sctx
->ws
->buffer_unmap(buf
->buf
);
2052 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
2053 si_copy_from_staging_texture(ctx
, stransfer
);
2055 if (stransfer
->staging
) {
2056 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2057 si_resource_reference(&stransfer
->staging
, NULL
);
2060 /* Heuristic for {upload, draw, upload, draw, ..}:
2062 * Flush the gfx IB if we've allocated too much texture storage.
2064 * The idea is that we don't want to build IBs that use too much
2065 * memory and put pressure on the kernel memory manager and we also
2066 * want to make temporary and invalidated buffers go idle ASAP to
2067 * decrease the total memory usage or make them reusable. The memory
2068 * usage will be slightly higher than given here because of the buffer
2069 * cache in the winsys.
2071 * The result is that the kernel memory manager is never a bottleneck.
2073 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2074 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2075 sctx
->num_alloc_tex_transfer_bytes
= 0;
2078 pipe_resource_reference(&transfer
->resource
, NULL
);
2082 static const struct u_resource_vtbl si_texture_vtbl
=
2084 NULL
, /* get_handle */
2085 si_texture_destroy
, /* resource_destroy */
2086 si_texture_transfer_map
, /* transfer_map */
2087 u_default_transfer_flush_region
, /* transfer_flush_region */
2088 si_texture_transfer_unmap
, /* transfer_unmap */
2091 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2093 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
2094 enum pipe_format format1
,
2095 enum pipe_format format2
)
2097 const struct util_format_description
*desc1
, *desc2
;
2099 /* No format change - exit early. */
2100 if (format1
== format2
)
2103 format1
= si_simplify_cb_format(format1
);
2104 format2
= si_simplify_cb_format(format2
);
2106 /* Check again after format adjustments. */
2107 if (format1
== format2
)
2110 desc1
= util_format_description(format1
);
2111 desc2
= util_format_description(format2
);
2113 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2114 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2117 /* Float and non-float are totally incompatible. */
2118 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2119 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2122 /* Channel sizes must match across DCC formats.
2123 * Comparing just the first 2 channels should be enough.
2125 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2126 (desc1
->nr_channels
>= 2 &&
2127 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2130 /* Everything below is not needed if the driver never uses the DCC
2131 * clear code with the value of 1.
2134 /* If the clear values are all 1 or all 0, this constraint can be
2136 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2139 /* Channel types must match if the clear value of 1 is used.
2140 * The type categories are only float, signed, unsigned.
2141 * NORM and INT are always compatible.
2143 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2144 (desc1
->nr_channels
>= 2 &&
2145 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2151 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2153 enum pipe_format view_format
)
2155 struct si_texture
*stex
= (struct si_texture
*)tex
;
2157 return vi_dcc_enabled(stex
, level
) &&
2158 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
,
2159 tex
->format
, view_format
);
2162 /* This can't be merged with the above function, because
2163 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2164 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2165 struct pipe_resource
*tex
,
2167 enum pipe_format view_format
)
2169 struct si_texture
*stex
= (struct si_texture
*)tex
;
2171 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2172 if (!si_texture_disable_dcc(sctx
, stex
))
2173 si_decompress_dcc(sctx
, stex
);
2176 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2177 struct pipe_resource
*texture
,
2178 const struct pipe_surface
*templ
,
2179 unsigned width0
, unsigned height0
,
2180 unsigned width
, unsigned height
)
2182 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2187 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2188 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2190 pipe_reference_init(&surface
->base
.reference
, 1);
2191 pipe_resource_reference(&surface
->base
.texture
, texture
);
2192 surface
->base
.context
= pipe
;
2193 surface
->base
.format
= templ
->format
;
2194 surface
->base
.width
= width
;
2195 surface
->base
.height
= height
;
2196 surface
->base
.u
= templ
->u
;
2198 surface
->width0
= width0
;
2199 surface
->height0
= height0
;
2201 surface
->dcc_incompatible
=
2202 texture
->target
!= PIPE_BUFFER
&&
2203 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2205 return &surface
->base
;
2208 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2209 struct pipe_resource
*tex
,
2210 const struct pipe_surface
*templ
)
2212 unsigned level
= templ
->u
.tex
.level
;
2213 unsigned width
= u_minify(tex
->width0
, level
);
2214 unsigned height
= u_minify(tex
->height0
, level
);
2215 unsigned width0
= tex
->width0
;
2216 unsigned height0
= tex
->height0
;
2218 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2219 const struct util_format_description
*tex_desc
2220 = util_format_description(tex
->format
);
2221 const struct util_format_description
*templ_desc
2222 = util_format_description(templ
->format
);
2224 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2226 /* Adjust size of surface if and only if the block width or
2227 * height is changed. */
2228 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2229 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2230 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2231 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2233 width
= nblks_x
* templ_desc
->block
.width
;
2234 height
= nblks_y
* templ_desc
->block
.height
;
2236 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2237 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2241 return si_create_surface_custom(pipe
, tex
, templ
,
2246 static void si_surface_destroy(struct pipe_context
*pipe
,
2247 struct pipe_surface
*surface
)
2249 pipe_resource_reference(&surface
->texture
, NULL
);
2253 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2255 const struct util_format_description
*desc
= util_format_description(format
);
2257 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2259 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2260 return V_028C70_SWAP_STD
;
2262 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2265 switch (desc
->nr_channels
) {
2267 if (HAS_SWIZZLE(0,X
))
2268 return V_028C70_SWAP_STD
; /* X___ */
2269 else if (HAS_SWIZZLE(3,X
))
2270 return V_028C70_SWAP_ALT_REV
; /* ___X */
2273 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2274 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2275 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2276 return V_028C70_SWAP_STD
; /* XY__ */
2277 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2278 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2279 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2281 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2282 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2283 return V_028C70_SWAP_ALT
; /* X__Y */
2284 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2285 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2288 if (HAS_SWIZZLE(0,X
))
2289 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2290 else if (HAS_SWIZZLE(0,Z
))
2291 return V_028C70_SWAP_STD_REV
; /* ZYX */
2294 /* check the middle channels, the 1st and 4th channel can be NONE */
2295 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2296 return V_028C70_SWAP_STD
; /* XYZW */
2297 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2298 return V_028C70_SWAP_STD_REV
; /* WZYX */
2299 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2300 return V_028C70_SWAP_ALT
; /* ZYXW */
2301 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2304 return V_028C70_SWAP_ALT_REV
;
2306 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2313 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2315 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2320 if (sctx
->dcc_stats
[slot
].query_active
)
2321 vi_separate_dcc_stop_query(sctx
,
2322 sctx
->dcc_stats
[slot
].tex
);
2324 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2325 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2326 sctx
->b
.destroy_query(&sctx
->b
,
2327 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2328 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2331 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2335 * Return the per-context slot where DCC statistics queries for the texture live.
2337 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2338 struct si_texture
*tex
)
2340 int i
, empty_slot
= -1;
2342 /* Remove zombie textures (textures kept alive by this array only). */
2343 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2344 if (sctx
->dcc_stats
[i
].tex
&&
2345 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2346 vi_dcc_clean_up_context_slot(sctx
, i
);
2348 /* Find the texture. */
2349 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2350 /* Return if found. */
2351 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2352 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2356 /* Record the first seen empty slot. */
2357 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2361 /* Not found. Remove the oldest member to make space in the array. */
2362 if (empty_slot
== -1) {
2363 int oldest_slot
= 0;
2365 /* Find the oldest slot. */
2366 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2367 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2368 sctx
->dcc_stats
[i
].last_use_timestamp
)
2371 /* Clean up the oldest slot. */
2372 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2373 empty_slot
= oldest_slot
;
2376 /* Add the texture to the new slot. */
2377 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2378 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2382 static struct pipe_query
*
2383 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2385 struct si_query_hw
*query
= (struct si_query_hw
*)
2386 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2388 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2389 return (struct pipe_query
*)query
;
2393 * Called when binding a color buffer.
2395 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2396 struct si_texture
*tex
)
2398 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2400 assert(!sctx
->dcc_stats
[i
].query_active
);
2402 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2403 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2405 /* begin or resume the query */
2406 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2407 sctx
->dcc_stats
[i
].query_active
= true;
2411 * Called when unbinding a color buffer.
2413 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2414 struct si_texture
*tex
)
2416 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2418 assert(sctx
->dcc_stats
[i
].query_active
);
2419 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2421 /* pause or end the query */
2422 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2423 sctx
->dcc_stats
[i
].query_active
= false;
2426 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2428 /* The minimum number of fullscreen draws per frame that is required
2430 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2433 /* Called by fast clear. */
2434 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2435 struct si_texture
*tex
)
2437 /* The intent is to use this with shared displayable back buffers,
2438 * but it's not strictly limited only to them.
2440 if (!tex
->buffer
.b
.is_shared
||
2441 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2442 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2443 tex
->buffer
.b
.b
.last_level
> 0 ||
2444 !tex
->surface
.dcc_size
||
2445 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2446 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2449 assert(sctx
->chip_class
>= GFX8
);
2451 if (tex
->surface
.dcc_offset
)
2452 return; /* already enabled */
2454 /* Enable the DCC stat gathering. */
2455 if (!tex
->dcc_gather_statistics
) {
2456 tex
->dcc_gather_statistics
= true;
2457 vi_separate_dcc_start_query(sctx
, tex
);
2460 if (!vi_should_enable_separate_dcc(tex
))
2461 return; /* stats show that DCC decompression is too expensive */
2463 assert(tex
->surface
.num_dcc_levels
);
2464 assert(!tex
->dcc_separate_buffer
);
2466 si_texture_discard_cmask(sctx
->screen
, tex
);
2468 /* Get a DCC buffer. */
2469 if (tex
->last_dcc_separate_buffer
) {
2470 assert(tex
->dcc_gather_statistics
);
2471 assert(!tex
->dcc_separate_buffer
);
2472 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2473 tex
->last_dcc_separate_buffer
= NULL
;
2475 tex
->dcc_separate_buffer
=
2476 si_aligned_buffer_create(sctx
->b
.screen
,
2477 SI_RESOURCE_FLAG_UNMAPPABLE
,
2479 tex
->surface
.dcc_size
,
2480 tex
->surface
.dcc_alignment
);
2481 if (!tex
->dcc_separate_buffer
)
2485 /* dcc_offset is the absolute GPUVM address. */
2486 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2488 /* no need to flag anything since this is called by fast clear that
2489 * flags framebuffer state
2494 * Called by pipe_context::flush_resource, the place where DCC decompression
2497 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2498 struct si_texture
*tex
)
2500 struct si_context
*sctx
= (struct si_context
*)ctx
;
2501 struct pipe_query
*tmp
;
2502 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2503 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2504 bool disable
= false;
2506 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2507 union pipe_query_result result
;
2509 /* Read the results. */
2510 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2511 ctx
->get_query_result(ctx
, query
,
2513 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2515 /* Compute the approximate number of fullscreen draws. */
2516 tex
->ps_draw_ratio
=
2517 result
.pipeline_statistics
.ps_invocations
/
2518 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2519 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2521 disable
= tex
->dcc_separate_buffer
&&
2522 !vi_should_enable_separate_dcc(tex
);
2525 tex
->num_slow_clears
= 0;
2527 /* stop the statistics query for ps_stats[0] */
2529 vi_separate_dcc_stop_query(sctx
, tex
);
2531 /* Move the queries in the queue by one. */
2532 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2533 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2534 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2535 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2537 /* create and start a new query as ps_stats[0] */
2539 vi_separate_dcc_start_query(sctx
, tex
);
2542 assert(!tex
->last_dcc_separate_buffer
);
2543 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2544 tex
->dcc_separate_buffer
= NULL
;
2545 tex
->surface
.dcc_offset
= 0;
2546 /* no need to flag anything since this is called after
2547 * decompression that re-sets framebuffer state
2552 static struct pipe_memory_object
*
2553 si_memobj_from_handle(struct pipe_screen
*screen
,
2554 struct winsys_handle
*whandle
,
2557 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2558 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2559 struct pb_buffer
*buf
= NULL
;
2564 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2565 sscreen
->info
.max_alignment
);
2571 memobj
->b
.dedicated
= dedicated
;
2573 memobj
->stride
= whandle
->stride
;
2575 return (struct pipe_memory_object
*)memobj
;
2580 si_memobj_destroy(struct pipe_screen
*screen
,
2581 struct pipe_memory_object
*_memobj
)
2583 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2585 pb_reference(&memobj
->buf
, NULL
);
2589 static struct pipe_resource
*
2590 si_texture_from_memobj(struct pipe_screen
*screen
,
2591 const struct pipe_resource
*templ
,
2592 struct pipe_memory_object
*_memobj
,
2595 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2596 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2597 struct pipe_resource
*tex
=
2598 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2599 memobj
->stride
, offset
,
2600 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2601 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2602 memobj
->b
.dedicated
);
2606 /* si_texture_from_winsys_buffer doesn't increment refcount of
2607 * memobj->buf, so increment it here.
2609 struct pb_buffer
*buf
= NULL
;
2610 pb_reference(&buf
, memobj
->buf
);
2614 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2615 struct pipe_resource
*resource
,
2618 struct si_texture
*tex
= (struct si_texture
*)resource
;
2620 /* Buffers only support the linear flag. */
2621 if (resource
->target
== PIPE_BUFFER
)
2622 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2624 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2627 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2630 /* TODO: PIPE_BIND_CURSOR - do we care? */
2634 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2636 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2637 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2638 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2639 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2640 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2641 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2642 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2643 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2646 void si_init_context_texture_functions(struct si_context
*sctx
)
2648 sctx
->b
.create_surface
= si_create_surface
;
2649 sctx
->b
.surface_destroy
= si_surface_destroy
;