gallium: pipe_get_tile_swizzle() accepts format parameter.
[mesa.git] / src / gallium / drivers / softpipe / sp_tex_tile_cache.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * Texture tile caching.
30 *
31 * Author:
32 * Brian Paul
33 */
34
35 #include "util/u_inlines.h"
36 #include "util/u_memory.h"
37 #include "util/u_tile.h"
38 #include "util/u_math.h"
39 #include "sp_context.h"
40 #include "sp_texture.h"
41 #include "sp_tex_tile_cache.h"
42
43
44
45 struct softpipe_tex_tile_cache *
46 sp_create_tex_tile_cache( struct pipe_screen *screen )
47 {
48 struct softpipe_tex_tile_cache *tc;
49 uint pos;
50
51 tc = CALLOC_STRUCT( softpipe_tex_tile_cache );
52 if (tc) {
53 tc->screen = screen;
54 for (pos = 0; pos < NUM_ENTRIES; pos++) {
55 tc->entries[pos].addr.bits.invalid = 1;
56 }
57 tc->last_tile = &tc->entries[0]; /* any tile */
58 }
59 return tc;
60 }
61
62
63 void
64 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc)
65 {
66 struct pipe_screen *screen;
67 uint pos;
68
69 for (pos = 0; pos < NUM_ENTRIES; pos++) {
70 /*assert(tc->entries[pos].x < 0);*/
71 }
72 if (tc->transfer) {
73 screen = tc->transfer->texture->screen;
74 screen->tex_transfer_destroy(tc->transfer);
75 }
76 if (tc->tex_trans) {
77 screen = tc->tex_trans->texture->screen;
78 screen->tex_transfer_destroy(tc->tex_trans);
79 }
80
81 FREE( tc );
82 }
83
84
85
86
87 void
88 sp_tex_tile_cache_map_transfers(struct softpipe_tex_tile_cache *tc)
89 {
90 if (tc->tex_trans && !tc->tex_trans_map)
91 tc->tex_trans_map = tc->screen->transfer_map(tc->screen, tc->tex_trans);
92 }
93
94
95 void
96 sp_tex_tile_cache_unmap_transfers(struct softpipe_tex_tile_cache *tc)
97 {
98 if (tc->tex_trans_map) {
99 tc->screen->transfer_unmap(tc->screen, tc->tex_trans);
100 tc->tex_trans_map = NULL;
101 }
102 }
103
104 /**
105 * Invalidate all cached tiles for the cached texture.
106 * Should be called when the texture is modified.
107 */
108 void
109 sp_tex_tile_cache_validate_texture(struct softpipe_tex_tile_cache *tc)
110 {
111 unsigned i;
112
113 assert(tc);
114 assert(tc->texture);
115
116 for (i = 0; i < NUM_ENTRIES; i++) {
117 tc->entries[i].addr.bits.invalid = 1;
118 }
119 }
120
121 /**
122 * Specify the sampler view to cache.
123 */
124 void
125 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
126 struct pipe_sampler_view *view)
127 {
128 struct pipe_texture *texture = view ? view->texture : NULL;
129 uint i;
130
131 assert(!tc->transfer);
132
133 if (tc->texture != texture) {
134 pipe_texture_reference(&tc->texture, texture);
135
136 if (tc->tex_trans) {
137 struct pipe_screen *screen = tc->tex_trans->texture->screen;
138
139 if (tc->tex_trans_map) {
140 screen->transfer_unmap(screen, tc->tex_trans);
141 tc->tex_trans_map = NULL;
142 }
143
144 screen->tex_transfer_destroy(tc->tex_trans);
145 tc->tex_trans = NULL;
146 }
147
148 if (view) {
149 tc->swizzle_r = view->swizzle_r;
150 tc->swizzle_g = view->swizzle_g;
151 tc->swizzle_b = view->swizzle_b;
152 tc->swizzle_a = view->swizzle_a;
153 tc->format = view->format;
154 }
155
156 /* mark as entries as invalid/empty */
157 /* XXX we should try to avoid this when the teximage hasn't changed */
158 for (i = 0; i < NUM_ENTRIES; i++) {
159 tc->entries[i].addr.bits.invalid = 1;
160 }
161
162 tc->tex_face = -1; /* any invalid value here */
163 }
164 }
165
166
167
168
169 /**
170 * Flush the tile cache: write all dirty tiles back to the transfer.
171 * any tiles "flagged" as cleared will be "really" cleared.
172 */
173 void
174 sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc)
175 {
176 int pos;
177
178 if (tc->texture) {
179 /* caching a texture, mark all entries as empty */
180 for (pos = 0; pos < NUM_ENTRIES; pos++) {
181 tc->entries[pos].addr.bits.invalid = 1;
182 }
183 tc->tex_face = -1;
184 }
185
186 }
187
188
189 /**
190 * Given the texture face, level, zslice, x and y values, compute
191 * the cache entry position/index where we'd hope to find the
192 * cached texture tile.
193 * This is basically a direct-map cache.
194 * XXX There's probably lots of ways in which we can improve this.
195 */
196 static INLINE uint
197 tex_cache_pos( union tex_tile_address addr )
198 {
199 uint entry = (addr.bits.x +
200 addr.bits.y * 9 +
201 addr.bits.z * 3 +
202 addr.bits.face +
203 addr.bits.level * 7);
204
205 return entry % NUM_ENTRIES;
206 }
207
208 /**
209 * Similar to sp_get_cached_tile() but for textures.
210 * Tiles are read-only and indexed with more params.
211 */
212 const struct softpipe_tex_cached_tile *
213 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
214 union tex_tile_address addr )
215 {
216 struct pipe_screen *screen = tc->screen;
217 struct softpipe_tex_cached_tile *tile;
218
219 tile = tc->entries + tex_cache_pos( addr );
220
221 if (addr.value != tile->addr.value) {
222
223 /* cache miss. Most misses are because we've invaldiated the
224 * texture cache previously -- most commonly on binding a new
225 * texture. Currently we effectively flush the cache on texture
226 * bind.
227 */
228 #if 0
229 _debug_printf("miss at %u: x=%d y=%d z=%d face=%d level=%d\n"
230 " tile %u: x=%d y=%d z=%d face=%d level=%d\n",
231 pos, x/TILE_SIZE, y/TILE_SIZE, z, face, level,
232 pos, tile->addr.bits.x, tile->addr.bits.y, tile->z, tile->face, tile->level);
233 #endif
234
235 /* check if we need to get a new transfer */
236 if (!tc->tex_trans ||
237 tc->tex_face != addr.bits.face ||
238 tc->tex_level != addr.bits.level ||
239 tc->tex_z != addr.bits.z) {
240 /* get new transfer (view into texture) */
241
242 if (tc->tex_trans) {
243 if (tc->tex_trans_map) {
244 tc->screen->transfer_unmap(tc->screen, tc->tex_trans);
245 tc->tex_trans_map = NULL;
246 }
247
248 screen->tex_transfer_destroy(tc->tex_trans);
249 tc->tex_trans = NULL;
250 }
251
252 tc->tex_trans =
253 screen->get_tex_transfer(screen, tc->texture,
254 addr.bits.face,
255 addr.bits.level,
256 addr.bits.z,
257 PIPE_TRANSFER_READ, 0, 0,
258 u_minify(tc->texture->width0, addr.bits.level),
259 u_minify(tc->texture->height0, addr.bits.level));
260
261 tc->tex_trans_map = screen->transfer_map(screen, tc->tex_trans);
262
263 tc->tex_face = addr.bits.face;
264 tc->tex_level = addr.bits.level;
265 tc->tex_z = addr.bits.z;
266 }
267
268 /* get tile from the transfer (view into texture) */
269 pipe_get_tile_swizzle(tc->tex_trans,
270 addr.bits.x * TILE_SIZE,
271 addr.bits.y * TILE_SIZE,
272 TILE_SIZE,
273 TILE_SIZE,
274 tc->swizzle_r,
275 tc->swizzle_g,
276 tc->swizzle_b,
277 tc->swizzle_a,
278 tc->format,
279 (float *) tile->data.color);
280 tile->addr = addr;
281 }
282
283 tc->last_tile = tile;
284 return tile;
285 }
286
287
288