s/Tungsten Graphics/VMware/
[mesa.git] / src / gallium / drivers / softpipe / sp_tex_tile_cache.h
1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef SP_TEX_TILE_CACHE_H
29 #define SP_TEX_TILE_CACHE_H
30
31
32 #include "pipe/p_compiler.h"
33 #include "sp_limits.h"
34
35
36 struct softpipe_context;
37 struct softpipe_tex_tile_cache;
38
39
40 /**
41 * Cache tile size (width and height). This needs to be a power of two.
42 */
43 #define TEX_TILE_SIZE_LOG2 5
44 #define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
45
46
47 #define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
48 #define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
49
50 /**
51 * Texture tile address as a union for fast compares.
52 */
53 union tex_tile_address {
54 struct {
55 unsigned x:TEX_ADDR_BITS; /* 16K / TILE_SIZE */
56 unsigned y:TEX_ADDR_BITS; /* 16K / TILE_SIZE */
57 unsigned z:TEX_Z_BITS; /* 16K -- z not tiled */
58 unsigned face:3;
59 unsigned level:4;
60 unsigned invalid:1;
61 } bits;
62 uint64_t value;
63 };
64
65
66 struct softpipe_tex_cached_tile
67 {
68 union tex_tile_address addr;
69 union {
70 float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
71 unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
72 int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
73 } data;
74 };
75
76 /*
77 * The number of cache entries.
78 * Should not be decreased to lower than 16, and even that
79 * seems too low to avoid cache thrashing in some cases (because
80 * the cache is direct mapped, see tex_cache_pos() function).
81 */
82 #define NUM_TEX_TILE_ENTRIES 16
83
84 struct softpipe_tex_tile_cache
85 {
86 struct pipe_context *pipe;
87 struct pipe_transfer *transfer;
88 void *transfer_map;
89
90 struct pipe_resource *texture; /**< if caching a texture */
91 unsigned timestamp;
92
93 struct softpipe_tex_cached_tile entries[NUM_TEX_TILE_ENTRIES];
94
95 struct pipe_transfer *tex_trans;
96 void *tex_trans_map;
97 int tex_face, tex_level, tex_z;
98
99 unsigned swizzle_r;
100 unsigned swizzle_g;
101 unsigned swizzle_b;
102 unsigned swizzle_a;
103 enum pipe_format format;
104
105 struct softpipe_tex_cached_tile *last_tile; /**< most recently retrieved tile */
106 };
107
108
109 extern struct softpipe_tex_tile_cache *
110 sp_create_tex_tile_cache( struct pipe_context *pipe );
111
112 extern void
113 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
114
115 extern void
116 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
117 struct pipe_sampler_view *view);
118
119 void
120 sp_tex_tile_cache_validate_texture(struct softpipe_tex_tile_cache *tc);
121
122 extern void
123 sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
124
125
126
127 extern const struct softpipe_tex_cached_tile *
128 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
129 union tex_tile_address addr );
130
131 static INLINE union tex_tile_address
132 tex_tile_address( unsigned x,
133 unsigned y,
134 unsigned z,
135 unsigned face,
136 unsigned level )
137 {
138 union tex_tile_address addr;
139
140 addr.value = 0;
141 addr.bits.x = x / TEX_TILE_SIZE;
142 addr.bits.y = y / TEX_TILE_SIZE;
143 addr.bits.z = z;
144 addr.bits.face = face;
145 addr.bits.level = level;
146
147 return addr;
148 }
149
150 /* Quickly retrieve tile if it matches last lookup.
151 */
152 static INLINE const struct softpipe_tex_cached_tile *
153 sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
154 union tex_tile_address addr )
155 {
156 if (tc->last_tile->addr.value == addr.value)
157 return tc->last_tile;
158
159 return sp_find_cached_tile_tex( tc, addr );
160 }
161
162
163 #endif /* SP_TEX_TILE_CACHE_H */
164