Merge remote branch 'origin/master' into radeon-rewrite
[mesa.git] / src / gallium / drivers / softpipe / sp_tile_cache.h
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef SP_TILE_CACHE_H
29 #define SP_TILE_CACHE_H
30
31 #define TILE_CLEAR_OPTIMIZATION 1
32
33
34 #include "pipe/p_compiler.h"
35
36
37 struct softpipe_context;
38 struct softpipe_tile_cache;
39
40
41 /**
42 * Cache tile size (width and height). This needs to be a power of two.
43 */
44 #define TILE_SIZE 64
45
46
47
48 struct softpipe_cached_tile
49 {
50 int x, y; /**< pos of tile in window coords */
51 int z, face, level; /**< Extra texture indexes */
52 union {
53 float color[TILE_SIZE][TILE_SIZE][4];
54 uint color32[TILE_SIZE][TILE_SIZE];
55 uint depth32[TILE_SIZE][TILE_SIZE];
56 ushort depth16[TILE_SIZE][TILE_SIZE];
57 ubyte stencil8[TILE_SIZE][TILE_SIZE];
58 ubyte any[1];
59 } data;
60 };
61
62
63 extern struct softpipe_tile_cache *
64 sp_create_tile_cache( struct pipe_screen *screen );
65
66 extern void
67 sp_destroy_tile_cache(struct softpipe_tile_cache *tc);
68
69 extern void
70 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
71 struct pipe_surface *sps);
72
73 extern struct pipe_surface *
74 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc);
75
76 extern void
77 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc);
78
79 extern void
80 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc);
81
82 extern void
83 sp_tile_cache_set_texture(struct pipe_context *pipe,
84 struct softpipe_tile_cache *tc,
85 struct pipe_texture *texture);
86
87 extern void
88 sp_flush_tile_cache(struct softpipe_context *softpipe,
89 struct softpipe_tile_cache *tc);
90
91 extern void
92 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
93 uint clearValue);
94
95 extern struct softpipe_cached_tile *
96 sp_get_cached_tile(struct softpipe_context *softpipe,
97 struct softpipe_tile_cache *tc, int x, int y);
98
99 extern const struct softpipe_cached_tile *
100 sp_get_cached_tile_tex(struct softpipe_context *softpipe,
101 struct softpipe_tile_cache *tc, int x, int y, int z,
102 int face, int level);
103
104
105 #endif /* SP_TILE_CACHE_H */
106