Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / svga / svga_context.h
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 #ifndef SVGA_CONTEXT_H
27 #define SVGA_CONTEXT_H
28
29
30 #include "pipe/p_context.h"
31 #include "pipe/p_defines.h"
32 #include "pipe/p_state.h"
33
34 #include "util/u_blitter.h"
35 #include "util/list.h"
36
37 #include "tgsi/tgsi_scan.h"
38
39 #include "svga_screen.h"
40 #include "svga_state.h"
41 #include "svga_winsys.h"
42 #include "svga_hw_reg.h"
43 #include "svga3d_shaderdefs.h"
44
45
46 /** Non-GPU queries for gallium HUD */
47 /* per-frame counters */
48 #define SVGA_QUERY_NUM_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
49 #define SVGA_QUERY_NUM_FALLBACKS (PIPE_QUERY_DRIVER_SPECIFIC + 1)
50 #define SVGA_QUERY_NUM_FLUSHES (PIPE_QUERY_DRIVER_SPECIFIC + 2)
51 #define SVGA_QUERY_NUM_VALIDATIONS (PIPE_QUERY_DRIVER_SPECIFIC + 3)
52 #define SVGA_QUERY_MAP_BUFFER_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 4)
53 #define SVGA_QUERY_NUM_RESOURCES_MAPPED (PIPE_QUERY_DRIVER_SPECIFIC + 5)
54 #define SVGA_QUERY_NUM_BYTES_UPLOADED (PIPE_QUERY_DRIVER_SPECIFIC + 6)
55
56 /* running total counters */
57 #define SVGA_QUERY_MEMORY_USED (PIPE_QUERY_DRIVER_SPECIFIC + 7)
58 #define SVGA_QUERY_NUM_SHADERS (PIPE_QUERY_DRIVER_SPECIFIC + 8)
59 #define SVGA_QUERY_NUM_RESOURCES (PIPE_QUERY_DRIVER_SPECIFIC + 9)
60 #define SVGA_QUERY_NUM_STATE_OBJECTS (PIPE_QUERY_DRIVER_SPECIFIC + 10)
61 #define SVGA_QUERY_NUM_SURFACE_VIEWS (PIPE_QUERY_DRIVER_SPECIFIC + 11)
62 /*SVGA_QUERY_MAX has to be last because it is size of an array*/
63 #define SVGA_QUERY_MAX (PIPE_QUERY_DRIVER_SPECIFIC + 12)
64
65 /**
66 * Maximum supported number of constant buffers per shader
67 */
68 #define SVGA_MAX_CONST_BUFS 14
69
70 /**
71 * Maximum constant buffer size that can be set in the
72 * DXSetSingleConstantBuffer command is
73 * DX10 constant buffer element count * 4 4-bytes components
74 */
75 #define SVGA_MAX_CONST_BUF_SIZE (4096 * 4 * sizeof(int))
76
77 struct draw_vertex_shader;
78 struct draw_fragment_shader;
79 struct svga_shader_variant;
80 struct SVGACmdMemory;
81 struct util_bitmask;
82
83
84 struct svga_cache_context;
85 struct svga_tracked_state;
86
87 struct svga_blend_state {
88 unsigned need_white_fragments:1;
89 unsigned independent_blend_enable:1;
90 unsigned alpha_to_coverage:1;
91 unsigned blend_color_alpha:1; /**< set blend color to alpha value */
92
93 /** Per-render target state */
94 struct {
95 uint8_t writemask;
96
97 boolean blend_enable;
98 uint8_t srcblend;
99 uint8_t dstblend;
100 uint8_t blendeq;
101
102 boolean separate_alpha_blend_enable;
103 uint8_t srcblend_alpha;
104 uint8_t dstblend_alpha;
105 uint8_t blendeq_alpha;
106 } rt[PIPE_MAX_COLOR_BUFS];
107
108 SVGA3dBlendStateId id; /**< vgpu10 */
109 };
110
111 struct svga_depth_stencil_state {
112 unsigned zfunc:8;
113 unsigned zenable:1;
114 unsigned zwriteenable:1;
115
116 unsigned alphatestenable:1;
117 unsigned alphafunc:8;
118
119 struct {
120 unsigned enabled:1;
121 unsigned func:8;
122 unsigned fail:8;
123 unsigned zfail:8;
124 unsigned pass:8;
125 } stencil[2];
126
127 /* SVGA3D has one ref/mask/writemask triple shared between front &
128 * back face stencil. We really need two:
129 */
130 unsigned stencil_mask:8;
131 unsigned stencil_writemask:8;
132
133 float alpharef;
134
135 SVGA3dDepthStencilStateId id; /**< vgpu10 */
136 };
137
138 #define SVGA_UNFILLED_DISABLE 0
139 #define SVGA_UNFILLED_LINE 1
140 #define SVGA_UNFILLED_POINT 2
141
142 #define SVGA_PIPELINE_FLAG_POINTS (1<<PIPE_PRIM_POINTS)
143 #define SVGA_PIPELINE_FLAG_LINES (1<<PIPE_PRIM_LINES)
144 #define SVGA_PIPELINE_FLAG_TRIS (1<<PIPE_PRIM_TRIANGLES)
145
146 struct svga_rasterizer_state {
147 struct pipe_rasterizer_state templ; /* needed for draw module */
148
149 unsigned shademode:8;
150 unsigned cullmode:8;
151 unsigned scissortestenable:1;
152 unsigned multisampleantialias:1;
153 unsigned antialiasedlineenable:1;
154 unsigned lastpixel:1;
155 unsigned pointsprite:1;
156
157 unsigned linepattern;
158
159 float slopescaledepthbias;
160 float depthbias;
161 float pointsize;
162 float linewidth;
163
164 unsigned hw_fillmode:2; /* PIPE_POLYGON_MODE_x */
165
166 /** Which prims do we need help for? Bitmask of (1 << PIPE_PRIM_x) flags */
167 unsigned need_pipeline:16;
168
169 SVGA3dRasterizerStateId id; /**< vgpu10 */
170
171 /** For debugging: */
172 const char* need_pipeline_tris_str;
173 const char* need_pipeline_lines_str;
174 const char* need_pipeline_points_str;
175 };
176
177 struct svga_sampler_state {
178 unsigned mipfilter;
179 unsigned magfilter;
180 unsigned minfilter;
181 unsigned aniso_level;
182 float lod_bias;
183 unsigned addressu;
184 unsigned addressv;
185 unsigned addressw;
186 unsigned bordercolor;
187 unsigned normalized_coords:1;
188 unsigned compare_mode:1;
189 unsigned compare_func:3;
190
191 unsigned min_lod;
192 unsigned view_min_lod;
193 unsigned view_max_lod;
194
195 SVGA3dSamplerId id;
196 };
197
198
199 struct svga_pipe_sampler_view
200 {
201 struct pipe_sampler_view base;
202
203 SVGA3dShaderResourceViewId id;
204 };
205
206
207 static inline struct svga_pipe_sampler_view *
208 svga_pipe_sampler_view(struct pipe_sampler_view *v)
209 {
210 return (struct svga_pipe_sampler_view *) v;
211 }
212
213
214 struct svga_velems_state {
215 unsigned count;
216 struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
217 SVGA3dDeclType decl_type[PIPE_MAX_ATTRIBS]; /**< vertex attrib formats */
218
219 /** Bitmasks indicating which attributes need format conversion */
220 unsigned adjust_attrib_range; /**< range adjustment */
221 unsigned attrib_is_pure_int; /**< pure int */
222 unsigned adjust_attrib_w_1; /**< set w = 1 */
223 unsigned adjust_attrib_itof; /**< int->float */
224 unsigned adjust_attrib_utof; /**< uint->float */
225 unsigned attrib_is_bgra; /**< R / B swizzling */
226 unsigned attrib_puint_to_snorm; /**< 10_10_10_2 packed uint -> snorm */
227 unsigned attrib_puint_to_uscaled; /**< 10_10_10_2 packed uint -> uscaled */
228 unsigned attrib_puint_to_sscaled; /**< 10_10_10_2 packed uint -> sscaled */
229
230 boolean need_swvfetch;
231
232 SVGA3dElementLayoutId id; /**< VGPU10 */
233 };
234
235 /* Use to calculate differences between state emitted to hardware and
236 * current driver-calculated state.
237 */
238 struct svga_state
239 {
240 const struct svga_blend_state *blend;
241 const struct svga_depth_stencil_state *depth;
242 const struct svga_rasterizer_state *rast;
243 const struct svga_sampler_state *sampler[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
244 const struct svga_velems_state *velems;
245
246 struct pipe_sampler_view *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS]; /* or texture ID's? */
247 struct svga_fragment_shader *fs;
248 struct svga_vertex_shader *vs;
249 struct svga_geometry_shader *user_gs; /* user-specified GS */
250 struct svga_geometry_shader *gs; /* derived GS */
251
252 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
253 struct pipe_index_buffer ib;
254 /** Constant buffers for each shader.
255 * The size should probably always match with that of
256 * svga_shader_emitter_v10.num_shader_consts.
257 */
258 struct pipe_constant_buffer constbufs[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
259
260 struct pipe_framebuffer_state framebuffer;
261 float depthscale;
262
263 /* Hack to limit the number of different render targets between
264 * flushes. Helps avoid blowing out our surface cache in EXA.
265 */
266 int nr_fbs;
267
268 struct pipe_poly_stipple poly_stipple;
269 struct pipe_scissor_state scissor;
270 struct pipe_blend_color blend_color;
271 struct pipe_stencil_ref stencil_ref;
272 struct pipe_clip_state clip;
273 struct pipe_viewport_state viewport;
274
275 unsigned num_samplers[PIPE_SHADER_TYPES];
276 unsigned num_sampler_views[PIPE_SHADER_TYPES];
277 unsigned num_vertex_buffers;
278 unsigned reduced_prim;
279
280 struct {
281 unsigned flag_1d;
282 unsigned flag_srgb;
283 } tex_flags;
284
285 unsigned sample_mask;
286 };
287
288 struct svga_prescale {
289 float translate[4];
290 float scale[4];
291 boolean enabled;
292 };
293
294
295 /* Updated by calling svga_update_state( SVGA_STATE_HW_CLEAR )
296 */
297 struct svga_hw_clear_state
298 {
299 SVGA3dRect viewport;
300
301 struct {
302 float zmin, zmax;
303 } depthrange;
304
305 struct pipe_framebuffer_state framebuffer;
306 struct svga_prescale prescale;
307 };
308
309 struct svga_hw_view_state
310 {
311 struct pipe_resource *texture;
312 struct svga_sampler_view *v;
313 unsigned min_lod;
314 unsigned max_lod;
315 int dirty;
316 };
317
318 /* Updated by calling svga_update_state( SVGA_STATE_HW_DRAW )
319 */
320 struct svga_hw_draw_state
321 {
322 unsigned rs[SVGA3D_RS_MAX];
323 unsigned ts[SVGA3D_PIXEL_SAMPLERREG_MAX][SVGA3D_TS_MAX];
324 float cb[PIPE_SHADER_TYPES][SVGA3D_CONSTREG_MAX][4];
325
326 struct svga_shader_variant *fs;
327 struct svga_shader_variant *vs;
328 struct svga_shader_variant *gs;
329 struct svga_hw_view_state views[PIPE_MAX_SAMPLERS];
330 unsigned num_views;
331 struct pipe_resource *constbuf[PIPE_SHADER_TYPES];
332
333 /* Bitmask of enabled constant bufffers */
334 unsigned enabled_constbufs[PIPE_SHADER_TYPES];
335
336 /* VGPU10 HW state (used to prevent emitting redundant state) */
337 SVGA3dDepthStencilStateId depth_stencil_id;
338 unsigned stencil_ref;
339 SVGA3dBlendStateId blend_id;
340 float blend_factor[4];
341 unsigned blend_sample_mask;
342 SVGA3dRasterizerStateId rasterizer_id;
343 SVGA3dElementLayoutId layout_id;
344 SVGA3dPrimitiveType topology;
345
346 /* used for rebinding */
347 unsigned num_sampler_views[PIPE_SHADER_TYPES];
348 unsigned default_constbuf_size[PIPE_SHADER_TYPES];
349 };
350
351
352 /* Updated by calling svga_update_state( SVGA_STATE_NEED_SWTNL )
353 */
354 struct svga_sw_state
355 {
356 /* which parts we need */
357 boolean need_swvfetch;
358 boolean need_pipeline;
359 boolean need_swtnl;
360
361 /* Flag to make sure that need sw is on while
362 * updating state within a swtnl call.
363 */
364 boolean in_swtnl_draw;
365 };
366
367
368 /* Queue some state updates (like rss) and submit them to hardware in
369 * a single packet.
370 */
371 struct svga_hw_queue;
372
373 struct svga_query;
374 struct svga_qmem_alloc_entry;
375
376 struct svga_context
377 {
378 struct pipe_context pipe;
379 struct svga_winsys_context *swc;
380 struct blitter_context *blitter;
381 struct u_upload_mgr *const0_upload;
382
383 struct {
384 boolean no_swtnl;
385 boolean force_swtnl;
386 boolean use_min_mipmap;
387
388 /* incremented for each shader */
389 unsigned shader_id;
390
391 unsigned disable_shader;
392
393 boolean no_line_width;
394 boolean force_hw_line_stipple;
395 } debug;
396
397 struct {
398 struct draw_context *draw;
399 struct vbuf_render *backend;
400 unsigned hw_prim;
401 boolean new_vbuf;
402 boolean new_vdecl;
403 } swtnl;
404
405 /* Bitmask of blend state objects IDs */
406 struct util_bitmask *blend_object_id_bm;
407
408 /* Bitmask of depth/stencil state objects IDs */
409 struct util_bitmask *ds_object_id_bm;
410
411 /* Bitmaks of input element object IDs */
412 struct util_bitmask *input_element_object_id_bm;
413
414 /* Bitmask of rasterizer object IDs */
415 struct util_bitmask *rast_object_id_bm;
416
417 /* Bitmask of sampler state objects IDs */
418 struct util_bitmask *sampler_object_id_bm;
419
420 /* Bitmask of sampler view IDs */
421 struct util_bitmask *sampler_view_id_bm;
422
423 /* Bitmask of used shader IDs */
424 struct util_bitmask *shader_id_bm;
425
426 /* Bitmask of used surface view IDs */
427 struct util_bitmask *surface_view_id_bm;
428
429 /* Bitmask of used stream output IDs */
430 struct util_bitmask *stream_output_id_bm;
431
432 /* Bitmask of used query IDs */
433 struct util_bitmask *query_id_bm;
434
435 struct {
436 unsigned dirty[SVGA_STATE_MAX];
437
438 /** bitmasks of which const buffers are changed */
439 unsigned dirty_constbufs[PIPE_SHADER_TYPES];
440
441 unsigned texture_timestamp;
442
443 /*
444 */
445 struct svga_sw_state sw;
446 struct svga_hw_draw_state hw_draw;
447 struct svga_hw_clear_state hw_clear;
448 } state;
449
450 struct svga_state curr; /* state from the state tracker */
451 unsigned dirty; /* statechanges since last update_state() */
452
453 union {
454 struct {
455 unsigned rendertargets:1;
456 unsigned texture_samplers:1;
457 unsigned constbufs:1;
458 unsigned vs:1;
459 unsigned fs:1;
460 unsigned gs:1;
461 unsigned query:1;
462 } flags;
463 unsigned val;
464 } rebind;
465
466 struct svga_hwtnl *hwtnl;
467
468 /** Queries states */
469 struct svga_winsys_gb_query *gb_query; /**< gb query object, one per context */
470 unsigned gb_query_len; /**< gb query object size */
471 struct util_bitmask *gb_query_alloc_mask; /**< gb query object allocation mask */
472 struct svga_qmem_alloc_entry *gb_query_map[SVGA_QUERY_MAX];
473 /**< query mem block mapping */
474 struct svga_query *sq[SVGA_QUERY_MAX]; /**< queries currently in progress */
475
476 /** List of buffers with queued transfers */
477 struct list_head dirty_buffers;
478
479 /** performance / info queries for HUD */
480 struct {
481 uint64_t num_draw_calls; /**< SVGA_QUERY_DRAW_CALLS */
482 uint64_t num_fallbacks; /**< SVGA_QUERY_NUM_FALLBACKS */
483 uint64_t num_flushes; /**< SVGA_QUERY_NUM_FLUSHES */
484 uint64_t num_validations; /**< SVGA_QUERY_NUM_VALIDATIONS */
485 uint64_t map_buffer_time; /**< SVGA_QUERY_MAP_BUFFER_TIME */
486 uint64_t num_resources_mapped; /**< SVGA_QUERY_NUM_RESOURCES_MAPPED */
487 uint64_t num_shaders; /**< SVGA_QUERY_NUM_SHADERS */
488 uint64_t num_state_objects; /**< SVGA_QUERY_NUM_STATE_OBJECTS */
489 uint64_t num_surface_views; /**< SVGA_QUERY_NUM_SURFACE_VIEWS */
490 uint64_t num_bytes_uploaded; /**< SVGA_QUERY_NUM_BYTES_UPLOADED */
491 } hud;
492
493 /** The currently bound stream output targets */
494 unsigned num_so_targets;
495 struct svga_winsys_surface *so_surfaces[SVGA3D_DX_MAX_SOTARGETS];
496 struct pipe_stream_output_target *so_targets[SVGA3D_DX_MAX_SOTARGETS];
497 struct svga_stream_output *current_so;
498
499 /** A blend state with blending disabled, for falling back to when blending
500 * is illegal (e.g. an integer texture is bound)
501 */
502 struct svga_blend_state *noop_blend;
503
504 struct {
505 struct pipe_resource *texture;
506 struct svga_pipe_sampler_view *sampler_view;
507 void *sampler;
508 } polygon_stipple;
509
510 /** Alternate rasterizer states created for point sprite */
511 struct svga_rasterizer_state *rasterizer_no_cull[2];
512 };
513
514 /* A flag for each state_tracker state object:
515 */
516 #define SVGA_NEW_BLEND 0x1
517 #define SVGA_NEW_DEPTH_STENCIL_ALPHA 0x2
518 #define SVGA_NEW_RAST 0x4
519 #define SVGA_NEW_SAMPLER 0x8
520 #define SVGA_NEW_TEXTURE 0x10
521 #define SVGA_NEW_VBUFFER 0x20
522 #define SVGA_NEW_VELEMENT 0x40
523 #define SVGA_NEW_FS 0x80
524 #define SVGA_NEW_VS 0x100
525 #define SVGA_NEW_FS_CONST_BUFFER 0x200
526 #define SVGA_NEW_VS_CONST_BUFFER 0x400
527 #define SVGA_NEW_FRAME_BUFFER 0x800
528 #define SVGA_NEW_STIPPLE 0x1000
529 #define SVGA_NEW_SCISSOR 0x2000
530 #define SVGA_NEW_BLEND_COLOR 0x4000
531 #define SVGA_NEW_CLIP 0x8000
532 #define SVGA_NEW_VIEWPORT 0x10000
533 #define SVGA_NEW_PRESCALE 0x20000
534 #define SVGA_NEW_REDUCED_PRIMITIVE 0x40000
535 #define SVGA_NEW_TEXTURE_BINDING 0x80000
536 #define SVGA_NEW_NEED_PIPELINE 0x100000
537 #define SVGA_NEW_NEED_SWVFETCH 0x200000
538 #define SVGA_NEW_NEED_SWTNL 0x400000
539 #define SVGA_NEW_FS_VARIANT 0x800000
540 #define SVGA_NEW_VS_VARIANT 0x1000000
541 #define SVGA_NEW_TEXTURE_FLAGS 0x4000000
542 #define SVGA_NEW_STENCIL_REF 0x8000000
543 #define SVGA_NEW_GS 0x10000000
544 #define SVGA_NEW_GS_CONST_BUFFER 0x20000000
545 #define SVGA_NEW_GS_VARIANT 0x40000000
546
547
548
549
550 /***********************************************************************
551 * svga_clear.c:
552 */
553 void svga_clear(struct pipe_context *pipe,
554 unsigned buffers,
555 const union pipe_color_union *color,
556 double depth,
557 unsigned stencil);
558
559
560 /***********************************************************************
561 * svga_screen_texture.c:
562 */
563 void svga_mark_surfaces_dirty(struct svga_context *svga);
564
565
566
567
568 void svga_init_state_functions( struct svga_context *svga );
569 void svga_init_flush_functions( struct svga_context *svga );
570 void svga_init_string_functions( struct svga_context *svga );
571 void svga_init_blit_functions(struct svga_context *svga);
572
573 void svga_init_blend_functions( struct svga_context *svga );
574 void svga_init_depth_stencil_functions( struct svga_context *svga );
575 void svga_init_misc_functions( struct svga_context *svga );
576 void svga_init_rasterizer_functions( struct svga_context *svga );
577 void svga_init_sampler_functions( struct svga_context *svga );
578 void svga_init_fs_functions( struct svga_context *svga );
579 void svga_init_vs_functions( struct svga_context *svga );
580 void svga_init_gs_functions( struct svga_context *svga );
581 void svga_init_vertex_functions( struct svga_context *svga );
582 void svga_init_constbuffer_functions( struct svga_context *svga );
583 void svga_init_draw_functions( struct svga_context *svga );
584 void svga_init_query_functions( struct svga_context *svga );
585 void svga_init_surface_functions(struct svga_context *svga);
586 void svga_init_stream_output_functions( struct svga_context *svga );
587
588 void svga_cleanup_vertex_state( struct svga_context *svga );
589 void svga_cleanup_tss_binding( struct svga_context *svga );
590 void svga_cleanup_framebuffer( struct svga_context *svga );
591
592 void svga_context_flush( struct svga_context *svga,
593 struct pipe_fence_handle **pfence );
594
595 void svga_context_finish(struct svga_context *svga);
596
597 void svga_hwtnl_flush_retry( struct svga_context *svga );
598 void svga_hwtnl_flush_buffer( struct svga_context *svga,
599 struct pipe_resource *buffer );
600
601 void svga_surfaces_flush(struct svga_context *svga);
602
603 struct pipe_context *
604 svga_context_create(struct pipe_screen *screen,
605 void *priv, unsigned flags);
606
607
608 /***********************************************************************
609 * Inline conversion functions. These are better-typed than the
610 * macros used previously:
611 */
612 static inline struct svga_context *
613 svga_context( struct pipe_context *pipe )
614 {
615 return (struct svga_context *)pipe;
616 }
617
618
619 static inline boolean
620 svga_have_gb_objects(const struct svga_context *svga)
621 {
622 return svga_screen(svga->pipe.screen)->sws->have_gb_objects;
623 }
624
625 static inline boolean
626 svga_have_gb_dma(const struct svga_context *svga)
627 {
628 return svga_screen(svga->pipe.screen)->sws->have_gb_dma;
629 }
630
631 static inline boolean
632 svga_have_vgpu10(const struct svga_context *svga)
633 {
634 return svga_screen(svga->pipe.screen)->sws->have_vgpu10;
635 }
636
637 static inline boolean
638 svga_need_to_rebind_resources(const struct svga_context *svga)
639 {
640 return svga_screen(svga->pipe.screen)->sws->need_to_rebind_resources;
641 }
642
643 static inline boolean
644 svga_rects_equal(const SVGA3dRect *r1, const SVGA3dRect *r2)
645 {
646 return memcmp(r1, r2, sizeof(*r1)) == 0;
647 }
648
649 #endif