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488c68785c193bb6217ed3a85b50c512a4afe302
[mesa.git] / src / gallium / drivers / svga / svga_format.c
1 /**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_format.h"
28 #include "util/u_debug.h"
29 #include "util/format/u_format.h"
30 #include "util/u_memory.h"
31
32 #include "svga_winsys.h"
33 #include "svga_screen.h"
34 #include "svga_format.h"
35
36
37 /** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38 struct vgpu10_format_entry
39 {
40 SVGA3dSurfaceFormat vertex_format;
41 SVGA3dSurfaceFormat pixel_format;
42 SVGA3dSurfaceFormat view_format; /* view format for texture buffer */
43 unsigned flags;
44 };
45
46 struct format_compat_entry
47 {
48 enum pipe_format pformat;
49 const SVGA3dSurfaceFormat *compat_format;
50 };
51
52
53 /**
54 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
55 * Note: the table is ordered according to PIPE_FORMAT_x order.
56 */
57 static const struct vgpu10_format_entry format_conversion_table[] =
58 {
59 /* Gallium format SVGA3D vertex format SVGA3D pixel format SVGA3D texbuf view format Flags */
60 [ PIPE_FORMAT_B8G8R8A8_UNORM ] = { SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
61 [ PIPE_FORMAT_B8G8R8X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
62 [ PIPE_FORMAT_B5G5R5A1_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
63 [ PIPE_FORMAT_B5G6R5_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
64 [ PIPE_FORMAT_R10G10B10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
65 [ PIPE_FORMAT_L8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXX1 },
66 [ PIPE_FORMAT_A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_000X},
67 [ PIPE_FORMAT_I8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXXX },
68 [ PIPE_FORMAT_L8A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UNORM, TF_XXXY },
69 [ PIPE_FORMAT_L16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXX1 },
70 [ PIPE_FORMAT_Z16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, SVGA3D_D16_UNORM, 0 },
71 [ PIPE_FORMAT_Z32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, SVGA3D_D32_FLOAT, 0 },
72 [ PIPE_FORMAT_Z24_UNORM_S8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
73 [ PIPE_FORMAT_Z24X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
74 [ PIPE_FORMAT_R32_FLOAT ] = { SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
75 [ PIPE_FORMAT_R32G32_FLOAT ] = { SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
76 [ PIPE_FORMAT_R32G32B32_FLOAT ] = { SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
77 [ PIPE_FORMAT_R32G32B32A32_FLOAT ] = { SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
78 [ PIPE_FORMAT_R32_USCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
79 [ PIPE_FORMAT_R32G32_USCALED ] = { SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
80 [ PIPE_FORMAT_R32G32B32_USCALED ] = { SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
81 [ PIPE_FORMAT_R32G32B32A32_USCALED ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
82 [ PIPE_FORMAT_R32_SSCALED ] = { SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
83 [ PIPE_FORMAT_R32G32_SSCALED ] = { SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
84 [ PIPE_FORMAT_R32G32B32_SSCALED ] = { SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
85 [ PIPE_FORMAT_R32G32B32A32_SSCALED ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
86 [ PIPE_FORMAT_R16_UNORM ] = { SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
87 [ PIPE_FORMAT_R16G16_UNORM ] = { SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
88 [ PIPE_FORMAT_R16G16B16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
89 [ PIPE_FORMAT_R16G16B16A16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
90 [ PIPE_FORMAT_R16_USCALED ] = { SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
91 [ PIPE_FORMAT_R16G16_USCALED ] = { SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
92 [ PIPE_FORMAT_R16G16B16_USCALED ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
93 [ PIPE_FORMAT_R16G16B16A16_USCALED ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
94 [ PIPE_FORMAT_R16_SNORM ] = { SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
95 [ PIPE_FORMAT_R16G16_SNORM ] = { SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
96 [ PIPE_FORMAT_R16G16B16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
97 [ PIPE_FORMAT_R16G16B16A16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
98 [ PIPE_FORMAT_R16_SSCALED ] = { SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
99 [ PIPE_FORMAT_R16G16_SSCALED ] = { SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
100 [ PIPE_FORMAT_R16G16B16_SSCALED ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
101 [ PIPE_FORMAT_R16G16B16A16_SSCALED ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
102 [ PIPE_FORMAT_R8_UNORM ] = { SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
103 [ PIPE_FORMAT_R8G8_UNORM ] = { SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
104 [ PIPE_FORMAT_R8G8B8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
105 [ PIPE_FORMAT_R8G8B8A8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
106 [ PIPE_FORMAT_R8_USCALED ] = { SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
107 [ PIPE_FORMAT_R8G8_USCALED ] = { SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
108 [ PIPE_FORMAT_R8G8B8_USCALED ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
109 [ PIPE_FORMAT_R8G8B8A8_USCALED ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
110
111 [ PIPE_FORMAT_R8_SNORM ] = { SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
112 [ PIPE_FORMAT_R8G8_SNORM ] = { SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
113 [ PIPE_FORMAT_R8G8B8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
114 [ PIPE_FORMAT_R8G8B8A8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
115
116 [ PIPE_FORMAT_R8_SSCALED ] = { SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
117 [ PIPE_FORMAT_R8G8_SSCALED ] = { SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
118 [ PIPE_FORMAT_R8G8B8_SSCALED ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
119 [ PIPE_FORMAT_R8G8B8A8_SSCALED ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
120
121 [ PIPE_FORMAT_R16_FLOAT ] = { SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
122 [ PIPE_FORMAT_R16G16_FLOAT ] = { SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
123 [ PIPE_FORMAT_R16G16B16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
124 [ PIPE_FORMAT_R16G16B16A16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
125 [ PIPE_FORMAT_B8G8R8A8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
126 [ PIPE_FORMAT_B8G8R8X8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
127 [ PIPE_FORMAT_R8G8B8A8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
128 [ PIPE_FORMAT_DXT1_RGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
129 [ PIPE_FORMAT_DXT1_RGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
130 [ PIPE_FORMAT_DXT3_RGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, SVGA3D_FORMAT_INVALID, 0 },
131 [ PIPE_FORMAT_DXT5_RGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, SVGA3D_FORMAT_INVALID, 0 },
132 [ PIPE_FORMAT_DXT1_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
133 [ PIPE_FORMAT_DXT1_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
134 [ PIPE_FORMAT_DXT3_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
135 [ PIPE_FORMAT_DXT5_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
136 [ PIPE_FORMAT_RGTC1_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, SVGA3D_FORMAT_INVALID, 0 },
137 [ PIPE_FORMAT_RGTC1_SNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, SVGA3D_FORMAT_INVALID, 0 },
138 [ PIPE_FORMAT_RGTC2_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, SVGA3D_FORMAT_INVALID, 0 },
139 [ PIPE_FORMAT_RGTC2_SNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, SVGA3D_FORMAT_INVALID, 0 },
140 [ PIPE_FORMAT_R10G10B10A2_USCALED ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
141 [ PIPE_FORMAT_R11G11B10_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
142 [ PIPE_FORMAT_R9G9B9E5_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3D_FORMAT_INVALID, 0 },
143 [ PIPE_FORMAT_Z32_FLOAT_S8X24_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
144 [ PIPE_FORMAT_B10G10R10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA },
145 [ PIPE_FORMAT_L16A16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UNORM, TF_XXXY },
146 [ PIPE_FORMAT_A16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_000X },
147 [ PIPE_FORMAT_I16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXXX },
148 [ PIPE_FORMAT_A16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_000X },
149 [ PIPE_FORMAT_L16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXX1 },
150 [ PIPE_FORMAT_L16A16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_FLOAT, TF_XXXY },
151 [ PIPE_FORMAT_I16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXXX },
152 [ PIPE_FORMAT_A32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_000X },
153 [ PIPE_FORMAT_L32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXX1 },
154 [ PIPE_FORMAT_L32A32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_FLOAT, TF_XXXY },
155 [ PIPE_FORMAT_I32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXXX },
156 [ PIPE_FORMAT_R10G10B10A2_SSCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
157 [ PIPE_FORMAT_R10G10B10A2_SNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
158 [ PIPE_FORMAT_B10G10R10A2_USCALED ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
159 [ PIPE_FORMAT_B10G10R10A2_SSCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
160 [ PIPE_FORMAT_B10G10R10A2_SNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
161 [ PIPE_FORMAT_R8_UINT ] = { SVGA3D_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
162 [ PIPE_FORMAT_R8G8_UINT ] = { SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
163 [ PIPE_FORMAT_R8G8B8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
164 [ PIPE_FORMAT_R8G8B8A8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
165 [ PIPE_FORMAT_R8_SINT ] = { SVGA3D_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
166 [ PIPE_FORMAT_R8G8_SINT ] = { SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
167 [ PIPE_FORMAT_R8G8B8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
168 [ PIPE_FORMAT_R8G8B8A8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
169 [ PIPE_FORMAT_R16_UINT ] = { SVGA3D_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
170 [ PIPE_FORMAT_R16G16_UINT ] = { SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
171 [ PIPE_FORMAT_R16G16B16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
172 [ PIPE_FORMAT_R16G16B16A16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
173 [ PIPE_FORMAT_R16_SINT ] = { SVGA3D_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
174 [ PIPE_FORMAT_R16G16_SINT ] = { SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
175 [ PIPE_FORMAT_R16G16B16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
176 [ PIPE_FORMAT_R16G16B16A16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
177 [ PIPE_FORMAT_R32_UINT ] = { SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
178 [ PIPE_FORMAT_R32G32_UINT ] = { SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
179 [ PIPE_FORMAT_R32G32B32_UINT ] = { SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
180 [ PIPE_FORMAT_R32G32B32A32_UINT ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
181 [ PIPE_FORMAT_R32_SINT ] = { SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
182 [ PIPE_FORMAT_R32G32_SINT ] = { SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
183 [ PIPE_FORMAT_R32G32B32_SINT ] = { SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
184 [ PIPE_FORMAT_R32G32B32A32_SINT ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
185 [ PIPE_FORMAT_A8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_000X },
186 [ PIPE_FORMAT_I8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXXX },
187 [ PIPE_FORMAT_L8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXX1 },
188 [ PIPE_FORMAT_L8A8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UINT, TF_XXXY },
189 [ PIPE_FORMAT_A8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_000X },
190 [ PIPE_FORMAT_I8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXXX },
191 [ PIPE_FORMAT_L8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXX1 },
192 [ PIPE_FORMAT_L8A8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_SINT, TF_XXXY },
193 [ PIPE_FORMAT_A16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_000X },
194 [ PIPE_FORMAT_I16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXXX },
195 [ PIPE_FORMAT_L16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXX1 },
196 [ PIPE_FORMAT_L16A16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UINT, TF_XXXY },
197 [ PIPE_FORMAT_A16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_000X },
198 [ PIPE_FORMAT_I16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXXX },
199 [ PIPE_FORMAT_L16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXX1 },
200 [ PIPE_FORMAT_L16A16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_SINT, TF_XXXY },
201 [ PIPE_FORMAT_A32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_000X },
202 [ PIPE_FORMAT_I32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXXX },
203 [ PIPE_FORMAT_L32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXX1 },
204 [ PIPE_FORMAT_L32A32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_UINT, TF_XXXY },
205 [ PIPE_FORMAT_A32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_000X },
206 [ PIPE_FORMAT_I32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXXX },
207 [ PIPE_FORMAT_L32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXX1 },
208 [ PIPE_FORMAT_L32A32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_SINT, TF_XXXY },
209 [ PIPE_FORMAT_R10G10B10A2_UINT ] = { SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
210 };
211
212
213 static const struct vgpu10_format_entry *
214 svga_format_entry(enum pipe_format format)
215 {
216 /* Sparse filling of the table requires this. */
217 STATIC_ASSERT(SVGA3D_FORMAT_INVALID == 0);
218 assert(format < ARRAY_SIZE(format_conversion_table));
219 if (format >= ARRAY_SIZE(format_conversion_table))
220 return &format_conversion_table[PIPE_FORMAT_NONE];
221 else
222 return &format_conversion_table[format];
223 }
224
225 /**
226 * Translate a gallium vertex format to a vgpu10 vertex format.
227 * Also, return any special vertex format flags.
228 */
229 void
230 svga_translate_vertex_format_vgpu10(enum pipe_format format,
231 SVGA3dSurfaceFormat *svga_format,
232 unsigned *vf_flags)
233 {
234 const struct vgpu10_format_entry *entry = svga_format_entry(format);
235
236 *svga_format = entry->vertex_format;
237 *vf_flags = entry->flags;
238 }
239
240
241 /**
242 * Translate a gallium pixel format to a vgpu10 format
243 * to be used in a shader resource view for a texture buffer.
244 * Also return any special texture format flags such as
245 * any special swizzle mask.
246 */
247 void
248 svga_translate_texture_buffer_view_format(enum pipe_format format,
249 SVGA3dSurfaceFormat *svga_format,
250 unsigned *tf_flags)
251 {
252 const struct vgpu10_format_entry *entry = svga_format_entry(format);
253
254 *svga_format = entry->view_format;
255 *tf_flags = entry->flags;
256 }
257
258
259 /**
260 * Translate a gallium scanout format to a svga format valid
261 * for screen target surface.
262 */
263 static SVGA3dSurfaceFormat
264 svga_translate_screen_target_format_vgpu10(enum pipe_format format)
265 {
266 switch (format) {
267 case PIPE_FORMAT_B8G8R8A8_UNORM:
268 return SVGA3D_B8G8R8A8_UNORM;
269 case PIPE_FORMAT_B8G8R8X8_UNORM:
270 return SVGA3D_B8G8R8X8_UNORM;
271 case PIPE_FORMAT_B5G6R5_UNORM:
272 return SVGA3D_R5G6B5;
273 case PIPE_FORMAT_B5G5R5A1_UNORM:
274 return SVGA3D_A1R5G5B5;
275 default:
276 debug_printf("Invalid format %s specified for screen target\n",
277 svga_format_name(format));
278 return SVGA3D_FORMAT_INVALID;
279 }
280 }
281
282 /*
283 * Translate from gallium format to SVGA3D format.
284 */
285 SVGA3dSurfaceFormat
286 svga_translate_format(const struct svga_screen *ss,
287 enum pipe_format format,
288 unsigned bind)
289 {
290 const struct vgpu10_format_entry *entry = svga_format_entry(format);
291
292 if (ss->sws->have_vgpu10) {
293 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
294 return entry->vertex_format;
295 }
296 else if (bind & PIPE_BIND_SCANOUT) {
297 return svga_translate_screen_target_format_vgpu10(format);
298 }
299 else {
300 return entry->pixel_format;
301 }
302 }
303
304 switch(format) {
305 case PIPE_FORMAT_B8G8R8A8_UNORM:
306 return SVGA3D_A8R8G8B8;
307 case PIPE_FORMAT_B8G8R8X8_UNORM:
308 return SVGA3D_X8R8G8B8;
309
310 /* sRGB required for GL2.1 */
311 case PIPE_FORMAT_B8G8R8A8_SRGB:
312 return SVGA3D_A8R8G8B8;
313 case PIPE_FORMAT_DXT1_SRGB:
314 case PIPE_FORMAT_DXT1_SRGBA:
315 return SVGA3D_DXT1;
316 case PIPE_FORMAT_DXT3_SRGBA:
317 return SVGA3D_DXT3;
318 case PIPE_FORMAT_DXT5_SRGBA:
319 return SVGA3D_DXT5;
320
321 case PIPE_FORMAT_B5G6R5_UNORM:
322 return SVGA3D_R5G6B5;
323 case PIPE_FORMAT_B5G5R5A1_UNORM:
324 return SVGA3D_A1R5G5B5;
325 case PIPE_FORMAT_B4G4R4A4_UNORM:
326 return SVGA3D_A4R4G4B4;
327
328 case PIPE_FORMAT_R16G16B16A16_UNORM:
329 return SVGA3D_A16B16G16R16;
330
331 case PIPE_FORMAT_Z16_UNORM:
332 assert(!ss->sws->have_vgpu10);
333 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
334 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
335 assert(!ss->sws->have_vgpu10);
336 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
337 case PIPE_FORMAT_X8Z24_UNORM:
338 assert(!ss->sws->have_vgpu10);
339 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
340
341 case PIPE_FORMAT_A8_UNORM:
342 return SVGA3D_ALPHA8;
343 case PIPE_FORMAT_L8_UNORM:
344 return SVGA3D_LUMINANCE8;
345
346 case PIPE_FORMAT_DXT1_RGB:
347 case PIPE_FORMAT_DXT1_RGBA:
348 return SVGA3D_DXT1;
349 case PIPE_FORMAT_DXT3_RGBA:
350 return SVGA3D_DXT3;
351 case PIPE_FORMAT_DXT5_RGBA:
352 return SVGA3D_DXT5;
353
354 /* Float formats (only 1, 2 and 4-component formats supported) */
355 case PIPE_FORMAT_R32_FLOAT:
356 return SVGA3D_R_S23E8;
357 case PIPE_FORMAT_R32G32_FLOAT:
358 return SVGA3D_RG_S23E8;
359 case PIPE_FORMAT_R32G32B32A32_FLOAT:
360 return SVGA3D_ARGB_S23E8;
361 case PIPE_FORMAT_R16_FLOAT:
362 return SVGA3D_R_S10E5;
363 case PIPE_FORMAT_R16G16_FLOAT:
364 return SVGA3D_RG_S10E5;
365 case PIPE_FORMAT_R16G16B16A16_FLOAT:
366 return SVGA3D_ARGB_S10E5;
367
368 case PIPE_FORMAT_Z32_UNORM:
369 /* SVGA3D_Z_D32 is not yet unsupported */
370 /* fall-through */
371 default:
372 return SVGA3D_FORMAT_INVALID;
373 }
374 }
375
376
377 /*
378 * Format capability description entry.
379 */
380 struct format_cap {
381 const char *name;
382
383 SVGA3dSurfaceFormat format;
384
385 /*
386 * Capability index corresponding to the format.
387 */
388 SVGA3dDevCapIndex devcap;
389
390 /* size of each pixel/block */
391 unsigned block_width, block_height, block_bytes;
392
393 /*
394 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
395 * capability is not explicitly present.
396 */
397 uint32 defaultOperations;
398 };
399
400
401 /*
402 * Format capability description table.
403 *
404 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
405 */
406 static const struct format_cap format_cap_table[] = {
407 {
408 "SVGA3D_FORMAT_INVALID",
409 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
410 },
411 {
412 "SVGA3D_X8R8G8B8",
413 SVGA3D_X8R8G8B8,
414 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
415 1, 1, 4,
416 SVGA3DFORMAT_OP_TEXTURE |
417 SVGA3DFORMAT_OP_CUBETEXTURE |
418 SVGA3DFORMAT_OP_VOLUMETEXTURE |
419 SVGA3DFORMAT_OP_DISPLAYMODE |
420 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
421 },
422 {
423 "SVGA3D_A8R8G8B8",
424 SVGA3D_A8R8G8B8,
425 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
426 1, 1, 4,
427 SVGA3DFORMAT_OP_TEXTURE |
428 SVGA3DFORMAT_OP_CUBETEXTURE |
429 SVGA3DFORMAT_OP_VOLUMETEXTURE |
430 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
431 },
432 {
433 "SVGA3D_R5G6B5",
434 SVGA3D_R5G6B5,
435 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
436 1, 1, 2,
437 SVGA3DFORMAT_OP_TEXTURE |
438 SVGA3DFORMAT_OP_CUBETEXTURE |
439 SVGA3DFORMAT_OP_VOLUMETEXTURE |
440 SVGA3DFORMAT_OP_DISPLAYMODE |
441 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
442 },
443 {
444 "SVGA3D_X1R5G5B5",
445 SVGA3D_X1R5G5B5,
446 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
447 1, 1, 2,
448 SVGA3DFORMAT_OP_TEXTURE |
449 SVGA3DFORMAT_OP_CUBETEXTURE |
450 SVGA3DFORMAT_OP_VOLUMETEXTURE |
451 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
452 },
453 {
454 "SVGA3D_A1R5G5B5",
455 SVGA3D_A1R5G5B5,
456 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
457 1, 1, 2,
458 SVGA3DFORMAT_OP_TEXTURE |
459 SVGA3DFORMAT_OP_CUBETEXTURE |
460 SVGA3DFORMAT_OP_VOLUMETEXTURE |
461 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
462 },
463 {
464 "SVGA3D_A4R4G4B4",
465 SVGA3D_A4R4G4B4,
466 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
467 1, 1, 2,
468 SVGA3DFORMAT_OP_TEXTURE |
469 SVGA3DFORMAT_OP_CUBETEXTURE |
470 SVGA3DFORMAT_OP_VOLUMETEXTURE |
471 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
472 },
473 {
474 /*
475 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
476 * SVGA3D_DEVCAP_xxx.
477 */
478 "SVGA3D_Z_D32",
479 SVGA3D_Z_D32, 0, 0, 0, 0, 0
480 },
481 {
482 "SVGA3D_Z_D16",
483 SVGA3D_Z_D16,
484 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
485 1, 1, 2,
486 SVGA3DFORMAT_OP_ZSTENCIL
487 },
488 {
489 "SVGA3D_Z_D24S8",
490 SVGA3D_Z_D24S8,
491 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
492 1, 1, 4,
493 SVGA3DFORMAT_OP_ZSTENCIL
494 },
495 {
496 "SVGA3D_Z_D15S1",
497 SVGA3D_Z_D15S1,
498 SVGA3D_DEVCAP_MAX,
499 1, 1, 2,
500 SVGA3DFORMAT_OP_ZSTENCIL
501 },
502 {
503 "SVGA3D_LUMINANCE8",
504 SVGA3D_LUMINANCE8,
505 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
506 1, 1, 1,
507 SVGA3DFORMAT_OP_TEXTURE |
508 SVGA3DFORMAT_OP_CUBETEXTURE |
509 SVGA3DFORMAT_OP_VOLUMETEXTURE
510 },
511 {
512 /*
513 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
514 * SVGA3D_DEVCAP_xxx.
515 */
516 "SVGA3D_LUMINANCE4_ALPHA4",
517 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
518 },
519 {
520 "SVGA3D_LUMINANCE16",
521 SVGA3D_LUMINANCE16,
522 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
523 1, 1, 2,
524 SVGA3DFORMAT_OP_TEXTURE |
525 SVGA3DFORMAT_OP_CUBETEXTURE |
526 SVGA3DFORMAT_OP_VOLUMETEXTURE
527 },
528 {
529 "SVGA3D_LUMINANCE8_ALPHA8",
530 SVGA3D_LUMINANCE8_ALPHA8,
531 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
532 1, 1, 2,
533 SVGA3DFORMAT_OP_TEXTURE |
534 SVGA3DFORMAT_OP_CUBETEXTURE |
535 SVGA3DFORMAT_OP_VOLUMETEXTURE
536 },
537 {
538 "SVGA3D_DXT1",
539 SVGA3D_DXT1,
540 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
541 4, 4, 8,
542 SVGA3DFORMAT_OP_TEXTURE |
543 SVGA3DFORMAT_OP_CUBETEXTURE
544 },
545 {
546 "SVGA3D_DXT2",
547 SVGA3D_DXT2,
548 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
549 4, 4, 8,
550 SVGA3DFORMAT_OP_TEXTURE |
551 SVGA3DFORMAT_OP_CUBETEXTURE
552 },
553 {
554 "SVGA3D_DXT3",
555 SVGA3D_DXT3,
556 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
557 4, 4, 16,
558 SVGA3DFORMAT_OP_TEXTURE |
559 SVGA3DFORMAT_OP_CUBETEXTURE
560 },
561 {
562 "SVGA3D_DXT4",
563 SVGA3D_DXT4,
564 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
565 4, 4, 16,
566 SVGA3DFORMAT_OP_TEXTURE |
567 SVGA3DFORMAT_OP_CUBETEXTURE
568 },
569 {
570 "SVGA3D_DXT5",
571 SVGA3D_DXT5,
572 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
573 4, 4, 8,
574 SVGA3DFORMAT_OP_TEXTURE |
575 SVGA3DFORMAT_OP_CUBETEXTURE
576 },
577 {
578 "SVGA3D_BUMPU8V8",
579 SVGA3D_BUMPU8V8,
580 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
581 1, 1, 2,
582 SVGA3DFORMAT_OP_TEXTURE |
583 SVGA3DFORMAT_OP_CUBETEXTURE |
584 SVGA3DFORMAT_OP_VOLUMETEXTURE
585 },
586 {
587 /*
588 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
589 * SVGA3D_DEVCAP_xxx.
590 */
591 "SVGA3D_BUMPL6V5U5",
592 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
593 },
594 {
595 "SVGA3D_BUMPX8L8V8U8",
596 SVGA3D_BUMPX8L8V8U8,
597 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
598 1, 1, 4,
599 SVGA3DFORMAT_OP_TEXTURE |
600 SVGA3DFORMAT_OP_CUBETEXTURE
601 },
602 {
603 "SVGA3D_FORMAT_DEAD1",
604 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
605 },
606 {
607 "SVGA3D_ARGB_S10E5",
608 SVGA3D_ARGB_S10E5,
609 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
610 1, 1, 2,
611 SVGA3DFORMAT_OP_TEXTURE |
612 SVGA3DFORMAT_OP_CUBETEXTURE |
613 SVGA3DFORMAT_OP_VOLUMETEXTURE |
614 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
615 },
616 {
617 "SVGA3D_ARGB_S23E8",
618 SVGA3D_ARGB_S23E8,
619 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
620 1, 1, 4,
621 SVGA3DFORMAT_OP_TEXTURE |
622 SVGA3DFORMAT_OP_CUBETEXTURE |
623 SVGA3DFORMAT_OP_VOLUMETEXTURE |
624 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
625 },
626 {
627 "SVGA3D_A2R10G10B10",
628 SVGA3D_A2R10G10B10,
629 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
630 1, 1, 4,
631 SVGA3DFORMAT_OP_TEXTURE |
632 SVGA3DFORMAT_OP_CUBETEXTURE |
633 SVGA3DFORMAT_OP_VOLUMETEXTURE |
634 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
635 },
636 {
637 /*
638 * SVGA3D_V8U8 is unsupported; it has no corresponding
639 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
640 */
641 "SVGA3D_V8U8",
642 SVGA3D_V8U8, 0, 0, 0, 0, 0
643 },
644 {
645 "SVGA3D_Q8W8V8U8",
646 SVGA3D_Q8W8V8U8,
647 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
648 1, 1, 4,
649 SVGA3DFORMAT_OP_TEXTURE |
650 SVGA3DFORMAT_OP_CUBETEXTURE
651 },
652 {
653 "SVGA3D_CxV8U8",
654 SVGA3D_CxV8U8,
655 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
656 1, 1, 2,
657 SVGA3DFORMAT_OP_TEXTURE
658 },
659 {
660 /*
661 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
662 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
663 */
664 "SVGA3D_X8L8V8U8",
665 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
666 },
667 {
668 "SVGA3D_A2W10V10U10",
669 SVGA3D_A2W10V10U10,
670 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
671 1, 1, 4,
672 SVGA3DFORMAT_OP_TEXTURE
673 },
674 {
675 "SVGA3D_ALPHA8",
676 SVGA3D_ALPHA8,
677 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
678 1, 1, 1,
679 SVGA3DFORMAT_OP_TEXTURE |
680 SVGA3DFORMAT_OP_CUBETEXTURE |
681 SVGA3DFORMAT_OP_VOLUMETEXTURE
682 },
683 {
684 "SVGA3D_R_S10E5",
685 SVGA3D_R_S10E5,
686 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
687 1, 1, 2,
688 SVGA3DFORMAT_OP_TEXTURE |
689 SVGA3DFORMAT_OP_VOLUMETEXTURE |
690 SVGA3DFORMAT_OP_CUBETEXTURE |
691 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
692 },
693 {
694 "SVGA3D_R_S23E8",
695 SVGA3D_R_S23E8,
696 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
697 1, 1, 4,
698 SVGA3DFORMAT_OP_TEXTURE |
699 SVGA3DFORMAT_OP_VOLUMETEXTURE |
700 SVGA3DFORMAT_OP_CUBETEXTURE |
701 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
702 },
703 {
704 "SVGA3D_RG_S10E5",
705 SVGA3D_RG_S10E5,
706 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
707 1, 1, 2,
708 SVGA3DFORMAT_OP_TEXTURE |
709 SVGA3DFORMAT_OP_VOLUMETEXTURE |
710 SVGA3DFORMAT_OP_CUBETEXTURE |
711 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
712 },
713 {
714 "SVGA3D_RG_S23E8",
715 SVGA3D_RG_S23E8,
716 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
717 1, 1, 4,
718 SVGA3DFORMAT_OP_TEXTURE |
719 SVGA3DFORMAT_OP_VOLUMETEXTURE |
720 SVGA3DFORMAT_OP_CUBETEXTURE |
721 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
722 },
723 {
724 /*
725 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
726 */
727 "SVGA3D_BUFFER",
728 SVGA3D_BUFFER, 0, 1, 1, 1, 0
729 },
730 {
731 "SVGA3D_Z_D24X8",
732 SVGA3D_Z_D24X8,
733 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
734 1, 1, 4,
735 SVGA3DFORMAT_OP_ZSTENCIL
736 },
737 {
738 "SVGA3D_V16U16",
739 SVGA3D_V16U16,
740 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
741 1, 1, 4,
742 SVGA3DFORMAT_OP_TEXTURE |
743 SVGA3DFORMAT_OP_CUBETEXTURE |
744 SVGA3DFORMAT_OP_VOLUMETEXTURE
745 },
746 {
747 "SVGA3D_G16R16",
748 SVGA3D_G16R16,
749 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
750 1, 1, 4,
751 SVGA3DFORMAT_OP_TEXTURE |
752 SVGA3DFORMAT_OP_CUBETEXTURE |
753 SVGA3DFORMAT_OP_VOLUMETEXTURE |
754 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
755 },
756 {
757 "SVGA3D_A16B16G16R16",
758 SVGA3D_A16B16G16R16,
759 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
760 1, 1, 8,
761 SVGA3DFORMAT_OP_TEXTURE |
762 SVGA3DFORMAT_OP_CUBETEXTURE |
763 SVGA3DFORMAT_OP_VOLUMETEXTURE |
764 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
765 },
766 {
767 "SVGA3D_UYVY",
768 SVGA3D_UYVY,
769 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
770 0, 0, 0, 0
771 },
772 {
773 "SVGA3D_YUY2",
774 SVGA3D_YUY2,
775 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
776 0, 0, 0, 0
777 },
778 {
779 "SVGA3D_NV12",
780 SVGA3D_NV12,
781 SVGA3D_DEVCAP_SURFACEFMT_NV12,
782 0, 0, 0, 0
783 },
784 {
785 "SVGA3D_AYUV",
786 SVGA3D_AYUV,
787 SVGA3D_DEVCAP_SURFACEFMT_AYUV,
788 0, 0, 0, 0
789 },
790 {
791 "SVGA3D_R32G32B32A32_TYPELESS",
792 SVGA3D_R32G32B32A32_TYPELESS,
793 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
794 1, 1, 16, 0
795 },
796 {
797 "SVGA3D_R32G32B32A32_UINT",
798 SVGA3D_R32G32B32A32_UINT,
799 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
800 1, 1, 16, 0
801 },
802 {
803 "SVGA3D_R32G32B32A32_SINT",
804 SVGA3D_R32G32B32A32_SINT,
805 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
806 1, 1, 16, 0
807 },
808 {
809 "SVGA3D_R32G32B32_TYPELESS",
810 SVGA3D_R32G32B32_TYPELESS,
811 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
812 1, 1, 12, 0
813 },
814 {
815 "SVGA3D_R32G32B32_FLOAT",
816 SVGA3D_R32G32B32_FLOAT,
817 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
818 1, 1, 12, 0
819 },
820 {
821 "SVGA3D_R32G32B32_UINT",
822 SVGA3D_R32G32B32_UINT,
823 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
824 1, 1, 12, 0
825 },
826 {
827 "SVGA3D_R32G32B32_SINT",
828 SVGA3D_R32G32B32_SINT,
829 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
830 1, 1, 12, 0
831 },
832 {
833 "SVGA3D_R16G16B16A16_TYPELESS",
834 SVGA3D_R16G16B16A16_TYPELESS,
835 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
836 1, 1, 8, 0
837 },
838 {
839 "SVGA3D_R16G16B16A16_UINT",
840 SVGA3D_R16G16B16A16_UINT,
841 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
842 1, 1, 8, 0
843 },
844 {
845 "SVGA3D_R16G16B16A16_SNORM",
846 SVGA3D_R16G16B16A16_SNORM,
847 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
848 1, 1, 8, 0
849 },
850 {
851 "SVGA3D_R16G16B16A16_SINT",
852 SVGA3D_R16G16B16A16_SINT,
853 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
854 1, 1, 8, 0
855 },
856 {
857 "SVGA3D_R32G32_TYPELESS",
858 SVGA3D_R32G32_TYPELESS,
859 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
860 1, 1, 8, 0
861 },
862 {
863 "SVGA3D_R32G32_UINT",
864 SVGA3D_R32G32_UINT,
865 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
866 1, 1, 8, 0
867 },
868 {
869 "SVGA3D_R32G32_SINT",
870 SVGA3D_R32G32_SINT,
871 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
872 1, 1, 8,
873 0
874 },
875 {
876 "SVGA3D_R32G8X24_TYPELESS",
877 SVGA3D_R32G8X24_TYPELESS,
878 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
879 1, 1, 8, 0
880 },
881 {
882 "SVGA3D_D32_FLOAT_S8X24_UINT",
883 SVGA3D_D32_FLOAT_S8X24_UINT,
884 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT,
885 1, 1, 8, 0
886 },
887 {
888 "SVGA3D_R32_FLOAT_X8X24",
889 SVGA3D_R32_FLOAT_X8X24,
890 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24,
891 1, 1, 8, 0
892 },
893 {
894 "SVGA3D_X32_G8X24_UINT",
895 SVGA3D_X32_G8X24_UINT,
896 SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT,
897 1, 1, 4, 0
898 },
899 {
900 "SVGA3D_R10G10B10A2_TYPELESS",
901 SVGA3D_R10G10B10A2_TYPELESS,
902 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
903 1, 1, 4, 0
904 },
905 {
906 "SVGA3D_R10G10B10A2_UINT",
907 SVGA3D_R10G10B10A2_UINT,
908 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
909 1, 1, 4, 0
910 },
911 {
912 "SVGA3D_R11G11B10_FLOAT",
913 SVGA3D_R11G11B10_FLOAT,
914 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
915 1, 1, 4, 0
916 },
917 {
918 "SVGA3D_R8G8B8A8_TYPELESS",
919 SVGA3D_R8G8B8A8_TYPELESS,
920 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
921 1, 1, 4, 0
922 },
923 {
924 "SVGA3D_R8G8B8A8_UNORM",
925 SVGA3D_R8G8B8A8_UNORM,
926 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
927 1, 1, 4, 0
928 },
929 {
930 "SVGA3D_R8G8B8A8_UNORM_SRGB",
931 SVGA3D_R8G8B8A8_UNORM_SRGB,
932 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
933 1, 1, 4, 0
934 },
935 {
936 "SVGA3D_R8G8B8A8_UINT",
937 SVGA3D_R8G8B8A8_UINT,
938 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
939 1, 1, 4, 0
940 },
941 {
942 "SVGA3D_R8G8B8A8_SINT",
943 SVGA3D_R8G8B8A8_SINT,
944 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
945 1, 1, 4, 0
946 },
947 {
948 "SVGA3D_R16G16_TYPELESS",
949 SVGA3D_R16G16_TYPELESS,
950 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
951 1, 1, 4, 0
952 },
953 {
954 "SVGA3D_R16G16_UINT",
955 SVGA3D_R16G16_UINT,
956 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
957 1, 1, 4, 0
958 },
959 {
960 "SVGA3D_R16G16_SINT",
961 SVGA3D_R16G16_SINT,
962 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
963 1, 1, 4, 0
964 },
965 {
966 "SVGA3D_R32_TYPELESS",
967 SVGA3D_R32_TYPELESS,
968 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
969 1, 1, 4, 0
970 },
971 {
972 "SVGA3D_D32_FLOAT",
973 SVGA3D_D32_FLOAT,
974 SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
975 1, 1, 4, 0
976 },
977 {
978 "SVGA3D_R32_UINT",
979 SVGA3D_R32_UINT,
980 SVGA3D_DEVCAP_DXFMT_R32_UINT,
981 1, 1, 4, 0
982 },
983 {
984 "SVGA3D_R32_SINT",
985 SVGA3D_R32_SINT,
986 SVGA3D_DEVCAP_DXFMT_R32_SINT,
987 1, 1, 4, 0
988 },
989 {
990 "SVGA3D_R24G8_TYPELESS",
991 SVGA3D_R24G8_TYPELESS,
992 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
993 1, 1, 4, 0
994 },
995 {
996 "SVGA3D_D24_UNORM_S8_UINT",
997 SVGA3D_D24_UNORM_S8_UINT,
998 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT,
999 1, 1, 4, 0
1000 },
1001 {
1002 "SVGA3D_R24_UNORM_X8",
1003 SVGA3D_R24_UNORM_X8,
1004 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8,
1005 1, 1, 4, 0
1006 },
1007 {
1008 "SVGA3D_X24_G8_UINT",
1009 SVGA3D_X24_G8_UINT,
1010 SVGA3D_DEVCAP_DXFMT_X24_G8_UINT,
1011 1, 1, 4, 0
1012 },
1013 {
1014 "SVGA3D_R8G8_TYPELESS",
1015 SVGA3D_R8G8_TYPELESS,
1016 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
1017 1, 1, 2, 0
1018 },
1019 {
1020 "SVGA3D_R8G8_UNORM",
1021 SVGA3D_R8G8_UNORM,
1022 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
1023 1, 1, 2, 0
1024 },
1025 {
1026 "SVGA3D_R8G8_UINT",
1027 SVGA3D_R8G8_UINT,
1028 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
1029 1, 1, 2, 0
1030 },
1031 {
1032 "SVGA3D_R8G8_SINT",
1033 SVGA3D_R8G8_SINT,
1034 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
1035 1, 1, 2, 0
1036 },
1037 {
1038 "SVGA3D_R16_TYPELESS",
1039 SVGA3D_R16_TYPELESS,
1040 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
1041 1, 1, 2, 0
1042 },
1043 {
1044 "SVGA3D_R16_UNORM",
1045 SVGA3D_R16_UNORM,
1046 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
1047 1, 1, 2, 0
1048 },
1049 {
1050 "SVGA3D_R16_UINT",
1051 SVGA3D_R16_UINT,
1052 SVGA3D_DEVCAP_DXFMT_R16_UINT,
1053 1, 1, 2, 0
1054 },
1055 {
1056 "SVGA3D_R16_SNORM",
1057 SVGA3D_R16_SNORM,
1058 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
1059 1, 1, 2, 0
1060 },
1061 {
1062 "SVGA3D_R16_SINT",
1063 SVGA3D_R16_SINT,
1064 SVGA3D_DEVCAP_DXFMT_R16_SINT,
1065 1, 1, 2, 0
1066 },
1067 {
1068 "SVGA3D_R8_TYPELESS",
1069 SVGA3D_R8_TYPELESS,
1070 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
1071 1, 1, 1, 0
1072 },
1073 {
1074 "SVGA3D_R8_UNORM",
1075 SVGA3D_R8_UNORM,
1076 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
1077 1, 1, 1, 0
1078 },
1079 {
1080 "SVGA3D_R8_UINT",
1081 SVGA3D_R8_UINT,
1082 SVGA3D_DEVCAP_DXFMT_R8_UINT,
1083 1, 1, 1, 0
1084 },
1085 {
1086 "SVGA3D_R8_SNORM",
1087 SVGA3D_R8_SNORM,
1088 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
1089 1, 1, 1, 0
1090 },
1091 {
1092 "SVGA3D_R8_SINT",
1093 SVGA3D_R8_SINT,
1094 SVGA3D_DEVCAP_DXFMT_R8_SINT,
1095 1, 1, 1, 0
1096 },
1097 {
1098 "SVGA3D_P8",
1099 SVGA3D_P8, 0, 0, 0, 0, 0
1100 },
1101 {
1102 "SVGA3D_R9G9B9E5_SHAREDEXP",
1103 SVGA3D_R9G9B9E5_SHAREDEXP,
1104 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
1105 1, 1, 4, 0
1106 },
1107 {
1108 "SVGA3D_R8G8_B8G8_UNORM",
1109 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1110 },
1111 {
1112 "SVGA3D_G8R8_G8B8_UNORM",
1113 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1114 },
1115 {
1116 "SVGA3D_BC1_TYPELESS",
1117 SVGA3D_BC1_TYPELESS,
1118 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
1119 4, 4, 8, 0
1120 },
1121 {
1122 "SVGA3D_BC1_UNORM_SRGB",
1123 SVGA3D_BC1_UNORM_SRGB,
1124 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
1125 4, 4, 8, 0
1126 },
1127 {
1128 "SVGA3D_BC2_TYPELESS",
1129 SVGA3D_BC2_TYPELESS,
1130 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
1131 4, 4, 16, 0
1132 },
1133 {
1134 "SVGA3D_BC2_UNORM_SRGB",
1135 SVGA3D_BC2_UNORM_SRGB,
1136 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
1137 4, 4, 16, 0
1138 },
1139 {
1140 "SVGA3D_BC3_TYPELESS",
1141 SVGA3D_BC3_TYPELESS,
1142 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
1143 4, 4, 16, 0
1144 },
1145 {
1146 "SVGA3D_BC3_UNORM_SRGB",
1147 SVGA3D_BC3_UNORM_SRGB,
1148 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB,
1149 4, 4, 16, 0
1150 },
1151 {
1152 "SVGA3D_BC4_TYPELESS",
1153 SVGA3D_BC4_TYPELESS,
1154 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
1155 4, 4, 8, 0
1156 },
1157 {
1158 "SVGA3D_ATI1",
1159 SVGA3D_ATI1, 0, 0, 0, 0, 0
1160 },
1161 {
1162 "SVGA3D_BC4_SNORM",
1163 SVGA3D_BC4_SNORM,
1164 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
1165 4, 4, 8, 0
1166 },
1167 {
1168 "SVGA3D_BC5_TYPELESS",
1169 SVGA3D_BC5_TYPELESS,
1170 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
1171 4, 4, 16, 0
1172 },
1173 {
1174 "SVGA3D_ATI2",
1175 SVGA3D_ATI2, 0, 0, 0, 0, 0
1176 },
1177 {
1178 "SVGA3D_BC5_SNORM",
1179 SVGA3D_BC5_SNORM,
1180 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
1181 4, 4, 16, 0
1182 },
1183 {
1184 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1185 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1186 },
1187 {
1188 "SVGA3D_B8G8R8A8_TYPELESS",
1189 SVGA3D_B8G8R8A8_TYPELESS,
1190 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
1191 1, 1, 4, 0
1192 },
1193 {
1194 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1195 SVGA3D_B8G8R8A8_UNORM_SRGB,
1196 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
1197 1, 1, 4, 0
1198 },
1199 {
1200 "SVGA3D_B8G8R8X8_TYPELESS",
1201 SVGA3D_B8G8R8X8_TYPELESS,
1202 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
1203 1, 1, 4, 0
1204 },
1205 {
1206 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1207 SVGA3D_B8G8R8X8_UNORM_SRGB,
1208 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
1209 1, 1, 4, 0
1210 },
1211 {
1212 "SVGA3D_Z_DF16",
1213 SVGA3D_Z_DF16,
1214 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
1215 1, 1, 2, 0
1216 },
1217 {
1218 "SVGA3D_Z_DF24",
1219 SVGA3D_Z_DF24,
1220 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
1221 1, 1, 4, 0
1222 },
1223 {
1224 "SVGA3D_Z_D24S8_INT",
1225 SVGA3D_Z_D24S8_INT,
1226 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
1227 1, 1, 4, 0
1228 },
1229 {
1230 "SVGA3D_YV12",
1231 SVGA3D_YV12, 0, 0, 0, 0, 0
1232 },
1233 {
1234 "SVGA3D_R32G32B32A32_FLOAT",
1235 SVGA3D_R32G32B32A32_FLOAT,
1236 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
1237 1, 1, 16, 0
1238 },
1239 {
1240 "SVGA3D_R16G16B16A16_FLOAT",
1241 SVGA3D_R16G16B16A16_FLOAT,
1242 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
1243 1, 1, 8, 0
1244 },
1245 {
1246 "SVGA3D_R16G16B16A16_UNORM",
1247 SVGA3D_R16G16B16A16_UNORM,
1248 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
1249 1, 1, 8, 0
1250 },
1251 {
1252 "SVGA3D_R32G32_FLOAT",
1253 SVGA3D_R32G32_FLOAT,
1254 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
1255 1, 1, 8, 0
1256 },
1257 {
1258 "SVGA3D_R10G10B10A2_UNORM",
1259 SVGA3D_R10G10B10A2_UNORM,
1260 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
1261 1, 1, 4, 0
1262 },
1263 {
1264 "SVGA3D_R8G8B8A8_SNORM",
1265 SVGA3D_R8G8B8A8_SNORM,
1266 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
1267 1, 1, 4, 0
1268 },
1269 {
1270 "SVGA3D_R16G16_FLOAT",
1271 SVGA3D_R16G16_FLOAT,
1272 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
1273 1, 1, 4, 0
1274 },
1275 {
1276 "SVGA3D_R16G16_UNORM",
1277 SVGA3D_R16G16_UNORM,
1278 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
1279 1, 1, 4, 0
1280 },
1281 {
1282 "SVGA3D_R16G16_SNORM",
1283 SVGA3D_R16G16_SNORM,
1284 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
1285 1, 1, 4, 0
1286 },
1287 {
1288 "SVGA3D_R32_FLOAT",
1289 SVGA3D_R32_FLOAT,
1290 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
1291 1, 1, 4, 0
1292 },
1293 {
1294 "SVGA3D_R8G8_SNORM",
1295 SVGA3D_R8G8_SNORM,
1296 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
1297 1, 1, 2, 0
1298 },
1299 {
1300 "SVGA3D_R16_FLOAT",
1301 SVGA3D_R16_FLOAT,
1302 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
1303 1, 1, 2, 0
1304 },
1305 {
1306 "SVGA3D_D16_UNORM",
1307 SVGA3D_D16_UNORM,
1308 SVGA3D_DEVCAP_DXFMT_D16_UNORM,
1309 1, 1, 2, 0
1310 },
1311 {
1312 "SVGA3D_A8_UNORM",
1313 SVGA3D_A8_UNORM,
1314 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
1315 1, 1, 1, 0
1316 },
1317 {
1318 "SVGA3D_BC1_UNORM",
1319 SVGA3D_BC1_UNORM,
1320 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
1321 4, 4, 8, 0
1322 },
1323 {
1324 "SVGA3D_BC2_UNORM",
1325 SVGA3D_BC2_UNORM,
1326 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
1327 4, 4, 16, 0
1328 },
1329 {
1330 "SVGA3D_BC3_UNORM",
1331 SVGA3D_BC3_UNORM,
1332 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
1333 4, 4, 16, 0
1334 },
1335 {
1336 "SVGA3D_B5G6R5_UNORM",
1337 SVGA3D_B5G6R5_UNORM,
1338 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
1339 1, 1, 2, 0
1340 },
1341 {
1342 "SVGA3D_B5G5R5A1_UNORM",
1343 SVGA3D_B5G5R5A1_UNORM,
1344 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
1345 1, 1, 2, 0
1346 },
1347 {
1348 "SVGA3D_B8G8R8A8_UNORM",
1349 SVGA3D_B8G8R8A8_UNORM,
1350 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
1351 1, 1, 4, 0
1352 },
1353 {
1354 "SVGA3D_B8G8R8X8_UNORM",
1355 SVGA3D_B8G8R8X8_UNORM,
1356 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
1357 1, 1, 4, 0
1358 },
1359 {
1360 "SVGA3D_BC4_UNORM",
1361 SVGA3D_BC4_UNORM,
1362 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
1363 4, 4, 8, 0
1364 },
1365 {
1366 "SVGA3D_BC5_UNORM",
1367 SVGA3D_BC5_UNORM,
1368 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
1369 4, 4, 16, 0
1370 }
1371 };
1372
1373 static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1374 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1375 SVGA3D_B8G8R8A8_UNORM, 0
1376 };
1377 static const SVGA3dSurfaceFormat compat_r8[] = {
1378 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1379 };
1380 static const SVGA3dSurfaceFormat compat_g8r8[] = {
1381 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1382 };
1383 static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1384 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1385 };
1386
1387 static const struct format_compat_entry format_compats[] = {
1388 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1389 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1390 {PIPE_FORMAT_R8_UNORM, compat_r8},
1391 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1392 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
1393 };
1394
1395 /**
1396 * Debug only:
1397 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1398 * 2. check that format_conversion_table[i].pformat == i.
1399 */
1400 static void
1401 check_format_tables(void)
1402 {
1403 static boolean first_call = TRUE;
1404
1405 if (first_call) {
1406 unsigned i;
1407
1408 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1409 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
1410 assert(format_cap_table[i].format == i);
1411 }
1412
1413 first_call = FALSE;
1414 }
1415 }
1416
1417
1418 /**
1419 * Return string name of an SVGA3dDevCapIndex value.
1420 * For debugging.
1421 */
1422 static const char *
1423 svga_devcap_name(SVGA3dDevCapIndex cap)
1424 {
1425 static const struct debug_named_value devcap_names[] = {
1426 /* Note, we only list the DXFMT devcaps so far */
1427 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8R8G8B8),
1428 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8R8G8B8),
1429 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R5G6B5),
1430 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X1R5G5B5),
1431 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A1R5G5B5),
1432 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A4R4G4B4),
1433 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D32),
1434 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D16),
1435 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8),
1436 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D15S1),
1437 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8),
1438 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4),
1439 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE16),
1440 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8),
1441 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT1),
1442 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT2),
1443 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT3),
1444 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT4),
1445 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT5),
1446 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPU8V8),
1447 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5),
1448 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8),
1449 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1),
1450 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5),
1451 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8),
1452 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2R10G10B10),
1453 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V8U8),
1454 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8),
1455 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_CxV8U8),
1456 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8L8V8U8),
1457 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2W10V10U10),
1458 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ALPHA8),
1459 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S10E5),
1460 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S23E8),
1461 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S10E5),
1462 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S23E8),
1463 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUFFER),
1464 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24X8),
1465 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V16U16),
1466 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G16R16),
1467 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A16B16G16R16),
1468 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
1469 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
1470 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
1471 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_AYUV),
1472 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
1473 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
1474 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
1475 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS),
1476 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT),
1477 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT),
1478 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT),
1479 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS),
1480 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT),
1481 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM),
1482 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT),
1483 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS),
1484 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_UINT),
1485 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_SINT),
1486 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS),
1487 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT),
1488 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24),
1489 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT),
1490 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS),
1491 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT),
1492 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT),
1493 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS),
1494 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM),
1495 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB),
1496 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT),
1497 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT),
1498 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS),
1499 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UINT),
1500 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SINT),
1501 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS),
1502 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT),
1503 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_UINT),
1504 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_SINT),
1505 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS),
1506 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT),
1507 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8),
1508 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT),
1509 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS),
1510 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM),
1511 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UINT),
1512 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SINT),
1513 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS),
1514 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UNORM),
1515 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UINT),
1516 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SNORM),
1517 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SINT),
1518 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS),
1519 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UNORM),
1520 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UINT),
1521 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SNORM),
1522 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SINT),
1523 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_P8),
1524 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP),
1525 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM),
1526 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM),
1527 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS),
1528 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB),
1529 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS),
1530 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB),
1531 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS),
1532 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB),
1533 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS),
1534 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI1),
1535 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_SNORM),
1536 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS),
1537 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI2),
1538 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_SNORM),
1539 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM),
1540 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS),
1541 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB),
1542 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS),
1543 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB),
1544 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF16),
1545 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF24),
1546 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT),
1547 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YV12),
1548 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT),
1549 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT),
1550 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM),
1551 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT),
1552 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM),
1553 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM),
1554 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT),
1555 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM),
1556 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM),
1557 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT),
1558 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM),
1559 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_FLOAT),
1560 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D16_UNORM),
1561 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8_UNORM),
1562 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM),
1563 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM),
1564 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM),
1565 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM),
1566 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM),
1567 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM),
1568 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM),
1569 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_UNORM),
1570 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_UNORM),
1571 DEBUG_NAMED_VALUE_END,
1572 };
1573 return debug_dump_enum(devcap_names, cap);
1574 }
1575
1576
1577 /**
1578 * Return string for a bitmask of name of SVGA3D_DXFMT_x flags.
1579 * For debugging.
1580 */
1581 static const char *
1582 svga_devcap_format_flags(unsigned flags)
1583 {
1584 static const struct debug_named_value devcap_flags[] = {
1585 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SUPPORTED),
1586 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SHADER_SAMPLE),
1587 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_COLOR_RENDERTARGET),
1588 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DEPTH_RENDERTARGET),
1589 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_BLENDABLE),
1590 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MIPS),
1591 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_ARRAY),
1592 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_VOLUME),
1593 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DX_VERTEX_BUFFER),
1594 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MULTISAMPLE),
1595 DEBUG_NAMED_VALUE_END
1596 };
1597
1598 return debug_dump_flags(devcap_flags, flags);
1599 }
1600
1601
1602 /*
1603 * Get format capabilities from the host. It takes in consideration
1604 * deprecated/unsupported formats, and formats which are implicitely assumed to
1605 * be supported when the host does not provide an explicit capability entry.
1606 */
1607 void
1608 svga_get_format_cap(struct svga_screen *ss,
1609 SVGA3dSurfaceFormat format,
1610 SVGA3dSurfaceFormatCaps *caps)
1611 {
1612 struct svga_winsys_screen *sws = ss->sws;
1613 SVGA3dDevCapResult result;
1614 const struct format_cap *entry;
1615
1616 #ifdef DEBUG
1617 check_format_tables();
1618 #else
1619 (void) check_format_tables;
1620 #endif
1621
1622 assert(format < ARRAY_SIZE(format_cap_table));
1623 entry = &format_cap_table[format];
1624 assert(entry->format == format);
1625
1626 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
1627 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1628 caps->value = result.u;
1629 } else {
1630 /* Implicitly advertised format -- use default caps */
1631 caps->value = entry->defaultOperations;
1632 }
1633 }
1634
1635
1636 /*
1637 * Get DX format capabilities from VGPU10 device.
1638 */
1639 static void
1640 svga_get_dx_format_cap(struct svga_screen *ss,
1641 SVGA3dSurfaceFormat format,
1642 SVGA3dDevCapResult *caps)
1643 {
1644 struct svga_winsys_screen *sws = ss->sws;
1645 const struct format_cap *entry;
1646
1647 #ifdef DEBUG
1648 check_format_tables();
1649 #else
1650 (void) check_format_tables;
1651 #endif
1652
1653 assert(sws->have_vgpu10);
1654 assert(format < ARRAY_SIZE(format_cap_table));
1655 entry = &format_cap_table[format];
1656 assert(entry->format == format);
1657 assert(entry->devcap > SVGA3D_DEVCAP_DXCONTEXT);
1658
1659 caps->u = 0;
1660 if (entry->devcap) {
1661 sws->get_cap(sws, entry->devcap, caps);
1662
1663 /* pre-SM41 capabable svga device supports SHADER_SAMPLE capability for
1664 * these formats but does not advertise the devcap.
1665 * So enable this bit here.
1666 */
1667 if (!sws->have_sm4_1 &&
1668 (format == SVGA3D_R32_FLOAT_X8X24 ||
1669 format == SVGA3D_R24_UNORM_X8)) {
1670 caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
1671 }
1672 }
1673
1674 if (0) {
1675 debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
1676 svga_format_name(format),
1677 svga_devcap_name(entry->devcap),
1678 caps->u,
1679 svga_devcap_format_flags(caps->u));
1680 }
1681 }
1682
1683
1684 void
1685 svga_format_size(SVGA3dSurfaceFormat format,
1686 unsigned *block_width,
1687 unsigned *block_height,
1688 unsigned *bytes_per_block)
1689 {
1690 assert(format < ARRAY_SIZE(format_cap_table));
1691 *block_width = format_cap_table[format].block_width;
1692 *block_height = format_cap_table[format].block_height;
1693 *bytes_per_block = format_cap_table[format].block_bytes;
1694 /* Make sure the table entry was valid */
1695 if (*block_width == 0)
1696 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1697 assert(*block_width);
1698 assert(*block_height);
1699 assert(*bytes_per_block);
1700 }
1701
1702
1703 const char *
1704 svga_format_name(SVGA3dSurfaceFormat format)
1705 {
1706 assert(format < ARRAY_SIZE(format_cap_table));
1707 return format_cap_table[format].name;
1708 }
1709
1710
1711 /**
1712 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1713 */
1714 boolean
1715 svga_format_is_integer(SVGA3dSurfaceFormat format)
1716 {
1717 switch (format) {
1718 case SVGA3D_R32G32B32A32_SINT:
1719 case SVGA3D_R32G32B32_SINT:
1720 case SVGA3D_R32G32_SINT:
1721 case SVGA3D_R32_SINT:
1722 case SVGA3D_R16G16B16A16_SINT:
1723 case SVGA3D_R16G16_SINT:
1724 case SVGA3D_R16_SINT:
1725 case SVGA3D_R8G8B8A8_SINT:
1726 case SVGA3D_R8G8_SINT:
1727 case SVGA3D_R8_SINT:
1728 case SVGA3D_R32G32B32A32_UINT:
1729 case SVGA3D_R32G32B32_UINT:
1730 case SVGA3D_R32G32_UINT:
1731 case SVGA3D_R32_UINT:
1732 case SVGA3D_R16G16B16A16_UINT:
1733 case SVGA3D_R16G16_UINT:
1734 case SVGA3D_R16_UINT:
1735 case SVGA3D_R8G8B8A8_UINT:
1736 case SVGA3D_R8G8_UINT:
1737 case SVGA3D_R8_UINT:
1738 case SVGA3D_R10G10B10A2_UINT:
1739 return TRUE;
1740 default:
1741 return FALSE;
1742 }
1743 }
1744
1745 boolean
1746 svga_format_support_gen_mips(enum pipe_format format)
1747 {
1748 const struct vgpu10_format_entry *entry = svga_format_entry(format);
1749
1750 return (entry->flags & TF_GEN_MIPS) > 0;
1751 }
1752
1753
1754 /**
1755 * Given a texture format, return the expected data type returned from
1756 * the texture sampler. For example, UNORM8 formats return floating point
1757 * values while SINT formats returned signed integer values.
1758 * Note: this function could be moved into the gallum u_format.[ch] code
1759 * if it's useful to anyone else.
1760 */
1761 enum tgsi_return_type
1762 svga_get_texture_datatype(enum pipe_format format)
1763 {
1764 const struct util_format_description *desc = util_format_description(format);
1765 enum tgsi_return_type t;
1766
1767 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1768 if (util_format_is_depth_or_stencil(format)) {
1769 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1770 }
1771 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1772 t = TGSI_RETURN_TYPE_FLOAT;
1773 }
1774 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1775 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1776 }
1777 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1778 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1779 }
1780 else {
1781 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1782 t = TGSI_RETURN_TYPE_FLOAT;
1783 }
1784 }
1785 else {
1786 /* compressed format, shared exponent format, etc. */
1787 switch (format) {
1788 case PIPE_FORMAT_DXT1_RGB:
1789 case PIPE_FORMAT_DXT1_RGBA:
1790 case PIPE_FORMAT_DXT3_RGBA:
1791 case PIPE_FORMAT_DXT5_RGBA:
1792 case PIPE_FORMAT_DXT1_SRGB:
1793 case PIPE_FORMAT_DXT1_SRGBA:
1794 case PIPE_FORMAT_DXT3_SRGBA:
1795 case PIPE_FORMAT_DXT5_SRGBA:
1796 case PIPE_FORMAT_RGTC1_UNORM:
1797 case PIPE_FORMAT_RGTC2_UNORM:
1798 case PIPE_FORMAT_LATC1_UNORM:
1799 case PIPE_FORMAT_LATC2_UNORM:
1800 case PIPE_FORMAT_ETC1_RGB8:
1801 t = TGSI_RETURN_TYPE_UNORM;
1802 break;
1803 case PIPE_FORMAT_RGTC1_SNORM:
1804 case PIPE_FORMAT_RGTC2_SNORM:
1805 case PIPE_FORMAT_LATC1_SNORM:
1806 case PIPE_FORMAT_LATC2_SNORM:
1807 case PIPE_FORMAT_R10G10B10X2_SNORM:
1808 t = TGSI_RETURN_TYPE_SNORM;
1809 break;
1810 case PIPE_FORMAT_R11G11B10_FLOAT:
1811 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1812 t = TGSI_RETURN_TYPE_FLOAT;
1813 break;
1814 default:
1815 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1816 t = TGSI_RETURN_TYPE_FLOAT;
1817 }
1818 }
1819
1820 return t;
1821 }
1822
1823
1824 /**
1825 * Given an svga context, return true iff there are currently any integer color
1826 * buffers attached to the framebuffer.
1827 */
1828 boolean
1829 svga_has_any_integer_cbufs(const struct svga_context *svga)
1830 {
1831 unsigned i;
1832 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
1833 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
1834
1835 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
1836 return TRUE;
1837 }
1838 }
1839 return FALSE;
1840 }
1841
1842
1843 /**
1844 * Given an SVGA format, return the corresponding typeless format.
1845 * If there is no typeless format, return the format unchanged.
1846 */
1847 SVGA3dSurfaceFormat
1848 svga_typeless_format(SVGA3dSurfaceFormat format)
1849 {
1850 switch (format) {
1851 case SVGA3D_R32G32B32A32_UINT:
1852 case SVGA3D_R32G32B32A32_SINT:
1853 case SVGA3D_R32G32B32A32_FLOAT:
1854 return SVGA3D_R32G32B32A32_TYPELESS;
1855 case SVGA3D_R32G32B32_FLOAT:
1856 case SVGA3D_R32G32B32_UINT:
1857 case SVGA3D_R32G32B32_SINT:
1858 return SVGA3D_R32G32B32_TYPELESS;
1859 case SVGA3D_R16G16B16A16_UINT:
1860 case SVGA3D_R16G16B16A16_UNORM:
1861 case SVGA3D_R16G16B16A16_SNORM:
1862 case SVGA3D_R16G16B16A16_SINT:
1863 case SVGA3D_R16G16B16A16_FLOAT:
1864 return SVGA3D_R16G16B16A16_TYPELESS;
1865 case SVGA3D_R32G32_UINT:
1866 case SVGA3D_R32G32_SINT:
1867 case SVGA3D_R32G32_FLOAT:
1868 return SVGA3D_R32G32_TYPELESS;
1869 case SVGA3D_D32_FLOAT_S8X24_UINT:
1870 case SVGA3D_X32_G8X24_UINT:
1871 case SVGA3D_R32G8X24_TYPELESS:
1872 return SVGA3D_R32G8X24_TYPELESS;
1873 case SVGA3D_R10G10B10A2_UINT:
1874 case SVGA3D_R10G10B10A2_UNORM:
1875 return SVGA3D_R10G10B10A2_TYPELESS;
1876 case SVGA3D_R8G8B8A8_UNORM:
1877 case SVGA3D_R8G8B8A8_SNORM:
1878 case SVGA3D_R8G8B8A8_UNORM_SRGB:
1879 case SVGA3D_R8G8B8A8_UINT:
1880 case SVGA3D_R8G8B8A8_SINT:
1881 case SVGA3D_R8G8B8A8_TYPELESS:
1882 return SVGA3D_R8G8B8A8_TYPELESS;
1883 case SVGA3D_R16G16_UINT:
1884 case SVGA3D_R16G16_SINT:
1885 case SVGA3D_R16G16_UNORM:
1886 case SVGA3D_R16G16_SNORM:
1887 case SVGA3D_R16G16_FLOAT:
1888 return SVGA3D_R16G16_TYPELESS;
1889 case SVGA3D_D32_FLOAT:
1890 case SVGA3D_R32_FLOAT:
1891 case SVGA3D_R32_UINT:
1892 case SVGA3D_R32_SINT:
1893 case SVGA3D_R32_TYPELESS:
1894 return SVGA3D_R32_TYPELESS;
1895 case SVGA3D_D24_UNORM_S8_UINT:
1896 case SVGA3D_R24G8_TYPELESS:
1897 return SVGA3D_R24G8_TYPELESS;
1898 case SVGA3D_X24_G8_UINT:
1899 return SVGA3D_R24_UNORM_X8;
1900 case SVGA3D_R8G8_UNORM:
1901 case SVGA3D_R8G8_SNORM:
1902 case SVGA3D_R8G8_UINT:
1903 case SVGA3D_R8G8_SINT:
1904 return SVGA3D_R8G8_TYPELESS;
1905 case SVGA3D_D16_UNORM:
1906 case SVGA3D_R16_UNORM:
1907 case SVGA3D_R16_UINT:
1908 case SVGA3D_R16_SNORM:
1909 case SVGA3D_R16_SINT:
1910 case SVGA3D_R16_FLOAT:
1911 case SVGA3D_R16_TYPELESS:
1912 return SVGA3D_R16_TYPELESS;
1913 case SVGA3D_R8_UNORM:
1914 case SVGA3D_R8_UINT:
1915 case SVGA3D_R8_SNORM:
1916 case SVGA3D_R8_SINT:
1917 return SVGA3D_R8_TYPELESS;
1918 case SVGA3D_B8G8R8A8_UNORM_SRGB:
1919 case SVGA3D_B8G8R8A8_UNORM:
1920 case SVGA3D_B8G8R8A8_TYPELESS:
1921 return SVGA3D_B8G8R8A8_TYPELESS;
1922 case SVGA3D_B8G8R8X8_UNORM_SRGB:
1923 case SVGA3D_B8G8R8X8_UNORM:
1924 case SVGA3D_B8G8R8X8_TYPELESS:
1925 return SVGA3D_B8G8R8X8_TYPELESS;
1926 case SVGA3D_BC1_UNORM:
1927 case SVGA3D_BC1_UNORM_SRGB:
1928 case SVGA3D_BC1_TYPELESS:
1929 return SVGA3D_BC1_TYPELESS;
1930 case SVGA3D_BC2_UNORM:
1931 case SVGA3D_BC2_UNORM_SRGB:
1932 case SVGA3D_BC2_TYPELESS:
1933 return SVGA3D_BC2_TYPELESS;
1934 case SVGA3D_BC3_UNORM:
1935 case SVGA3D_BC3_UNORM_SRGB:
1936 case SVGA3D_BC3_TYPELESS:
1937 return SVGA3D_BC3_TYPELESS;
1938 case SVGA3D_BC4_UNORM:
1939 case SVGA3D_BC4_SNORM:
1940 return SVGA3D_BC4_TYPELESS;
1941 case SVGA3D_BC5_UNORM:
1942 case SVGA3D_BC5_SNORM:
1943 return SVGA3D_BC5_TYPELESS;
1944
1945 /* Special cases (no corresponding _TYPELESS formats) */
1946 case SVGA3D_A8_UNORM:
1947 case SVGA3D_B5G5R5A1_UNORM:
1948 case SVGA3D_B5G6R5_UNORM:
1949 case SVGA3D_R11G11B10_FLOAT:
1950 case SVGA3D_R9G9B9E5_SHAREDEXP:
1951 return format;
1952 default:
1953 debug_printf("Unexpected format %s in %s\n",
1954 svga_format_name(format), __FUNCTION__);
1955 return format;
1956 }
1957 }
1958
1959
1960 /**
1961 * Given a surface format, return the corresponding format to use for
1962 * a texture sampler. In most cases, it's the format unchanged, but there
1963 * are some special cases.
1964 */
1965 SVGA3dSurfaceFormat
1966 svga_sampler_format(SVGA3dSurfaceFormat format)
1967 {
1968 switch (format) {
1969 case SVGA3D_D16_UNORM:
1970 return SVGA3D_R16_UNORM;
1971 case SVGA3D_D24_UNORM_S8_UINT:
1972 return SVGA3D_R24_UNORM_X8;
1973 case SVGA3D_D32_FLOAT:
1974 return SVGA3D_R32_FLOAT;
1975 case SVGA3D_D32_FLOAT_S8X24_UINT:
1976 return SVGA3D_R32_FLOAT_X8X24;
1977 default:
1978 return format;
1979 }
1980 }
1981
1982
1983 /**
1984 * Is the given format an uncompressed snorm format?
1985 */
1986 bool
1987 svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
1988 {
1989 switch (format) {
1990 case SVGA3D_R8G8B8A8_SNORM:
1991 case SVGA3D_R8G8_SNORM:
1992 case SVGA3D_R8_SNORM:
1993 case SVGA3D_R16G16B16A16_SNORM:
1994 case SVGA3D_R16G16_SNORM:
1995 case SVGA3D_R16_SNORM:
1996 return true;
1997 default:
1998 return false;
1999 }
2000 }
2001
2002
2003 bool
2004 svga_format_is_typeless(SVGA3dSurfaceFormat format)
2005 {
2006 switch (format) {
2007 case SVGA3D_R32G32B32A32_TYPELESS:
2008 case SVGA3D_R32G32B32_TYPELESS:
2009 case SVGA3D_R16G16B16A16_TYPELESS:
2010 case SVGA3D_R32G32_TYPELESS:
2011 case SVGA3D_R32G8X24_TYPELESS:
2012 case SVGA3D_R10G10B10A2_TYPELESS:
2013 case SVGA3D_R8G8B8A8_TYPELESS:
2014 case SVGA3D_R16G16_TYPELESS:
2015 case SVGA3D_R32_TYPELESS:
2016 case SVGA3D_R24G8_TYPELESS:
2017 case SVGA3D_R8G8_TYPELESS:
2018 case SVGA3D_R16_TYPELESS:
2019 case SVGA3D_R8_TYPELESS:
2020 case SVGA3D_BC1_TYPELESS:
2021 case SVGA3D_BC2_TYPELESS:
2022 case SVGA3D_BC3_TYPELESS:
2023 case SVGA3D_BC4_TYPELESS:
2024 case SVGA3D_BC5_TYPELESS:
2025 case SVGA3D_B8G8R8A8_TYPELESS:
2026 case SVGA3D_B8G8R8X8_TYPELESS:
2027 return true;
2028 default:
2029 return false;
2030 }
2031 }
2032
2033
2034 /**
2035 * \brief Can we import a surface with a given SVGA3D format as a texture?
2036 *
2037 * \param ss[in] pointer to the svga screen.
2038 * \param pformat[in] pipe format of the local texture.
2039 * \param sformat[in] svga3d format of the imported surface.
2040 * \param bind[in] bind flags of the imported texture.
2041 * \param verbose[in] Print out incompatibilities in debug mode.
2042 */
2043 bool
2044 svga_format_is_shareable(const struct svga_screen *ss,
2045 enum pipe_format pformat,
2046 SVGA3dSurfaceFormat sformat,
2047 unsigned bind,
2048 bool verbose)
2049 {
2050 SVGA3dSurfaceFormat default_format =
2051 svga_translate_format(ss, pformat, bind);
2052 int i;
2053
2054 if (default_format == SVGA3D_FORMAT_INVALID)
2055 return false;
2056 if (default_format == sformat)
2057 return true;
2058
2059 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2060 if (format_compats[i].pformat == pformat) {
2061 const SVGA3dSurfaceFormat *compat_format =
2062 format_compats[i].compat_format;
2063 while (*compat_format != 0) {
2064 if (*compat_format == sformat)
2065 return true;
2066 compat_format++;
2067 }
2068 }
2069 }
2070
2071 if (verbose) {
2072 debug_printf("Incompatible imported surface format.\n");
2073 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2074 svga_format_name(default_format),
2075 svga_format_name(sformat));
2076 }
2077
2078 return false;
2079 }
2080
2081
2082 /**
2083 * Return the sRGB format which corresponds to the given (linear) format.
2084 * If there's no such sRGB format, return the format as-is.
2085 */
2086 SVGA3dSurfaceFormat
2087 svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2088 {
2089 switch (format) {
2090 case SVGA3D_R8G8B8A8_UNORM:
2091 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2092 case SVGA3D_BC1_UNORM:
2093 return SVGA3D_BC1_UNORM_SRGB;
2094 case SVGA3D_BC2_UNORM:
2095 return SVGA3D_BC2_UNORM_SRGB;
2096 case SVGA3D_BC3_UNORM:
2097 return SVGA3D_BC3_UNORM_SRGB;
2098 case SVGA3D_B8G8R8A8_UNORM:
2099 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2100 case SVGA3D_B8G8R8X8_UNORM:
2101 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2102 default:
2103 return format;
2104 }
2105 }
2106
2107
2108 /**
2109 * Implement pipe_screen::is_format_supported().
2110 * \param bindings bitmask of PIPE_BIND_x flags
2111 */
2112 bool
2113 svga_is_format_supported(struct pipe_screen *screen,
2114 enum pipe_format format,
2115 enum pipe_texture_target target,
2116 unsigned sample_count,
2117 unsigned storage_sample_count,
2118 unsigned bindings)
2119 {
2120 struct svga_screen *ss = svga_screen(screen);
2121 SVGA3dSurfaceFormat svga_format;
2122 SVGA3dSurfaceFormatCaps caps;
2123 SVGA3dSurfaceFormatCaps mask;
2124
2125 assert(bindings);
2126 assert(!ss->sws->have_vgpu10);
2127
2128 /* Multisamples is not supported in VGPU9 device */
2129 if (sample_count > 1)
2130 return false;
2131
2132 svga_format = svga_translate_format(ss, format, bindings);
2133 if (svga_format == SVGA3D_FORMAT_INVALID) {
2134 return false;
2135 }
2136
2137 if (util_format_is_srgb(format) &&
2138 (bindings & PIPE_BIND_DISPLAY_TARGET)) {
2139 /* We only support sRGB rendering with vgpu10 */
2140 return false;
2141 }
2142
2143 /*
2144 * Override host capabilities, so that we end up with the same
2145 * visuals for all virtual hardware implementations.
2146 */
2147 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2148 switch (svga_format) {
2149 case SVGA3D_A8R8G8B8:
2150 case SVGA3D_X8R8G8B8:
2151 case SVGA3D_R5G6B5:
2152 break;
2153
2154 /* VGPU10 formats */
2155 case SVGA3D_B8G8R8A8_UNORM:
2156 case SVGA3D_B8G8R8X8_UNORM:
2157 case SVGA3D_B5G6R5_UNORM:
2158 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2159 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2160 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2161 break;
2162
2163 /* Often unsupported/problematic. This means we end up with the same
2164 * visuals for all virtual hardware implementations.
2165 */
2166 case SVGA3D_A4R4G4B4:
2167 case SVGA3D_A1R5G5B5:
2168 return false;
2169
2170 default:
2171 return false;
2172 }
2173 }
2174
2175 /*
2176 * Query the host capabilities.
2177 */
2178 svga_get_format_cap(ss, svga_format, &caps);
2179
2180 if (bindings & PIPE_BIND_RENDER_TARGET) {
2181 /* Check that the color surface is blendable, unless it's an
2182 * integer format.
2183 */
2184 if (!svga_format_is_integer(svga_format) &&
2185 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
2186 return false;
2187 }
2188 }
2189
2190 mask.value = 0;
2191 if (bindings & PIPE_BIND_RENDER_TARGET)
2192 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
2193
2194 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2195 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
2196
2197 if (bindings & PIPE_BIND_SAMPLER_VIEW)
2198 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
2199
2200 if (target == PIPE_TEXTURE_CUBE)
2201 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
2202 else if (target == PIPE_TEXTURE_3D)
2203 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
2204
2205 return (caps.value & mask.value) == mask.value;
2206 }
2207
2208
2209 /**
2210 * Implement pipe_screen::is_format_supported() for VGPU10 device.
2211 * \param bindings bitmask of PIPE_BIND_x flags
2212 */
2213 bool
2214 svga_is_dx_format_supported(struct pipe_screen *screen,
2215 enum pipe_format format,
2216 enum pipe_texture_target target,
2217 unsigned sample_count,
2218 unsigned storage_sample_count,
2219 unsigned bindings)
2220 {
2221 struct svga_screen *ss = svga_screen(screen);
2222 SVGA3dSurfaceFormat svga_format;
2223 SVGA3dDevCapResult caps;
2224 unsigned int mask = 0;
2225
2226 assert(bindings);
2227 assert(ss->sws->have_vgpu10);
2228
2229 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
2230 return false;
2231
2232 if (sample_count > 1) {
2233 /* In ms_samples, if bit N is set it means that we support
2234 * multisample with N+1 samples per pixel.
2235 */
2236 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
2237 return false;
2238 }
2239 mask |= SVGA3D_DXFMT_MULTISAMPLE;
2240 }
2241
2242 /*
2243 * For VGPU10 vertex formats, skip querying host capabilities
2244 */
2245
2246 if (bindings & PIPE_BIND_VERTEX_BUFFER) {
2247 SVGA3dSurfaceFormat svga_format;
2248 unsigned flags;
2249 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
2250 return svga_format != SVGA3D_FORMAT_INVALID;
2251 }
2252
2253 svga_format = svga_translate_format(ss, format, bindings);
2254 if (svga_format == SVGA3D_FORMAT_INVALID) {
2255 return false;
2256 }
2257
2258 /*
2259 * Override host capabilities, so that we end up with the same
2260 * visuals for all virtual hardware implementations.
2261 */
2262 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2263 switch (svga_format) {
2264 case SVGA3D_A8R8G8B8:
2265 case SVGA3D_X8R8G8B8:
2266 case SVGA3D_R5G6B5:
2267 break;
2268
2269 /* VGPU10 formats */
2270 case SVGA3D_B8G8R8A8_UNORM:
2271 case SVGA3D_B8G8R8X8_UNORM:
2272 case SVGA3D_B5G6R5_UNORM:
2273 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2274 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2275 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2276 break;
2277
2278 /* Often unsupported/problematic. This means we end up with the same
2279 * visuals for all virtual hardware implementations.
2280 */
2281 case SVGA3D_A4R4G4B4:
2282 case SVGA3D_A1R5G5B5:
2283 return false;
2284
2285 default:
2286 return false;
2287 }
2288 }
2289
2290 /*
2291 * Query the host capabilities.
2292 */
2293 svga_get_dx_format_cap(ss, svga_format, &caps);
2294
2295 if (bindings & PIPE_BIND_RENDER_TARGET) {
2296 /* Check that the color surface is blendable, unless it's an
2297 * integer format.
2298 */
2299 if (!(svga_format_is_integer(svga_format) ||
2300 (caps.u & SVGA3D_DXFMT_BLENDABLE))) {
2301 return false;
2302 }
2303 mask |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
2304 }
2305
2306 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2307 mask |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
2308
2309 switch (target) {
2310 case PIPE_TEXTURE_3D:
2311 mask |= SVGA3D_DXFMT_VOLUME;
2312 break;
2313 case PIPE_TEXTURE_1D_ARRAY:
2314 case PIPE_TEXTURE_2D_ARRAY:
2315 case PIPE_TEXTURE_CUBE_ARRAY:
2316 mask |= SVGA3D_DXFMT_ARRAY;
2317 break;
2318 default:
2319 break;
2320 }
2321
2322 /* Is the format supported for rendering */
2323 if ((caps.u & mask) != mask)
2324 return false;
2325
2326 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
2327 SVGA3dSurfaceFormat sampler_format;
2328
2329 /* Get the sampler view format */
2330 sampler_format = svga_sampler_format(svga_format);
2331 if (sampler_format != svga_format) {
2332 caps.u = 0;
2333 svga_get_dx_format_cap(ss, sampler_format, &caps);
2334 mask &= SVGA3D_DXFMT_VOLUME;
2335 mask |= SVGA3D_DXFMT_SHADER_SAMPLE;
2336 if ((caps.u & mask) != mask)
2337 return false;
2338 }
2339 }
2340
2341 return true;
2342 }