1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "util/u_inlines.h"
31 #include "os/os_thread.h"
32 #include "util/u_format.h"
33 #include "util/u_math.h"
34 #include "util/u_memory.h"
36 #include "svga_screen.h"
37 #include "svga_context.h"
38 #include "svga_resource_texture.h"
39 #include "svga_resource_buffer.h"
40 #include "svga_sampler_view.h"
41 #include "svga_winsys.h"
42 #include "svga_debug.h"
45 /* XXX: This isn't a real hardware flag, but just a hack for kernel to
46 * know about primary surfaces. Find a better way to accomplish this.
48 #define SVGA3D_SURFACE_HINT_SCANOUT (1 << 9)
52 * Helper function and arrays
56 svga_translate_format(enum pipe_format format
)
60 case PIPE_FORMAT_B8G8R8A8_UNORM
:
61 return SVGA3D_A8R8G8B8
;
62 case PIPE_FORMAT_B8G8R8X8_UNORM
:
63 return SVGA3D_X8R8G8B8
;
65 /* Required for GL2.1:
67 case PIPE_FORMAT_B8G8R8A8_SRGB
:
68 return SVGA3D_A8R8G8B8
;
70 case PIPE_FORMAT_B5G6R5_UNORM
:
72 case PIPE_FORMAT_B5G5R5A1_UNORM
:
73 return SVGA3D_A1R5G5B5
;
74 case PIPE_FORMAT_B4G4R4A4_UNORM
:
75 return SVGA3D_A4R4G4B4
;
78 /* XXX: Doesn't seem to work properly.
79 case PIPE_FORMAT_Z32_UNORM:
82 case PIPE_FORMAT_Z16_UNORM
:
84 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
85 return SVGA3D_Z_D24S8
;
86 case PIPE_FORMAT_X8Z24_UNORM
:
87 return SVGA3D_Z_D24X8
;
89 case PIPE_FORMAT_A8_UNORM
:
91 case PIPE_FORMAT_L8_UNORM
:
92 return SVGA3D_LUMINANCE8
;
94 case PIPE_FORMAT_DXT1_RGB
:
95 case PIPE_FORMAT_DXT1_RGBA
:
97 case PIPE_FORMAT_DXT3_RGBA
:
99 case PIPE_FORMAT_DXT5_RGBA
:
103 return SVGA3D_FORMAT_INVALID
;
109 svga_translate_format_render(enum pipe_format format
)
112 case PIPE_FORMAT_B8G8R8A8_UNORM
:
113 case PIPE_FORMAT_B8G8R8X8_UNORM
:
114 case PIPE_FORMAT_B5G5R5A1_UNORM
:
115 case PIPE_FORMAT_B4G4R4A4_UNORM
:
116 case PIPE_FORMAT_B5G6R5_UNORM
:
117 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
118 case PIPE_FORMAT_X8Z24_UNORM
:
119 case PIPE_FORMAT_Z32_UNORM
:
120 case PIPE_FORMAT_Z16_UNORM
:
121 case PIPE_FORMAT_L8_UNORM
:
122 return svga_translate_format(format
);
125 return SVGA3D_FORMAT_INVALID
;
131 svga_transfer_dma_band(struct svga_context
*svga
,
132 struct svga_transfer
*st
,
133 SVGA3dTransferType transfer
,
134 unsigned y
, unsigned h
, unsigned srcy
,
135 SVGA3dSurfaceDMAFlags flags
)
137 struct svga_texture
*texture
= svga_texture(st
->base
.resource
);
141 box
.x
= st
->base
.box
.x
;
143 box
.z
= st
->base
.box
.z
;
144 box
.w
= st
->base
.box
.width
;
151 if (st
->base
.resource
->target
== PIPE_TEXTURE_CUBE
) {
152 st
->face
= st
->base
.box
.z
;
158 SVGA_DBG(DEBUG_DMA
, "dma %s sid %p, face %u, (%u, %u, %u) - (%u, %u, %u), %ubpp\n",
159 transfer
== SVGA3D_WRITE_HOST_VRAM
? "to" : "from",
165 st
->base
.box
.x
+ st
->base
.box
.width
,
168 util_format_get_blocksize(texture
->b
.b
.format
) * 8 /
169 (util_format_get_blockwidth(texture
->b
.b
.format
)*util_format_get_blockheight(texture
->b
.b
.format
)));
171 ret
= SVGA3D_SurfaceDMA(svga
->swc
, st
, transfer
, &box
, 1, flags
);
173 svga_context_flush(svga
, NULL
);
174 ret
= SVGA3D_SurfaceDMA(svga
->swc
, st
, transfer
, &box
, 1, flags
);
175 assert(ret
== PIPE_OK
);
181 svga_transfer_dma(struct svga_context
*svga
,
182 struct svga_transfer
*st
,
183 SVGA3dTransferType transfer
,
184 SVGA3dSurfaceDMAFlags flags
)
186 struct svga_texture
*texture
= svga_texture(st
->base
.resource
);
187 struct svga_screen
*screen
= svga_screen(texture
->b
.b
.screen
);
188 struct svga_winsys_screen
*sws
= screen
->sws
;
189 struct pipe_fence_handle
*fence
= NULL
;
191 if (transfer
== SVGA3D_READ_HOST_VRAM
) {
192 SVGA_DBG(DEBUG_PERF
, "%s: readback transfer\n", __FUNCTION__
);
195 /* Ensure any pending operations on host surfaces are queued on the command
198 svga_surfaces_flush( svga
);
201 /* Do the DMA transfer in a single go */
203 svga_transfer_dma_band(svga
, st
, transfer
,
204 st
->base
.box
.y
, st
->base
.box
.height
, 0,
207 if(transfer
== SVGA3D_READ_HOST_VRAM
) {
208 svga_context_flush(svga
, &fence
);
209 sws
->fence_finish(sws
, fence
, 0);
210 sws
->fence_reference(sws
, &fence
, NULL
);
215 unsigned blockheight
= util_format_get_blockheight(st
->base
.resource
->format
);
216 h
= st
->hw_nblocksy
* blockheight
;
218 for(y
= 0; y
< st
->base
.box
.height
; y
+= h
) {
219 unsigned offset
, length
;
222 if (y
+ h
> st
->base
.box
.height
)
223 h
= st
->base
.box
.height
- y
;
225 /* Transfer band must be aligned to pixel block boundaries */
226 assert(y
% blockheight
== 0);
227 assert(h
% blockheight
== 0);
229 offset
= y
* st
->base
.stride
/ blockheight
;
230 length
= h
* st
->base
.stride
/ blockheight
;
232 sw
= (uint8_t *)st
->swbuf
+ offset
;
234 if(transfer
== SVGA3D_WRITE_HOST_VRAM
) {
235 /* Wait for the previous DMAs to complete */
236 /* TODO: keep one DMA (at half the size) in the background */
238 svga_context_flush(svga
, &fence
);
239 sws
->fence_finish(sws
, fence
, 0);
240 sws
->fence_reference(sws
, &fence
, NULL
);
243 hw
= sws
->buffer_map(sws
, st
->hwbuf
, PIPE_TRANSFER_WRITE
);
246 memcpy(hw
, sw
, length
);
247 sws
->buffer_unmap(sws
, st
->hwbuf
);
251 svga_transfer_dma_band(svga
, st
, transfer
, y
, h
, srcy
, flags
);
254 * Prevent the texture contents to be discarded on the next band
258 flags
.discard
= FALSE
;
260 if(transfer
== SVGA3D_READ_HOST_VRAM
) {
261 svga_context_flush(svga
, &fence
);
262 sws
->fence_finish(sws
, fence
, 0);
264 hw
= sws
->buffer_map(sws
, st
->hwbuf
, PIPE_TRANSFER_READ
);
267 memcpy(sw
, hw
, length
);
268 sws
->buffer_unmap(sws
, st
->hwbuf
);
280 svga_texture_get_handle(struct pipe_screen
*screen
,
281 struct pipe_resource
*texture
,
282 struct winsys_handle
*whandle
)
284 struct svga_winsys_screen
*sws
= svga_winsys_screen(texture
->screen
);
287 assert(svga_texture(texture
)->key
.cachable
== 0);
288 svga_texture(texture
)->key
.cachable
= 0;
289 stride
= util_format_get_nblocksx(texture
->format
, texture
->width0
) *
290 util_format_get_blocksize(texture
->format
);
291 return sws
->surface_get_handle(sws
, svga_texture(texture
)->handle
, stride
, whandle
);
296 svga_texture_destroy(struct pipe_screen
*screen
,
297 struct pipe_resource
*pt
)
299 struct svga_screen
*ss
= svga_screen(screen
);
300 struct svga_texture
*tex
= (struct svga_texture
*)pt
;
302 ss
->texture_timestamp
++;
304 svga_sampler_view_reference(&tex
->cached_view
, NULL
);
307 DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
309 SVGA_DBG(DEBUG_DMA
, "unref sid %p (texture)\n", tex
->handle
);
310 svga_screen_surface_destroy(ss
, &tex
->key
, &tex
->handle
);
321 /* XXX: Still implementing this as if it was a screen function, but
322 * can now modify it to queue transfers on the context.
324 static struct pipe_transfer
*
325 svga_texture_get_transfer(struct pipe_context
*pipe
,
326 struct pipe_resource
*texture
,
329 const struct pipe_box
*box
)
331 struct svga_context
*svga
= svga_context(pipe
);
332 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
333 struct svga_winsys_screen
*sws
= ss
->sws
;
334 struct svga_transfer
*st
;
335 unsigned nblocksx
= util_format_get_nblocksx(texture
->format
, box
->width
);
336 unsigned nblocksy
= util_format_get_nblocksy(texture
->format
, box
->height
);
338 /* We can't map texture storage directly */
339 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)
342 assert(box
->depth
== 1);
343 st
= CALLOC_STRUCT(svga_transfer
);
347 pipe_resource_reference(&st
->base
.resource
, texture
);
348 st
->base
.level
= level
;
349 st
->base
.usage
= usage
;
351 st
->base
.stride
= nblocksx
*util_format_get_blocksize(texture
->format
);
352 st
->base
.layer_stride
= 0;
354 st
->hw_nblocksy
= nblocksy
;
356 st
->hwbuf
= svga_winsys_buffer_create(svga
,
359 st
->hw_nblocksy
*st
->base
.stride
);
360 while(!st
->hwbuf
&& (st
->hw_nblocksy
/= 2)) {
361 st
->hwbuf
= svga_winsys_buffer_create(svga
,
364 st
->hw_nblocksy
*st
->base
.stride
);
370 if(st
->hw_nblocksy
< nblocksy
) {
371 /* We couldn't allocate a hardware buffer big enough for the transfer,
372 * so allocate regular malloc memory instead */
374 debug_printf("%s: failed to allocate %u KB of DMA, "
375 "splitting into %u x %u KB DMA transfers\n",
377 (nblocksy
*st
->base
.stride
+ 1023)/1024,
378 (nblocksy
+ st
->hw_nblocksy
- 1)/st
->hw_nblocksy
,
379 (st
->hw_nblocksy
*st
->base
.stride
+ 1023)/1024);
382 st
->swbuf
= MALLOC(nblocksy
*st
->base
.stride
);
387 if (usage
& PIPE_TRANSFER_READ
) {
388 SVGA3dSurfaceDMAFlags flags
;
389 memset(&flags
, 0, sizeof flags
);
390 svga_transfer_dma(svga
, st
, SVGA3D_READ_HOST_VRAM
, flags
);
396 sws
->buffer_destroy(sws
, st
->hwbuf
);
403 /* XXX: Still implementing this as if it was a screen function, but
404 * can now modify it to queue transfers on the context.
407 svga_texture_transfer_map( struct pipe_context
*pipe
,
408 struct pipe_transfer
*transfer
)
410 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
411 struct svga_winsys_screen
*sws
= ss
->sws
;
412 struct svga_transfer
*st
= svga_transfer(transfer
);
417 /* The wait for read transfers already happened when svga_transfer_dma
419 return sws
->buffer_map(sws
, st
->hwbuf
, transfer
->usage
);
423 /* XXX: Still implementing this as if it was a screen function, but
424 * can now modify it to queue transfers on the context.
427 svga_texture_transfer_unmap(struct pipe_context
*pipe
,
428 struct pipe_transfer
*transfer
)
430 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
431 struct svga_winsys_screen
*sws
= ss
->sws
;
432 struct svga_transfer
*st
= svga_transfer(transfer
);
435 sws
->buffer_unmap(sws
, st
->hwbuf
);
440 svga_texture_transfer_destroy(struct pipe_context
*pipe
,
441 struct pipe_transfer
*transfer
)
443 struct svga_context
*svga
= svga_context(pipe
);
444 struct svga_texture
*tex
= svga_texture(transfer
->resource
);
445 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
446 struct svga_winsys_screen
*sws
= ss
->sws
;
447 struct svga_transfer
*st
= svga_transfer(transfer
);
449 if (st
->base
.usage
& PIPE_TRANSFER_WRITE
) {
450 SVGA3dSurfaceDMAFlags flags
;
452 memset(&flags
, 0, sizeof flags
);
453 if (transfer
->usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
454 flags
.discard
= TRUE
;
456 if (transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
457 flags
.unsynchronized
= TRUE
;
460 svga_transfer_dma(svga
, st
, SVGA3D_WRITE_HOST_VRAM
, flags
);
461 ss
->texture_timestamp
++;
462 tex
->view_age
[transfer
->level
] = ++(tex
->age
);
463 if (transfer
->resource
->target
== PIPE_TEXTURE_CUBE
)
464 tex
->defined
[transfer
->box
.z
][transfer
->level
] = TRUE
;
466 tex
->defined
[0][transfer
->level
] = TRUE
;
469 pipe_resource_reference(&st
->base
.resource
, NULL
);
471 sws
->buffer_destroy(sws
, st
->hwbuf
);
479 struct u_resource_vtbl svga_texture_vtbl
=
481 svga_texture_get_handle
, /* get_handle */
482 svga_texture_destroy
, /* resource_destroy */
483 svga_texture_get_transfer
, /* get_transfer */
484 svga_texture_transfer_destroy
, /* transfer_destroy */
485 svga_texture_transfer_map
, /* transfer_map */
486 u_default_transfer_flush_region
, /* transfer_flush_region */
487 svga_texture_transfer_unmap
, /* transfer_unmap */
488 u_default_transfer_inline_write
/* transfer_inline_write */
494 struct pipe_resource
*
495 svga_texture_create(struct pipe_screen
*screen
,
496 const struct pipe_resource
*template)
498 struct svga_screen
*svgascreen
= svga_screen(screen
);
499 struct svga_texture
*tex
= CALLOC_STRUCT(svga_texture
);
504 tex
->b
.b
= *template;
505 tex
->b
.vtbl
= &svga_texture_vtbl
;
506 pipe_reference_init(&tex
->b
.b
.reference
, 1);
507 tex
->b
.b
.screen
= screen
;
509 assert(template->last_level
< SVGA_MAX_TEXTURE_LEVELS
);
510 if(template->last_level
>= SVGA_MAX_TEXTURE_LEVELS
)
514 tex
->key
.size
.width
= template->width0
;
515 tex
->key
.size
.height
= template->height0
;
516 tex
->key
.size
.depth
= template->depth0
;
518 if(template->target
== PIPE_TEXTURE_CUBE
) {
519 tex
->key
.flags
|= SVGA3D_SURFACE_CUBEMAP
;
520 tex
->key
.numFaces
= 6;
523 tex
->key
.numFaces
= 1;
526 /* XXX: Disabled for now */
527 tex
->key
.cachable
= 0;
529 if (template->bind
& PIPE_BIND_SAMPLER_VIEW
)
530 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_TEXTURE
;
532 if (template->bind
& PIPE_BIND_DISPLAY_TARGET
) {
533 tex
->key
.cachable
= 0;
536 if (template->bind
& PIPE_BIND_SHARED
) {
537 tex
->key
.cachable
= 0;
540 if (template->bind
& PIPE_BIND_SCANOUT
) {
541 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_SCANOUT
;
542 tex
->key
.cachable
= 0;
546 * XXX: Never pass the SVGA3D_SURFACE_HINT_RENDERTARGET hint. Mesa cannot
547 * know beforehand whether a texture will be used as a rendertarget or not
548 * and it always requests PIPE_BIND_RENDER_TARGET, therefore
549 * passing the SVGA3D_SURFACE_HINT_RENDERTARGET here defeats its purpose.
552 if((template->bind
& PIPE_BIND_RENDER_TARGET
) &&
553 !util_format_is_s3tc(template->format
))
554 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_RENDERTARGET
;
557 if(template->bind
& PIPE_BIND_DEPTH_STENCIL
)
558 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_DEPTHSTENCIL
;
560 tex
->key
.numMipLevels
= template->last_level
+ 1;
562 tex
->key
.format
= svga_translate_format(template->format
);
563 if(tex
->key
.format
== SVGA3D_FORMAT_INVALID
)
566 SVGA_DBG(DEBUG_DMA
, "surface_create for texture\n", tex
->handle
);
567 tex
->handle
= svga_screen_surface_create(svgascreen
, &tex
->key
);
569 SVGA_DBG(DEBUG_DMA
, " --> got sid %p (texture)\n", tex
->handle
);
571 debug_reference(&tex
->b
.b
.reference
,
572 (debug_reference_descriptor
)debug_describe_resource
, 0);
585 struct pipe_resource
*
586 svga_texture_from_handle(struct pipe_screen
*screen
,
587 const struct pipe_resource
*template,
588 struct winsys_handle
*whandle
)
590 struct svga_winsys_screen
*sws
= svga_winsys_screen(screen
);
591 struct svga_winsys_surface
*srf
;
592 struct svga_texture
*tex
;
593 enum SVGA3dSurfaceFormat format
= 0;
596 /* Only supports one type */
597 if ((template->target
!= PIPE_TEXTURE_2D
&&
598 template->target
!= PIPE_TEXTURE_RECT
) ||
599 template->last_level
!= 0 ||
600 template->depth0
!= 1) {
604 srf
= sws
->surface_from_handle(sws
, whandle
, &format
);
609 if (svga_translate_format(template->format
) != format
) {
610 unsigned f1
= svga_translate_format(template->format
);
611 unsigned f2
= format
;
613 /* It's okay for XRGB and ARGB or depth with/out stencil to get mixed up */
614 if ( !( (f1
== SVGA3D_X8R8G8B8
&& f2
== SVGA3D_A8R8G8B8
) ||
615 (f1
== SVGA3D_A8R8G8B8
&& f2
== SVGA3D_X8R8G8B8
) ||
616 (f1
== SVGA3D_Z_D24X8
&& f2
== SVGA3D_Z_D24S8
) ) ) {
617 debug_printf("%s wrong format %u != %u\n", __FUNCTION__
, f1
, f2
);
622 tex
= CALLOC_STRUCT(svga_texture
);
626 tex
->b
.b
= *template;
627 tex
->b
.vtbl
= &svga_texture_vtbl
;
628 pipe_reference_init(&tex
->b
.b
.reference
, 1);
629 tex
->b
.b
.screen
= screen
;
631 if (format
== SVGA3D_X8R8G8B8
)
632 tex
->b
.b
.format
= PIPE_FORMAT_B8G8R8X8_UNORM
;
633 else if (format
== SVGA3D_A8R8G8B8
)
634 tex
->b
.b
.format
= PIPE_FORMAT_B8G8R8A8_UNORM
;
639 SVGA_DBG(DEBUG_DMA
, "wrap surface sid %p\n", srf
);
641 tex
->key
.cachable
= 0;