src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifdef DEBUG
  53 int SVGA_DEBUG = 0;
  54
  55 static const struct debug_named_value svga_debug_flags[] = {
  56    { "dma",         DEBUG_DMA, NULL },
  57    { "tgsi",        DEBUG_TGSI, NULL },
  58    { "pipe",        DEBUG_PIPE, NULL },
  59    { "state",       DEBUG_STATE, NULL },
  60    { "screen",      DEBUG_SCREEN, NULL },
  61    { "tex",         DEBUG_TEX, NULL },
  62    { "swtnl",       DEBUG_SWTNL, NULL },
  63    { "const",       DEBUG_CONSTS, NULL },
  64    { "viewport",    DEBUG_VIEWPORT, NULL },
  65    { "views",       DEBUG_VIEWS, NULL },
  66    { "perf",        DEBUG_PERF, NULL },
  67    { "flush",       DEBUG_FLUSH, NULL },
  68    { "sync",        DEBUG_SYNC, NULL },
  69    { "cache",       DEBUG_CACHE, NULL },
  70    { "streamout",   DEBUG_STREAMOUT, NULL },
  71    { "query",       DEBUG_QUERY, NULL },
  72    { "samplers",    DEBUG_SAMPLERS, NULL },
  73    DEBUG_NAMED_VALUE_END
  74 };
  75 #endif
  76
  77 static const char *
  78 svga_get_vendor( struct pipe_screen *pscreen )
  79 {
  80    return "VMware, Inc.";
  81 }
  82
  83
  84 static const char *
  85 svga_get_name( struct pipe_screen *pscreen )
  86 {
  87    const char *build = "", *llvm = "", *mutex = "";
  88    static char name[100];
  89 #ifdef DEBUG
  90    /* Only return internal details in the DEBUG version:
  91     */
  92    build = "build: DEBUG;";
  93    mutex = "mutex: " PIPE_ATOMIC ";";
  94 #elif defined(VMX86_STATS)
  95    build = "build: OPT;";
  96 #else
  97    build = "build: RELEASE;";
  98 #endif
  99 #ifdef HAVE_LLVM
 100    llvm = "LLVM;";
 101 #endif
 102
 103    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 104    return name;
 105 }
 106
 107
 108 /** Helper for querying float-valued device cap */
 109 static float
 110 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 111 {
 112    SVGA3dDevCapResult result;
 113    if (sws->get_cap(sws, cap, &result))
 114       return result.f;
 115    else
 116       return defaultVal;
 117 }
 118
 119
 120 /** Helper for querying uint-valued device cap */
 121 static unsigned
 122 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 123 {
 124    SVGA3dDevCapResult result;
 125    if (sws->get_cap(sws, cap, &result))
 126       return result.u;
 127    else
 128       return defaultVal;
 129 }
 130
 131
 132 /** Helper for querying boolean-valued device cap */
 133 static boolean
 134 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 135 {
 136    SVGA3dDevCapResult result;
 137    if (sws->get_cap(sws, cap, &result))
 138       return result.b;
 139    else
 140       return defaultVal;
 141 }
 142
 143
 144 static float
 145 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 146 {
 147    struct svga_screen *svgascreen = svga_screen(screen);
 148    struct svga_winsys_screen *sws = svgascreen->sws;
 149
 150    switch (param) {
 151    case PIPE_CAPF_MAX_LINE_WIDTH:
 152       return svgascreen->maxLineWidth;
 153    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 154       return svgascreen->maxLineWidthAA;
 155
 156    case PIPE_CAPF_MAX_POINT_WIDTH:
 157       /* fall-through */
 158    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 159       return svgascreen->maxPointSize;
 160
 161    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 162       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 163
 164    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 165       return 15.0;
 166
 167    case PIPE_CAPF_GUARD_BAND_LEFT:
 168    case PIPE_CAPF_GUARD_BAND_TOP:
 169    case PIPE_CAPF_GUARD_BAND_RIGHT:
 170    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 171       return 0.0;
 172    }
 173
 174    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 175    return 0;
 176 }
 177
 178
 179 static int
 180 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 181 {
 182    struct svga_screen *svgascreen = svga_screen(screen);
 183    struct svga_winsys_screen *sws = svgascreen->sws;
 184    SVGA3dDevCapResult result;
 185
 186    switch (param) {
 187    case PIPE_CAP_NPOT_TEXTURES:
 188    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 189    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 190       return 1;
 191    case PIPE_CAP_TWO_SIDED_STENCIL:
 192       return 1;
 193    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 194       /*
 195        * "In virtually every OpenGL implementation and hardware,
 196        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 197        * http://www.opengl.org/wiki/Blending
 198        */
 199       return sws->have_vgpu10 ? 1 : 0;
 200    case PIPE_CAP_ANISOTROPIC_FILTER:
 201       return 1;
 202    case PIPE_CAP_POINT_SPRITE:
 203       return 1;
 204    case PIPE_CAP_TGSI_TEXCOORD:
 205       return 0;
 206    case PIPE_CAP_MAX_RENDER_TARGETS:
 207       return svgascreen->max_color_buffers;
 208    case PIPE_CAP_OCCLUSION_QUERY:
 209       return 1;
 210    case PIPE_CAP_QUERY_TIME_ELAPSED:
 211       return 0;
 212    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 213       return sws->have_vgpu10;
 214    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 215       return 1;
 216    case PIPE_CAP_TEXTURE_SWIZZLE:
 217       return 1;
 218    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 219       return 0;
 220    case PIPE_CAP_USER_VERTEX_BUFFERS:
 221       return 0;
 222    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 223       return 1;
 224    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 225       return 256;
 226
 227    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 228       {
 229          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 230          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 231             levels = MIN2(util_logbase2(result.u) + 1, levels);
 232          else
 233             levels = 12 /* 2048x2048 */;
 234          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 235             levels = MIN2(util_logbase2(result.u) + 1, levels);
 236          else
 237             levels = 12 /* 2048x2048 */;
 238          return levels;
 239       }
 240
 241    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 242       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 243          return 8;  /* max 128x128x128 */
 244       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 245
 246    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 247       /*
 248        * No mechanism to query the host, and at least limited to 2048x2048 on
 249        * certain hardware.
 250        */
 251       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 252                   12 /* 2048x2048 */);
 253
 254    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 255       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 256
 257    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 258       return 1;
 259
 260    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 261       return 1;
 262    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 263       return sws->have_vgpu10;
 264    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 265       return 0;
 266    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 267       return !sws->have_vgpu10;
 268
 269    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 270       return 1; /* The color outputs of vertex shaders are not clamped */
 271    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 272       return 0; /* The driver can't clamp vertex colors */
 273    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 274       return 0; /* The driver can't clamp fragment colors */
 275
 276    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 277       return 1; /* expected for GL_ARB_framebuffer_object */
 278
 279    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 280       return sws->have_vgpu10 ? 330 : 120;
 281
 282    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 283       return 0;
 284
 285    case PIPE_CAP_SM3:
 286       return 1;
 287
 288    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 289    case PIPE_CAP_INDEP_BLEND_ENABLE:
 290    case PIPE_CAP_CONDITIONAL_RENDER:
 291    case PIPE_CAP_QUERY_TIMESTAMP:
 292    case PIPE_CAP_TGSI_INSTANCEID:
 293    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 294    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 295    case PIPE_CAP_FAKE_SW_MSAA:
 296       return sws->have_vgpu10;
 297
 298    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 299       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 300    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 301       return sws->have_vgpu10 ? 4 : 0;
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 303       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 304    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 305    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 306       return 0;
 307    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 308       return svgascreen->ms_samples ? 1 : 0;
 309
 310    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 311       /* convert bytes to texels for the case of the largest texel
 312        * size: float[4].
 313        */
 314       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 315
 316    case PIPE_CAP_MIN_TEXEL_OFFSET:
 317       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 318    case PIPE_CAP_MAX_TEXEL_OFFSET:
 319       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 320
 321    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 322    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 323       return 0;
 324
 325    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 326       return sws->have_vgpu10 ? 256 : 0;
 327    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 328       return sws->have_vgpu10 ? 1024 : 0;
 329
 330    case PIPE_CAP_PRIMITIVE_RESTART:
 331       return 1; /* may be a sw fallback, depending on restart index */
 332
 333    case PIPE_CAP_GENERATE_MIPMAP:
 334       return sws->have_generate_mipmap_cmd;
 335
 336    case PIPE_CAP_NATIVE_FENCE_FD:
 337       return sws->have_fence_fd;
 338
 339    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 340       return 1;
 341
 342    /* Unsupported features */
 343    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 344    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 345    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 346    case PIPE_CAP_INDEP_BLEND_FUNC:
 347    case PIPE_CAP_TEXTURE_BARRIER:
 348    case PIPE_CAP_MAX_VERTEX_STREAMS:
 349    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 350    case PIPE_CAP_COMPUTE:
 351    case PIPE_CAP_START_INSTANCE:
 352    case PIPE_CAP_CUBE_MAP_ARRAY:
 353    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 354    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 355    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 356    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 357    case PIPE_CAP_TEXTURE_GATHER_SM5:
 358    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 359    case PIPE_CAP_TEXTURE_QUERY_LOD:
 360    case PIPE_CAP_SAMPLE_SHADING:
 361    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 362    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 363    case PIPE_CAP_DRAW_INDIRECT:
 364    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 365    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 366    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 367    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 368    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 369    case PIPE_CAP_CLIP_HALFZ:
 370    case PIPE_CAP_VERTEXID_NOBASE:
 371    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 372    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 373    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 374    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 375    case PIPE_CAP_INVALIDATE_BUFFER:
 376    case PIPE_CAP_STRING_MARKER:
 377    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 378    case PIPE_CAP_QUERY_MEMORY_INFO:
 379    case PIPE_CAP_PCI_GROUP:
 380    case PIPE_CAP_PCI_BUS:
 381    case PIPE_CAP_PCI_DEVICE:
 382    case PIPE_CAP_PCI_FUNCTION:
 383    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 384       return 0;
 385    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 386       return 64;
 387    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 388    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 389    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 390       return 1;  /* need 4-byte alignment for all offsets and strides */
 391    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 392       return 2048;
 393    case PIPE_CAP_MAX_VIEWPORTS:
 394       return 1;
 395    case PIPE_CAP_ENDIANNESS:
 396       return PIPE_ENDIAN_LITTLE;
 397
 398    case PIPE_CAP_VENDOR_ID:
 399       return 0x15ad; /* VMware Inc. */
 400    case PIPE_CAP_DEVICE_ID:
 401       return 0x0405; /* assume SVGA II */
 402    case PIPE_CAP_ACCELERATED:
 403       return 0; /* XXX: */
 404    case PIPE_CAP_VIDEO_MEMORY:
 405       /* XXX: Query the host ? */
 406       return 1;
 407    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 408       return sws->have_vgpu10;
 409    case PIPE_CAP_CLEAR_TEXTURE:
 410       return sws->have_vgpu10;
 411    case PIPE_CAP_UMA:
 412    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 413    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 414    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 415    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 416    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 417    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 418    case PIPE_CAP_TGSI_TXQS:
 419    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 420    case PIPE_CAP_SHAREABLE_SHADERS:
 421    case PIPE_CAP_DRAW_PARAMETERS:
 422    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 423    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 424    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 425    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 426    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 427    case PIPE_CAP_CULL_DISTANCE:
 428    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 429    case PIPE_CAP_TGSI_VOTE:
 430    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 431    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 432    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 433    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 434    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 435    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 436    case PIPE_CAP_TGSI_FS_FBFETCH:
 437    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 438    case PIPE_CAP_DOUBLES:
 439    case PIPE_CAP_INT64:
 440    case PIPE_CAP_INT64_DIVMOD:
 441    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 442    case PIPE_CAP_TGSI_CLOCK:
 443    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 444    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 445    case PIPE_CAP_TGSI_BALLOT:
 446    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 447    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 448    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 449    case PIPE_CAP_POST_DEPTH_COVERAGE:
 450    case PIPE_CAP_BINDLESS_TEXTURE:
 451    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 452    case PIPE_CAP_QUERY_SO_OVERFLOW:
 453    case PIPE_CAP_MEMOBJ:
 454    case PIPE_CAP_LOAD_CONSTBUF:
 455    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 456    case PIPE_CAP_TILE_RASTER_ORDER:
 457       return 0;
 458    }
 459
 460    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 461    return 0;
 462 }
 463
 464
 465 static int
 466 vgpu9_get_shader_param(struct pipe_screen *screen,
 467                        enum pipe_shader_type shader,
 468                        enum pipe_shader_cap param)
 469 {
 470    struct svga_screen *svgascreen = svga_screen(screen);
 471    struct svga_winsys_screen *sws = svgascreen->sws;
 472    unsigned val;
 473
 474    assert(!sws->have_vgpu10);
 475
 476    switch (shader)
 477    {
 478    case PIPE_SHADER_FRAGMENT:
 479       switch (param)
 480       {
 481       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 482       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 483          return get_uint_cap(sws,
 484                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 485                              512);
 486       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 487       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 488          return 512;
 489       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 490          return SVGA3D_MAX_NESTING_LEVEL;
 491       case PIPE_SHADER_CAP_MAX_INPUTS:
 492          return 10;
 493       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 494          return svgascreen->max_color_buffers;
 495       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 496          return 224 * sizeof(float[4]);
 497       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 498          return 1;
 499       case PIPE_SHADER_CAP_MAX_TEMPS:
 500          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 501          return MIN2(val, SVGA3D_TEMPREG_MAX);
 502       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 503          /*
 504           * Although PS 3.0 has some addressing abilities it can only represent
 505           * loops that can be statically determined and unrolled. Given we can
 506           * only handle a subset of the cases that the state tracker already
 507           * does it is better to defer loop unrolling to the state tracker.
 508           */
 509          return 0;
 510       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 511          return 0;
 512       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 513          return 0;
 514       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 515       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 516       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 517          return 0;
 518       case PIPE_SHADER_CAP_SUBROUTINES:
 519          return 0;
 520       case PIPE_SHADER_CAP_INT64_ATOMICS:
 521       case PIPE_SHADER_CAP_INTEGERS:
 522          return 0;
 523       case PIPE_SHADER_CAP_FP16:
 524          return 0;
 525       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 526       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 527          return 16;
 528       case PIPE_SHADER_CAP_PREFERRED_IR:
 529          return PIPE_SHADER_IR_TGSI;
 530       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 531          return 0;
 532       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 533       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 534       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 535       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 536       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 537       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 538       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 539       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 540       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 541          return 0;
 542       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 543          return 32;
 544       }
 545       /* If we get here, we failed to handle a cap above */
 546       debug_printf("Unexpected fragment shader query %u\n", param);
 547       return 0;
 548    case PIPE_SHADER_VERTEX:
 549       switch (param)
 550       {
 551       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 552       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 553          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 554                              512);
 555       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 556       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 557          /* XXX: until we have vertex texture support */
 558          return 0;
 559       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 560          return SVGA3D_MAX_NESTING_LEVEL;
 561       case PIPE_SHADER_CAP_MAX_INPUTS:
 562          return 16;
 563       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 564          return 10;
 565       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 566          return 256 * sizeof(float[4]);
 567       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 568          return 1;
 569       case PIPE_SHADER_CAP_MAX_TEMPS:
 570          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 571          return MIN2(val, SVGA3D_TEMPREG_MAX);
 572       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 573          return 0;
 574       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 575          return 0;
 576       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 577       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 578          return 1;
 579       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 580          return 0;
 581       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 582          return 1;
 583       case PIPE_SHADER_CAP_SUBROUTINES:
 584          return 0;
 585       case PIPE_SHADER_CAP_INT64_ATOMICS:
 586       case PIPE_SHADER_CAP_INTEGERS:
 587          return 0;
 588       case PIPE_SHADER_CAP_FP16:
 589          return 0;
 590       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 591       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 592          return 0;
 593       case PIPE_SHADER_CAP_PREFERRED_IR:
 594          return PIPE_SHADER_IR_TGSI;
 595       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 596          return 0;
 597       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 598       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 599       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 600       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 601       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 602       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 603       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 604       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 605       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 606          return 0;
 607       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 608          return 32;
 609       }
 610       /* If we get here, we failed to handle a cap above */
 611       debug_printf("Unexpected vertex shader query %u\n", param);
 612       return 0;
 613    case PIPE_SHADER_GEOMETRY:
 614    case PIPE_SHADER_COMPUTE:
 615    case PIPE_SHADER_TESS_CTRL:
 616    case PIPE_SHADER_TESS_EVAL:
 617       /* no support for geometry, tess or compute shaders at this time */
 618       return 0;
 619    default:
 620       debug_printf("Unexpected shader type (%u) query\n", shader);
 621       return 0;
 622    }
 623    return 0;
 624 }
 625
 626
 627 static int
 628 vgpu10_get_shader_param(struct pipe_screen *screen,
 629                         enum pipe_shader_type shader,
 630                         enum pipe_shader_cap param)
 631 {
 632    struct svga_screen *svgascreen = svga_screen(screen);
 633    struct svga_winsys_screen *sws = svgascreen->sws;
 634
 635    assert(sws->have_vgpu10);
 636    (void) sws;  /* silence unused var warnings in non-debug builds */
 637
 638    /* Only VS, GS, FS supported */
 639    if (shader != PIPE_SHADER_VERTEX &&
 640        shader != PIPE_SHADER_GEOMETRY &&
 641        shader != PIPE_SHADER_FRAGMENT) {
 642       return 0;
 643    }
 644
 645    /* NOTE: we do not query the device for any caps/limits at this time */
 646
 647    /* Generally the same limits for vertex, geometry and fragment shaders */
 648    switch (param) {
 649    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 650    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 651    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 652    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 653       return 64 * 1024;
 654    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 655       return 64;
 656    case PIPE_SHADER_CAP_MAX_INPUTS:
 657       if (shader == PIPE_SHADER_FRAGMENT)
 658          return VGPU10_MAX_FS_INPUTS;
 659       else if (shader == PIPE_SHADER_GEOMETRY)
 660          return VGPU10_MAX_GS_INPUTS;
 661       else
 662          return VGPU10_MAX_VS_INPUTS;
 663    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 664       if (shader == PIPE_SHADER_FRAGMENT)
 665          return VGPU10_MAX_FS_OUTPUTS;
 666       else if (shader == PIPE_SHADER_GEOMETRY)
 667          return VGPU10_MAX_GS_OUTPUTS;
 668       else
 669          return VGPU10_MAX_VS_OUTPUTS;
 670    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 671       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 672    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 673       return svgascreen->max_const_buffers;
 674    case PIPE_SHADER_CAP_MAX_TEMPS:
 675       return VGPU10_MAX_TEMPS;
 676    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 677    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 678    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 679    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 680       return TRUE; /* XXX verify */
 681    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 682    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 683    case PIPE_SHADER_CAP_SUBROUTINES:
 684    case PIPE_SHADER_CAP_INTEGERS:
 685       return TRUE;
 686    case PIPE_SHADER_CAP_FP16:
 687       return FALSE;
 688    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 689    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 690       return SVGA3D_DX_MAX_SAMPLERS;
 691    case PIPE_SHADER_CAP_PREFERRED_IR:
 692       return PIPE_SHADER_IR_TGSI;
 693    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 694       return 0;
 695    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 696    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 697    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 698    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 699    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 700    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 701    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 702    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 703    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 704    case PIPE_SHADER_CAP_INT64_ATOMICS:
 705       return 0;
 706    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 707       return 32;
 708    default:
 709       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 710       return 0;
 711    }
 712    return 0;
 713 }
 714
 715
 716 static int
 717 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 718                       enum pipe_shader_cap param)
 719 {
 720    struct svga_screen *svgascreen = svga_screen(screen);
 721    struct svga_winsys_screen *sws = svgascreen->sws;
 722    if (sws->have_vgpu10) {
 723       return vgpu10_get_shader_param(screen, shader, param);
 724    }
 725    else {
 726       return vgpu9_get_shader_param(screen, shader, param);
 727    }
 728 }
 729
 730
 731 /**
 732  * Implement pipe_screen::is_format_supported().
 733  * \param bindings  bitmask of PIPE_BIND_x flags
 734  */
 735 static boolean
 736 svga_is_format_supported( struct pipe_screen *screen,
 737                           enum pipe_format format,
 738                           enum pipe_texture_target target,
 739                           unsigned sample_count,
 740                           unsigned bindings)
 741 {
 742    struct svga_screen *ss = svga_screen(screen);
 743    SVGA3dSurfaceFormat svga_format;
 744    SVGA3dSurfaceFormatCaps caps;
 745    SVGA3dSurfaceFormatCaps mask;
 746
 747    assert(bindings);
 748
 749    if (sample_count > 1) {
 750       /* In ms_samples, if bit N is set it means that we support
 751        * multisample with N+1 samples per pixel.
 752        */
 753       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 754          return FALSE;
 755       }
 756    }
 757
 758    svga_format = svga_translate_format(ss, format, bindings);
 759    if (svga_format == SVGA3D_FORMAT_INVALID) {
 760       return FALSE;
 761    }
 762
 763    if (!ss->sws->have_vgpu10 &&
 764        util_format_is_srgb(format) &&
 765        (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 766        /* We only support sRGB rendering with vgpu10 */
 767       return FALSE;
 768    }
 769
 770    /*
 771     * For VGPU10 vertex formats, skip querying host capabilities
 772     */
 773
 774    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 775       SVGA3dSurfaceFormat svga_format;
 776       unsigned flags;
 777       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 778       return svga_format != SVGA3D_FORMAT_INVALID;
 779    }
 780
 781    /*
 782     * Override host capabilities, so that we end up with the same
 783     * visuals for all virtual hardware implementations.
 784     */
 785
 786    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 787       switch (svga_format) {
 788       case SVGA3D_A8R8G8B8:
 789       case SVGA3D_X8R8G8B8:
 790       case SVGA3D_R5G6B5:
 791          break;
 792
 793       /* VGPU10 formats */
 794       case SVGA3D_B8G8R8A8_UNORM:
 795       case SVGA3D_B8G8R8X8_UNORM:
 796       case SVGA3D_B5G6R5_UNORM:
 797       case SVGA3D_B8G8R8X8_UNORM_SRGB:
 798       case SVGA3D_B8G8R8A8_UNORM_SRGB:
 799       case SVGA3D_R8G8B8A8_UNORM_SRGB:
 800          break;
 801
 802       /* Often unsupported/problematic. This means we end up with the same
 803        * visuals for all virtual hardware implementations.
 804        */
 805       case SVGA3D_A4R4G4B4:
 806       case SVGA3D_A1R5G5B5:
 807          return FALSE;
 808
 809       default:
 810          return FALSE;
 811       }
 812    }
 813
 814    /*
 815     * Query the host capabilities.
 816     */
 817
 818    svga_get_format_cap(ss, svga_format, &caps);
 819
 820    if (bindings & PIPE_BIND_RENDER_TARGET) {
 821       /* Check that the color surface is blendable, unless it's an
 822        * integer format.
 823        */
 824       if (!svga_format_is_integer(svga_format) &&
 825           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 826          return FALSE;
 827       }
 828    }
 829
 830    mask.value = 0;
 831    if (bindings & PIPE_BIND_RENDER_TARGET) {
 832       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 833    }
 834    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 835       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 836    }
 837    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 838       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 839    }
 840
 841    if (target == PIPE_TEXTURE_CUBE) {
 842       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 843    }
 844    else if (target == PIPE_TEXTURE_3D) {
 845       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 846    }
 847
 848    return (caps.value & mask.value) == mask.value;
 849 }
 850
 851
 852 static void
 853 svga_fence_reference(struct pipe_screen *screen,
 854                      struct pipe_fence_handle **ptr,
 855                      struct pipe_fence_handle *fence)
 856 {
 857    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 858    sws->fence_reference(sws, ptr, fence);
 859 }
 860
 861
 862 static boolean
 863 svga_fence_finish(struct pipe_screen *screen,
 864                   struct pipe_context *ctx,
 865                   struct pipe_fence_handle *fence,
 866                   uint64_t timeout)
 867 {
 868    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 869    boolean retVal;
 870
 871    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 872
 873    if (!timeout) {
 874       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 875    }
 876    else {
 877       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 878                __FUNCTION__, fence);
 879
 880       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 881    }
 882
 883    SVGA_STATS_TIME_POP(sws);
 884
 885    return retVal;
 886 }
 887
 888
 889 static int
 890 svga_fence_get_fd(struct pipe_screen *screen,
 891                   struct pipe_fence_handle *fence)
 892 {
 893    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 894
 895    return sws->fence_get_fd(sws, fence, TRUE);
 896 }
 897
 898
 899 static int
 900 svga_get_driver_query_info(struct pipe_screen *screen,
 901                            unsigned index,
 902                            struct pipe_driver_query_info *info)
 903 {
 904 #define QUERY(NAME, ENUM, UNITS) \
 905    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 906
 907    static const struct pipe_driver_query_info queries[] = {
 908       /* per-frame counters */
 909       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 910             PIPE_DRIVER_QUERY_TYPE_UINT64),
 911       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 912             PIPE_DRIVER_QUERY_TYPE_UINT64),
 913       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 914             PIPE_DRIVER_QUERY_TYPE_UINT64),
 915       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 916             PIPE_DRIVER_QUERY_TYPE_UINT64),
 917       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 918             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 919       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 920             PIPE_DRIVER_QUERY_TYPE_UINT64),
 921       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 922             PIPE_DRIVER_QUERY_TYPE_UINT64),
 923       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 924             PIPE_DRIVER_QUERY_TYPE_BYTES),
 925       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 926             PIPE_DRIVER_QUERY_TYPE_BYTES),
 927       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 928             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 929       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 930             PIPE_DRIVER_QUERY_TYPE_UINT64),
 931       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 932             PIPE_DRIVER_QUERY_TYPE_UINT64),
 933       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 934             PIPE_DRIVER_QUERY_TYPE_UINT64),
 935       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 936             PIPE_DRIVER_QUERY_TYPE_UINT64),
 937       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 938             PIPE_DRIVER_QUERY_TYPE_UINT64),
 939       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 940             PIPE_DRIVER_QUERY_TYPE_UINT64),
 941
 942       /* running total counters */
 943       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 944             PIPE_DRIVER_QUERY_TYPE_BYTES),
 945       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 946             PIPE_DRIVER_QUERY_TYPE_UINT64),
 947       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 948             PIPE_DRIVER_QUERY_TYPE_UINT64),
 949       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 950             PIPE_DRIVER_QUERY_TYPE_UINT64),
 951       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 952             PIPE_DRIVER_QUERY_TYPE_UINT64),
 953       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 954             PIPE_DRIVER_QUERY_TYPE_UINT64),
 955       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 956             PIPE_DRIVER_QUERY_TYPE_UINT64),
 957    };
 958 #undef QUERY
 959
 960    if (!info)
 961       return ARRAY_SIZE(queries);
 962
 963    if (index >= ARRAY_SIZE(queries))
 964       return 0;
 965
 966    *info = queries[index];
 967    return 1;
 968 }
 969
 970
 971 static void
 972 init_logging(struct pipe_screen *screen)
 973 {
 974    static const char *log_prefix = "Mesa: ";
 975    char host_log[1000];
 976
 977    /* Log Version to Host */
 978    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 979                  "%s%s", log_prefix, svga_get_name(screen));
 980    svga_host_log(host_log);
 981
 982    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 983                  "%s%s"
 984 #ifdef MESA_GIT_SHA1
 985                  " (" MESA_GIT_SHA1 ")"
 986 #endif
 987                  , log_prefix, PACKAGE_VERSION);
 988    svga_host_log(host_log);
 989
 990    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 991     * line (program name and arguments).
 992     */
 993    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 994       char cmdline[1000];
 995       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 996          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 997                        "%s%s", log_prefix, cmdline);
 998          svga_host_log(host_log);
 999       }
1000    }
1001 }
1002
1003
1004 static void
1005 svga_destroy_screen( struct pipe_screen *screen )
1006 {
1007    struct svga_screen *svgascreen = svga_screen(screen);
1008
1009    svga_screen_cache_cleanup(svgascreen);
1010
1011    mtx_destroy(&svgascreen->swc_mutex);
1012    mtx_destroy(&svgascreen->tex_mutex);
1013
1014    svgascreen->sws->destroy(svgascreen->sws);
1015
1016    FREE(svgascreen);
1017 }
1018
1019
1020 /**
1021  * Create a new svga_screen object
1022  */
1023 struct pipe_screen *
1024 svga_screen_create(struct svga_winsys_screen *sws)
1025 {
1026    struct svga_screen *svgascreen;
1027    struct pipe_screen *screen;
1028
1029 #ifdef DEBUG
1030    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
1031 #endif
1032
1033    svgascreen = CALLOC_STRUCT(svga_screen);
1034    if (!svgascreen)
1035       goto error1;
1036
1037    svgascreen->debug.force_level_surface_view =
1038       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
1039    svgascreen->debug.force_surface_view =
1040       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
1041    svgascreen->debug.force_sampler_view =
1042       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
1043    svgascreen->debug.no_surface_view =
1044       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
1045    svgascreen->debug.no_sampler_view =
1046       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
1047    svgascreen->debug.no_cache_index_buffers =
1048       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
1049
1050    screen = &svgascreen->screen;
1051
1052    screen->destroy = svga_destroy_screen;
1053    screen->get_name = svga_get_name;
1054    screen->get_vendor = svga_get_vendor;
1055    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
1056    screen->get_param = svga_get_param;
1057    screen->get_shader_param = svga_get_shader_param;
1058    screen->get_paramf = svga_get_paramf;
1059    screen->get_timestamp = NULL;
1060    screen->is_format_supported = svga_is_format_supported;
1061    screen->context_create = svga_context_create;
1062    screen->fence_reference = svga_fence_reference;
1063    screen->fence_finish = svga_fence_finish;
1064    screen->fence_get_fd = svga_fence_get_fd;
1065
1066    screen->get_driver_query_info = svga_get_driver_query_info;
1067    svgascreen->sws = sws;
1068
1069    svga_init_screen_resource_functions(svgascreen);
1070
1071    if (sws->get_hw_version) {
1072       svgascreen->hw_version = sws->get_hw_version(sws);
1073    } else {
1074       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
1075    }
1076
1077    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
1078       /* too old for 3D acceleration */
1079       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1080                    svgascreen->hw_version);
1081       goto error2;
1082    }
1083
1084    /*
1085     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1086     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1087     * we prefer the later when available.
1088     *
1089     * This mimics hardware vendors extensions for D3D depth sampling. See also
1090     * http://aras-p.info/texts/D3D9GPUHacks.html
1091     */
1092
1093    {
1094       boolean has_df16, has_df24, has_d24s8_int;
1095       SVGA3dSurfaceFormatCaps caps;
1096       SVGA3dSurfaceFormatCaps mask;
1097       mask.value = 0;
1098       mask.zStencil = 1;
1099       mask.texture = 1;
1100
1101       svgascreen->depth.z16 = SVGA3D_Z_D16;
1102       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1103       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1104
1105       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1106       has_df16 = (caps.value & mask.value) == mask.value;
1107
1108       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1109       has_df24 = (caps.value & mask.value) == mask.value;
1110
1111       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1112       has_d24s8_int = (caps.value & mask.value) == mask.value;
1113
1114       /* XXX: We might want some other logic here.
1115        * Like if we only have d24s8_int we should
1116        * emulate the other formats with that.
1117        */
1118       if (has_df16) {
1119          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1120       }
1121       if (has_df24) {
1122          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1123       }
1124       if (has_d24s8_int) {
1125          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1126       }
1127    }
1128
1129    /* Query device caps
1130     */
1131    if (sws->have_vgpu10) {
1132       svgascreen->haveProvokingVertex
1133          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1134       svgascreen->haveLineSmooth = TRUE;
1135       svgascreen->maxPointSize = 80.0F;
1136       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1137
1138       /* Multisample samples per pixel */
1139       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1140          svgascreen->ms_samples =
1141             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1142       }
1143
1144       /* We only support 4x, 8x, 16x MSAA */
1145       svgascreen->ms_samples &= ((1 << (4-1)) |
1146                                  (1 << (8-1)) |
1147                                  (1 << (16-1)));
1148
1149       /* Maximum number of constant buffers */
1150       svgascreen->max_const_buffers =
1151          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1152       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1153    }
1154    else {
1155       /* VGPU9 */
1156       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1157                                      SVGA3DVSVERSION_NONE);
1158       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1159                                      SVGA3DPSVERSION_NONE);
1160
1161       /* we require Shader model 3.0 or later */
1162       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1163          goto error2;
1164       }
1165
1166       svgascreen->haveProvokingVertex = FALSE;
1167
1168       svgascreen->haveLineSmooth =
1169          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1170
1171       svgascreen->maxPointSize =
1172          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1173       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1174       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1175
1176       /* The SVGA3D device always supports 4 targets at this time, regardless
1177        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1178        */
1179       svgascreen->max_color_buffers = 4;
1180
1181       /* Only support one constant buffer
1182        */
1183       svgascreen->max_const_buffers = 1;
1184
1185       /* No multisampling */
1186       svgascreen->ms_samples = 0;
1187    }
1188
1189    /* common VGPU9 / VGPU10 caps */
1190    svgascreen->haveLineStipple =
1191       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1192
1193    svgascreen->maxLineWidth =
1194       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1195
1196    svgascreen->maxLineWidthAA =
1197       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1198
1199    if (0) {
1200       debug_printf("svga: haveProvokingVertex %u\n",
1201                    svgascreen->haveProvokingVertex);
1202       debug_printf("svga: haveLineStip %u  "
1203                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1204                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1205                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1206       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1207       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1208    }
1209
1210    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1211    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1212
1213    svga_screen_cache_init(svgascreen);
1214
1215    init_logging(screen);
1216
1217    return screen;
1218 error2:
1219    FREE(svgascreen);
1220 error1:
1221    return NULL;
1222 }
1223
1224
1225 struct svga_winsys_screen *
1226 svga_winsys_screen(struct pipe_screen *screen)
1227 {
1228    return svga_screen(screen)->sws;
1229 }
1230
1231
1232 #ifdef DEBUG
1233 struct svga_screen *
1234 svga_screen(struct pipe_screen *screen)
1235 {
1236    assert(screen);
1237    assert(screen->destroy == svga_destroy_screen);
1238    return (struct svga_screen *)screen;
1239 }
1240 #endif