src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifndef MESA_GIT_SHA1
  53 #define MESA_GIT_SHA1 "(unknown git revision)"
  54 #endif
  55
  56 #ifdef DEBUG
  57 int SVGA_DEBUG = 0;
  58
  59 static const struct debug_named_value svga_debug_flags[] = {
  60    { "dma",         DEBUG_DMA, NULL },
  61    { "tgsi",        DEBUG_TGSI, NULL },
  62    { "pipe",        DEBUG_PIPE, NULL },
  63    { "state",       DEBUG_STATE, NULL },
  64    { "screen",      DEBUG_SCREEN, NULL },
  65    { "tex",         DEBUG_TEX, NULL },
  66    { "swtnl",       DEBUG_SWTNL, NULL },
  67    { "const",       DEBUG_CONSTS, NULL },
  68    { "viewport",    DEBUG_VIEWPORT, NULL },
  69    { "views",       DEBUG_VIEWS, NULL },
  70    { "perf",        DEBUG_PERF, NULL },
  71    { "flush",       DEBUG_FLUSH, NULL },
  72    { "sync",        DEBUG_SYNC, NULL },
  73    { "cache",       DEBUG_CACHE, NULL },
  74    { "streamout",   DEBUG_STREAMOUT, NULL },
  75    { "query",       DEBUG_QUERY, NULL },
  76    { "samplers",    DEBUG_SAMPLERS, NULL },
  77    DEBUG_NAMED_VALUE_END
  78 };
  79 #endif
  80
  81 static const char *
  82 svga_get_vendor( struct pipe_screen *pscreen )
  83 {
  84    return "VMware, Inc.";
  85 }
  86
  87
  88 static const char *
  89 svga_get_name( struct pipe_screen *pscreen )
  90 {
  91    const char *build = "", *llvm = "", *mutex = "";
  92    static char name[100];
  93 #ifdef DEBUG
  94    /* Only return internal details in the DEBUG version:
  95     */
  96    build = "build: DEBUG;";
  97    mutex = "mutex: " PIPE_ATOMIC ";";
  98 #elif defined(VMX86_STATS)
  99    build = "build: OPT;";
 100 #else
 101    build = "build: RELEASE;";
 102 #endif
 103 #ifdef HAVE_LLVM
 104    llvm = "LLVM;";
 105 #endif
 106
 107    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 108    return name;
 109 }
 110
 111
 112 /** Helper for querying float-valued device cap */
 113 static float
 114 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 115 {
 116    SVGA3dDevCapResult result;
 117    if (sws->get_cap(sws, cap, &result))
 118       return result.f;
 119    else
 120       return defaultVal;
 121 }
 122
 123
 124 /** Helper for querying uint-valued device cap */
 125 static unsigned
 126 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 127 {
 128    SVGA3dDevCapResult result;
 129    if (sws->get_cap(sws, cap, &result))
 130       return result.u;
 131    else
 132       return defaultVal;
 133 }
 134
 135
 136 /** Helper for querying boolean-valued device cap */
 137 static boolean
 138 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 139 {
 140    SVGA3dDevCapResult result;
 141    if (sws->get_cap(sws, cap, &result))
 142       return result.b;
 143    else
 144       return defaultVal;
 145 }
 146
 147
 148 static float
 149 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 150 {
 151    struct svga_screen *svgascreen = svga_screen(screen);
 152    struct svga_winsys_screen *sws = svgascreen->sws;
 153
 154    switch (param) {
 155    case PIPE_CAPF_MAX_LINE_WIDTH:
 156       return svgascreen->maxLineWidth;
 157    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 158       return svgascreen->maxLineWidthAA;
 159
 160    case PIPE_CAPF_MAX_POINT_WIDTH:
 161       /* fall-through */
 162    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 163       return svgascreen->maxPointSize;
 164
 165    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 166       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 167
 168    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 169       return 15.0;
 170
 171    case PIPE_CAPF_GUARD_BAND_LEFT:
 172    case PIPE_CAPF_GUARD_BAND_TOP:
 173    case PIPE_CAPF_GUARD_BAND_RIGHT:
 174    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 175       return 0.0;
 176    }
 177
 178    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 179    return 0;
 180 }
 181
 182
 183 static int
 184 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 185 {
 186    struct svga_screen *svgascreen = svga_screen(screen);
 187    struct svga_winsys_screen *sws = svgascreen->sws;
 188    SVGA3dDevCapResult result;
 189
 190    switch (param) {
 191    case PIPE_CAP_NPOT_TEXTURES:
 192    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 193    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 194       return 1;
 195    case PIPE_CAP_TWO_SIDED_STENCIL:
 196       return 1;
 197    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 198       /*
 199        * "In virtually every OpenGL implementation and hardware,
 200        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 201        * http://www.opengl.org/wiki/Blending
 202        */
 203       return sws->have_vgpu10 ? 1 : 0;
 204    case PIPE_CAP_ANISOTROPIC_FILTER:
 205       return 1;
 206    case PIPE_CAP_POINT_SPRITE:
 207       return 1;
 208    case PIPE_CAP_TGSI_TEXCOORD:
 209       return 0;
 210    case PIPE_CAP_MAX_RENDER_TARGETS:
 211       return svgascreen->max_color_buffers;
 212    case PIPE_CAP_OCCLUSION_QUERY:
 213       return 1;
 214    case PIPE_CAP_QUERY_TIME_ELAPSED:
 215       return 0;
 216    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 217       return sws->have_vgpu10;
 218    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 219       return 1;
 220    case PIPE_CAP_TEXTURE_SWIZZLE:
 221       return 1;
 222    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 223       return 0;
 224    case PIPE_CAP_USER_VERTEX_BUFFERS:
 225       return 0;
 226    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 227       return 1;
 228    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 229       return 256;
 230
 231    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 232       {
 233          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 234          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 235             levels = MIN2(util_logbase2(result.u) + 1, levels);
 236          else
 237             levels = 12 /* 2048x2048 */;
 238          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 239             levels = MIN2(util_logbase2(result.u) + 1, levels);
 240          else
 241             levels = 12 /* 2048x2048 */;
 242          return levels;
 243       }
 244
 245    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 246       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 247          return 8;  /* max 128x128x128 */
 248       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 249
 250    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 251       /*
 252        * No mechanism to query the host, and at least limited to 2048x2048 on
 253        * certain hardware.
 254        */
 255       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 256                   12 /* 2048x2048 */);
 257
 258    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 259       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 260
 261    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 262       return 1;
 263
 264    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 265       return 1;
 266    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 267       return sws->have_vgpu10;
 268    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 269       return 0;
 270    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 271       return !sws->have_vgpu10;
 272
 273    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 274       return 1; /* The color outputs of vertex shaders are not clamped */
 275    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 276       return 0; /* The driver can't clamp vertex colors */
 277    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 278       return 0; /* The driver can't clamp fragment colors */
 279
 280    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 281       return 1; /* expected for GL_ARB_framebuffer_object */
 282
 283    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 284       return sws->have_vgpu10 ? 330 : 120;
 285
 286    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 287       return 0;
 288
 289    case PIPE_CAP_SM3:
 290       return 1;
 291
 292    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 293    case PIPE_CAP_INDEP_BLEND_ENABLE:
 294    case PIPE_CAP_CONDITIONAL_RENDER:
 295    case PIPE_CAP_QUERY_TIMESTAMP:
 296    case PIPE_CAP_TGSI_INSTANCEID:
 297    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 298    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 299    case PIPE_CAP_FAKE_SW_MSAA:
 300       return sws->have_vgpu10;
 301
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 303       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 304    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 305       return sws->have_vgpu10 ? 4 : 0;
 306    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 307       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 308    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 309    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 310       return 0;
 311    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 312       return svgascreen->ms_samples ? 1 : 0;
 313
 314    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 315       /* convert bytes to texels for the case of the largest texel
 316        * size: float[4].
 317        */
 318       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 319
 320    case PIPE_CAP_MIN_TEXEL_OFFSET:
 321       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 322    case PIPE_CAP_MAX_TEXEL_OFFSET:
 323       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 324
 325    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 326    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 327       return 0;
 328
 329    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 330       return sws->have_vgpu10 ? 256 : 0;
 331    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 332       return sws->have_vgpu10 ? 1024 : 0;
 333
 334    case PIPE_CAP_PRIMITIVE_RESTART:
 335       return 1; /* may be a sw fallback, depending on restart index */
 336
 337    case PIPE_CAP_GENERATE_MIPMAP:
 338       return sws->have_generate_mipmap_cmd;
 339
 340    case PIPE_CAP_NATIVE_FENCE_FD:
 341       return sws->have_fence_fd;
 342
 343    /* Unsupported features */
 344    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 345    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 346    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 347    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 348    case PIPE_CAP_INDEP_BLEND_FUNC:
 349    case PIPE_CAP_TEXTURE_BARRIER:
 350    case PIPE_CAP_MAX_VERTEX_STREAMS:
 351    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 352    case PIPE_CAP_COMPUTE:
 353    case PIPE_CAP_START_INSTANCE:
 354    case PIPE_CAP_CUBE_MAP_ARRAY:
 355    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 356    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 358    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 359    case PIPE_CAP_TEXTURE_GATHER_SM5:
 360    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 361    case PIPE_CAP_TEXTURE_QUERY_LOD:
 362    case PIPE_CAP_SAMPLE_SHADING:
 363    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 364    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 365    case PIPE_CAP_DRAW_INDIRECT:
 366    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 367    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 368    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 369    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 370    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 371    case PIPE_CAP_CLIP_HALFZ:
 372    case PIPE_CAP_VERTEXID_NOBASE:
 373    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 374    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 375    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 376    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 377    case PIPE_CAP_INVALIDATE_BUFFER:
 378    case PIPE_CAP_STRING_MARKER:
 379    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 380    case PIPE_CAP_QUERY_MEMORY_INFO:
 381    case PIPE_CAP_PCI_GROUP:
 382    case PIPE_CAP_PCI_BUS:
 383    case PIPE_CAP_PCI_DEVICE:
 384    case PIPE_CAP_PCI_FUNCTION:
 385    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 386       return 0;
 387    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 388       return 64;
 389    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 390    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 391    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 392       return 1;  /* need 4-byte alignment for all offsets and strides */
 393    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 394       return 2048;
 395    case PIPE_CAP_MAX_VIEWPORTS:
 396       return 1;
 397    case PIPE_CAP_ENDIANNESS:
 398       return PIPE_ENDIAN_LITTLE;
 399
 400    case PIPE_CAP_VENDOR_ID:
 401       return 0x15ad; /* VMware Inc. */
 402    case PIPE_CAP_DEVICE_ID:
 403       return 0x0405; /* assume SVGA II */
 404    case PIPE_CAP_ACCELERATED:
 405       return 0; /* XXX: */
 406    case PIPE_CAP_VIDEO_MEMORY:
 407       /* XXX: Query the host ? */
 408       return 1;
 409    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 410       return sws->have_vgpu10;
 411    case PIPE_CAP_CLEAR_TEXTURE:
 412       return sws->have_vgpu10;
 413    case PIPE_CAP_UMA:
 414    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 415    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 416    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 417    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 418    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 419    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 420    case PIPE_CAP_TGSI_TXQS:
 421    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 422    case PIPE_CAP_SHAREABLE_SHADERS:
 423    case PIPE_CAP_DRAW_PARAMETERS:
 424    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 425    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 426    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 427    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 428    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 429    case PIPE_CAP_CULL_DISTANCE:
 430    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 431    case PIPE_CAP_TGSI_VOTE:
 432    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 433    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 434    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 435    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 436    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 437    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 438    case PIPE_CAP_TGSI_FS_FBFETCH:
 439    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 440    case PIPE_CAP_DOUBLES:
 441    case PIPE_CAP_INT64:
 442    case PIPE_CAP_INT64_DIVMOD:
 443    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 444    case PIPE_CAP_TGSI_CLOCK:
 445    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 446    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 447    case PIPE_CAP_TGSI_BALLOT:
 448    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 449    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 450    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 451    case PIPE_CAP_POST_DEPTH_COVERAGE:
 452    case PIPE_CAP_BINDLESS_TEXTURE:
 453    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 454       return 0;
 455    }
 456
 457    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 458    return 0;
 459 }
 460
 461
 462 static int
 463 vgpu9_get_shader_param(struct pipe_screen *screen,
 464                        enum pipe_shader_type shader,
 465                        enum pipe_shader_cap param)
 466 {
 467    struct svga_screen *svgascreen = svga_screen(screen);
 468    struct svga_winsys_screen *sws = svgascreen->sws;
 469    unsigned val;
 470
 471    assert(!sws->have_vgpu10);
 472
 473    switch (shader)
 474    {
 475    case PIPE_SHADER_FRAGMENT:
 476       switch (param)
 477       {
 478       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 479       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 480          return get_uint_cap(sws,
 481                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 482                              512);
 483       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 484       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 485          return 512;
 486       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 487          return SVGA3D_MAX_NESTING_LEVEL;
 488       case PIPE_SHADER_CAP_MAX_INPUTS:
 489          return 10;
 490       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 491          return svgascreen->max_color_buffers;
 492       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 493          return 224 * sizeof(float[4]);
 494       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 495          return 1;
 496       case PIPE_SHADER_CAP_MAX_TEMPS:
 497          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 498          return MIN2(val, SVGA3D_TEMPREG_MAX);
 499       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 500          /*
 501           * Although PS 3.0 has some addressing abilities it can only represent
 502           * loops that can be statically determined and unrolled. Given we can
 503           * only handle a subset of the cases that the state tracker already
 504           * does it is better to defer loop unrolling to the state tracker.
 505           */
 506          return 0;
 507       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 508          return 0;
 509       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 510          return 0;
 511       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 512       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 513       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 514          return 0;
 515       case PIPE_SHADER_CAP_SUBROUTINES:
 516          return 0;
 517       case PIPE_SHADER_CAP_INTEGERS:
 518          return 0;
 519       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 520       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 521          return 16;
 522       case PIPE_SHADER_CAP_PREFERRED_IR:
 523          return PIPE_SHADER_IR_TGSI;
 524       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 525          return 0;
 526       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 527       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 528       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 529       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 530       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 531       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 532       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 533       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 534          return 0;
 535       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 536          return 32;
 537       }
 538       /* If we get here, we failed to handle a cap above */
 539       debug_printf("Unexpected fragment shader query %u\n", param);
 540       return 0;
 541    case PIPE_SHADER_VERTEX:
 542       switch (param)
 543       {
 544       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 545       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 546          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 547                              512);
 548       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 549       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 550          /* XXX: until we have vertex texture support */
 551          return 0;
 552       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 553          return SVGA3D_MAX_NESTING_LEVEL;
 554       case PIPE_SHADER_CAP_MAX_INPUTS:
 555          return 16;
 556       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 557          return 10;
 558       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 559          return 256 * sizeof(float[4]);
 560       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 561          return 1;
 562       case PIPE_SHADER_CAP_MAX_TEMPS:
 563          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 564          return MIN2(val, SVGA3D_TEMPREG_MAX);
 565       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 566          return 0;
 567       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 568          return 0;
 569       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 570       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 571          return 1;
 572       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 573          return 0;
 574       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 575          return 1;
 576       case PIPE_SHADER_CAP_SUBROUTINES:
 577          return 0;
 578       case PIPE_SHADER_CAP_INTEGERS:
 579          return 0;
 580       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 581       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 582          return 0;
 583       case PIPE_SHADER_CAP_PREFERRED_IR:
 584          return PIPE_SHADER_IR_TGSI;
 585       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 586          return 0;
 587       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 588       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 589       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 590       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 591       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 592       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 593       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 594       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 595          return 0;
 596       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 597          return 32;
 598       }
 599       /* If we get here, we failed to handle a cap above */
 600       debug_printf("Unexpected vertex shader query %u\n", param);
 601       return 0;
 602    case PIPE_SHADER_GEOMETRY:
 603    case PIPE_SHADER_COMPUTE:
 604    case PIPE_SHADER_TESS_CTRL:
 605    case PIPE_SHADER_TESS_EVAL:
 606       /* no support for geometry, tess or compute shaders at this time */
 607       return 0;
 608    default:
 609       debug_printf("Unexpected shader type (%u) query\n", shader);
 610       return 0;
 611    }
 612    return 0;
 613 }
 614
 615
 616 static int
 617 vgpu10_get_shader_param(struct pipe_screen *screen,
 618                         enum pipe_shader_type shader,
 619                         enum pipe_shader_cap param)
 620 {
 621    struct svga_screen *svgascreen = svga_screen(screen);
 622    struct svga_winsys_screen *sws = svgascreen->sws;
 623
 624    assert(sws->have_vgpu10);
 625    (void) sws;  /* silence unused var warnings in non-debug builds */
 626
 627    /* Only VS, GS, FS supported */
 628    if (shader != PIPE_SHADER_VERTEX &&
 629        shader != PIPE_SHADER_GEOMETRY &&
 630        shader != PIPE_SHADER_FRAGMENT) {
 631       return 0;
 632    }
 633
 634    /* NOTE: we do not query the device for any caps/limits at this time */
 635
 636    /* Generally the same limits for vertex, geometry and fragment shaders */
 637    switch (param) {
 638    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 639    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 640    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 641    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 642       return 64 * 1024;
 643    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 644       return 64;
 645    case PIPE_SHADER_CAP_MAX_INPUTS:
 646       if (shader == PIPE_SHADER_FRAGMENT)
 647          return VGPU10_MAX_FS_INPUTS;
 648       else if (shader == PIPE_SHADER_GEOMETRY)
 649          return VGPU10_MAX_GS_INPUTS;
 650       else
 651          return VGPU10_MAX_VS_INPUTS;
 652    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 653       if (shader == PIPE_SHADER_FRAGMENT)
 654          return VGPU10_MAX_FS_OUTPUTS;
 655       else if (shader == PIPE_SHADER_GEOMETRY)
 656          return VGPU10_MAX_GS_OUTPUTS;
 657       else
 658          return VGPU10_MAX_VS_OUTPUTS;
 659    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 660       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 661    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 662       return svgascreen->max_const_buffers;
 663    case PIPE_SHADER_CAP_MAX_TEMPS:
 664       return VGPU10_MAX_TEMPS;
 665    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 666    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 667    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 668    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 669       return TRUE; /* XXX verify */
 670    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 671    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 672    case PIPE_SHADER_CAP_SUBROUTINES:
 673    case PIPE_SHADER_CAP_INTEGERS:
 674       return TRUE;
 675    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 676    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 677       return SVGA3D_DX_MAX_SAMPLERS;
 678    case PIPE_SHADER_CAP_PREFERRED_IR:
 679       return PIPE_SHADER_IR_TGSI;
 680    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 681          return 0;
 682    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 683    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 684    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 685    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 686    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 687    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 688    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 689    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 690       return 0;
 691    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 692       return 32;
 693    default:
 694       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 695       return 0;
 696    }
 697    return 0;
 698 }
 699
 700
 701 static int
 702 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 703                       enum pipe_shader_cap param)
 704 {
 705    struct svga_screen *svgascreen = svga_screen(screen);
 706    struct svga_winsys_screen *sws = svgascreen->sws;
 707    if (sws->have_vgpu10) {
 708       return vgpu10_get_shader_param(screen, shader, param);
 709    }
 710    else {
 711       return vgpu9_get_shader_param(screen, shader, param);
 712    }
 713 }
 714
 715
 716 /**
 717  * Implement pipe_screen::is_format_supported().
 718  * \param bindings  bitmask of PIPE_BIND_x flags
 719  */
 720 static boolean
 721 svga_is_format_supported( struct pipe_screen *screen,
 722                           enum pipe_format format,
 723                           enum pipe_texture_target target,
 724                           unsigned sample_count,
 725                           unsigned bindings)
 726 {
 727    struct svga_screen *ss = svga_screen(screen);
 728    SVGA3dSurfaceFormat svga_format;
 729    SVGA3dSurfaceFormatCaps caps;
 730    SVGA3dSurfaceFormatCaps mask;
 731
 732    assert(bindings);
 733
 734    if (sample_count > 1) {
 735       /* In ms_samples, if bit N is set it means that we support
 736        * multisample with N+1 samples per pixel.
 737        */
 738       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 739          return FALSE;
 740       }
 741    }
 742
 743    svga_format = svga_translate_format(ss, format, bindings);
 744    if (svga_format == SVGA3D_FORMAT_INVALID) {
 745       return FALSE;
 746    }
 747
 748    /* we don't support sRGB rendering into display targets */
 749    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 750       return FALSE;
 751    }
 752
 753    /*
 754     * For VGPU10 vertex formats, skip querying host capabilities
 755     */
 756
 757    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 758       SVGA3dSurfaceFormat svga_format;
 759       unsigned flags;
 760       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 761       return svga_format != SVGA3D_FORMAT_INVALID;
 762    }
 763
 764    /*
 765     * Override host capabilities, so that we end up with the same
 766     * visuals for all virtual hardware implementations.
 767     */
 768
 769    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 770       switch (svga_format) {
 771       case SVGA3D_A8R8G8B8:
 772       case SVGA3D_X8R8G8B8:
 773       case SVGA3D_R5G6B5:
 774          break;
 775
 776       /* VGPU10 formats */
 777       case SVGA3D_B8G8R8A8_UNORM:
 778       case SVGA3D_B8G8R8X8_UNORM:
 779       case SVGA3D_B5G6R5_UNORM:
 780          break;
 781
 782       /* Often unsupported/problematic. This means we end up with the same
 783        * visuals for all virtual hardware implementations.
 784        */
 785       case SVGA3D_A4R4G4B4:
 786       case SVGA3D_A1R5G5B5:
 787          return FALSE;
 788
 789       default:
 790          return FALSE;
 791       }
 792    }
 793
 794    /*
 795     * Query the host capabilities.
 796     */
 797
 798    svga_get_format_cap(ss, svga_format, &caps);
 799
 800    if (bindings & PIPE_BIND_RENDER_TARGET) {
 801       /* Check that the color surface is blendable, unless it's an
 802        * integer format.
 803        */
 804       if (!svga_format_is_integer(svga_format) &&
 805           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 806          return FALSE;
 807       }
 808    }
 809
 810    mask.value = 0;
 811    if (bindings & PIPE_BIND_RENDER_TARGET) {
 812       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 813    }
 814    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 815       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 816    }
 817    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 818       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 819    }
 820
 821    if (target == PIPE_TEXTURE_CUBE) {
 822       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 823    }
 824    else if (target == PIPE_TEXTURE_3D) {
 825       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 826    }
 827
 828    return (caps.value & mask.value) == mask.value;
 829 }
 830
 831
 832 static void
 833 svga_fence_reference(struct pipe_screen *screen,
 834                      struct pipe_fence_handle **ptr,
 835                      struct pipe_fence_handle *fence)
 836 {
 837    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 838    sws->fence_reference(sws, ptr, fence);
 839 }
 840
 841
 842 static boolean
 843 svga_fence_finish(struct pipe_screen *screen,
 844                   struct pipe_context *ctx,
 845                   struct pipe_fence_handle *fence,
 846                   uint64_t timeout)
 847 {
 848    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 849    boolean retVal;
 850
 851    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 852
 853    if (!timeout) {
 854       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 855    }
 856    else {
 857       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 858                __FUNCTION__, fence);
 859
 860       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 861    }
 862
 863    SVGA_STATS_TIME_POP(sws);
 864
 865    return retVal;
 866 }
 867
 868
 869 static int
 870 svga_fence_get_fd(struct pipe_screen *screen,
 871                   struct pipe_fence_handle *fence)
 872 {
 873    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 874
 875    return sws->fence_get_fd(sws, fence, TRUE);
 876 }
 877
 878
 879 static int
 880 svga_get_driver_query_info(struct pipe_screen *screen,
 881                            unsigned index,
 882                            struct pipe_driver_query_info *info)
 883 {
 884 #define QUERY(NAME, ENUM, UNITS) \
 885    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 886
 887    static const struct pipe_driver_query_info queries[] = {
 888       /* per-frame counters */
 889       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 890             PIPE_DRIVER_QUERY_TYPE_UINT64),
 891       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 892             PIPE_DRIVER_QUERY_TYPE_UINT64),
 893       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 894             PIPE_DRIVER_QUERY_TYPE_UINT64),
 895       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 896             PIPE_DRIVER_QUERY_TYPE_UINT64),
 897       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 898             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 899       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 900             PIPE_DRIVER_QUERY_TYPE_UINT64),
 901       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 902             PIPE_DRIVER_QUERY_TYPE_UINT64),
 903       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 904             PIPE_DRIVER_QUERY_TYPE_BYTES),
 905       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 906             PIPE_DRIVER_QUERY_TYPE_BYTES),
 907       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 908             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 909       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 910             PIPE_DRIVER_QUERY_TYPE_UINT64),
 911       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 912             PIPE_DRIVER_QUERY_TYPE_UINT64),
 913       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 914             PIPE_DRIVER_QUERY_TYPE_UINT64),
 915       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 916             PIPE_DRIVER_QUERY_TYPE_UINT64),
 917       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 918             PIPE_DRIVER_QUERY_TYPE_UINT64),
 919       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 920             PIPE_DRIVER_QUERY_TYPE_UINT64),
 921
 922       /* running total counters */
 923       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 924             PIPE_DRIVER_QUERY_TYPE_BYTES),
 925       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 926             PIPE_DRIVER_QUERY_TYPE_UINT64),
 927       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 928             PIPE_DRIVER_QUERY_TYPE_UINT64),
 929       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 930             PIPE_DRIVER_QUERY_TYPE_UINT64),
 931       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 932             PIPE_DRIVER_QUERY_TYPE_UINT64),
 933       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 934             PIPE_DRIVER_QUERY_TYPE_UINT64),
 935       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 936             PIPE_DRIVER_QUERY_TYPE_UINT64),
 937    };
 938 #undef QUERY
 939
 940    if (!info)
 941       return ARRAY_SIZE(queries);
 942
 943    if (index >= ARRAY_SIZE(queries))
 944       return 0;
 945
 946    *info = queries[index];
 947    return 1;
 948 }
 949
 950
 951 static void
 952 init_logging(struct pipe_screen *screen)
 953 {
 954    static const char *log_prefix = "Mesa: ";
 955    char host_log[1000];
 956
 957    /* Log Version to Host */
 958    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 959                  "%s%s", log_prefix, svga_get_name(screen));
 960    svga_host_log(host_log);
 961
 962    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 963                  "%s%s (%s)", log_prefix, PACKAGE_VERSION, MESA_GIT_SHA1);
 964    svga_host_log(host_log);
 965
 966    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 967     * line (program name and arguments).
 968     */
 969    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 970       char cmdline[1000];
 971       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 972          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 973                        "%s%s", log_prefix, cmdline);
 974          svga_host_log(host_log);
 975       }
 976    }
 977 }
 978
 979
 980 static void
 981 svga_destroy_screen( struct pipe_screen *screen )
 982 {
 983    struct svga_screen *svgascreen = svga_screen(screen);
 984
 985    svga_screen_cache_cleanup(svgascreen);
 986
 987    mtx_destroy(&svgascreen->swc_mutex);
 988    mtx_destroy(&svgascreen->tex_mutex);
 989
 990    svgascreen->sws->destroy(svgascreen->sws);
 991
 992    FREE(svgascreen);
 993 }
 994
 995
 996 /**
 997  * Create a new svga_screen object
 998  */
 999 struct pipe_screen *
1000 svga_screen_create(struct svga_winsys_screen *sws)
1001 {
1002    struct svga_screen *svgascreen;
1003    struct pipe_screen *screen;
1004
1005 #ifdef DEBUG
1006    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
1007 #endif
1008
1009    svgascreen = CALLOC_STRUCT(svga_screen);
1010    if (!svgascreen)
1011       goto error1;
1012
1013    svgascreen->debug.force_level_surface_view =
1014       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
1015    svgascreen->debug.force_surface_view =
1016       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
1017    svgascreen->debug.force_sampler_view =
1018       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
1019    svgascreen->debug.no_surface_view =
1020       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
1021    svgascreen->debug.no_sampler_view =
1022       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
1023    svgascreen->debug.no_cache_index_buffers =
1024       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
1025
1026    screen = &svgascreen->screen;
1027
1028    screen->destroy = svga_destroy_screen;
1029    screen->get_name = svga_get_name;
1030    screen->get_vendor = svga_get_vendor;
1031    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
1032    screen->get_param = svga_get_param;
1033    screen->get_shader_param = svga_get_shader_param;
1034    screen->get_paramf = svga_get_paramf;
1035    screen->get_timestamp = NULL;
1036    screen->is_format_supported = svga_is_format_supported;
1037    screen->context_create = svga_context_create;
1038    screen->fence_reference = svga_fence_reference;
1039    screen->fence_finish = svga_fence_finish;
1040    screen->fence_get_fd = svga_fence_get_fd;
1041
1042    screen->get_driver_query_info = svga_get_driver_query_info;
1043    svgascreen->sws = sws;
1044
1045    svga_init_screen_resource_functions(svgascreen);
1046
1047    if (sws->get_hw_version) {
1048       svgascreen->hw_version = sws->get_hw_version(sws);
1049    } else {
1050       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
1051    }
1052
1053    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
1054       /* too old for 3D acceleration */
1055       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1056                    svgascreen->hw_version);
1057       goto error2;
1058    }
1059
1060    /*
1061     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1062     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1063     * we prefer the later when available.
1064     *
1065     * This mimics hardware vendors extensions for D3D depth sampling. See also
1066     * http://aras-p.info/texts/D3D9GPUHacks.html
1067     */
1068
1069    {
1070       boolean has_df16, has_df24, has_d24s8_int;
1071       SVGA3dSurfaceFormatCaps caps;
1072       SVGA3dSurfaceFormatCaps mask;
1073       mask.value = 0;
1074       mask.zStencil = 1;
1075       mask.texture = 1;
1076
1077       svgascreen->depth.z16 = SVGA3D_Z_D16;
1078       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1079       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1080
1081       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1082       has_df16 = (caps.value & mask.value) == mask.value;
1083
1084       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1085       has_df24 = (caps.value & mask.value) == mask.value;
1086
1087       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1088       has_d24s8_int = (caps.value & mask.value) == mask.value;
1089
1090       /* XXX: We might want some other logic here.
1091        * Like if we only have d24s8_int we should
1092        * emulate the other formats with that.
1093        */
1094       if (has_df16) {
1095          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1096       }
1097       if (has_df24) {
1098          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1099       }
1100       if (has_d24s8_int) {
1101          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1102       }
1103    }
1104
1105    /* Query device caps
1106     */
1107    if (sws->have_vgpu10) {
1108       svgascreen->haveProvokingVertex
1109          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1110       svgascreen->haveLineSmooth = TRUE;
1111       svgascreen->maxPointSize = 80.0F;
1112       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1113
1114       /* Multisample samples per pixel */
1115       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1116          svgascreen->ms_samples =
1117             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1118       }
1119
1120       /* We only support 4x, 8x, 16x MSAA */
1121       svgascreen->ms_samples &= ((1 << (4-1)) |
1122                                  (1 << (8-1)) |
1123                                  (1 << (16-1)));
1124
1125       /* Maximum number of constant buffers */
1126       svgascreen->max_const_buffers =
1127          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1128       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1129    }
1130    else {
1131       /* VGPU9 */
1132       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1133                                      SVGA3DVSVERSION_NONE);
1134       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1135                                      SVGA3DPSVERSION_NONE);
1136
1137       /* we require Shader model 3.0 or later */
1138       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1139          goto error2;
1140       }
1141
1142       svgascreen->haveProvokingVertex = FALSE;
1143
1144       svgascreen->haveLineSmooth =
1145          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1146
1147       svgascreen->maxPointSize =
1148          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1149       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1150       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1151
1152       /* The SVGA3D device always supports 4 targets at this time, regardless
1153        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1154        */
1155       svgascreen->max_color_buffers = 4;
1156
1157       /* Only support one constant buffer
1158        */
1159       svgascreen->max_const_buffers = 1;
1160
1161       /* No multisampling */
1162       svgascreen->ms_samples = 0;
1163    }
1164
1165    /* common VGPU9 / VGPU10 caps */
1166    svgascreen->haveLineStipple =
1167       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1168
1169    svgascreen->maxLineWidth =
1170       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1171
1172    svgascreen->maxLineWidthAA =
1173       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1174
1175    if (0) {
1176       debug_printf("svga: haveProvokingVertex %u\n",
1177                    svgascreen->haveProvokingVertex);
1178       debug_printf("svga: haveLineStip %u  "
1179                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1180                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1181                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1182       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1183       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1184    }
1185
1186    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1187    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1188
1189    svga_screen_cache_init(svgascreen);
1190
1191    init_logging(screen);
1192
1193    return screen;
1194 error2:
1195    FREE(svgascreen);
1196 error1:
1197    return NULL;
1198 }
1199
1200 struct svga_winsys_screen *
1201 svga_winsys_screen(struct pipe_screen *screen)
1202 {
1203    return svga_screen(screen)->sws;
1204 }
1205
1206 #ifdef DEBUG
1207 struct svga_screen *
1208 svga_screen(struct pipe_screen *screen)
1209 {
1210    assert(screen);
1211    assert(screen->destroy == svga_destroy_screen);
1212    return (struct svga_screen *)screen;
1213 }
1214 #endif