src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "svga_winsys.h"
  34 #include "svga_public.h"
  35 #include "svga_context.h"
  36 #include "svga_format.h"
  37 #include "svga_screen.h"
  38 #include "svga_tgsi.h"
  39 #include "svga_resource_texture.h"
  40 #include "svga_resource.h"
  41 #include "svga_debug.h"
  42
  43 #include "svga3d_shaderdefs.h"
  44 #include "VGPU10ShaderTokens.h"
  45
  46 /* NOTE: this constant may get moved into a svga3d*.h header file */
  47 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  48
  49 #ifndef MESA_GIT_SHA1
  50 #define MESA_GIT_SHA1 "(unknown git revision)"
  51 #endif
  52
  53 #ifdef DEBUG
  54 int SVGA_DEBUG = 0;
  55
  56 static const struct debug_named_value svga_debug_flags[] = {
  57    { "dma",         DEBUG_DMA, NULL },
  58    { "tgsi",        DEBUG_TGSI, NULL },
  59    { "pipe",        DEBUG_PIPE, NULL },
  60    { "state",       DEBUG_STATE, NULL },
  61    { "screen",      DEBUG_SCREEN, NULL },
  62    { "tex",         DEBUG_TEX, NULL },
  63    { "swtnl",       DEBUG_SWTNL, NULL },
  64    { "const",       DEBUG_CONSTS, NULL },
  65    { "viewport",    DEBUG_VIEWPORT, NULL },
  66    { "views",       DEBUG_VIEWS, NULL },
  67    { "perf",        DEBUG_PERF, NULL },
  68    { "flush",       DEBUG_FLUSH, NULL },
  69    { "sync",        DEBUG_SYNC, NULL },
  70    { "cache",       DEBUG_CACHE, NULL },
  71    { "streamout",   DEBUG_STREAMOUT, NULL },
  72    { "query",       DEBUG_QUERY, NULL },
  73    { "samplers",    DEBUG_SAMPLERS, NULL },
  74    DEBUG_NAMED_VALUE_END
  75 };
  76 #endif
  77
  78 static const char *
  79 svga_get_vendor( struct pipe_screen *pscreen )
  80 {
  81    return "VMware, Inc.";
  82 }
  83
  84
  85 static const char *
  86 svga_get_name( struct pipe_screen *pscreen )
  87 {
  88    const char *build = "", *llvm = "", *mutex = "";
  89    static char name[100];
  90 #ifdef DEBUG
  91    /* Only return internal details in the DEBUG version:
  92     */
  93    build = "build: DEBUG;";
  94    mutex = "mutex: " PIPE_ATOMIC ";";
  95 #elif defined(VMX86_STATS)
  96    build = "build: OPT;";
  97 #else
  98    build = "build: RELEASE;";
  99 #endif
 100 #ifdef HAVE_LLVM
 101    llvm = "LLVM;";
 102 #endif
 103
 104    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 105    return name;
 106 }
 107
 108
 109 /** Helper for querying float-valued device cap */
 110 static float
 111 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 112 {
 113    SVGA3dDevCapResult result;
 114    if (sws->get_cap(sws, cap, &result))
 115       return result.f;
 116    else
 117       return defaultVal;
 118 }
 119
 120
 121 /** Helper for querying uint-valued device cap */
 122 static unsigned
 123 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 124 {
 125    SVGA3dDevCapResult result;
 126    if (sws->get_cap(sws, cap, &result))
 127       return result.u;
 128    else
 129       return defaultVal;
 130 }
 131
 132
 133 /** Helper for querying boolean-valued device cap */
 134 static boolean
 135 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 136 {
 137    SVGA3dDevCapResult result;
 138    if (sws->get_cap(sws, cap, &result))
 139       return result.b;
 140    else
 141       return defaultVal;
 142 }
 143
 144
 145 static float
 146 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 147 {
 148    struct svga_screen *svgascreen = svga_screen(screen);
 149    struct svga_winsys_screen *sws = svgascreen->sws;
 150
 151    switch (param) {
 152    case PIPE_CAPF_MAX_LINE_WIDTH:
 153       return svgascreen->maxLineWidth;
 154    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 155       return svgascreen->maxLineWidthAA;
 156
 157    case PIPE_CAPF_MAX_POINT_WIDTH:
 158       /* fall-through */
 159    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 160       return svgascreen->maxPointSize;
 161
 162    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 163       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 164
 165    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 166       return 15.0;
 167
 168    case PIPE_CAPF_GUARD_BAND_LEFT:
 169    case PIPE_CAPF_GUARD_BAND_TOP:
 170    case PIPE_CAPF_GUARD_BAND_RIGHT:
 171    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 172       return 0.0;
 173    }
 174
 175    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 176    return 0;
 177 }
 178
 179
 180 static int
 181 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 182 {
 183    struct svga_screen *svgascreen = svga_screen(screen);
 184    struct svga_winsys_screen *sws = svgascreen->sws;
 185    SVGA3dDevCapResult result;
 186
 187    switch (param) {
 188    case PIPE_CAP_NPOT_TEXTURES:
 189    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 190    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 191       return 1;
 192    case PIPE_CAP_TWO_SIDED_STENCIL:
 193       return 1;
 194    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 195       /*
 196        * "In virtually every OpenGL implementation and hardware,
 197        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 198        * http://www.opengl.org/wiki/Blending
 199        */
 200       return sws->have_vgpu10 ? 1 : 0;
 201    case PIPE_CAP_ANISOTROPIC_FILTER:
 202       return 1;
 203    case PIPE_CAP_POINT_SPRITE:
 204       return 1;
 205    case PIPE_CAP_TGSI_TEXCOORD:
 206       return 0;
 207    case PIPE_CAP_MAX_RENDER_TARGETS:
 208       return svgascreen->max_color_buffers;
 209    case PIPE_CAP_OCCLUSION_QUERY:
 210       return 1;
 211    case PIPE_CAP_QUERY_TIME_ELAPSED:
 212       return 0;
 213    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 214       return sws->have_vgpu10;
 215    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 216       return 1;
 217    case PIPE_CAP_TEXTURE_SWIZZLE:
 218       return 1;
 219    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 220       return 0;
 221    case PIPE_CAP_USER_VERTEX_BUFFERS:
 222       return 0;
 223    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 224       return 1;
 225    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 226       return 256;
 227
 228    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 229       {
 230          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 231          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 232             levels = MIN2(util_logbase2(result.u) + 1, levels);
 233          else
 234             levels = 12 /* 2048x2048 */;
 235          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 236             levels = MIN2(util_logbase2(result.u) + 1, levels);
 237          else
 238             levels = 12 /* 2048x2048 */;
 239          return levels;
 240       }
 241
 242    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 243       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 244          return 8;  /* max 128x128x128 */
 245       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 246
 247    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 248       /*
 249        * No mechanism to query the host, and at least limited to 2048x2048 on
 250        * certain hardware.
 251        */
 252       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 253                   12 /* 2048x2048 */);
 254
 255    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 256       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 257
 258    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 259       return 1;
 260
 261    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 262       return 1;
 263    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 264       return sws->have_vgpu10;
 265    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 266       return 0;
 267    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 268       return !sws->have_vgpu10;
 269
 270    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 271       return 1; /* The color outputs of vertex shaders are not clamped */
 272    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 273       return 0; /* The driver can't clamp vertex colors */
 274    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 275       return 0; /* The driver can't clamp fragment colors */
 276
 277    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 278       return 1; /* expected for GL_ARB_framebuffer_object */
 279
 280    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 281       return sws->have_vgpu10 ? 330 : 120;
 282
 283    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 284       return 0;
 285
 286    case PIPE_CAP_SM3:
 287       return 1;
 288
 289    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 290    case PIPE_CAP_INDEP_BLEND_ENABLE:
 291    case PIPE_CAP_CONDITIONAL_RENDER:
 292    case PIPE_CAP_QUERY_TIMESTAMP:
 293    case PIPE_CAP_TGSI_INSTANCEID:
 294    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 295    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 296    case PIPE_CAP_FAKE_SW_MSAA:
 297       return sws->have_vgpu10;
 298
 299    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 300       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 301    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 302       return sws->have_vgpu10 ? 4 : 0;
 303    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 304       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 305    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 306    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 307       return 0;
 308    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 309       return svgascreen->ms_samples ? 1 : 0;
 310
 311    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 312       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 313
 314    case PIPE_CAP_MIN_TEXEL_OFFSET:
 315       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 316    case PIPE_CAP_MAX_TEXEL_OFFSET:
 317       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 318
 319    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 320    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 321       return 0;
 322
 323    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 324       return sws->have_vgpu10 ? 256 : 0;
 325    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 326       return sws->have_vgpu10 ? 1024 : 0;
 327
 328    case PIPE_CAP_PRIMITIVE_RESTART:
 329       return 1; /* may be a sw fallback, depending on restart index */
 330
 331    case PIPE_CAP_GENERATE_MIPMAP:
 332       return sws->have_generate_mipmap_cmd;
 333
 334    /* Unsupported features */
 335    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 336    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 337    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 338    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 339    case PIPE_CAP_INDEP_BLEND_FUNC:
 340    case PIPE_CAP_TEXTURE_BARRIER:
 341    case PIPE_CAP_MAX_VERTEX_STREAMS:
 342    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 343    case PIPE_CAP_COMPUTE:
 344    case PIPE_CAP_START_INSTANCE:
 345    case PIPE_CAP_CUBE_MAP_ARRAY:
 346    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 347    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 348    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 349    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 350    case PIPE_CAP_TEXTURE_GATHER_SM5:
 351    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 352    case PIPE_CAP_TEXTURE_QUERY_LOD:
 353    case PIPE_CAP_SAMPLE_SHADING:
 354    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 355    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 356    case PIPE_CAP_DRAW_INDIRECT:
 357    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 358    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 359    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 360    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 361    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 362    case PIPE_CAP_CLIP_HALFZ:
 363    case PIPE_CAP_VERTEXID_NOBASE:
 364    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 365    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 366    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 367    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 368    case PIPE_CAP_INVALIDATE_BUFFER:
 369    case PIPE_CAP_STRING_MARKER:
 370    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 371    case PIPE_CAP_QUERY_MEMORY_INFO:
 372    case PIPE_CAP_PCI_GROUP:
 373    case PIPE_CAP_PCI_BUS:
 374    case PIPE_CAP_PCI_DEVICE:
 375    case PIPE_CAP_PCI_FUNCTION:
 376    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 377    case PIPE_CAP_NATIVE_FENCE_FD:
 378       return 0;
 379    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 380       return 64;
 381    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 382    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 383    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 384       return 1;  /* need 4-byte alignment for all offsets and strides */
 385    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 386       return 2048;
 387    case PIPE_CAP_MAX_VIEWPORTS:
 388       return 1;
 389    case PIPE_CAP_ENDIANNESS:
 390       return PIPE_ENDIAN_LITTLE;
 391
 392    case PIPE_CAP_VENDOR_ID:
 393       return 0x15ad; /* VMware Inc. */
 394    case PIPE_CAP_DEVICE_ID:
 395       return 0x0405; /* assume SVGA II */
 396    case PIPE_CAP_ACCELERATED:
 397       return 0; /* XXX: */
 398    case PIPE_CAP_VIDEO_MEMORY:
 399       /* XXX: Query the host ? */
 400       return 1;
 401    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 402       return sws->have_vgpu10;
 403    case PIPE_CAP_CLEAR_TEXTURE:
 404       return sws->have_vgpu10;
 405    case PIPE_CAP_UMA:
 406    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 407    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 408    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 409    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 410    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 411    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 412    case PIPE_CAP_TGSI_TXQS:
 413    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 414    case PIPE_CAP_SHAREABLE_SHADERS:
 415    case PIPE_CAP_DRAW_PARAMETERS:
 416    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 417    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 418    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 419    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 420    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 421    case PIPE_CAP_CULL_DISTANCE:
 422    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 423    case PIPE_CAP_TGSI_VOTE:
 424    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 425    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 426    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 427    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 428    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 429    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 430    case PIPE_CAP_TGSI_FS_FBFETCH:
 431    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 432    case PIPE_CAP_DOUBLES:
 433    case PIPE_CAP_INT64:
 434    case PIPE_CAP_INT64_DIVMOD:
 435    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 436    case PIPE_CAP_TGSI_CLOCK:
 437    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 438    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 439    case PIPE_CAP_TGSI_BALLOT:
 440    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 441    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 442    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 443       return 0;
 444    }
 445
 446    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 447    return 0;
 448 }
 449
 450
 451 static int
 452 vgpu9_get_shader_param(struct pipe_screen *screen,
 453                        enum pipe_shader_type shader,
 454                        enum pipe_shader_cap param)
 455 {
 456    struct svga_screen *svgascreen = svga_screen(screen);
 457    struct svga_winsys_screen *sws = svgascreen->sws;
 458    unsigned val;
 459
 460    assert(!sws->have_vgpu10);
 461
 462    switch (shader)
 463    {
 464    case PIPE_SHADER_FRAGMENT:
 465       switch (param)
 466       {
 467       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 468       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 469          return get_uint_cap(sws,
 470                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 471                              512);
 472       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 473       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 474          return 512;
 475       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 476          return SVGA3D_MAX_NESTING_LEVEL;
 477       case PIPE_SHADER_CAP_MAX_INPUTS:
 478          return 10;
 479       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 480          return svgascreen->max_color_buffers;
 481       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 482          return 224 * sizeof(float[4]);
 483       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 484          return 1;
 485       case PIPE_SHADER_CAP_MAX_TEMPS:
 486          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 487          return MIN2(val, SVGA3D_TEMPREG_MAX);
 488       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 489          /*
 490           * Although PS 3.0 has some addressing abilities it can only represent
 491           * loops that can be statically determined and unrolled. Given we can
 492           * only handle a subset of the cases that the state tracker already
 493           * does it is better to defer loop unrolling to the state tracker.
 494           */
 495          return 0;
 496       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 497          return 0;
 498       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 499          return 0;
 500       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 501       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 502       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 503          return 0;
 504       case PIPE_SHADER_CAP_SUBROUTINES:
 505          return 0;
 506       case PIPE_SHADER_CAP_INTEGERS:
 507          return 0;
 508       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 509       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 510          return 16;
 511       case PIPE_SHADER_CAP_PREFERRED_IR:
 512          return PIPE_SHADER_IR_TGSI;
 513       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 514          return 0;
 515       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 516       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 517       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 518       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 519       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 520       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 521       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 522       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 523          return 0;
 524       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 525          return 32;
 526       }
 527       /* If we get here, we failed to handle a cap above */
 528       debug_printf("Unexpected fragment shader query %u\n", param);
 529       return 0;
 530    case PIPE_SHADER_VERTEX:
 531       switch (param)
 532       {
 533       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 534       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 535          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 536                              512);
 537       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 538       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 539          /* XXX: until we have vertex texture support */
 540          return 0;
 541       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 542          return SVGA3D_MAX_NESTING_LEVEL;
 543       case PIPE_SHADER_CAP_MAX_INPUTS:
 544          return 16;
 545       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 546          return 10;
 547       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 548          return 256 * sizeof(float[4]);
 549       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 550          return 1;
 551       case PIPE_SHADER_CAP_MAX_TEMPS:
 552          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 553          return MIN2(val, SVGA3D_TEMPREG_MAX);
 554       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 555          return 0;
 556       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 557          return 0;
 558       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 559       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 560          return 1;
 561       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 562          return 0;
 563       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 564          return 1;
 565       case PIPE_SHADER_CAP_SUBROUTINES:
 566          return 0;
 567       case PIPE_SHADER_CAP_INTEGERS:
 568          return 0;
 569       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 570       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 571          return 0;
 572       case PIPE_SHADER_CAP_PREFERRED_IR:
 573          return PIPE_SHADER_IR_TGSI;
 574       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 575          return 0;
 576       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 577       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 578       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 579       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 580       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 581       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 582       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 583       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 584          return 0;
 585       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 586          return 32;
 587       }
 588       /* If we get here, we failed to handle a cap above */
 589       debug_printf("Unexpected vertex shader query %u\n", param);
 590       return 0;
 591    case PIPE_SHADER_GEOMETRY:
 592    case PIPE_SHADER_COMPUTE:
 593    case PIPE_SHADER_TESS_CTRL:
 594    case PIPE_SHADER_TESS_EVAL:
 595       /* no support for geometry, tess or compute shaders at this time */
 596       return 0;
 597    default:
 598       debug_printf("Unexpected shader type (%u) query\n", shader);
 599       return 0;
 600    }
 601    return 0;
 602 }
 603
 604
 605 static int
 606 vgpu10_get_shader_param(struct pipe_screen *screen,
 607                         enum pipe_shader_type shader,
 608                         enum pipe_shader_cap param)
 609 {
 610    struct svga_screen *svgascreen = svga_screen(screen);
 611    struct svga_winsys_screen *sws = svgascreen->sws;
 612
 613    assert(sws->have_vgpu10);
 614    (void) sws;  /* silence unused var warnings in non-debug builds */
 615
 616    /* Only VS, GS, FS supported */
 617    if (shader != PIPE_SHADER_VERTEX &&
 618        shader != PIPE_SHADER_GEOMETRY &&
 619        shader != PIPE_SHADER_FRAGMENT) {
 620       return 0;
 621    }
 622
 623    /* NOTE: we do not query the device for any caps/limits at this time */
 624
 625    /* Generally the same limits for vertex, geometry and fragment shaders */
 626    switch (param) {
 627    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 628    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 629    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 630    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 631       return 64 * 1024;
 632    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 633       return 64;
 634    case PIPE_SHADER_CAP_MAX_INPUTS:
 635       if (shader == PIPE_SHADER_FRAGMENT)
 636          return VGPU10_MAX_FS_INPUTS;
 637       else if (shader == PIPE_SHADER_GEOMETRY)
 638          return VGPU10_MAX_GS_INPUTS;
 639       else
 640          return VGPU10_MAX_VS_INPUTS;
 641    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 642       if (shader == PIPE_SHADER_FRAGMENT)
 643          return VGPU10_MAX_FS_OUTPUTS;
 644       else if (shader == PIPE_SHADER_GEOMETRY)
 645          return VGPU10_MAX_GS_OUTPUTS;
 646       else
 647          return VGPU10_MAX_VS_OUTPUTS;
 648    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 649       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 650    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 651       return svgascreen->max_const_buffers;
 652    case PIPE_SHADER_CAP_MAX_TEMPS:
 653       return VGPU10_MAX_TEMPS;
 654    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 655    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 656    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 657    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 658       return TRUE; /* XXX verify */
 659    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 660    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 661    case PIPE_SHADER_CAP_SUBROUTINES:
 662    case PIPE_SHADER_CAP_INTEGERS:
 663       return TRUE;
 664    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 665    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 666       return SVGA3D_DX_MAX_SAMPLERS;
 667    case PIPE_SHADER_CAP_PREFERRED_IR:
 668       return PIPE_SHADER_IR_TGSI;
 669    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 670          return 0;
 671    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 672    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 673    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 674    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 675    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 676    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 677    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 678    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 679       return 0;
 680    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 681       return 32;
 682    default:
 683       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 684       return 0;
 685    }
 686    return 0;
 687 }
 688
 689
 690 static int
 691 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 692                       enum pipe_shader_cap param)
 693 {
 694    struct svga_screen *svgascreen = svga_screen(screen);
 695    struct svga_winsys_screen *sws = svgascreen->sws;
 696    if (sws->have_vgpu10) {
 697       return vgpu10_get_shader_param(screen, shader, param);
 698    }
 699    else {
 700       return vgpu9_get_shader_param(screen, shader, param);
 701    }
 702 }
 703
 704
 705 /**
 706  * Implement pipe_screen::is_format_supported().
 707  * \param bindings  bitmask of PIPE_BIND_x flags
 708  */
 709 static boolean
 710 svga_is_format_supported( struct pipe_screen *screen,
 711                           enum pipe_format format,
 712                           enum pipe_texture_target target,
 713                           unsigned sample_count,
 714                           unsigned bindings)
 715 {
 716    struct svga_screen *ss = svga_screen(screen);
 717    SVGA3dSurfaceFormat svga_format;
 718    SVGA3dSurfaceFormatCaps caps;
 719    SVGA3dSurfaceFormatCaps mask;
 720
 721    assert(bindings);
 722
 723    if (sample_count > 1) {
 724       /* In ms_samples, if bit N is set it means that we support
 725        * multisample with N+1 samples per pixel.
 726        */
 727       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 728          return FALSE;
 729       }
 730    }
 731
 732    svga_format = svga_translate_format(ss, format, bindings);
 733    if (svga_format == SVGA3D_FORMAT_INVALID) {
 734       return FALSE;
 735    }
 736
 737    /* we don't support sRGB rendering into display targets */
 738    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 739       return FALSE;
 740    }
 741
 742    /*
 743     * For VGPU10 vertex formats, skip querying host capabilities
 744     */
 745
 746    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 747       SVGA3dSurfaceFormat svga_format;
 748       unsigned flags;
 749       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 750       return svga_format != SVGA3D_FORMAT_INVALID;
 751    }
 752
 753    /*
 754     * Override host capabilities, so that we end up with the same
 755     * visuals for all virtual hardware implementations.
 756     */
 757
 758    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 759       switch (svga_format) {
 760       case SVGA3D_A8R8G8B8:
 761       case SVGA3D_X8R8G8B8:
 762       case SVGA3D_R5G6B5:
 763          break;
 764
 765       /* VGPU10 formats */
 766       case SVGA3D_B8G8R8A8_UNORM:
 767       case SVGA3D_B8G8R8X8_UNORM:
 768       case SVGA3D_B5G6R5_UNORM:
 769          break;
 770
 771       /* Often unsupported/problematic. This means we end up with the same
 772        * visuals for all virtual hardware implementations.
 773        */
 774       case SVGA3D_A4R4G4B4:
 775       case SVGA3D_A1R5G5B5:
 776          return FALSE;
 777
 778       default:
 779          return FALSE;
 780       }
 781    }
 782
 783    /*
 784     * Query the host capabilities.
 785     */
 786
 787    svga_get_format_cap(ss, svga_format, &caps);
 788
 789    if (bindings & PIPE_BIND_RENDER_TARGET) {
 790       /* Check that the color surface is blendable, unless it's an
 791        * integer format.
 792        */
 793       if (!svga_format_is_integer(svga_format) &&
 794           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 795          return FALSE;
 796       }
 797    }
 798
 799    mask.value = 0;
 800    if (bindings & PIPE_BIND_RENDER_TARGET) {
 801       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 802    }
 803    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 804       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 805    }
 806    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 807       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 808    }
 809
 810    if (target == PIPE_TEXTURE_CUBE) {
 811       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 812    }
 813    else if (target == PIPE_TEXTURE_3D) {
 814       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 815    }
 816
 817    return (caps.value & mask.value) == mask.value;
 818 }
 819
 820
 821 static void
 822 svga_fence_reference(struct pipe_screen *screen,
 823                      struct pipe_fence_handle **ptr,
 824                      struct pipe_fence_handle *fence)
 825 {
 826    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 827    sws->fence_reference(sws, ptr, fence);
 828 }
 829
 830
 831 static boolean
 832 svga_fence_finish(struct pipe_screen *screen,
 833                   struct pipe_context *ctx,
 834                   struct pipe_fence_handle *fence,
 835                   uint64_t timeout)
 836 {
 837    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 838    boolean retVal;
 839
 840    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 841
 842    if (!timeout) {
 843       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 844    }
 845    else {
 846       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 847                __FUNCTION__, fence);
 848
 849       retVal = sws->fence_finish(sws, fence, 0) == 0;
 850    }
 851
 852    SVGA_STATS_TIME_POP(sws);
 853
 854    return retVal;
 855 }
 856
 857
 858 static int
 859 svga_get_driver_query_info(struct pipe_screen *screen,
 860                            unsigned index,
 861                            struct pipe_driver_query_info *info)
 862 {
 863 #define QUERY(NAME, ENUM, UNITS) \
 864    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 865
 866    static const struct pipe_driver_query_info queries[] = {
 867       /* per-frame counters */
 868       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 869             PIPE_DRIVER_QUERY_TYPE_UINT64),
 870       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 871             PIPE_DRIVER_QUERY_TYPE_UINT64),
 872       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 873             PIPE_DRIVER_QUERY_TYPE_UINT64),
 874       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 875             PIPE_DRIVER_QUERY_TYPE_UINT64),
 876       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 877             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 878       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 879             PIPE_DRIVER_QUERY_TYPE_UINT64),
 880       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 881             PIPE_DRIVER_QUERY_TYPE_UINT64),
 882       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 883             PIPE_DRIVER_QUERY_TYPE_BYTES),
 884       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 885             PIPE_DRIVER_QUERY_TYPE_BYTES),
 886       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 887             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 888       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 889             PIPE_DRIVER_QUERY_TYPE_UINT64),
 890       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 891             PIPE_DRIVER_QUERY_TYPE_UINT64),
 892       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 893             PIPE_DRIVER_QUERY_TYPE_UINT64),
 894       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 895             PIPE_DRIVER_QUERY_TYPE_UINT64),
 896       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 897             PIPE_DRIVER_QUERY_TYPE_UINT64),
 898       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 899             PIPE_DRIVER_QUERY_TYPE_UINT64),
 900
 901       /* running total counters */
 902       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 903             PIPE_DRIVER_QUERY_TYPE_BYTES),
 904       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 905             PIPE_DRIVER_QUERY_TYPE_UINT64),
 906       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 907             PIPE_DRIVER_QUERY_TYPE_UINT64),
 908       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 909             PIPE_DRIVER_QUERY_TYPE_UINT64),
 910       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 911             PIPE_DRIVER_QUERY_TYPE_UINT64),
 912       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 913             PIPE_DRIVER_QUERY_TYPE_UINT64),
 914    };
 915 #undef QUERY
 916
 917    if (!info)
 918       return ARRAY_SIZE(queries);
 919
 920    if (index >= ARRAY_SIZE(queries))
 921       return 0;
 922
 923    *info = queries[index];
 924    return 1;
 925 }
 926
 927
 928 static void
 929 svga_destroy_screen( struct pipe_screen *screen )
 930 {
 931    struct svga_screen *svgascreen = svga_screen(screen);
 932
 933    svga_screen_cache_cleanup(svgascreen);
 934
 935    mtx_destroy(&svgascreen->swc_mutex);
 936    mtx_destroy(&svgascreen->tex_mutex);
 937
 938    svgascreen->sws->destroy(svgascreen->sws);
 939
 940    FREE(svgascreen);
 941 }
 942
 943
 944 /**
 945  * Create a new svga_screen object
 946  */
 947 struct pipe_screen *
 948 svga_screen_create(struct svga_winsys_screen *sws)
 949 {
 950    struct svga_screen *svgascreen;
 951    struct pipe_screen *screen;
 952
 953 #ifdef DEBUG
 954    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 955 #endif
 956
 957    svgascreen = CALLOC_STRUCT(svga_screen);
 958    if (!svgascreen)
 959       goto error1;
 960
 961    svgascreen->debug.force_level_surface_view =
 962       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 963    svgascreen->debug.force_surface_view =
 964       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 965    svgascreen->debug.force_sampler_view =
 966       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 967    svgascreen->debug.no_surface_view =
 968       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 969    svgascreen->debug.no_sampler_view =
 970       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 971    svgascreen->debug.no_cache_index_buffers =
 972       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 973
 974    screen = &svgascreen->screen;
 975
 976    screen->destroy = svga_destroy_screen;
 977    screen->get_name = svga_get_name;
 978    screen->get_vendor = svga_get_vendor;
 979    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 980    screen->get_param = svga_get_param;
 981    screen->get_shader_param = svga_get_shader_param;
 982    screen->get_paramf = svga_get_paramf;
 983    screen->get_timestamp = NULL;
 984    screen->is_format_supported = svga_is_format_supported;
 985    screen->context_create = svga_context_create;
 986    screen->fence_reference = svga_fence_reference;
 987    screen->fence_finish = svga_fence_finish;
 988    screen->get_driver_query_info = svga_get_driver_query_info;
 989    svgascreen->sws = sws;
 990
 991    svga_init_screen_resource_functions(svgascreen);
 992
 993    if (sws->get_hw_version) {
 994       svgascreen->hw_version = sws->get_hw_version(sws);
 995    } else {
 996       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 997    }
 998
 999    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
1000       /* too old for 3D acceleration */
1001       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1002                    svgascreen->hw_version);
1003       goto error2;
1004    }
1005
1006    /*
1007     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1008     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1009     * we prefer the later when available.
1010     *
1011     * This mimics hardware vendors extensions for D3D depth sampling. See also
1012     * http://aras-p.info/texts/D3D9GPUHacks.html
1013     */
1014
1015    {
1016       boolean has_df16, has_df24, has_d24s8_int;
1017       SVGA3dSurfaceFormatCaps caps;
1018       SVGA3dSurfaceFormatCaps mask;
1019       mask.value = 0;
1020       mask.zStencil = 1;
1021       mask.texture = 1;
1022
1023       svgascreen->depth.z16 = SVGA3D_Z_D16;
1024       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1025       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1026
1027       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1028       has_df16 = (caps.value & mask.value) == mask.value;
1029
1030       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1031       has_df24 = (caps.value & mask.value) == mask.value;
1032
1033       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1034       has_d24s8_int = (caps.value & mask.value) == mask.value;
1035
1036       /* XXX: We might want some other logic here.
1037        * Like if we only have d24s8_int we should
1038        * emulate the other formats with that.
1039        */
1040       if (has_df16) {
1041          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1042       }
1043       if (has_df24) {
1044          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1045       }
1046       if (has_d24s8_int) {
1047          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1048       }
1049    }
1050
1051    /* Query device caps
1052     */
1053    if (sws->have_vgpu10) {
1054       svgascreen->haveProvokingVertex
1055          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1056       svgascreen->haveLineSmooth = TRUE;
1057       svgascreen->maxPointSize = 80.0F;
1058       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1059
1060       /* Multisample samples per pixel */
1061       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1062          svgascreen->ms_samples =
1063             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1064       }
1065
1066       /* Maximum number of constant buffers */
1067       svgascreen->max_const_buffers =
1068          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1069       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1070    }
1071    else {
1072       /* VGPU9 */
1073       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1074                                      SVGA3DVSVERSION_NONE);
1075       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1076                                      SVGA3DPSVERSION_NONE);
1077
1078       /* we require Shader model 3.0 or later */
1079       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1080          goto error2;
1081       }
1082
1083       svgascreen->haveProvokingVertex = FALSE;
1084
1085       svgascreen->haveLineSmooth =
1086          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1087
1088       svgascreen->maxPointSize =
1089          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1090       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1091       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1092
1093       /* The SVGA3D device always supports 4 targets at this time, regardless
1094        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1095        */
1096       svgascreen->max_color_buffers = 4;
1097
1098       /* Only support one constant buffer
1099        */
1100       svgascreen->max_const_buffers = 1;
1101
1102       /* No multisampling */
1103       svgascreen->ms_samples = 0;
1104    }
1105
1106    /* common VGPU9 / VGPU10 caps */
1107    svgascreen->haveLineStipple =
1108       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1109
1110    svgascreen->maxLineWidth =
1111       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1112
1113    svgascreen->maxLineWidthAA =
1114       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1115
1116    if (0) {
1117       debug_printf("svga: haveProvokingVertex %u\n",
1118                    svgascreen->haveProvokingVertex);
1119       debug_printf("svga: haveLineStip %u  "
1120                    "haveLineSmooth %u  maxLineWidth %f\n",
1121                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1122                    svgascreen->maxLineWidth);
1123       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1124       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1125    }
1126
1127    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1128    (void) mtx_init(&svgascreen->swc_mutex, mtx_plain);
1129
1130    svga_screen_cache_init(svgascreen);
1131
1132    /* Log Version to Host */
1133    util_snprintf(host_log, sizeof(host_log) - strlen(HOST_LOG_PREFIX),
1134                  "%s%s", HOST_LOG_PREFIX, svga_get_name(screen));
1135    svga_host_log(host_log);
1136
1137    util_snprintf(host_log, sizeof(host_log) - strlen(HOST_LOG_PREFIX),
1138                  "%s%s (%s)", HOST_LOG_PREFIX, PACKAGE_VERSION, MESA_GIT_SHA1);
1139    svga_host_log(host_log);
1140
1141    return screen;
1142 error2:
1143    FREE(svgascreen);
1144 error1:
1145    return NULL;
1146 }
1147
1148 struct svga_winsys_screen *
1149 svga_winsys_screen(struct pipe_screen *screen)
1150 {
1151    return svga_screen(screen)->sws;
1152 }
1153
1154 #ifdef DEBUG
1155 struct svga_screen *
1156 svga_screen(struct pipe_screen *screen)
1157 {
1158    assert(screen);
1159    assert(screen->destroy == svga_destroy_screen);
1160    return (struct svga_screen *)screen;
1161 }
1162 #endif