src/gallium/drivers/svga/svga_state_rss.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_inlines.h"
  27 #include "pipe/p_defines.h"
  28 #include "util/u_math.h"
  29
  30 #include "svga_context.h"
  31 #include "svga_state.h"
  32 #include "svga_cmd.h"
  33
  34
  35 struct rs_queue {
  36    unsigned rs_count;
  37    SVGA3dRenderState rs[SVGA3D_RS_MAX];
  38 };
  39
  40
  41 #define EMIT_RS(svga, value, token, fail)                       \
  42 do {                                                            \
  43    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  44       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  45       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  46    }                                                            \
  47 } while (0)
  48
  49 #define EMIT_RS_FLOAT(svga, fvalue, token, fail)                \
  50 do {                                                            \
  51    unsigned value = fui(fvalue);                                \
  52    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  53       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  54       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  55    }                                                            \
  56 } while (0)
  57
  58
  59 static INLINE void
  60 svga_queue_rs( struct rs_queue *q,
  61                unsigned rss,
  62                unsigned value )
  63 {
  64    q->rs[q->rs_count].state = rss;
  65    q->rs[q->rs_count].uintValue = value;
  66    q->rs_count++;
  67 }
  68
  69
  70 /* Compare old and new render states and emit differences between them
  71  * to hardware.  Simplest implementation would be to emit the whole of
  72  * the "to" state.
  73  */
  74 static int emit_rss( struct svga_context *svga,
  75                      unsigned dirty )
  76 {
  77    struct rs_queue queue;
  78
  79    queue.rs_count = 0;
  80
  81    if (dirty & SVGA_NEW_BLEND) {
  82       const struct svga_blend_state *curr = svga->curr.blend;
  83
  84       EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
  85       EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail );
  86
  87       if (curr->rt[0].blend_enable) {
  88          EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail );
  89          EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail );
  90          EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail );
  91
  92          EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable,
  93                   SEPARATEALPHABLENDENABLE, fail );
  94
  95          if (curr->rt[0].separate_alpha_blend_enable) {
  96             EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail );
  97             EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail );
  98             EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail );
  99          }
 100       }
 101    }
 102
 103
 104    if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) {
 105       const struct svga_depth_stencil_state *curr = svga->curr.depth;
 106       const struct svga_rasterizer_state *rast = svga->curr.rast;
 107
 108       if (!curr->stencil[0].enabled)
 109       {
 110          /* Stencil disabled
 111           */
 112          EMIT_RS( svga, FALSE, STENCILENABLE, fail );
 113          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 114       }
 115       else if (curr->stencil[0].enabled && !curr->stencil[1].enabled)
 116       {
 117          /* Regular stencil
 118           */
 119          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 120          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 121
 122          EMIT_RS( svga, curr->stencil[0].func,  STENCILFUNC, fail );
 123          EMIT_RS( svga, curr->stencil[0].fail,  STENCILFAIL, fail );
 124          EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail );
 125          EMIT_RS( svga, curr->stencil[0].pass,  STENCILPASS, fail );
 126
 127          EMIT_RS( svga, curr->stencil_ref, STENCILREF, fail );
 128          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 129          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 130       }
 131       else
 132       {
 133          int cw, ccw;
 134
 135          /* Hardware frontwinding is always CW, so if ours is also CW,
 136           * then our definition of front face agrees with hardware.
 137           * Otherwise need to flip.
 138           */
 139          if (rast->templ.front_winding == PIPE_WINDING_CW) {
 140             cw = 0;
 141             ccw = 1;
 142          }
 143          else {
 144             cw = 1;
 145             ccw = 0;
 146          }
 147
 148          /* Twoside stencil
 149           */
 150          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 151          EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail );
 152
 153          EMIT_RS( svga, curr->stencil[cw].func,  STENCILFUNC, fail );
 154          EMIT_RS( svga, curr->stencil[cw].fail,  STENCILFAIL, fail );
 155          EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail );
 156          EMIT_RS( svga, curr->stencil[cw].pass,  STENCILPASS, fail );
 157
 158          EMIT_RS( svga, curr->stencil[ccw].func,  CCWSTENCILFUNC, fail );
 159          EMIT_RS( svga, curr->stencil[ccw].fail,  CCWSTENCILFAIL, fail );
 160          EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail );
 161          EMIT_RS( svga, curr->stencil[ccw].pass,  CCWSTENCILPASS, fail );
 162
 163          EMIT_RS( svga, curr->stencil_ref, STENCILREF, fail );
 164          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 165          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 166       }
 167
 168       EMIT_RS( svga, curr->zenable, ZENABLE, fail );
 169       if (curr->zenable) {
 170          EMIT_RS( svga, curr->zfunc, ZFUNC, fail );
 171          EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail );
 172       }
 173
 174       EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail );
 175       if (curr->alphatestenable) {
 176          EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail );
 177          EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail );
 178       }
 179    }
 180
 181
 182    if (dirty & SVGA_NEW_RAST)
 183    {
 184       const struct svga_rasterizer_state *curr = svga->curr.rast;
 185
 186       /* Shademode: still need to rearrange index list to move
 187        * flat-shading PV first vertex.
 188        */
 189       EMIT_RS( svga, curr->shademode, SHADEMODE, fail );
 190       EMIT_RS( svga, curr->cullmode, CULLMODE, fail );
 191       EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail );
 192       EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail );
 193       EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail );
 194       EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail );
 195       EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail );
 196       /* XXX still need to set this? */
 197       EMIT_RS_FLOAT( svga, 0.0, POINTSIZEMIN, fail );
 198       EMIT_RS_FLOAT( svga, SVGA_MAX_POINTSIZE, POINTSIZEMAX, fail );
 199    }
 200
 201    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE))
 202    {
 203       const struct svga_rasterizer_state *curr = svga->curr.rast;
 204       float slope = 0.0;
 205       float bias  = 0.0;
 206
 207       /* Need to modify depth bias according to bound depthbuffer
 208        * format.  Don't do hardware depthbias while the software
 209        * pipeline is active.
 210        */
 211       if (!svga->state.sw.need_pipeline &&
 212           svga->curr.framebuffer.zsbuf)
 213       {
 214          slope = curr->slopescaledepthbias;
 215          bias  = svga->curr.depthscale * curr->depthbias;
 216       }
 217
 218       EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail );
 219       EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail );
 220    }
 221
 222
 223    if (queue.rs_count) {
 224       SVGA3dRenderState *rs;
 225
 226       if (SVGA3D_BeginSetRenderState( svga->swc,
 227                                       &rs,
 228                                       queue.rs_count ) != PIPE_OK)
 229          goto fail;
 230
 231       memcpy( rs,
 232               queue.rs,
 233               queue.rs_count * sizeof queue.rs[0]);
 234
 235       SVGA_FIFOCommitAll( svga->swc );
 236    }
 237
 238    /* Also blend color:
 239     */
 240
 241    return 0;
 242
 243 fail:
 244    /* XXX: need to poison cached hardware state on failure to ensure
 245     * dirty state gets re-emitted.  Fix this by re-instating partial
 246     * FIFOCommit command and only updating cached hw state once the
 247     * initial allocation has succeeded.
 248     */
 249    memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
 250
 251    return PIPE_ERROR_OUT_OF_MEMORY;
 252 }
 253
 254
 255 struct svga_tracked_state svga_hw_rss =
 256 {
 257    "hw rss state",
 258
 259    (SVGA_NEW_BLEND |
 260     SVGA_NEW_DEPTH_STENCIL |
 261     SVGA_NEW_RAST |
 262     SVGA_NEW_FRAME_BUFFER |
 263     SVGA_NEW_NEED_PIPELINE),
 264
 265    emit_rss
 266 };