src/gallium/drivers/svga/svga_state_rss.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_inlines.h"
  27 #include "pipe/p_defines.h"
  28 #include "util/u_math.h"
  29 #include "util/u_pack_color.h"
  30
  31 #include "svga_context.h"
  32 #include "svga_state.h"
  33 #include "svga_cmd.h"
  34
  35
  36 struct rs_queue {
  37    unsigned rs_count;
  38    SVGA3dRenderState rs[SVGA3D_RS_MAX];
  39 };
  40
  41
  42 #define EMIT_RS(svga, value, token, fail)                       \
  43 do {                                                            \
  44    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  45       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  46       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  47    }                                                            \
  48 } while (0)
  49
  50 #define EMIT_RS_FLOAT(svga, fvalue, token, fail)                \
  51 do {                                                            \
  52    unsigned value = fui(fvalue);                                \
  53    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  54       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  55       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  56    }                                                            \
  57 } while (0)
  58
  59
  60 static INLINE void
  61 svga_queue_rs( struct rs_queue *q,
  62                unsigned rss,
  63                unsigned value )
  64 {
  65    q->rs[q->rs_count].state = rss;
  66    q->rs[q->rs_count].uintValue = value;
  67    q->rs_count++;
  68 }
  69
  70
  71 /* Compare old and new render states and emit differences between them
  72  * to hardware.  Simplest implementation would be to emit the whole of
  73  * the "to" state.
  74  */
  75 static int emit_rss( struct svga_context *svga,
  76                      unsigned dirty )
  77 {
  78    struct rs_queue queue;
  79
  80    queue.rs_count = 0;
  81
  82    if (dirty & SVGA_NEW_BLEND) {
  83       const struct svga_blend_state *curr = svga->curr.blend;
  84
  85       EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
  86       EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail );
  87
  88       if (curr->rt[0].blend_enable) {
  89          EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail );
  90          EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail );
  91          EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail );
  92
  93          EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable,
  94                   SEPARATEALPHABLENDENABLE, fail );
  95
  96          if (curr->rt[0].separate_alpha_blend_enable) {
  97             EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail );
  98             EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail );
  99             EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail );
 100          }
 101       }
 102    }
 103
 104    if (dirty & SVGA_NEW_BLEND_COLOR) {
 105       union util_color uc;
 106       ubyte r = float_to_ubyte(svga->curr.blend_color.color[0]);
 107       ubyte g = float_to_ubyte(svga->curr.blend_color.color[1]);
 108       ubyte b = float_to_ubyte(svga->curr.blend_color.color[2]);
 109       ubyte a = float_to_ubyte(svga->curr.blend_color.color[3]);
 110
 111       util_pack_color_ub( r, g, b, a,
 112                           PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 113
 114       EMIT_RS( svga, uc.ui, BLENDCOLOR, fail );
 115    }
 116
 117    if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) {
 118       const struct svga_depth_stencil_state *curr = svga->curr.depth;
 119       const struct svga_rasterizer_state *rast = svga->curr.rast;
 120
 121       if (!curr->stencil[0].enabled)
 122       {
 123          /* Stencil disabled
 124           */
 125          EMIT_RS( svga, FALSE, STENCILENABLE, fail );
 126          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 127       }
 128       else if (curr->stencil[0].enabled && !curr->stencil[1].enabled)
 129       {
 130          /* Regular stencil
 131           */
 132          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 133          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 134
 135          EMIT_RS( svga, curr->stencil[0].func,  STENCILFUNC, fail );
 136          EMIT_RS( svga, curr->stencil[0].fail,  STENCILFAIL, fail );
 137          EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail );
 138          EMIT_RS( svga, curr->stencil[0].pass,  STENCILPASS, fail );
 139
 140          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 141          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 142       }
 143       else
 144       {
 145          int cw, ccw;
 146
 147          /* Hardware frontwinding is always CW, so if ours is also CW,
 148           * then our definition of front face agrees with hardware.
 149           * Otherwise need to flip.
 150           */
 151          if (rast->templ.front_winding == PIPE_WINDING_CW) {
 152             cw = 0;
 153             ccw = 1;
 154          }
 155          else {
 156             cw = 1;
 157             ccw = 0;
 158          }
 159
 160          /* Twoside stencil
 161           */
 162          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 163          EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail );
 164
 165          EMIT_RS( svga, curr->stencil[cw].func,  STENCILFUNC, fail );
 166          EMIT_RS( svga, curr->stencil[cw].fail,  STENCILFAIL, fail );
 167          EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail );
 168          EMIT_RS( svga, curr->stencil[cw].pass,  STENCILPASS, fail );
 169
 170          EMIT_RS( svga, curr->stencil[ccw].func,  CCWSTENCILFUNC, fail );
 171          EMIT_RS( svga, curr->stencil[ccw].fail,  CCWSTENCILFAIL, fail );
 172          EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail );
 173          EMIT_RS( svga, curr->stencil[ccw].pass,  CCWSTENCILPASS, fail );
 174
 175          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 176          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 177       }
 178
 179       EMIT_RS( svga, curr->zenable, ZENABLE, fail );
 180       if (curr->zenable) {
 181          EMIT_RS( svga, curr->zfunc, ZFUNC, fail );
 182          EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail );
 183       }
 184
 185       EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail );
 186       if (curr->alphatestenable) {
 187          EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail );
 188          EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail );
 189       }
 190    }
 191
 192    if (dirty & SVGA_NEW_STENCIL_REF) {
 193       EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail );
 194    }
 195
 196    if (dirty & SVGA_NEW_RAST)
 197    {
 198       const struct svga_rasterizer_state *curr = svga->curr.rast;
 199
 200       /* Shademode: still need to rearrange index list to move
 201        * flat-shading PV first vertex.
 202        */
 203       EMIT_RS( svga, curr->shademode, SHADEMODE, fail );
 204       EMIT_RS( svga, curr->cullmode, CULLMODE, fail );
 205       EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail );
 206       EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail );
 207       EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail );
 208       EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail );
 209       EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail );
 210       /* XXX still need to set this? */
 211       EMIT_RS_FLOAT( svga, 0.0, POINTSIZEMIN, fail );
 212       EMIT_RS_FLOAT( svga, SVGA_MAX_POINTSIZE, POINTSIZEMAX, fail );
 213    }
 214
 215    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE))
 216    {
 217       const struct svga_rasterizer_state *curr = svga->curr.rast;
 218       float slope = 0.0;
 219       float bias  = 0.0;
 220
 221       /* Need to modify depth bias according to bound depthbuffer
 222        * format.  Don't do hardware depthbias while the software
 223        * pipeline is active.
 224        */
 225       if (!svga->state.sw.need_pipeline &&
 226           svga->curr.framebuffer.zsbuf)
 227       {
 228          slope = curr->slopescaledepthbias;
 229          bias  = svga->curr.depthscale * curr->depthbias;
 230       }
 231
 232       EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail );
 233       EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail );
 234    }
 235
 236
 237    if (queue.rs_count) {
 238       SVGA3dRenderState *rs;
 239
 240       if (SVGA3D_BeginSetRenderState( svga->swc,
 241                                       &rs,
 242                                       queue.rs_count ) != PIPE_OK)
 243          goto fail;
 244
 245       memcpy( rs,
 246               queue.rs,
 247               queue.rs_count * sizeof queue.rs[0]);
 248
 249       SVGA_FIFOCommitAll( svga->swc );
 250    }
 251
 252    return 0;
 253
 254 fail:
 255    /* XXX: need to poison cached hardware state on failure to ensure
 256     * dirty state gets re-emitted.  Fix this by re-instating partial
 257     * FIFOCommit command and only updating cached hw state once the
 258     * initial allocation has succeeded.
 259     */
 260    memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
 261
 262    return PIPE_ERROR_OUT_OF_MEMORY;
 263 }
 264
 265
 266 struct svga_tracked_state svga_hw_rss =
 267 {
 268    "hw rss state",
 269
 270    (SVGA_NEW_BLEND |
 271     SVGA_NEW_BLEND_COLOR |
 272     SVGA_NEW_DEPTH_STENCIL |
 273     SVGA_NEW_STENCIL_REF |
 274     SVGA_NEW_RAST |
 275     SVGA_NEW_FRAME_BUFFER |
 276     SVGA_NEW_NEED_PIPELINE),
 277
 278    emit_rss
 279 };