src/gallium/drivers/swr/rasterizer/core/state.h

   1 /****************************************************************************
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  21 * IN THE SOFTWARE.
  22 *
  23 * @file state.h
  24 *
  25 * @brief Definitions for API state.
  26 *
  27 ******************************************************************************/
  28 #pragma once
  29
  30 #include "common/formats.h"
  31 #include "common/intrin.h"
  32 using gfxptr_t = unsigned long long;
  33 #include <functional>
  34 #include <algorithm>
  35
  36 //////////////////////////////////////////////////////////////////////////
  37 /// PRIMITIVE_TOPOLOGY.
  38 //////////////////////////////////////////////////////////////////////////
  39 enum PRIMITIVE_TOPOLOGY
  40 {
  41     TOP_UNKNOWN = 0x0,
  42     TOP_POINT_LIST = 0x1,
  43     TOP_LINE_LIST = 0x2,
  44     TOP_LINE_STRIP = 0x3,
  45     TOP_TRIANGLE_LIST = 0x4,
  46     TOP_TRIANGLE_STRIP = 0x5,
  47     TOP_TRIANGLE_FAN = 0x6,
  48     TOP_QUAD_LIST = 0x7,
  49     TOP_QUAD_STRIP = 0x8,
  50     TOP_LINE_LIST_ADJ = 0x9,
  51     TOP_LISTSTRIP_ADJ = 0xA,
  52     TOP_TRI_LIST_ADJ = 0xB,
  53     TOP_TRI_STRIP_ADJ = 0xC,
  54     TOP_TRI_STRIP_REVERSE = 0xD,
  55     TOP_POLYGON = 0xE,
  56     TOP_RECT_LIST = 0xF,
  57     TOP_LINE_LOOP = 0x10,
  58     TOP_POINT_LIST_BF = 0x11,
  59     TOP_LINE_STRIP_CONT = 0x12,
  60     TOP_LINE_STRIP_BF = 0x13,
  61     TOP_LINE_STRIP_CONT_BF = 0x14,
  62     TOP_TRIANGLE_FAN_NOSTIPPLE = 0x16,
  63     TOP_TRIANGLE_DISC = 0x17,   /// @todo What is this??
  64
  65     TOP_PATCHLIST_BASE = 0x1F,  // Invalid topology, used to calculate num verts for a patchlist.
  66     TOP_PATCHLIST_1 = 0x20,     // List of 1-vertex patches
  67     TOP_PATCHLIST_2 = 0x21,
  68     TOP_PATCHLIST_3 = 0x22,
  69     TOP_PATCHLIST_4 = 0x23,
  70     TOP_PATCHLIST_5 = 0x24,
  71     TOP_PATCHLIST_6 = 0x25,
  72     TOP_PATCHLIST_7 = 0x26,
  73     TOP_PATCHLIST_8 = 0x27,
  74     TOP_PATCHLIST_9 = 0x28,
  75     TOP_PATCHLIST_10 = 0x29,
  76     TOP_PATCHLIST_11 = 0x2A,
  77     TOP_PATCHLIST_12 = 0x2B,
  78     TOP_PATCHLIST_13 = 0x2C,
  79     TOP_PATCHLIST_14 = 0x2D,
  80     TOP_PATCHLIST_15 = 0x2E,
  81     TOP_PATCHLIST_16 = 0x2F,
  82     TOP_PATCHLIST_17 = 0x30,
  83     TOP_PATCHLIST_18 = 0x31,
  84     TOP_PATCHLIST_19 = 0x32,
  85     TOP_PATCHLIST_20 = 0x33,
  86     TOP_PATCHLIST_21 = 0x34,
  87     TOP_PATCHLIST_22 = 0x35,
  88     TOP_PATCHLIST_23 = 0x36,
  89     TOP_PATCHLIST_24 = 0x37,
  90     TOP_PATCHLIST_25 = 0x38,
  91     TOP_PATCHLIST_26 = 0x39,
  92     TOP_PATCHLIST_27 = 0x3A,
  93     TOP_PATCHLIST_28 = 0x3B,
  94     TOP_PATCHLIST_29 = 0x3C,
  95     TOP_PATCHLIST_30 = 0x3D,
  96     TOP_PATCHLIST_31 = 0x3E,
  97     TOP_PATCHLIST_32 = 0x3F,   // List of 32-vertex patches
  98 };
  99
 100 //////////////////////////////////////////////////////////////////////////
 101 /// SWR_SHADER_TYPE
 102 //////////////////////////////////////////////////////////////////////////
 103 enum SWR_SHADER_TYPE
 104 {
 105     SHADER_VERTEX,
 106     SHADER_GEOMETRY,
 107     SHADER_DOMAIN,
 108     SHADER_HULL,
 109     SHADER_PIXEL,
 110     SHADER_COMPUTE,
 111
 112     NUM_SHADER_TYPES,
 113 };
 114
 115 //////////////////////////////////////////////////////////////////////////
 116 /// SWR_RENDERTARGET_ATTACHMENT
 117 /// @todo Its not clear what an "attachment" means. Its not common term.
 118 //////////////////////////////////////////////////////////////////////////
 119 enum SWR_RENDERTARGET_ATTACHMENT
 120 {
 121     SWR_ATTACHMENT_COLOR0,
 122     SWR_ATTACHMENT_COLOR1,
 123     SWR_ATTACHMENT_COLOR2,
 124     SWR_ATTACHMENT_COLOR3,
 125     SWR_ATTACHMENT_COLOR4,
 126     SWR_ATTACHMENT_COLOR5,
 127     SWR_ATTACHMENT_COLOR6,
 128     SWR_ATTACHMENT_COLOR7,
 129     SWR_ATTACHMENT_DEPTH,
 130     SWR_ATTACHMENT_STENCIL,
 131
 132     SWR_NUM_ATTACHMENTS
 133 };
 134
 135 #define SWR_NUM_RENDERTARGETS 8
 136
 137 #define SWR_ATTACHMENT_COLOR0_BIT 0x001
 138 #define SWR_ATTACHMENT_COLOR1_BIT 0x002
 139 #define SWR_ATTACHMENT_COLOR2_BIT 0x004
 140 #define SWR_ATTACHMENT_COLOR3_BIT 0x008
 141 #define SWR_ATTACHMENT_COLOR4_BIT 0x010
 142 #define SWR_ATTACHMENT_COLOR5_BIT 0x020
 143 #define SWR_ATTACHMENT_COLOR6_BIT 0x040
 144 #define SWR_ATTACHMENT_COLOR7_BIT 0x080
 145 #define SWR_ATTACHMENT_DEPTH_BIT 0x100
 146 #define SWR_ATTACHMENT_STENCIL_BIT 0x200
 147 #define SWR_ATTACHMENT_MASK_ALL 0x3ff
 148 #define SWR_ATTACHMENT_MASK_COLOR 0x0ff
 149
 150
 151 //////////////////////////////////////////////////////////////////////////
 152 /// @brief SWR Inner Tessellation factor ID
 153 /// See above GetTessFactorOutputPosition code for documentation
 154 enum SWR_INNER_TESSFACTOR_ID
 155 {
 156     SWR_QUAD_U_TRI_INSIDE,
 157     SWR_QUAD_V_INSIDE,
 158
 159     SWR_NUM_INNER_TESS_FACTORS,
 160 };
 161
 162 //////////////////////////////////////////////////////////////////////////
 163 /// @brief SWR Outer Tessellation factor ID
 164 /// See above GetTessFactorOutputPosition code for documentation
 165 enum SWR_OUTER_TESSFACTOR_ID
 166 {
 167     SWR_QUAD_U_EQ0_TRI_U_LINE_DETAIL,
 168     SWR_QUAD_V_EQ0_TRI_V_LINE_DENSITY,
 169     SWR_QUAD_U_EQ1_TRI_W,
 170     SWR_QUAD_V_EQ1,
 171
 172     SWR_NUM_OUTER_TESS_FACTORS,
 173 };
 174
 175
 176 /////////////////////////////////////////////////////////////////////////
 177 /// simdvertex
 178 /// @brief Defines a vertex element that holds all the data for SIMD vertices.
 179 ///        Contains space for position, SGV, and 32 generic attributes
 180 /////////////////////////////////////////////////////////////////////////
 181 enum SWR_VTX_SLOTS
 182 {
 183     VERTEX_SGV_SLOT                 = 0,
 184         VERTEX_SGV_RTAI_COMP        = 0,
 185         VERTEX_SGV_VAI_COMP         = 1,
 186         VERTEX_SGV_POINT_SIZE_COMP  = 2,
 187     VERTEX_POSITION_SLOT            = 1,
 188     VERTEX_POSITION_END_SLOT        = 1,
 189     VERTEX_CLIPCULL_DIST_LO_SLOT    = (1 + VERTEX_POSITION_END_SLOT), // VS writes lower 4 clip/cull dist
 190     VERTEX_CLIPCULL_DIST_HI_SLOT    = (2 + VERTEX_POSITION_END_SLOT), // VS writes upper 4 clip/cull dist
 191     VERTEX_ATTRIB_START_SLOT        = (3 + VERTEX_POSITION_END_SLOT),
 192     VERTEX_ATTRIB_END_SLOT          = (34 + VERTEX_POSITION_END_SLOT),
 193     SWR_VTX_NUM_SLOTS               = (1 + VERTEX_ATTRIB_END_SLOT)
 194 };
 195
 196 // SoAoSoA
 197 struct simdvertex
 198 {
 199     simdvector      attrib[SWR_VTX_NUM_SLOTS];
 200 };
 201
 202 #if ENABLE_AVX512_SIMD16
 203 struct simd16vertex
 204 {
 205     simd16vector    attrib[SWR_VTX_NUM_SLOTS];
 206 };
 207
 208 #endif
 209
 210 template<typename SIMD_T>
 211 struct SIMDVERTEX_T
 212 {
 213     typename SIMD_T::Vec4               attrib[SWR_VTX_NUM_SLOTS];
 214 };
 215
 216 //////////////////////////////////////////////////////////////////////////
 217 /// SWR_VS_CONTEXT
 218 /// @brief Input to vertex shader
 219 /////////////////////////////////////////////////////////////////////////
 220 struct SWR_VS_CONTEXT
 221 {
 222     simdvertex* pVin;           // IN: SIMD input vertex data store
 223     simdvertex* pVout;          // OUT: SIMD output vertex data store
 224
 225     uint32_t InstanceID;        // IN: Instance ID, constant across all verts of the SIMD
 226     simdscalari VertexID;       // IN: Vertex ID
 227     simdscalari mask;           // IN: Active mask for shader
 228 #if USE_SIMD16_FRONTEND
 229     uint32_t AlternateOffset;   // IN: amount to offset for interleaving even/odd simd8 in simd16vertex output
 230 #endif
 231 };
 232
 233 /////////////////////////////////////////////////////////////////////////
 234 /// ScalarCPoint
 235 /// @brief defines a control point element as passed from the output
 236 /// of the hull shader to the input of the domain shader
 237 /////////////////////////////////////////////////////////////////////////
 238 struct ScalarAttrib
 239 {
 240     float x;
 241     float y;
 242     float z;
 243     float w;
 244 };
 245
 246 struct ScalarCPoint
 247 {
 248     ScalarAttrib attrib[SWR_VTX_NUM_SLOTS];
 249 };
 250
 251 //////////////////////////////////////////////////////////////////////////
 252 /// SWR_TESSELLATION_FACTORS
 253 /// @brief Tessellation factors structure (non-vector)
 254 /////////////////////////////////////////////////////////////////////////
 255 struct SWR_TESSELLATION_FACTORS
 256 {
 257     float  OuterTessFactors[SWR_NUM_OUTER_TESS_FACTORS];
 258     float  InnerTessFactors[SWR_NUM_INNER_TESS_FACTORS];
 259 };
 260
 261 #define MAX_NUM_VERTS_PER_PRIM 32 // support up to 32 control point patches
 262 struct ScalarPatch
 263 {
 264     SWR_TESSELLATION_FACTORS tessFactors;
 265     ScalarCPoint cp[MAX_NUM_VERTS_PER_PRIM];
 266     ScalarCPoint patchData;
 267 };
 268
 269 //////////////////////////////////////////////////////////////////////////
 270 /// SWR_HS_CONTEXT
 271 /// @brief Input to hull shader
 272 /////////////////////////////////////////////////////////////////////////
 273 struct SWR_HS_CONTEXT
 274 {
 275     simdvertex vert[MAX_NUM_VERTS_PER_PRIM]; // IN: (SIMD) input primitive data
 276     simdscalari PrimitiveID;    // IN: (SIMD) primitive ID generated from the draw call
 277     simdscalari mask;           // IN: Active mask for shader
 278     ScalarPatch* pCPout;        // OUT: Output control point patch
 279                                 // SIMD-sized-array of SCALAR patches
 280 };
 281
 282 //////////////////////////////////////////////////////////////////////////
 283 /// SWR_DS_CONTEXT
 284 /// @brief Input to domain shader
 285 /////////////////////////////////////////////////////////////////////////
 286 struct SWR_DS_CONTEXT
 287 {
 288     uint32_t        PrimitiveID;    // IN: (SCALAR) PrimitiveID for the patch associated with the DS invocation
 289     uint32_t        vectorOffset;   // IN: (SCALAR) vector index offset into SIMD data.
 290     uint32_t        vectorStride;   // IN: (SCALAR) stride (in vectors) of output data per attribute-component
 291     ScalarPatch*    pCpIn;          // IN: (SCALAR) Control patch
 292     simdscalar*     pDomainU;       // IN: (SIMD) Domain Point U coords
 293     simdscalar*     pDomainV;       // IN: (SIMD) Domain Point V coords
 294     simdscalari     mask;           // IN: Active mask for shader
 295     simdscalar*     pOutputData;    // OUT: (SIMD) Vertex Attributes (2D array of vectors, one row per attribute-component)
 296 };
 297
 298 //////////////////////////////////////////////////////////////////////////
 299 /// SWR_GS_CONTEXT
 300 /// @brief Input to geometry shader.
 301 /////////////////////////////////////////////////////////////////////////
 302 struct SWR_GS_CONTEXT
 303 {
 304     simdvector* pVerts;                 // IN: input primitive data for SIMD prims
 305     uint32_t inputVertStride;           // IN: input vertex stride, in attributes
 306     simdscalari PrimitiveID;            // IN: input primitive ID generated from the draw call
 307     uint32_t InstanceID;                // IN: input instance ID
 308     simdscalari mask;                   // IN: Active mask for shader
 309     uint8_t* pStreams[KNOB_SIMD_WIDTH]; // OUT: output stream (contains vertices for all output streams)
 310 };
 311
 312 struct PixelPositions
 313 {
 314     simdscalar UL;
 315     simdscalar center;
 316     simdscalar sample;
 317     simdscalar centroid;
 318 };
 319
 320 #define SWR_MAX_NUM_MULTISAMPLES 16
 321
 322 //////////////////////////////////////////////////////////////////////////
 323 /// SWR_PS_CONTEXT
 324 /// @brief Input to pixel shader.
 325 /////////////////////////////////////////////////////////////////////////
 326 struct SWR_PS_CONTEXT
 327 {
 328     PixelPositions vX;          // IN: x location(s) of pixels
 329     PixelPositions vY;          // IN: x location(s) of pixels
 330     simdscalar vZ;              // INOUT: z location of pixels
 331     simdscalari activeMask;     // OUT: mask for kill
 332     simdscalar  inputMask;      // IN: input coverage mask for all samples
 333     simdscalari oMask;          // OUT: mask for output coverage
 334
 335     PixelPositions vI;          // barycentric coords evaluated at pixel center, sample position, centroid
 336     PixelPositions vJ;
 337     PixelPositions vOneOverW;   // IN: 1/w
 338
 339     const float* pAttribs;      // IN: pointer to attribute barycentric coefficients
 340     const float* pPerspAttribs; // IN: pointer to attribute/w barycentric coefficients
 341     const float* pRecipW;       // IN: pointer to 1/w coord for each vertex
 342     const float *I;             // IN: Barycentric A, B, and C coefs used to compute I
 343     const float *J;             // IN: Barycentric A, B, and C coefs used to compute J
 344     float recipDet;             // IN: 1/Det, used when barycentric interpolating attributes
 345     const float* pSamplePosX;   // IN: array of sample positions
 346     const float* pSamplePosY;   // IN: array of sample positions
 347     simdvector shaded[SWR_NUM_RENDERTARGETS];
 348                                 // OUT: result color per rendertarget
 349
 350     uint32_t frontFace;                 // IN: front- 1, back- 0
 351     uint32_t sampleIndex;               // IN: sampleIndex
 352     uint32_t renderTargetArrayIndex;    // IN: render target array index from GS
 353     uint32_t rasterizerSampleCount;     // IN: sample count used by the rasterizer
 354
 355     uint8_t* pColorBuffer[SWR_NUM_RENDERTARGETS]; // IN: Pointers to render target hottiles
 356 };
 357
 358 //////////////////////////////////////////////////////////////////////////
 359 /// SWR_CS_CONTEXT
 360 /// @brief Input to compute shader.
 361 /////////////////////////////////////////////////////////////////////////
 362 struct SWR_CS_CONTEXT
 363 {
 364     // The ThreadGroupId is the current thread group index relative
 365     // to all thread groups in the Dispatch call. The ThreadId, ThreadIdInGroup,
 366     // and ThreadIdInGroupFlattened can be derived from ThreadGroupId in the shader.
 367
 368     // Compute shader accepts the following system values.
 369     // o ThreadId - Current thread id relative to all other threads in dispatch.
 370     // o ThreadGroupId - Current thread group id relative to all other groups in dispatch.
 371     // o ThreadIdInGroup - Current thread relative to all threads in the current thread group.
 372     // o ThreadIdInGroupFlattened - Flattened linear id derived from ThreadIdInGroup.
 373     //
 374     // All of these system values can be computed in the shader. They will be
 375     // derived from the current tile counter. The tile counter is an atomic counter that
 376     // resides in the draw context and is initialized to the product of the dispatch dims.
 377     //
 378     //  tileCounter = dispatchDims.x * dispatchDims.y * dispatchDims.z
 379     //
 380     // Each CPU worker thread will atomically decrement this counter and passes the current
 381     // count into the shader. When the count reaches 0 then all thread groups in the
 382     // dispatch call have been completed.
 383
 384     uint32_t tileCounter;  // The tile counter value for this thread group.
 385
 386     // Dispatch dimensions used by shader to compute system values from the tile counter.
 387     uint32_t dispatchDims[3];
 388
 389     uint8_t* pTGSM;  // Thread Group Shared Memory pointer.
 390
 391     uint8_t* pSpillFillBuffer;  // Spill/fill buffer for barrier support
 392
 393     uint8_t* pScratchSpace;     // Pointer to scratch space buffer used by the shader, shader is responsible
 394                                 // for subdividing scratch space per instance/simd
 395
 396     uint32_t scratchSpacePerSimd; // Scratch space per work item x SIMD_WIDTH
 397 };
 398
 399 // enums
 400 enum SWR_TILE_MODE
 401 {
 402     SWR_TILE_NONE = 0x0,    // Linear mode (no tiling)
 403     SWR_TILE_MODE_WMAJOR,   // W major tiling
 404     SWR_TILE_MODE_XMAJOR,   // X major tiling
 405     SWR_TILE_MODE_YMAJOR,   // Y major tiling
 406     SWR_TILE_SWRZ,          // SWR-Z tiling
 407
 408     SWR_TILE_MODE_COUNT
 409 };
 410
 411 enum SWR_SURFACE_TYPE
 412 {
 413     SURFACE_1D        = 0,
 414     SURFACE_2D        = 1,
 415     SURFACE_3D        = 2,
 416     SURFACE_CUBE      = 3,
 417     SURFACE_BUFFER    = 4,
 418     SURFACE_STRUCTURED_BUFFER = 5,
 419     SURFACE_NULL       = 7
 420 };
 421
 422 enum SWR_ZFUNCTION
 423 {
 424     ZFUNC_ALWAYS,
 425     ZFUNC_NEVER,
 426     ZFUNC_LT,
 427     ZFUNC_EQ,
 428     ZFUNC_LE,
 429     ZFUNC_GT,
 430     ZFUNC_NE,
 431     ZFUNC_GE,
 432     NUM_ZFUNC
 433 };
 434
 435 enum SWR_STENCILOP
 436 {
 437     STENCILOP_KEEP,
 438     STENCILOP_ZERO,
 439     STENCILOP_REPLACE,
 440     STENCILOP_INCRSAT,
 441     STENCILOP_DECRSAT,
 442     STENCILOP_INCR,
 443     STENCILOP_DECR,
 444     STENCILOP_INVERT
 445 };
 446
 447 enum SWR_BLEND_FACTOR
 448 {
 449     BLENDFACTOR_ONE,
 450     BLENDFACTOR_SRC_COLOR,
 451     BLENDFACTOR_SRC_ALPHA,
 452     BLENDFACTOR_DST_ALPHA,
 453     BLENDFACTOR_DST_COLOR,
 454     BLENDFACTOR_SRC_ALPHA_SATURATE,
 455     BLENDFACTOR_CONST_COLOR,
 456     BLENDFACTOR_CONST_ALPHA,
 457     BLENDFACTOR_SRC1_COLOR,
 458     BLENDFACTOR_SRC1_ALPHA,
 459     BLENDFACTOR_ZERO,
 460     BLENDFACTOR_INV_SRC_COLOR,
 461     BLENDFACTOR_INV_SRC_ALPHA,
 462     BLENDFACTOR_INV_DST_ALPHA,
 463     BLENDFACTOR_INV_DST_COLOR,
 464     BLENDFACTOR_INV_CONST_COLOR,
 465     BLENDFACTOR_INV_CONST_ALPHA,
 466     BLENDFACTOR_INV_SRC1_COLOR,
 467     BLENDFACTOR_INV_SRC1_ALPHA
 468 };
 469
 470 enum SWR_BLEND_OP
 471 {
 472     BLENDOP_ADD,
 473     BLENDOP_SUBTRACT,
 474     BLENDOP_REVSUBTRACT,
 475     BLENDOP_MIN,
 476     BLENDOP_MAX,
 477 };
 478
 479 enum SWR_LOGIC_OP
 480 {
 481     LOGICOP_CLEAR,
 482     LOGICOP_NOR,
 483     LOGICOP_AND_INVERTED,
 484     LOGICOP_COPY_INVERTED,
 485     LOGICOP_AND_REVERSE,
 486     LOGICOP_INVERT,
 487     LOGICOP_XOR,
 488     LOGICOP_NAND,
 489     LOGICOP_AND,
 490     LOGICOP_EQUIV,
 491     LOGICOP_NOOP,
 492     LOGICOP_OR_INVERTED,
 493     LOGICOP_COPY,
 494     LOGICOP_OR_REVERSE,
 495     LOGICOP_OR,
 496     LOGICOP_SET,
 497 };
 498
 499 //////////////////////////////////////////////////////////////////////////
 500 /// SWR_AUX_MODE
 501 /// @brief Specifies how the auxiliary buffer is used by the driver.
 502 //////////////////////////////////////////////////////////////////////////
 503 enum SWR_AUX_MODE
 504 {
 505     AUX_MODE_NONE,
 506     AUX_MODE_COLOR,
 507     AUX_MODE_UAV,
 508     AUX_MODE_DEPTH,
 509 };
 510
 511 //////////////////////////////////////////////////////////////////////////
 512 /// SWR_SURFACE_STATE
 513 //////////////////////////////////////////////////////////////////////////
 514 struct SWR_SURFACE_STATE
 515 {
 516     gfxptr_t xpBaseAddress;
 517     SWR_SURFACE_TYPE type;  // @llvm_enum
 518     SWR_FORMAT format;      // @llvm_enum
 519     uint32_t width;
 520     uint32_t height;
 521     uint32_t depth;
 522     uint32_t numSamples;
 523     uint32_t samplePattern;
 524     uint32_t pitch;
 525     uint32_t qpitch;
 526     uint32_t minLod;            // for sampled surfaces, the most detailed LOD that can be accessed by sampler
 527     uint32_t maxLod;            // for sampled surfaces, the max LOD that can be accessed
 528     float resourceMinLod;       // for sampled surfaces, the most detailed fractional mip that can be accessed by sampler
 529     uint32_t lod;               // for render targets, the lod being rendered to
 530     uint32_t arrayIndex;        // for render targets, the array index being rendered to for arrayed surfaces
 531     SWR_TILE_MODE tileMode;     // @llvm_enum
 532     uint32_t halign;
 533     uint32_t valign;
 534     uint32_t xOffset;
 535     uint32_t yOffset;
 536
 537     uint32_t lodOffsets[2][15]; // lod offsets for sampled surfaces
 538
 539     gfxptr_t xpAuxBaseAddress;   // Used for compression, append/consume counter, etc.
 540     SWR_AUX_MODE auxMode;      // @llvm_enum
 541
 542
 543     bool bInterleavedSamples;   // are MSAA samples stored interleaved or planar
 544 };
 545
 546 // vertex fetch state
 547 // WARNING- any changes to this struct need to be reflected
 548 // in the fetch shader jit
 549 struct SWR_VERTEX_BUFFER_STATE
 550 {
 551     uint32_t index;
 552     uint32_t pitch;
 553     const uint8_t *pData;
 554     uint32_t size;
 555     uint32_t numaNode;
 556     uint32_t minVertex;             // min vertex (for bounds checking)
 557     uint32_t maxVertex;             // size / pitch.  precalculated value used by fetch shader for OOB checks
 558     uint32_t partialInboundsSize;   // size % pitch.  precalculated value used by fetch shader for partially OOB vertices
 559 };
 560
 561 struct SWR_INDEX_BUFFER_STATE
 562 {
 563     // Format type for indices (e.g. UINT16, UINT32, etc.)
 564     SWR_FORMAT format; // @llvm_enum
 565     const void *pIndices;
 566     uint32_t size;
 567 };
 568
 569
 570 //////////////////////////////////////////////////////////////////////////
 571 /// SWR_FETCH_CONTEXT
 572 /// @brief Input to fetch shader.
 573 /// @note WARNING - Changes to this struct need to be reflected in the
 574 ///                 fetch shader jit.
 575 /////////////////////////////////////////////////////////////////////////
 576 struct SWR_FETCH_CONTEXT
 577 {
 578     const SWR_VERTEX_BUFFER_STATE* pStreams;    // IN: array of bound vertex buffers
 579     const int32_t* pIndices;                    // IN: pointer to index buffer for indexed draws
 580     const int32_t* pLastIndex;                  // IN: pointer to end of index buffer, used for bounds checking
 581     uint32_t CurInstance;                       // IN: current instance
 582     uint32_t BaseVertex;                        // IN: base vertex
 583     uint32_t StartVertex;                       // IN: start vertex
 584     uint32_t StartInstance;                     // IN: start instance
 585     simdscalari VertexID;                       // OUT: vector of vertex IDs
 586     simdscalari CutMask;                        // OUT: vector mask of indices which have the cut index value
 587 #if USE_SIMD16_SHADERS
 588 //    simd16scalari VertexID;                     // OUT: vector of vertex IDs
 589 //    simd16scalari CutMask;                      // OUT: vector mask of indices which have the cut index value
 590     simdscalari VertexID2;                      // OUT: vector of vertex IDs
 591     simdscalari CutMask2;                       // OUT: vector mask of indices which have the cut index value
 592 #endif
 593 };
 594
 595 //////////////////////////////////////////////////////////////////////////
 596 /// SWR_STATS
 597 ///
 598 /// @brief All statistics generated by SWR go here. These are public
 599 ///        to driver.
 600 /////////////////////////////////////////////////////////////////////////
 601 OSALIGNLINE(struct) SWR_STATS
 602 {
 603     // Occlusion Query
 604     uint64_t DepthPassCount; // Number of passing depth tests. Not exact.
 605
 606     // Pipeline Stats
 607     uint64_t PsInvocations;  // Number of Pixel Shader invocations
 608     uint64_t CsInvocations;  // Number of Compute Shader invocations
 609
 610 };
 611
 612 //////////////////////////////////////////////////////////////////////////
 613 /// SWR_STATS
 614 ///
 615 /// @brief All statistics generated by FE.
 616 /////////////////////////////////////////////////////////////////////////
 617 OSALIGNLINE(struct) SWR_STATS_FE
 618 {
 619     uint64_t IaVertices;    // Number of Fetch Shader vertices
 620     uint64_t IaPrimitives;  // Number of PA primitives.
 621     uint64_t VsInvocations; // Number of Vertex Shader invocations
 622     uint64_t HsInvocations; // Number of Hull Shader invocations
 623     uint64_t DsInvocations; // Number of Domain Shader invocations
 624     uint64_t GsInvocations; // Number of Geometry Shader invocations
 625     uint64_t GsPrimitives;  // Number of prims GS outputs.
 626     uint64_t CInvocations;  // Number of clipper invocations
 627     uint64_t CPrimitives;   // Number of clipper primitives.
 628
 629     // Streamout Stats
 630     uint64_t SoPrimStorageNeeded[4];
 631     uint64_t SoNumPrimsWritten[4];
 632 };
 633
 634 //////////////////////////////////////////////////////////////////////////
 635 /// STREAMOUT_BUFFERS
 636 /////////////////////////////////////////////////////////////////////////
 637
 638 #define MAX_SO_STREAMS 4
 639 #define MAX_SO_BUFFERS 4
 640 #define MAX_ATTRIBUTES 32
 641
 642 struct SWR_STREAMOUT_BUFFER
 643 {
 644     bool enable;
 645     bool soWriteEnable;
 646
 647     // Pointers to streamout buffers.
 648     uint32_t* pBuffer;
 649
 650     // Size of buffer in dwords.
 651     uint32_t bufferSize;
 652
 653     // Vertex pitch of buffer in dwords.
 654     uint32_t pitch;
 655
 656     // Offset into buffer in dwords. SOS will increment this offset.
 657     uint32_t streamOffset;
 658
 659     // Offset to the SO write offset. If not null then we update offset here.
 660     uint32_t* pWriteOffset;
 661
 662 };
 663
 664 //////////////////////////////////////////////////////////////////////////
 665 /// STREAMOUT_STATE
 666 /////////////////////////////////////////////////////////////////////////
 667 struct SWR_STREAMOUT_STATE
 668 {
 669     // This disables stream output.
 670     bool soEnable;
 671
 672     // which streams are enabled for streamout
 673     bool streamEnable[MAX_SO_STREAMS];
 674
 675     // If set then do not send any streams to the rasterizer.
 676     bool rasterizerDisable;
 677
 678     // Specifies which stream to send to the rasterizer.
 679     uint32_t streamToRasterizer;
 680
 681     // The stream masks specify which attributes are sent to which streams.
 682     // These masks help the FE to setup the pPrimData buffer that is passed
 683     // the Stream Output Shader (SOS) function.
 684     uint32_t streamMasks[MAX_SO_STREAMS];
 685
 686     // Number of attributes, including position, per vertex that are streamed out.
 687     // This should match number of bits in stream mask.
 688     uint32_t streamNumEntries[MAX_SO_STREAMS];
 689
 690     // Offset to the start of the attributes of the input vertices, in simdvector units
 691     uint32_t vertexAttribOffset[MAX_SO_STREAMS];
 692 };
 693
 694 //////////////////////////////////////////////////////////////////////////
 695 /// STREAMOUT_CONTEXT - Passed to SOS
 696 /////////////////////////////////////////////////////////////////////////
 697 struct SWR_STREAMOUT_CONTEXT
 698 {
 699     uint32_t* pPrimData;
 700     SWR_STREAMOUT_BUFFER* pBuffer[MAX_SO_STREAMS];
 701
 702     // Num prims written for this stream
 703     uint32_t numPrimsWritten;
 704
 705     // Num prims that should have been written if there were no overflow.
 706     uint32_t numPrimStorageNeeded;
 707 };
 708
 709 //////////////////////////////////////////////////////////////////////////
 710 /// SWR_GS_STATE - Geometry shader state
 711 /////////////////////////////////////////////////////////////////////////
 712 struct SWR_GS_STATE
 713 {
 714     bool gsEnable;
 715
 716     // Number of input attributes per vertex. Used by the frontend to
 717     // optimize assembling primitives for GS
 718     uint32_t numInputAttribs;
 719
 720     // Stride of incoming verts in attributes
 721     uint32_t inputVertStride;
 722
 723     // Output topology - can be point, tristrip, or linestrip
 724     PRIMITIVE_TOPOLOGY outputTopology;      // @llvm_enum
 725
 726     // Maximum number of verts that can be emitted by a single instance of the GS
 727     uint32_t maxNumVerts;
 728
 729     // Instance count
 730     uint32_t instanceCount;
 731
 732     // If true, geometry shader emits a single stream, with separate cut buffer.
 733     // If false, geometry shader emits vertices for multiple streams to the stream buffer, with a separate StreamID buffer
 734     // to map vertices to streams
 735     bool isSingleStream;
 736
 737     // When single stream is enabled, singleStreamID dictates which stream is being output.
 738     // field ignored if isSingleStream is false
 739     uint32_t singleStreamID;
 740
 741     // Total amount of memory to allocate for one instance of the shader output in bytes
 742     uint32_t allocationSize;
 743
 744     // Offset to the start of the attributes of the input vertices, in simdvector units, as read by the GS
 745     uint32_t vertexAttribOffset;
 746
 747     // Offset to the attributes as stored by the preceding shader stage.
 748     uint32_t srcVertexAttribOffset;
 749
 750     // Size of the control data section which contains cut or streamID data, in simdscalar units. Should be sized to handle
 751     // the maximum number of verts output by the GS. Can be 0 if there are no cuts or streamID bits.
 752     uint32_t controlDataSize;
 753
 754     // Offset to the control data section, in bytes
 755     uint32_t controlDataOffset;
 756
 757     // Total size of an output vertex, in simdvector units
 758     uint32_t outputVertexSize;
 759
 760     // Offset to the start of the vertex section, in bytes
 761     uint32_t outputVertexOffset;
 762
 763     // Set this to non-zero to indicate that the shader outputs a static number of verts. If zero, shader is
 764     // expected to store the final vertex count in the first dword of the gs output stream.
 765     uint32_t staticVertexCount;
 766 };
 767
 768
 769 //////////////////////////////////////////////////////////////////////////
 770 /// SWR_TS_OUTPUT_TOPOLOGY - Defines data output by the tessellator / DS
 771 /////////////////////////////////////////////////////////////////////////
 772 enum SWR_TS_OUTPUT_TOPOLOGY
 773 {
 774     SWR_TS_OUTPUT_POINT,
 775     SWR_TS_OUTPUT_LINE,
 776     SWR_TS_OUTPUT_TRI_CW,
 777     SWR_TS_OUTPUT_TRI_CCW,
 778
 779     SWR_TS_OUTPUT_TOPOLOGY_COUNT
 780 };
 781
 782 //////////////////////////////////////////////////////////////////////////
 783 /// SWR_TS_PARTITIONING - Defines tessellation algorithm
 784 /////////////////////////////////////////////////////////////////////////
 785 enum SWR_TS_PARTITIONING
 786 {
 787     SWR_TS_INTEGER,
 788     SWR_TS_ODD_FRACTIONAL,
 789     SWR_TS_EVEN_FRACTIONAL,
 790
 791     SWR_TS_PARTITIONING_COUNT
 792 };
 793
 794 //////////////////////////////////////////////////////////////////////////
 795 /// SWR_TS_DOMAIN - Defines Tessellation Domain
 796 /////////////////////////////////////////////////////////////////////////
 797 enum SWR_TS_DOMAIN
 798 {
 799     SWR_TS_QUAD,
 800     SWR_TS_TRI,
 801     SWR_TS_ISOLINE,
 802
 803     SWR_TS_DOMAIN_COUNT
 804 };
 805
 806 //////////////////////////////////////////////////////////////////////////
 807 /// SWR_TS_STATE - Tessellation state
 808 /////////////////////////////////////////////////////////////////////////
 809 struct SWR_TS_STATE
 810 {
 811     bool                    tsEnable;
 812     SWR_TS_OUTPUT_TOPOLOGY  tsOutputTopology;   // @llvm_enum
 813     SWR_TS_PARTITIONING     partitioning;       // @llvm_enum
 814     SWR_TS_DOMAIN           domain;             // @llvm_enum
 815
 816     PRIMITIVE_TOPOLOGY      postDSTopology;     // @llvm_enum
 817
 818     uint32_t                numHsInputAttribs;
 819     uint32_t                numHsOutputAttribs;
 820     uint32_t                numDsOutputAttribs;
 821
 822     // Offset to the start of the attributes of the input vertices, in simdvector units
 823     uint32_t vertexAttribOffset;
 824 };
 825
 826 // output merger state
 827 struct SWR_RENDER_TARGET_BLEND_STATE
 828 {
 829     uint8_t writeDisableRed : 1;
 830     uint8_t writeDisableGreen : 1;
 831     uint8_t writeDisableBlue : 1;
 832     uint8_t writeDisableAlpha : 1;
 833 };
 834 static_assert(sizeof(SWR_RENDER_TARGET_BLEND_STATE) == 1, "Invalid SWR_RENDER_TARGET_BLEND_STATE size");
 835
 836 enum SWR_MULTISAMPLE_COUNT
 837 {
 838     SWR_MULTISAMPLE_1X = 0,
 839     SWR_MULTISAMPLE_2X,
 840     SWR_MULTISAMPLE_4X,
 841     SWR_MULTISAMPLE_8X,
 842     SWR_MULTISAMPLE_16X,
 843     SWR_MULTISAMPLE_TYPE_COUNT
 844 };
 845
 846 INLINE uint32_t GetNumSamples(SWR_MULTISAMPLE_COUNT sampleCount) // @llvm_func_start
 847 {
 848     static const uint32_t sampleCountLUT[SWR_MULTISAMPLE_TYPE_COUNT] {1, 2, 4, 8, 16};
 849     assert(sampleCount < SWR_MULTISAMPLE_TYPE_COUNT);
 850     return sampleCountLUT[sampleCount];
 851 } // @llvm_func_end
 852
 853 struct SWR_BLEND_STATE
 854 {
 855     // constant blend factor color in RGBA float
 856     float constantColor[4];
 857
 858     // alpha test reference value in unorm8 or float32
 859     uint32_t alphaTestReference;
 860     uint32_t sampleMask;
 861     // all RT's have the same sample count
 862     ///@todo move this to Output Merger state when we refactor
 863     SWR_MULTISAMPLE_COUNT sampleCount;  // @llvm_enum
 864
 865     SWR_RENDER_TARGET_BLEND_STATE renderTarget[SWR_NUM_RENDERTARGETS];
 866 };
 867 static_assert(sizeof(SWR_BLEND_STATE) == 36, "Invalid SWR_BLEND_STATE size");
 868
 869 //////////////////////////////////////////////////////////////////////////
 870 /// FUNCTION POINTERS FOR SHADERS
 871
 872 #if USE_SIMD16_SHADERS
 873 typedef void(__cdecl *PFN_FETCH_FUNC)(SWR_FETCH_CONTEXT& fetchInfo, simd16vertex& out);
 874 #else
 875 typedef void(__cdecl *PFN_FETCH_FUNC)(SWR_FETCH_CONTEXT& fetchInfo, simdvertex& out);
 876 #endif
 877 typedef void(__cdecl *PFN_VERTEX_FUNC)(HANDLE hPrivateData, SWR_VS_CONTEXT* pVsContext);
 878 typedef void(__cdecl *PFN_HS_FUNC)(HANDLE hPrivateData, SWR_HS_CONTEXT* pHsContext);
 879 typedef void(__cdecl *PFN_DS_FUNC)(HANDLE hPrivateData, SWR_DS_CONTEXT* pDsContext);
 880 typedef void(__cdecl *PFN_GS_FUNC)(HANDLE hPrivateData, SWR_GS_CONTEXT* pGsContext);
 881 typedef void(__cdecl *PFN_CS_FUNC)(HANDLE hPrivateData, SWR_CS_CONTEXT* pCsContext);
 882 typedef void(__cdecl *PFN_SO_FUNC)(SWR_STREAMOUT_CONTEXT& soContext);
 883 typedef void(__cdecl *PFN_PIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT *pContext);
 884 typedef void(__cdecl *PFN_CPIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT *pContext);
 885 typedef void(__cdecl *PFN_BLEND_JIT_FUNC)(const SWR_BLEND_STATE*,
 886     simdvector& vSrc, simdvector& vSrc1, simdscalar& vSrc0Alpha, uint32_t sample,
 887     uint8_t* pDst, simdvector& vResult, simdscalari* vOMask, simdscalari* vCoverageMask);
 888 typedef simdscalar(*PFN_QUANTIZE_DEPTH)(simdscalar const &);
 889
 890
 891
 892 //////////////////////////////////////////////////////////////////////////
 893 /// FRONTEND_STATE
 894 /////////////////////////////////////////////////////////////////////////
 895 struct SWR_FRONTEND_STATE
 896 {
 897     // skip clip test, perspective divide, and viewport transform
 898     // intended for verts in screen space
 899     bool vpTransformDisable;
 900     bool bEnableCutIndex;
 901     union
 902     {
 903         struct
 904         {
 905             uint32_t triFan : 2;
 906             uint32_t lineStripList : 1;
 907             uint32_t triStripList : 2;
 908         };
 909         uint32_t bits;
 910     } provokingVertex;
 911     uint32_t topologyProvokingVertex; // provoking vertex for the draw topology
 912
 913     // Size of a vertex in simdvector units. Should be sized to the
 914     // maximum of the input/output of the vertex shader.
 915     uint32_t vsVertexSize;
 916 };
 917
 918 //////////////////////////////////////////////////////////////////////////
 919 /// VIEWPORT_MATRIX
 920 /////////////////////////////////////////////////////////////////////////
 921 struct SWR_VIEWPORT_MATRIX
 922 {
 923     float m00;
 924     float m11;
 925     float m22;
 926     float m30;
 927     float m31;
 928     float m32;
 929 };
 930
 931 //////////////////////////////////////////////////////////////////////////
 932 /// VIEWPORT_MATRIXES
 933 /////////////////////////////////////////////////////////////////////////
 934 struct SWR_VIEWPORT_MATRICES
 935 {
 936     float m00[KNOB_NUM_VIEWPORTS_SCISSORS];
 937     float m11[KNOB_NUM_VIEWPORTS_SCISSORS];
 938     float m22[KNOB_NUM_VIEWPORTS_SCISSORS];
 939     float m30[KNOB_NUM_VIEWPORTS_SCISSORS];
 940     float m31[KNOB_NUM_VIEWPORTS_SCISSORS];
 941     float m32[KNOB_NUM_VIEWPORTS_SCISSORS];
 942 };
 943
 944 //////////////////////////////////////////////////////////////////////////
 945 /// SWR_VIEWPORT
 946 /////////////////////////////////////////////////////////////////////////
 947 struct SWR_VIEWPORT
 948 {
 949     float x;
 950     float y;
 951     float width;
 952     float height;
 953     float minZ;
 954     float maxZ;
 955 };
 956
 957 //////////////////////////////////////////////////////////////////////////
 958 /// SWR_CULLMODE
 959 //////////////////////////////////////////////////////////////////////////
 960 enum SWR_CULLMODE
 961 {
 962     SWR_CULLMODE_BOTH,
 963     SWR_CULLMODE_NONE,
 964     SWR_CULLMODE_FRONT,
 965     SWR_CULLMODE_BACK
 966 };
 967
 968 enum SWR_FILLMODE
 969 {
 970     SWR_FILLMODE_POINT,
 971     SWR_FILLMODE_WIREFRAME,
 972     SWR_FILLMODE_SOLID
 973 };
 974
 975 enum SWR_FRONTWINDING
 976 {
 977     SWR_FRONTWINDING_CW,
 978     SWR_FRONTWINDING_CCW
 979 };
 980
 981
 982 enum SWR_PIXEL_LOCATION
 983 {
 984     SWR_PIXEL_LOCATION_CENTER,
 985     SWR_PIXEL_LOCATION_UL,
 986 };
 987
 988 // fixed point screen space sample locations within a pixel
 989 struct SWR_MULTISAMPLE_POS
 990 {
 991 public:
 992     INLINE void SetXi(uint32_t sampleNum, uint32_t val) { _xi[sampleNum] = val; }; // @llvm_func
 993     INLINE void SetYi(uint32_t sampleNum, uint32_t val) { _yi[sampleNum] = val; }; // @llvm_func
 994     INLINE uint32_t Xi(uint32_t sampleNum) const { return _xi[sampleNum]; }; // @llvm_func
 995     INLINE uint32_t Yi(uint32_t sampleNum) const { return _yi[sampleNum]; }; // @llvm_func
 996     INLINE void SetX(uint32_t sampleNum, float val) { _x[sampleNum] = val; }; // @llvm_func
 997     INLINE void SetY(uint32_t sampleNum, float val) { _y[sampleNum] = val; }; // @llvm_func
 998     INLINE float X(uint32_t sampleNum) const { return _x[sampleNum]; }; // @llvm_func
 999     INLINE float Y(uint32_t sampleNum) const { return _y[sampleNum]; }; // @llvm_func
1000     typedef const float(&sampleArrayT)[SWR_MAX_NUM_MULTISAMPLES]; //@llvm_typedef
1001     INLINE sampleArrayT X() const { return _x; }; // @llvm_func
1002     INLINE sampleArrayT Y() const { return _y; }; // @llvm_func
1003     INLINE const __m128i& vXi(uint32_t sampleNum) const { return _vXi[sampleNum]; }; // @llvm_func
1004     INLINE const __m128i& vYi(uint32_t sampleNum) const { return _vYi[sampleNum]; }; // @llvm_func
1005     INLINE const simdscalar& vX(uint32_t sampleNum) const { return _vX[sampleNum]; }; // @llvm_func
1006     INLINE const simdscalar& vY(uint32_t sampleNum) const { return _vY[sampleNum]; }; // @llvm_func
1007     INLINE const __m128i& TileSampleOffsetsX() const { return tileSampleOffsetsX; }; // @llvm_func
1008     INLINE const __m128i& TileSampleOffsetsY() const { return tileSampleOffsetsY; }; // @llvm_func
1009
1010     INLINE void PrecalcSampleData(int numSamples); //@llvm_func
1011
1012 private:
1013     template <typename MaskT>
1014     INLINE __m128i expandThenBlend4(uint32_t* min, uint32_t* max); // @llvm_func
1015     INLINE void CalcTileSampleOffsets(int numSamples);   // @llvm_func
1016
1017     // scalar sample values
1018     uint32_t _xi[SWR_MAX_NUM_MULTISAMPLES];
1019     uint32_t _yi[SWR_MAX_NUM_MULTISAMPLES];
1020     float _x[SWR_MAX_NUM_MULTISAMPLES];
1021     float _y[SWR_MAX_NUM_MULTISAMPLES];
1022
1023     // precalc'd / vectorized samples
1024     __m128i _vXi[SWR_MAX_NUM_MULTISAMPLES];
1025     __m128i _vYi[SWR_MAX_NUM_MULTISAMPLES];
1026     simdscalar _vX[SWR_MAX_NUM_MULTISAMPLES];
1027     simdscalar _vY[SWR_MAX_NUM_MULTISAMPLES];
1028     __m128i tileSampleOffsetsX;
1029     __m128i tileSampleOffsetsY;
1030 };
1031
1032 //////////////////////////////////////////////////////////////////////////
1033 /// SWR_RASTSTATE
1034 //////////////////////////////////////////////////////////////////////////
1035 struct SWR_RASTSTATE
1036 {
1037     uint32_t cullMode               : 2;
1038     uint32_t fillMode               : 2;
1039     uint32_t frontWinding           : 1;
1040     uint32_t scissorEnable          : 1;
1041     uint32_t depthClipEnable        : 1;
1042     uint32_t clipHalfZ              : 1;
1043     uint32_t pointParam             : 1;
1044     uint32_t pointSpriteEnable      : 1;
1045     uint32_t pointSpriteTopOrigin   : 1;
1046     uint32_t forcedSampleCount      : 1;
1047     uint32_t pixelOffset            : 1;
1048     uint32_t depthBiasPreAdjusted   : 1;    ///< depth bias constant is in float units, not per-format Z units
1049     uint32_t conservativeRast       : 1;
1050
1051     float pointSize;
1052     float lineWidth;
1053
1054     float depthBias;
1055     float slopeScaledDepthBias;
1056     float depthBiasClamp;
1057     SWR_FORMAT depthFormat;     // @llvm_enum
1058
1059     // sample count the rasterizer is running at
1060     SWR_MULTISAMPLE_COUNT sampleCount;  // @llvm_enum
1061     uint32_t pixelLocation;     // UL or Center
1062     SWR_MULTISAMPLE_POS samplePositions;    // @llvm_struct
1063     bool bIsCenterPattern;   // @llvm_enum
1064 };
1065
1066
1067 enum SWR_CONSTANT_SOURCE
1068 {
1069     SWR_CONSTANT_SOURCE_CONST_0000,
1070     SWR_CONSTANT_SOURCE_CONST_0001_FLOAT,
1071     SWR_CONSTANT_SOURCE_CONST_1111_FLOAT,
1072     SWR_CONSTANT_SOURCE_PRIM_ID
1073 };
1074
1075 struct SWR_ATTRIB_SWIZZLE
1076 {
1077     uint16_t sourceAttrib : 5;          // source attribute
1078     uint16_t constantSource : 2;        // constant source to apply
1079     uint16_t componentOverrideMask : 4; // override component with constant source
1080 };
1081
1082 // backend state
1083 struct SWR_BACKEND_STATE
1084 {
1085     uint32_t constantInterpolationMask;     // bitmask indicating which attributes have constant interpolation
1086     uint32_t pointSpriteTexCoordMask;       // bitmask indicating the attribute(s) which should be interpreted as tex coordinates
1087
1088     uint8_t numAttributes;                  // total number of attributes to send to backend (up to 32)
1089     uint8_t numComponents[32];              // number of components to setup per attribute, this reduces some calculations for unneeded components
1090
1091     bool swizzleEnable;                 // when enabled, core will parse the swizzle map when
1092                                         // setting up attributes for the backend, otherwise
1093                                         // all attributes up to numAttributes will be sent
1094     SWR_ATTRIB_SWIZZLE swizzleMap[32];
1095
1096     bool readRenderTargetArrayIndex;    // Forward render target array index from last FE stage to the backend
1097     bool readViewportArrayIndex;        // Read viewport array index from last FE stage during binning
1098
1099         // Offset to the start of the attributes of the input vertices, in simdvector units
1100     uint32_t vertexAttribOffset;
1101
1102     // User clip/cull distance enables
1103     uint8_t cullDistanceMask;
1104     uint8_t clipDistanceMask;
1105
1106     // Offset to clip/cull attrib section of the vertex, in simdvector units
1107     uint32_t vertexClipCullOffset;
1108 };
1109
1110
1111 union SWR_DEPTH_STENCIL_STATE
1112 {
1113     struct
1114     {
1115         // dword 0
1116         uint32_t depthWriteEnable : 1;
1117         uint32_t depthTestEnable : 1;
1118         uint32_t stencilWriteEnable : 1;
1119         uint32_t stencilTestEnable : 1;
1120         uint32_t doubleSidedStencilTestEnable : 1;
1121
1122         uint32_t depthTestFunc : 3;
1123         uint32_t stencilTestFunc : 3;
1124
1125         uint32_t backfaceStencilPassDepthPassOp : 3;
1126         uint32_t backfaceStencilPassDepthFailOp : 3;
1127         uint32_t backfaceStencilFailOp : 3;
1128         uint32_t backfaceStencilTestFunc : 3;
1129         uint32_t stencilPassDepthPassOp : 3;
1130         uint32_t stencilPassDepthFailOp : 3;
1131         uint32_t stencilFailOp : 3;
1132
1133         // dword 1
1134         uint8_t backfaceStencilWriteMask;
1135         uint8_t backfaceStencilTestMask;
1136         uint8_t stencilWriteMask;
1137         uint8_t stencilTestMask;
1138
1139         // dword 2
1140         uint8_t backfaceStencilRefValue;
1141         uint8_t stencilRefValue;
1142     };
1143     uint32_t value[3];
1144 };
1145
1146 enum SWR_SHADING_RATE
1147 {
1148     SWR_SHADING_RATE_PIXEL,
1149     SWR_SHADING_RATE_SAMPLE,
1150     SWR_SHADING_RATE_COUNT,
1151 };
1152
1153 enum SWR_INPUT_COVERAGE
1154 {
1155     SWR_INPUT_COVERAGE_NONE,
1156     SWR_INPUT_COVERAGE_NORMAL,
1157     SWR_INPUT_COVERAGE_INNER_CONSERVATIVE,
1158     SWR_INPUT_COVERAGE_COUNT,
1159 };
1160
1161 enum SWR_PS_POSITION_OFFSET
1162 {
1163     SWR_PS_POSITION_SAMPLE_NONE,
1164     SWR_PS_POSITION_SAMPLE_OFFSET,
1165     SWR_PS_POSITION_CENTROID_OFFSET,
1166     SWR_PS_POSITION_OFFSET_COUNT,
1167 };
1168
1169 enum SWR_BARYCENTRICS_MASK
1170 {
1171     SWR_BARYCENTRIC_PER_PIXEL_MASK = 0x1,
1172     SWR_BARYCENTRIC_CENTROID_MASK = 0x2,
1173     SWR_BARYCENTRIC_PER_SAMPLE_MASK = 0x4,
1174 };
1175
1176 // pixel shader state
1177 struct SWR_PS_STATE
1178 {
1179     // dword 0-1
1180     PFN_PIXEL_KERNEL pfnPixelShader;  // @llvm_pfn
1181
1182     // dword 2
1183     uint32_t killsPixel             : 1;    // pixel shader can kill pixels
1184     uint32_t inputCoverage          : 2;    // ps uses input coverage
1185     uint32_t writesODepth           : 1;    // pixel shader writes to depth
1186     uint32_t usesSourceDepth        : 1;    // pixel shader reads depth
1187     uint32_t shadingRate            : 2;    // shading per pixel / sample / coarse pixel
1188     uint32_t posOffset              : 2;    // type of offset (none, sample, centroid) to add to pixel position
1189     uint32_t barycentricsMask       : 3;    // which type(s) of barycentric coords does the PS interpolate attributes with
1190     uint32_t usesUAV                : 1;    // pixel shader accesses UAV
1191     uint32_t forceEarlyZ            : 1;    // force execution of early depth/stencil test
1192
1193     uint8_t renderTargetMask;               // Mask of render targets written
1194 };
1195
1196 // depth bounds state
1197 struct SWR_DEPTH_BOUNDS_STATE
1198 {
1199     bool    depthBoundsTestEnable;
1200     float   depthBoundsTestMinValue;
1201     float   depthBoundsTestMaxValue;
1202 };
1203