src/gallium/drivers/swr/swr_draw.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_screen.h"
  25 #include "swr_context.h"
  26 #include "swr_resource.h"
  27 #include "swr_fence.h"
  28 #include "swr_query.h"
  29 #include "jit_api.h"
  30
  31 #include "util/u_draw.h"
  32 #include "util/u_prim.h"
  33
  34 /*
  35  * Draw vertex arrays, with optional indexing, optional instancing.
  36  */
  37 static void
  38 swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
  39 {
  40    struct swr_context *ctx = swr_context(pipe);
  41
  42    if (!info->count_from_stream_output && !info->indirect &&
  43        !info->primitive_restart &&
  44        !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
  45       return;
  46
  47    if (!swr_check_render_cond(pipe))
  48       return;
  49
  50    if (info->indirect) {
  51       util_draw_indirect(pipe, info);
  52       return;
  53    }
  54
  55    /* Update derived state, pass draw info to update function */
  56    swr_update_derived(pipe, info);
  57
  58    swr_update_draw_context(ctx);
  59
  60    if (ctx->vs->pipe.stream_output.num_outputs) {
  61       if (!ctx->vs->soFunc[info->mode]) {
  62          STREAMOUT_COMPILE_STATE state = {0};
  63          struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
  64
  65          state.numVertsPerPrim = u_vertices_per_prim(info->mode);
  66
  67          uint32_t offsets[MAX_SO_STREAMS] = {0};
  68          uint32_t num = 0;
  69
  70          for (uint32_t i = 0; i < so->num_outputs; i++) {
  71             assert(so->output[i].stream == 0); // @todo
  72             uint32_t output_buffer = so->output[i].output_buffer;
  73             if (so->output[i].dst_offset != offsets[output_buffer]) {
  74                // hole - need to fill
  75                state.stream.decl[num].bufferIndex = output_buffer;
  76                state.stream.decl[num].hole = true;
  77                state.stream.decl[num].componentMask =
  78                   (1 << (so->output[i].dst_offset - offsets[output_buffer]))
  79                   - 1;
  80                num++;
  81                offsets[output_buffer] = so->output[i].dst_offset;
  82             }
  83
  84             state.stream.decl[num].bufferIndex = output_buffer;
  85             state.stream.decl[num].attribSlot = so->output[i].register_index - 1;
  86             state.stream.decl[num].componentMask =
  87                ((1 << so->output[i].num_components) - 1)
  88                << so->output[i].start_component;
  89             state.stream.decl[num].hole = false;
  90             num++;
  91
  92             offsets[output_buffer] += so->output[i].num_components;
  93          }
  94
  95          state.stream.numDecls = num;
  96
  97          HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
  98          ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
  99          debug_printf("so shader    %p\n", ctx->vs->soFunc[info->mode]);
 100          assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
 101       }
 102
 103       SwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
 104    }
 105
 106    struct swr_vertex_element_state *velems = ctx->velems;
 107    velems->fsState.cutIndex = info->restart_index;
 108    velems->fsState.bEnableCutIndex = info->primitive_restart;
 109    velems->fsState.bPartialVertexBuffer = (info->min_index > 0);
 110
 111    swr_jit_fetch_key key;
 112    swr_generate_fetch_key(key, velems);
 113    auto search = velems->map.find(key);
 114    if (search != velems->map.end()) {
 115       velems->fsFunc = search->second;
 116    } else {
 117       HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
 118       velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
 119
 120       debug_printf("fetch shader %p\n", velems->fsFunc);
 121       assert(velems->fsFunc && "Error: FetchShader = NULL");
 122
 123       velems->map.insert(std::make_pair(key, velems->fsFunc));
 124    }
 125
 126    SwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
 127
 128    /* Set up frontend state
 129     * XXX setup provokingVertex & topologyProvokingVertex */
 130    SWR_FRONTEND_STATE feState = {0};
 131
 132    /* XXX this value should be minimized based on the shader set */
 133    feState.vsVertexSize = SWR_VTX_NUM_SLOTS;
 134
 135    if (ctx->rasterizer->flatshade_first) {
 136       feState.provokingVertex = {1, 0, 0};
 137    } else {
 138       feState.provokingVertex = {2, 1, 2};
 139    }
 140
 141    enum pipe_prim_type topology;
 142    if (ctx->gs)
 143       topology = (pipe_prim_type)ctx->gs->info.base.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
 144    else
 145       topology = info->mode;
 146
 147    switch (topology) {
 148    case PIPE_PRIM_TRIANGLE_FAN:
 149       feState.topologyProvokingVertex = feState.provokingVertex.triFan;
 150       break;
 151    case PIPE_PRIM_TRIANGLE_STRIP:
 152    case PIPE_PRIM_TRIANGLES:
 153       feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
 154       break;
 155    case PIPE_PRIM_QUAD_STRIP:
 156    case PIPE_PRIM_QUADS:
 157       if (ctx->rasterizer->flatshade_first)
 158          feState.topologyProvokingVertex = 0;
 159       else
 160          feState.topologyProvokingVertex = 3;
 161       break;
 162    case PIPE_PRIM_LINES:
 163    case PIPE_PRIM_LINE_LOOP:
 164    case PIPE_PRIM_LINE_STRIP:
 165       feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
 166       break;
 167    default:
 168       feState.topologyProvokingVertex = 0;
 169    }
 170
 171    feState.bEnableCutIndex = info->primitive_restart;
 172    SwrSetFrontendState(ctx->swrContext, &feState);
 173
 174    if (info->index_size)
 175       SwrDrawIndexedInstanced(ctx->swrContext,
 176                               swr_convert_prim_topology(info->mode),
 177                               info->count,
 178                               info->instance_count,
 179                               info->start,
 180                               info->index_bias,
 181                               info->start_instance);
 182    else
 183       SwrDrawInstanced(ctx->swrContext,
 184                        swr_convert_prim_topology(info->mode),
 185                        info->count,
 186                        info->instance_count,
 187                        info->start,
 188                        info->start_instance);
 189 }
 190
 191
 192 static void
 193 swr_flush(struct pipe_context *pipe,
 194           struct pipe_fence_handle **fence,
 195           unsigned flags)
 196 {
 197    struct swr_context *ctx = swr_context(pipe);
 198    struct swr_screen *screen = swr_screen(pipe->screen);
 199    struct pipe_surface *cb = ctx->framebuffer.cbufs[0];
 200
 201    /* If the current renderTarget is the display surface, store tiles back to
 202     * the surface, in preparation for present (swr_flush_frontbuffer).
 203     * Other renderTargets get stored back when attachment changes or
 204     * swr_surface_destroy */
 205    if (cb && swr_resource(cb->texture)->display_target)
 206       swr_store_dirty_resource(pipe, cb->texture, SWR_TILE_RESOLVED);
 207
 208    if (fence)
 209       swr_fence_reference(pipe->screen, fence, screen->flush_fence);
 210 }
 211
 212 void
 213 swr_finish(struct pipe_context *pipe)
 214 {
 215    struct pipe_fence_handle *fence = nullptr;
 216
 217    swr_flush(pipe, &fence, 0);
 218    swr_fence_finish(pipe->screen, NULL, fence, 0);
 219    swr_fence_reference(pipe->screen, &fence, NULL);
 220 }
 221
 222
 223 /*
 224  * Store SWR HotTiles back to renderTarget surface.
 225  */
 226 void
 227 swr_store_render_target(struct pipe_context *pipe,
 228                         uint32_t attachment,
 229                         enum SWR_TILE_STATE post_tile_state)
 230 {
 231    struct swr_context *ctx = swr_context(pipe);
 232    struct swr_draw_context *pDC = &ctx->swrDC;
 233    struct SWR_SURFACE_STATE *renderTarget = &pDC->renderTargets[attachment];
 234
 235    /* Only proceed if there's a valid surface to store to */
 236    if (renderTarget->pBaseAddress) {
 237       swr_update_draw_context(ctx);
 238       SWR_RECT full_rect =
 239          {0, 0,
 240           (int32_t)u_minify(renderTarget->width, renderTarget->lod),
 241           (int32_t)u_minify(renderTarget->height, renderTarget->lod)};
 242       SwrStoreTiles(ctx->swrContext,
 243                     1 << attachment,
 244                     post_tile_state,
 245                     full_rect);
 246    }
 247 }
 248
 249 void
 250 swr_store_dirty_resource(struct pipe_context *pipe,
 251                          struct pipe_resource *resource,
 252                          enum SWR_TILE_STATE post_tile_state)
 253 {
 254    /* Only store resource if it has been written to */
 255    if (swr_resource(resource)->status & SWR_RESOURCE_WRITE) {
 256       struct swr_context *ctx = swr_context(pipe);
 257       struct swr_screen *screen = swr_screen(pipe->screen);
 258       struct swr_resource *spr = swr_resource(resource);
 259
 260       swr_draw_context *pDC = &ctx->swrDC;
 261       SWR_SURFACE_STATE *renderTargets = pDC->renderTargets;
 262       for (uint32_t i = 0; i < SWR_NUM_ATTACHMENTS; i++)
 263          if (renderTargets[i].pBaseAddress == spr->swr.pBaseAddress ||
 264              (spr->secondary.pBaseAddress &&
 265               renderTargets[i].pBaseAddress == spr->secondary.pBaseAddress)) {
 266             swr_store_render_target(pipe, i, post_tile_state);
 267
 268             /* Mesa thinks depth/stencil are fused, so we'll never get an
 269              * explicit resource for stencil.  So, if checking depth, then
 270              * also check for stencil. */
 271             if (spr->has_stencil && (i == SWR_ATTACHMENT_DEPTH)) {
 272                swr_store_render_target(
 273                   pipe, SWR_ATTACHMENT_STENCIL, post_tile_state);
 274             }
 275
 276             /* This fence signals StoreTiles completion */
 277             swr_fence_submit(ctx, screen->flush_fence);
 278
 279             break;
 280          }
 281    }
 282 }
 283
 284 void
 285 swr_draw_init(struct pipe_context *pipe)
 286 {
 287    pipe->draw_vbo = swr_draw_vbo;
 288    pipe->flush = swr_flush;
 289 }